1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 /* Includes ------------------------------------------------------------------*/
19 #include "stm32h7xx_ll_utils.h"
20 #include "stm32h7xx_ll_rcc.h"
21 #include "stm32h7xx_ll_pwr.h"
22
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32H7xx_LL_Driver
30 * @{
31 */
32
33 /** @addtogroup UTILS_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /** @addtogroup UTILS_LL_Private_Constants
41 * @{
42 */
43 #if (STM32H7_DEV_ID == 0x450UL)
44 #define UTILS_MAX_FREQUENCY_SCALE1 480000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
45 #define UTILS_MAX_FREQUENCY_SCALE2 300000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
46 #define UTILS_MAX_FREQUENCY_SCALE3 200000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
47 #elif (STM32H7_DEV_ID == 0x480UL)
48 #define UTILS_MAX_FREQUENCY_SCALE0 280000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
49 #define UTILS_MAX_FREQUENCY_SCALE1 225000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
50 #define UTILS_MAX_FREQUENCY_SCALE2 160000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
51 #define UTILS_MAX_FREQUENCY_SCALE3 88000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
52 #elif (STM32H7_DEV_ID == 0x483UL)
53 #define UTILS_MAX_FREQUENCY_SCALE0 550000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
54 #define UTILS_MAX_FREQUENCY_SCALE1 200000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
55 #define UTILS_MAX_FREQUENCY_SCALE2 150000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
56 #define UTILS_MAX_FREQUENCY_SCALE3 85000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
57 #endif /*STM32H7_DEV_ID == 0x450UL*/
58
59 /* Defines used for PLL range */
60 #define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
61 #define UTILS_PLLVCO_INPUT_MAX1 2000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
62 #define UTILS_PLLVCO_INPUT_MIN2 2000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
63 #define UTILS_PLLVCO_INPUT_MAX2 4000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
64 #define UTILS_PLLVCO_INPUT_MIN3 4000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
65 #define UTILS_PLLVCO_INPUT_MAX3 8000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
66 #define UTILS_PLLVCO_INPUT_MIN4 8000000U /*!< Frequency min for the low range PLLVCO input, in Hz */
67 #define UTILS_PLLVCO_INPUT_MAX4 16000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */
68
69 #if (POWER_DOMAINS_NUMBER == 3U)
70 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */
71 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */
72 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */
73 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */
74 #else
75 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */
76 #define UTILS_PLLVCO_WIDE_OUTPUT_MIN 128000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */
77 #define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */
78 #define UTILS_PLLVCO_WIDE_OUTPUT_MAX 560000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */
79 #endif /*POWER_DOMAINS_NUMBER == 3U*/
80
81 /* Defines used for HSE range */
82 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
83 #define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
84
85 /* Defines used for FLASH latency according to HCLK Frequency */
86 #if (STM32H7_DEV_ID == 0x480UL)
87 #define UTILS_SCALE0_LATENCY0_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
88 #define UTILS_SCALE0_LATENCY1_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
89 #define UTILS_SCALE0_LATENCY2_FREQ 132000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
90 #define UTILS_SCALE0_LATENCY3_FREQ 176000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
91 #define UTILS_SCALE0_LATENCY4_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */
92 #define UTILS_SCALE0_LATENCY5_FREQ 264000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */
93 #define UTILS_SCALE0_LATENCY6_FREQ 280000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 0 */
94
95 #define UTILS_SCALE1_LATENCY0_FREQ 42000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
96 #define UTILS_SCALE1_LATENCY1_FREQ 84000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
97 #define UTILS_SCALE1_LATENCY2_FREQ 126000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
98 #define UTILS_SCALE1_LATENCY3_FREQ 168000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
99 #define UTILS_SCALE1_LATENCY4_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
100 #define UTILS_SCALE1_LATENCY5_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
101
102 #define UTILS_SCALE2_LATENCY0_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
103 #define UTILS_SCALE2_LATENCY1_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
104 #define UTILS_SCALE2_LATENCY2_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
105 #define UTILS_SCALE2_LATENCY3_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
106 #define UTILS_SCALE2_LATENCY4_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
107
108 #define UTILS_SCALE3_LATENCY0_FREQ 22000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
109 #define UTILS_SCALE3_LATENCY1_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
110 #define UTILS_SCALE3_LATENCY2_FREQ 66000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
111 #define UTILS_SCALE3_LATENCY3_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
112
113 #elif (STM32H7_DEV_ID == 0x450UL)
114
115 #define UTILS_SCALE1_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
116 #define UTILS_SCALE1_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
117 #define UTILS_SCALE1_LATENCY2_FREQ 240000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
118
119 #define UTILS_SCALE2_LATENCY0_FREQ 55000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
120 #define UTILS_SCALE2_LATENCY1_FREQ 110000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
121 #define UTILS_SCALE2_LATENCY2_FREQ 165000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
122 #define UTILS_SCALE2_LATENCY3_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
123
124 #define UTILS_SCALE3_LATENCY0_FREQ 45000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
125 #define UTILS_SCALE3_LATENCY1_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
126 #define UTILS_SCALE3_LATENCY2_FREQ 135000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
127 #define UTILS_SCALE3_LATENCY3_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
128 #define UTILS_SCALE3_LATENCY4_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
129
130 #elif (STM32H7_DEV_ID == 0x483UL)
131
132 #define UTILS_SCALE0_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */
133 #define UTILS_SCALE0_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
134 #define UTILS_SCALE0_LATENCY2_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
135 #define UTILS_SCALE0_LATENCY3_FREQ 275000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
136
137 #define UTILS_SCALE1_LATENCY0_FREQ 67000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */
138 #define UTILS_SCALE1_LATENCY1_FREQ 133000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
139 #define UTILS_SCALE1_LATENCY2_FREQ 200000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
140
141 #define UTILS_SCALE2_LATENCY0_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */
142 #define UTILS_SCALE2_LATENCY1_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
143 #define UTILS_SCALE2_LATENCY2_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
144
145 #define UTILS_SCALE3_LATENCY0_FREQ 35000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */
146 #define UTILS_SCALE3_LATENCY1_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
147 #define UTILS_SCALE3_LATENCY2_FREQ 85000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
148
149 #endif /*STM32H7_DEV_ID == 0x480UL*/
150 /**
151 * @}
152 */
153
154 /* Private macros ------------------------------------------------------------*/
155 /** @addtogroup UTILS_LL_Private_Macros
156 * @{
157 */
158 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
159 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
160 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
161 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
162 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
163 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
164 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
165 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
166 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
167
168 #define IS_LL_UTILS_AHB_DIV(__VALUE__) (((__VALUE__) == LL_RCC_AHB_DIV_1) \
169 || ((__VALUE__) == LL_RCC_AHB_DIV_2) \
170 || ((__VALUE__) == LL_RCC_AHB_DIV_4) \
171 || ((__VALUE__) == LL_RCC_AHB_DIV_8) \
172 || ((__VALUE__) == LL_RCC_AHB_DIV_16) \
173 || ((__VALUE__) == LL_RCC_AHB_DIV_64) \
174 || ((__VALUE__) == LL_RCC_AHB_DIV_128) \
175 || ((__VALUE__) == LL_RCC_AHB_DIV_256) \
176 || ((__VALUE__) == LL_RCC_AHB_DIV_512))
177
178 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
179 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
180 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
181 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
182 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
183
184 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
185 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
186 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
187 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
188 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
189
190 #define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \
191 || ((__VALUE__) == LL_RCC_APB3_DIV_2) \
192 || ((__VALUE__) == LL_RCC_APB3_DIV_4) \
193 || ((__VALUE__) == LL_RCC_APB3_DIV_8) \
194 || ((__VALUE__) == LL_RCC_APB3_DIV_16))
195
196 #define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \
197 || ((__VALUE__) == LL_RCC_APB4_DIV_2) \
198 || ((__VALUE__) == LL_RCC_APB4_DIV_4) \
199 || ((__VALUE__) == LL_RCC_APB4_DIV_8) \
200 || ((__VALUE__) == LL_RCC_APB4_DIV_16))
201
202 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U))
203
204 #if (POWER_DOMAINS_NUMBER == 3U)
205 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U))
206 #else
207 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U))
208 #endif /*POWER_DOMAINS_NUMBER == 3U*/
209
210 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U))
211
212 #define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU)
213
214 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) ( \
215 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \
216 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \
217 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \
218 (((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4)))
219
220 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \
221 (((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \
222 (((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX)))
223
224 #define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \
225 (((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \
226 (((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE)))
227
228 #if (STM32H7_DEV_ID == 0x450UL)
229 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
230 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
231 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
232 #else
233 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \
234 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
235 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
236 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
237 #endif /* STM32H7_DEV_ID == 0x450UL */
238
239 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
240 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
241
242 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
243 /**
244 * @}
245 */
246 /* Private function prototypes -----------------------------------------------*/
247 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
248 * @{
249 */
250 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
251 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
252 static ErrorStatus UTILS_IsPLLsReady(void);
253 static uint32_t UTILS_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
254 /**
255 * @}
256 */
257
258 /* Exported functions --------------------------------------------------------*/
259 /** @addtogroup UTILS_LL_Exported_Functions
260 * @{
261 */
262
263 /** @addtogroup UTILS_LL_EF_DELAY
264 * @{
265 */
266 #if defined (DUAL_CORE)
267 /**
268 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
269 * @note When a RTOS is used, it is recommended to avoid changing the Systick
270 * configuration by calling this function, for a delay use rather osDelay RTOS service.
271 * @param CPU_Frequency Core frequency in Hz
272 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
273 * @ref LL_RCC_GetSystemClocksFreq
274 * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
275 * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency.
276 * @retval None
277 */
278 #else
279 /**
280 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
281 * @note When a RTOS is used, it is recommended to avoid changing the Systick
282 * configuration by calling this function, for a delay use rather osDelay RTOS service.
283 * @param CPU_Frequency Core frequency in Hz
284 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
285 * @ref LL_RCC_GetSystemClocksFreq
286 * @retval None
287 */
288 #endif /* DUAL_CORE */
LL_Init1msTick(uint32_t CPU_Frequency)289 void LL_Init1msTick(uint32_t CPU_Frequency)
290 {
291 /* Use frequency provided in argument */
292 LL_InitTick(CPU_Frequency, 1000U);
293 }
294
295
296 /**
297 * @brief This function provides accurate delay (in milliseconds) based
298 * on SysTick counter flag
299 * @note When a RTOS is used, it is recommended to avoid using blocking delay
300 * and use rather osDelay service.
301 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
302 * will configure Systick to 1ms
303 * @param Delay specifies the delay time length, in milliseconds.
304 * @retval None
305 */
LL_mDelay(uint32_t Delay)306 void LL_mDelay(uint32_t Delay)
307 {
308 uint32_t count = Delay;
309 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
310 /* Add this code to indicate that local variable is not used */
311 ((void)tmp);
312
313 /* Add a period to guaranty minimum wait */
314 if(count < LL_MAX_DELAY)
315 {
316 count++;
317 }
318
319 while (count != 0U)
320 {
321 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
322 {
323 count--;
324 }
325 }
326 }
327
328 /**
329 * @}
330 */
331
332 #if (STM32H7_DEV_ID == 0x450UL)
333 /** @addtogroup UTILS_EF_SYSTEM
334 * @brief System Configuration functions
335 *
336 @verbatim
337 ===============================================================================
338 ##### System Configuration functions #####
339 ===============================================================================
340 [..]
341 System, AHB and APB buses clocks configuration
342
343 (+) The maximum frequency of the SYSCLK is 480 MHz(*) and HCLK is 240 MHz.
344 (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 120 MHz.
345 @endverbatim
346 @internal
347 Depending on the device voltage range, the maximum frequency should be
348 adapted accordingly:
349 (++) +----------------------------------------------------------------------------+
350 (++) | Wait states | HCLK clock frequency (MHz) |
351 (++) | |-----------------------------------------------------------|
352 (++) | (Latency) | voltage range 1 | voltage range 2 | voltage range 3 |
353 (++) | | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
354 (++) |----------------|-------------------|-------------------|-------------------|
355 (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 55 | 0 < HCLK <= 45 |
356 (++) |----------------|-------------------|-------------------|-------------------|
357 (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 55 < HCLK <= 110 | 45 < HCLK <= 90 |
358 (++) |----------------|-------------------|-------------------|-------------------|
359 (++) |2WS(3CPU cycle) | 140 < HCLK <= 240 | 110 < HCLK <= 165 | 90 < HCLK <= 135 |
360 (++) |----------------|-------------------|-------------------|-------------------|
361 (++) |3WS(4CPU cycle) | -- | 165 < HCLK <= 220 | 135 < HCLK <= 180 |
362 (++) |----------------|-------------------|-------------------|-------------------|
363 (++) |4WS(5CPU cycle) | -- | -- | 180 < HCLK <= 225 |
364 (++) +----------------------------------------------------------------------------+
365
366 (*) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
367 @endinternal
368 * @{
369 */
370
371 #elif (STM32H7_DEV_ID == 0x480UL)
372 /** @addtogroup UTILS_EF_SYSTEM
373 * @brief System Configuration functions
374 *
375 @verbatim
376 ===============================================================================
377 ##### System Configuration functions #####
378 ===============================================================================
379 [..]
380 System, AHB and APB buses clocks configuration
381
382 (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz.
383 (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz.
384 @endverbatim
385 @internal
386 Depending on the device voltage range, the maximum frequency should be
387 adapted accordingly:
388 (++) +------------------------------------------------------------------------------------------------+
389 (++) | Wait states | HCLK clock frequency (MHz) |
390 (++) | |-------------------------------------------------------------------------------|
391 (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 |
392 (++) | | 1.26V - 1.35V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
393 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
394 (++) |0WS(1CPU cycle) | 0 < HCLK <= 44 | 0 < HCLK <= 42 | 0 < HCLK <= 34 | 0 < HCLK <= 22 |
395 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
396 (++) |1WS(2CPU cycle) | 44 < HCLK <= 88 | 42 < HCLK <= 84 | 34 < HCLK <= 68 | 22 < HCLK <= 44 |
397 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
398 (++) |2WS(3CPU cycle) | 88 < HCLK <= 132 | 84 < HCLK <= 126 | 68 < HCLK <= 102 | 44 < HCLK <= 66 |
399 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
400 (++) |3WS(4CPU cycle) | 132 < HCLK <= 176 | 126 < HCLK <= 168 | 102 < HCLK <= 136 | 66 < HCLK <= 88 |
401 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
402 (++) |4WS(5CPU cycle) | 176 < HCLK <= 220 | 168 < HCLK <= 210 | 136 < HCLK <= 160 | -- |
403 (++) +------------------------------------------------------------------------------------------------+
404 (++) |5WS(6CPU cycle) | 220 < HCLK <= 264 | 210 < HCLK <= 225 | -- | -- |
405 (++) +------------------------------------------------------------------------------------------------+
406 (++) |6WS(7CPU cycle) | 264 < HCLK <= 280 | -- | -- | -- |
407 (++) +------------------------------------------------------------------------------------------------+
408 (++) |7WS(8CPU cycle) | -- | -- | -- | -- |
409 (++) +------------------------------------------------------------------------------------------------+
410
411 @endinternal
412 * @{
413 */
414
415 #elif (STM32H7_DEV_ID == 0x483UL)
416 /** @addtogroup UTILS_EF_SYSTEM
417 * @brief System Configuration functions
418 *
419 @verbatim
420 ===============================================================================
421 ##### System Configuration functions #####
422 ===============================================================================
423 [..]
424 System, AHB and APB buses clocks configuration
425
426 (+) The maximum frequency of the SYSCLK is 550 MHz(*) and HCLK is 275 MHz.
427 (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 137.5 MHz.
428 @endverbatim
429 @internal
430 Depending on the device voltage range, the maximum frequency should be
431 adapted accordingly:
432 (++) +------------------------------------------------------------------------------------------------+
433 (++) | Wait states | HCLK clock frequency (MHz) |
434 (++) | |-------------------------------------------------------------------------------|
435 (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 |
436 (++) | | 1.26V - 1.40V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V |
437 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
438 (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 67 | 0 < HCLK <= 50 | 0 < HCLK <= 35 |
439 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
440 (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 67 < HCLK <= 133 | 50 < HCLK <= 100 | 35 < HCLK <= 70 |
441 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
442 (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 133 < HCLK <= 200 | 100 < HCLK <= 150 | 70 < HCLK <= 85 |
443 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
444 (++) |3WS(4CPU cycle) | 210 < HCLK <= 275 | -- | -- | -- |
445 (++) +----------------|-------------------|-------------------|-------------------|-------------------|
446
447 (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
448 @endinternal
449 * @{
450 */
451 #endif /* STM32H7_DEV_ID == 0x450UL */
452
453 #if defined (DUAL_CORE)
454 /**
455 * @brief This function sets directly SystemCoreClock CMSIS variable.
456 * @note Variable can be calculated also through SystemCoreClockUpdate function.
457 * @param CPU_Frequency Core frequency in Hz
458 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
459 * @ref LL_RCC_GetSystemClocksFreq
460 * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency
461 * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency.
462 * @retval None
463 */
464 #else
465 /**
466 * @brief This function sets directly SystemCoreClock CMSIS variable.
467 * @note Variable can be calculated also through SystemCoreClockUpdate function.
468 * @param CPU_Frequency Core frequency in Hz
469 * @note CPU_Frequency can be calculated thanks to RCC helper macro or function
470 * @ref LL_RCC_GetSystemClocksFreq
471 * @retval None
472 */
473 #endif /* DUAL_CORE */
LL_SetSystemCoreClock(uint32_t CPU_Frequency)474 void LL_SetSystemCoreClock(uint32_t CPU_Frequency)
475 {
476 /* HCLK clock frequency */
477 SystemCoreClock = CPU_Frequency;
478 }
479
480 /**
481 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
482 * @note The application need to ensure that PLL is disabled.
483 * @note Function is based on the following formula:
484 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
485 * - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
486 * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
487 * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reach (PLLVCO_output / PLLP)
488 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
489 * the configuration information for the PLL.
490 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
491 * the configuration information for the BUS prescalers.
492 * @retval An ErrorStatus enumeration value:
493 * - SUCCESS: Max frequency configuration done
494 * - ERROR: Max frequency configuration not done
495 *
496 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
497 * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
498 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
499 *
500 */
LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)501 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
502 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
503 {
504 ErrorStatus status;
505 #ifdef USE_FULL_ASSERT
506 uint32_t vcoinput_freq, vcooutput_freq;
507 #endif
508 uint32_t pllfreq, hsi_clk;
509
510 /* Check the parameters */
511 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
512 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
513 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
514 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
515
516 hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
517
518 /* Check VCO Input frequency */
519 #ifdef USE_FULL_ASSERT
520 vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
521 #endif
522 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
523
524 /* Check VCO Output frequency */
525 #ifdef USE_FULL_ASSERT
526 vcooutput_freq = UTILS_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
527 #endif
528 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
529
530 /* Check VCO Input ranges */
531 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
532
533 /* Check if one of the PLL is enabled */
534 if(UTILS_IsPLLsReady() == SUCCESS)
535 {
536 /* Calculate the new PLL output frequency */
537 pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
538
539 /* Enable HSI if not enabled */
540 if(LL_RCC_HSI_IsReady() != 1U)
541 {
542 LL_RCC_HSI_Enable();
543 while (LL_RCC_HSI_IsReady() != 1U)
544 {
545 /* Wait for HSI ready */
546 }
547 }
548
549 /* Configure PLL */
550 LL_RCC_PLL1P_Enable();
551 LL_RCC_PLL1FRACN_Enable();
552 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
553 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
554 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
555 LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
556 LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
557 LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
558 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
559
560 /* Enable PLL and switch system clock to PLL */
561 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
562 }
563 else
564 {
565 /* Current PLL configuration cannot be modified */
566 status = ERROR;
567 }
568
569 return status;
570 }
571
572 /**
573 * @brief This function configures system clock with HSE as clock source of the PLL
574 * @note The application need to ensure that PLL is disabled.
575 * @note Function is based on the following formula:
576 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
577 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
578 * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN)
579 * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reached (PLLVCO_output / PLLP)
580 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
581 * @param HSEBypass This parameter can be one of the following values:
582 * @arg @ref LL_UTILS_HSEBYPASS_ON
583 * @arg @ref LL_UTILS_HSEBYPASS_OFF
584 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
585 * the configuration information for the PLL.
586 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
587 * the configuration information for the BUS prescalers.
588 * @retval An ErrorStatus enumeration value:
589 * - SUCCESS: Max frequency configuration done
590 * - ERROR: Max frequency configuration not done
591 *
592 * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise.
593 * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise.
594 * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
595 *
596 */
LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,uint32_t HSEBypass,LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct,LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct)597 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
598 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
599 {
600 ErrorStatus status;
601 #ifdef USE_FULL_ASSERT
602 uint32_t vcoinput_freq, vcooutput_freq;
603 #endif
604 uint32_t pllfreq;
605
606 /* Check the parameters */
607 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
608 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
609 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
610 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
611 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
612 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
613
614 /* Check VCO Input frequency */
615 #ifdef USE_FULL_ASSERT
616 vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM;
617 #endif
618 assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
619
620 /* Check VCO output frequency */
621 #ifdef USE_FULL_ASSERT
622 vcooutput_freq = UTILS_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
623 #endif
624 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
625
626 /* Check VCO Input/output ranges compatibility */
627 assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
628
629 /* Check if one of the PLL is enabled */
630 if(UTILS_IsPLLsReady() == SUCCESS)
631 {
632 /* Calculate the new PLL output frequency */
633 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
634
635 /* Enable HSE if not enabled */
636 if(LL_RCC_HSE_IsReady() != 1U)
637 {
638 /* Check if need to enable HSE bypass feature or not */
639 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
640 {
641 LL_RCC_HSE_EnableBypass();
642 }
643 else
644 {
645 LL_RCC_HSE_DisableBypass();
646 }
647
648 /* Enable HSE */
649 LL_RCC_HSE_Enable();
650 while (LL_RCC_HSE_IsReady() != 1U)
651 {
652 /* Wait for HSE ready */
653 }
654 }
655
656 /* Configure PLL */
657 LL_RCC_PLL1P_Enable();
658 LL_RCC_PLL1FRACN_Enable();
659 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
660 LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
661 LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
662 LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
663 LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
664 LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
665 LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
666
667 /* Enable PLL and switch system clock to PLL */
668 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
669 }
670 else
671 {
672 /* Current PLL configuration cannot be modified */
673 status = ERROR;
674 }
675
676 return status;
677 }
678
679 /**
680 * @}
681 */
682
683 /**
684 * @brief Update number of Flash wait states in line with new frequency and current
685 voltage range.
686 * @param HCLK_Frequency HCLK frequency
687 * @retval An ErrorStatus enumeration value:
688 * - SUCCESS: Latency has been modified
689 * - ERROR: Latency cannot be modified
690 */
LL_SetFlashLatency(uint32_t HCLK_Frequency)691 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
692 {
693 ErrorStatus status = SUCCESS;
694 uint32_t timeout;
695 uint32_t getlatency;
696 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
697
698
699
700 /* Frequency cannot be equal to 0 */
701 if (HCLK_Frequency == 0U)
702 {
703 status = ERROR;
704 }
705 else
706 {
707 #if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x483UL)
708 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
709 {
710 #if (STM32H7_DEV_ID == 0x480UL)
711 if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ))
712 {
713 /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */
714 latency = LL_FLASH_LATENCY_6;
715 }
716 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ))
717 {
718 /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */
719 latency = LL_FLASH_LATENCY_5;
720 }
721 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ))
722 {
723 /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */
724 latency = LL_FLASH_LATENCY_4;
725 }
726 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
727 #elif (STM32H7_DEV_ID == 0x483UL)
728 if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ))
729 #endif /* STM32H7_DEV_ID == 0x480UL */
730 {
731 /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */
732 latency = LL_FLASH_LATENCY_3;
733 }
734 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ))
735 {
736 /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */
737 latency = LL_FLASH_LATENCY_2;
738 }
739 else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ))
740 {
741 /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */
742 latency = LL_FLASH_LATENCY_1;
743 }
744 else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ)
745 {
746 /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
747 }
748 else
749 {
750 status = ERROR;
751 }
752 }
753 #if (STM32H7_DEV_ID == 0x480UL)
754 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
755 {
756 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ))
757 {
758 /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */
759 latency = LL_FLASH_LATENCY_5;
760 }
761 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ))
762 {
763 /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */
764 latency = LL_FLASH_LATENCY_4;
765 }
766 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ))
767 {
768 /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */
769 latency = LL_FLASH_LATENCY_3;
770 }
771 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
772 #else
773 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
774 {
775 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
776 #endif /* STM32H7_DEV_ID == 0x480UL */
777 #else
778 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
779 {
780 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ))
781 #endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x483UL */
782 {
783 /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */
784 latency = LL_FLASH_LATENCY_2;
785 }
786 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ))
787 {
788 /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */
789 latency = LL_FLASH_LATENCY_1;
790 }
791 else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ)
792 {
793 /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
794 }
795 else
796 {
797 status = ERROR;
798 }
799 }
800 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
801 {
802 #if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x450UL)
803 #if (STM32H7_DEV_ID == 0x480UL)
804 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ))
805 {
806 /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */
807 latency = LL_FLASH_LATENCY_4;
808 }
809 else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
810 #else
811 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ))
812 #endif /* STM32H7_DEV_ID == 0x480UL */
813 {
814 /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */
815 latency = LL_FLASH_LATENCY_3;
816 }
817 else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
818 #else
819 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ))
820 #endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x450UL */
821 {
822 /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */
823 latency = LL_FLASH_LATENCY_2;
824 }
825 else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ))
826 {
827 /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */
828 latency = LL_FLASH_LATENCY_1;
829 }
830 else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ)
831 {
832 /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
833 }
834 else
835 {
836 status = ERROR;
837 }
838 }
839 else /* Scale 3 */
840 {
841 #if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL)
842 #if (STM32H7_DEV_ID == 0x450UL)
843 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ))
844 {
845 /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */
846 latency = LL_FLASH_LATENCY_4;
847 }
848 else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
849 #else
850 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ))
851 #endif /*STM32H7_DEV_ID == 0x450UL*/
852 {
853 /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */
854 latency = LL_FLASH_LATENCY_3;
855 }
856 else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
857 #else
858 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ))
859 #endif /* STM32H7_DEV_ID == 0x450UL || STM32H7_DEV_ID == 0x480UL */
860 {
861 /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */
862 latency = LL_FLASH_LATENCY_2;
863 }
864 else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ))
865 {
866 /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */
867 latency = LL_FLASH_LATENCY_1;
868 }
869 else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ)
870 {
871 /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */
872 }
873 else
874 {
875 status = ERROR;
876 }
877 }
878
879 if(status == SUCCESS)
880 {
881 LL_FLASH_SetLatency(latency);
882
883 /* Check that the new number of wait states is taken into account to access the Flash
884 memory by reading the FLASH_ACR register */
885 timeout = 2;
886 do
887 {
888 /* Wait for Flash latency to be updated */
889 getlatency = LL_FLASH_GetLatency();
890 timeout--;
891 } while ((getlatency != latency) && (timeout > 0U));
892
893 if(getlatency != latency)
894 {
895 status = ERROR;
896 }
897 }
898 }
899
900 return status;
901 }
902
903
904 /**
905 * @}
906 */
907
908 /** @addtogroup UTILS_LL_Private_Functions
909 * @{
910 */
911
912
913 /**
914 * @brief Function to check that PLL can be modified
915 * @param PLL_InputFrequency PLL input frequency (in Hz)
916 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
917 * the configuration information for the PLL.
918 * @retval PLL output frequency (in Hz)
919 */
920 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
921 {
922 uint32_t pllfreq;
923
924 /* Check the parameters */
925 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
926 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
927 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
928 assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
929
930 pllfreq = UTILS_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
931
932 return pllfreq;
933 }
934
935 /**
936 * @brief Check that all PLLs are ready therefore configuration can be done
937 * @retval An ErrorStatus enumeration value:
938 * - SUCCESS: All PLLs are ready so configuration can be done
939 * - ERROR: One PLL at least is busy
940 */
941 static ErrorStatus UTILS_IsPLLsReady(void)
942 {
943 ErrorStatus status = SUCCESS;
944
945 /* Check if one of the PLL1 is busy */
946 if(LL_RCC_PLL1_IsReady() != 0U)
947 {
948 /* PLL1 configuration cannot be done */
949 status = ERROR;
950 }
951
952 /* Check if one of the PLL2 is busy */
953 if(LL_RCC_PLL2_IsReady() != 0U)
954 {
955 /* PLL2 configuration cannot be done */
956 status = ERROR;
957 }
958
959 /* Check if one of the PLL3 is busy */
960 if(LL_RCC_PLL3_IsReady() != 0U)
961 {
962 /* PLL3 configuration cannot be done */
963 status = ERROR;
964 }
965
966 return status;
967 }
968
969 /**
970 * @brief Helper function to calculate the PLL frequency output
971 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
972 * @param M Between 1 and 63
973 * @param N Between 4 and 512
974 * @param FRACN Between 0 and 0x1FFF
975 * @param PQR VCO output divider (P, Q or R)
976 * Between 1 and 128, except for PLL1P Odd value not allowed
977 * @retval PLL1 clock frequency (in Hz)
978 */
979 static uint32_t UTILS_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
980 {
981 float_t freq;
982
983 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
984
985 freq = freq / (float_t)PQR;
986
987 return (uint32_t)freq;
988 }
989
990 /**
991 * @brief Function to enable PLL and switch system clock to PLL
992 * @param SYSCLK_Frequency SYSCLK frequency
993 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
994 * the configuration information for the BUS prescalers.
995 * @retval An ErrorStatus enumeration value:
996 * - SUCCESS: No problem to switch system to PLL
997 * - ERROR: Problem to switch system to PLL
998 */
999 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
1000 {
1001 ErrorStatus status = SUCCESS;
1002 uint32_t new_hclk_frequency;
1003
1004 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
1005 assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
1006 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
1007 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
1008 assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
1009 assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
1010
1011 /* Calculate the new HCLK frequency */
1012 new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
1013
1014 /* Increasing the number of wait states because of higher CPU frequency */
1015 if (SystemD2Clock < new_hclk_frequency)
1016 {
1017 /* Set FLASH latency to highest latency */
1018 status = LL_SetFlashLatency(new_hclk_frequency);
1019 }
1020
1021 /* Update system clock configuration */
1022 if(status == SUCCESS)
1023 {
1024 /* Enable PLL */
1025 LL_RCC_PLL1_Enable();
1026 while (LL_RCC_PLL1_IsReady() != 1U)
1027 {
1028 /* Wait for PLL ready */
1029 }
1030
1031 /* Set All APBxPrescaler to the Highest Divider */
1032 LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
1033 LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
1034 LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
1035 LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
1036
1037 /* Set SYS prescaler*/
1038 LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
1039
1040 /* Set AHB prescaler*/
1041 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
1042
1043 /* Sysclk activation on the main PLL */
1044 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
1045 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
1046 {
1047 /* Wait for system clock switch to PLL */
1048 }
1049
1050 /* Set APBn prescaler*/
1051 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
1052 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
1053 LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
1054 LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
1055
1056 /* Decreasing the number of wait states because of lower CPU frequency */
1057 if (SystemD2Clock > new_hclk_frequency)
1058 {
1059 /* Set FLASH latency to lowest latency */
1060 status = LL_SetFlashLatency(new_hclk_frequency);
1061 }
1062
1063 /* Update the SystemD2Clock global variable */
1064 #if defined(RCC_D1CFGR_HPRE)
1065 SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
1066 #else
1067 SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
1068 #endif
1069
1070 /* Update SystemCoreClock variable */
1071 #if defined(DUAL_CORE) && defined(CORE_CM4)
1072 LL_SetSystemCoreClock(SystemD2Clock);
1073 #else
1074 LL_SetSystemCoreClock(SYSCLK_Frequency);
1075 #endif /* DUAL_CORE && CORE_CM4 */
1076
1077 }
1078
1079
1080 return status;
1081 }
1082
1083 /**
1084 * @}
1085 */
1086
1087 /**
1088 * @}
1089 */
1090
1091 /**
1092 * @}
1093 */
1094
1095
