1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (overridden) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (overridden) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
95 and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 or HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (overridden) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32h7xx_hal.h"
117
118
119 /** @addtogroup STM32H7xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SRAM_MODULE_ENABLED
124
125 /** @defgroup SRAM SRAM
126 * @brief SRAM driver modules
127 * @{
128 */
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
136 * @{
137 */
138 static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
139 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
140 static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma);
141 /**
142 * @}
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146
147 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
148 * @{
149 */
150
151 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
152 * @brief Initialization and Configuration functions.
153 *
154 @verbatim
155 ==============================================================================
156 ##### SRAM Initialization and de_initialization functions #####
157 ==============================================================================
158 [..] This section provides functions allowing to initialize/de-initialize
159 the SRAM memory
160
161 @endverbatim
162 * @{
163 */
164
165 /**
166 * @brief Performs the SRAM device initialization sequence
167 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
168 * the configuration information for SRAM module.
169 * @param Timing Pointer to SRAM control timing structure
170 * @param ExtTiming Pointer to SRAM extended mode timing structure
171 * @retval HAL status
172 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)173 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
174 FMC_NORSRAM_TimingTypeDef *ExtTiming)
175 {
176 /* Check the SRAM handle parameter */
177 if (hsram == NULL)
178 {
179 return HAL_ERROR;
180 }
181
182 if (hsram->State == HAL_SRAM_STATE_RESET)
183 {
184 /* Allocate lock resource and initialize it */
185 hsram->Lock = HAL_UNLOCKED;
186
187 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
188 if (hsram->MspInitCallback == NULL)
189 {
190 hsram->MspInitCallback = HAL_SRAM_MspInit;
191 }
192 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
193 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
194
195 /* Init the low level hardware */
196 hsram->MspInitCallback(hsram);
197 #else
198 /* Initialize the low level hardware (MSP) */
199 HAL_SRAM_MspInit(hsram);
200 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
201 }
202
203 /* Initialize SRAM control Interface */
204 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
205
206 /* Initialize SRAM timing Interface */
207 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
208
209 /* Initialize SRAM extended mode timing Interface */
210 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
211 hsram->Init.ExtendedMode);
212
213 /* Enable the NORSRAM device */
214 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
215
216 /* Enable FMC Peripheral */
217 __FMC_ENABLE();
218
219 /* Initialize the SRAM controller state */
220 hsram->State = HAL_SRAM_STATE_READY;
221
222 return HAL_OK;
223 }
224
225 /**
226 * @brief Performs the SRAM device De-initialization sequence.
227 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
228 * the configuration information for SRAM module.
229 * @retval HAL status
230 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)231 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
232 {
233 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
234 if (hsram->MspDeInitCallback == NULL)
235 {
236 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
237 }
238
239 /* DeInit the low level hardware */
240 hsram->MspDeInitCallback(hsram);
241 #else
242 /* De-Initialize the low level hardware (MSP) */
243 HAL_SRAM_MspDeInit(hsram);
244 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
245
246 /* Configure the SRAM registers with their reset values */
247 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
248
249 /* Reset the SRAM controller state */
250 hsram->State = HAL_SRAM_STATE_RESET;
251
252 /* Release Lock */
253 __HAL_UNLOCK(hsram);
254
255 return HAL_OK;
256 }
257
258 /**
259 * @brief SRAM MSP Init.
260 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
261 * the configuration information for SRAM module.
262 * @retval None
263 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)264 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
265 {
266 /* Prevent unused argument(s) compilation warning */
267 UNUSED(hsram);
268
269 /* NOTE : This function Should not be modified, when the callback is needed,
270 the HAL_SRAM_MspInit could be implemented in the user file
271 */
272 }
273
274 /**
275 * @brief SRAM MSP DeInit.
276 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
277 * the configuration information for SRAM module.
278 * @retval None
279 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)280 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
281 {
282 /* Prevent unused argument(s) compilation warning */
283 UNUSED(hsram);
284
285 /* NOTE : This function Should not be modified, when the callback is needed,
286 the HAL_SRAM_MspDeInit could be implemented in the user file
287 */
288 }
289
290 /**
291 * @brief DMA transfer complete callback.
292 * @param hmdma pointer to a SRAM_HandleTypeDef structure that contains
293 * the configuration information for SRAM module.
294 * @retval None
295 */
HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef * hmdma)296 __weak void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
297 {
298 /* Prevent unused argument(s) compilation warning */
299 UNUSED(hmdma);
300
301 /* NOTE : This function Should not be modified, when the callback is needed,
302 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
303 */
304 }
305
306 /**
307 * @brief DMA transfer complete error callback.
308 * @param hmdma pointer to a SRAM_HandleTypeDef structure that contains
309 * the configuration information for SRAM module.
310 * @retval None
311 */
HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef * hmdma)312 __weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
313 {
314 /* Prevent unused argument(s) compilation warning */
315 UNUSED(hmdma);
316
317 /* NOTE : This function Should not be modified, when the callback is needed,
318 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
319 */
320 }
321
322 /**
323 * @}
324 */
325
326 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
327 * @brief Input Output and memory control functions
328 *
329 @verbatim
330 ==============================================================================
331 ##### SRAM Input and Output functions #####
332 ==============================================================================
333 [..]
334 This section provides functions allowing to use and control the SRAM memory
335
336 @endverbatim
337 * @{
338 */
339
340 /**
341 * @brief Reads 8-bit buffer from SRAM memory.
342 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
343 * the configuration information for SRAM module.
344 * @param pAddress Pointer to read start address
345 * @param pDstBuffer Pointer to destination buffer
346 * @param BufferSize Size of the buffer to read from memory
347 * @retval HAL status
348 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)349 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
350 uint32_t BufferSize)
351 {
352 uint32_t size;
353 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
354 uint8_t *pdestbuff = pDstBuffer;
355 HAL_SRAM_StateTypeDef state = hsram->State;
356
357 /* Check the SRAM controller state */
358 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
359 {
360 /* Process Locked */
361 __HAL_LOCK(hsram);
362
363 /* Update the SRAM controller state */
364 hsram->State = HAL_SRAM_STATE_BUSY;
365
366 /* Read data from memory */
367 for (size = BufferSize; size != 0U; size--)
368 {
369 *pdestbuff = *psramaddress;
370 pdestbuff++;
371 psramaddress++;
372 }
373
374 /* Update the SRAM controller state */
375 hsram->State = state;
376
377 /* Process unlocked */
378 __HAL_UNLOCK(hsram);
379 }
380 else
381 {
382 return HAL_ERROR;
383 }
384
385 return HAL_OK;
386 }
387
388 /**
389 * @brief Writes 8-bit buffer to SRAM memory.
390 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
391 * the configuration information for SRAM module.
392 * @param pAddress Pointer to write start address
393 * @param pSrcBuffer Pointer to source buffer to write
394 * @param BufferSize Size of the buffer to write to memory
395 * @retval HAL status
396 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)397 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
398 uint32_t BufferSize)
399 {
400 uint32_t size;
401 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
402 uint8_t *psrcbuff = pSrcBuffer;
403
404 /* Check the SRAM controller state */
405 if (hsram->State == HAL_SRAM_STATE_READY)
406 {
407 /* Process Locked */
408 __HAL_LOCK(hsram);
409
410 /* Update the SRAM controller state */
411 hsram->State = HAL_SRAM_STATE_BUSY;
412
413 /* Write data to memory */
414 for (size = BufferSize; size != 0U; size--)
415 {
416 *psramaddress = *psrcbuff;
417 psrcbuff++;
418 psramaddress++;
419 }
420
421 /* Update the SRAM controller state */
422 hsram->State = HAL_SRAM_STATE_READY;
423
424 /* Process unlocked */
425 __HAL_UNLOCK(hsram);
426 }
427 else
428 {
429 return HAL_ERROR;
430 }
431
432 return HAL_OK;
433 }
434
435 /**
436 * @brief Reads 16-bit buffer from SRAM memory.
437 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
438 * the configuration information for SRAM module.
439 * @param pAddress Pointer to read start address
440 * @param pDstBuffer Pointer to destination buffer
441 * @param BufferSize Size of the buffer to read from memory
442 * @retval HAL status
443 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)444 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
445 uint32_t BufferSize)
446 {
447 uint32_t size;
448 __IO uint32_t *psramaddress = pAddress;
449 uint16_t *pdestbuff = pDstBuffer;
450 uint8_t limit;
451 HAL_SRAM_StateTypeDef state = hsram->State;
452
453 /* Check the SRAM controller state */
454 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
455 {
456 /* Process Locked */
457 __HAL_LOCK(hsram);
458
459 /* Update the SRAM controller state */
460 hsram->State = HAL_SRAM_STATE_BUSY;
461
462 /* Check if the size is a 32-bits multiple */
463 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
464
465 /* Read data from memory */
466 for (size = BufferSize; size != limit; size -= 2U)
467 {
468 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
469 pdestbuff++;
470 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
471 pdestbuff++;
472 psramaddress++;
473 }
474
475 /* Read last 16-bits if size is not 32-bits multiple */
476 if (limit != 0U)
477 {
478 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
479 }
480
481 /* Update the SRAM controller state */
482 hsram->State = state;
483
484 /* Process unlocked */
485 __HAL_UNLOCK(hsram);
486 }
487 else
488 {
489 return HAL_ERROR;
490 }
491
492 return HAL_OK;
493 }
494
495 /**
496 * @brief Writes 16-bit buffer to SRAM memory.
497 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
498 * the configuration information for SRAM module.
499 * @param pAddress Pointer to write start address
500 * @param pSrcBuffer Pointer to source buffer to write
501 * @param BufferSize Size of the buffer to write to memory
502 * @retval HAL status
503 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)504 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
505 uint32_t BufferSize)
506 {
507 uint32_t size;
508 __IO uint32_t *psramaddress = pAddress;
509 uint16_t *psrcbuff = pSrcBuffer;
510 uint8_t limit;
511
512 /* Check the SRAM controller state */
513 if (hsram->State == HAL_SRAM_STATE_READY)
514 {
515 /* Process Locked */
516 __HAL_LOCK(hsram);
517
518 /* Update the SRAM controller state */
519 hsram->State = HAL_SRAM_STATE_BUSY;
520
521 /* Check if the size is a 32-bits multiple */
522 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
523
524 /* Write data to memory */
525 for (size = BufferSize; size != limit; size -= 2U)
526 {
527 *psramaddress = (uint32_t)(*psrcbuff);
528 psrcbuff++;
529 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
530 psrcbuff++;
531 psramaddress++;
532 }
533
534 /* Write last 16-bits if size is not 32-bits multiple */
535 if (limit != 0U)
536 {
537 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
538 }
539
540 /* Update the SRAM controller state */
541 hsram->State = HAL_SRAM_STATE_READY;
542
543 /* Process unlocked */
544 __HAL_UNLOCK(hsram);
545 }
546 else
547 {
548 return HAL_ERROR;
549 }
550
551 return HAL_OK;
552 }
553
554 /**
555 * @brief Reads 32-bit buffer from SRAM memory.
556 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
557 * the configuration information for SRAM module.
558 * @param pAddress Pointer to read start address
559 * @param pDstBuffer Pointer to destination buffer
560 * @param BufferSize Size of the buffer to read from memory
561 * @retval HAL status
562 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)563 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
564 uint32_t BufferSize)
565 {
566 uint32_t size;
567 __IO uint32_t *psramaddress = pAddress;
568 uint32_t *pdestbuff = pDstBuffer;
569 HAL_SRAM_StateTypeDef state = hsram->State;
570
571 /* Check the SRAM controller state */
572 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
573 {
574 /* Process Locked */
575 __HAL_LOCK(hsram);
576
577 /* Update the SRAM controller state */
578 hsram->State = HAL_SRAM_STATE_BUSY;
579
580 /* Read data from memory */
581 for (size = BufferSize; size != 0U; size--)
582 {
583 *pdestbuff = *psramaddress;
584 pdestbuff++;
585 psramaddress++;
586 }
587
588 /* Update the SRAM controller state */
589 hsram->State = state;
590
591 /* Process unlocked */
592 __HAL_UNLOCK(hsram);
593 }
594 else
595 {
596 return HAL_ERROR;
597 }
598
599 return HAL_OK;
600 }
601
602 /**
603 * @brief Writes 32-bit buffer to SRAM memory.
604 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
605 * the configuration information for SRAM module.
606 * @param pAddress Pointer to write start address
607 * @param pSrcBuffer Pointer to source buffer to write
608 * @param BufferSize Size of the buffer to write to memory
609 * @retval HAL status
610 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)611 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
612 uint32_t BufferSize)
613 {
614 uint32_t size;
615 __IO uint32_t *psramaddress = pAddress;
616 uint32_t *psrcbuff = pSrcBuffer;
617
618 /* Check the SRAM controller state */
619 if (hsram->State == HAL_SRAM_STATE_READY)
620 {
621 /* Process Locked */
622 __HAL_LOCK(hsram);
623
624 /* Update the SRAM controller state */
625 hsram->State = HAL_SRAM_STATE_BUSY;
626
627 /* Write data to memory */
628 for (size = BufferSize; size != 0U; size--)
629 {
630 *psramaddress = *psrcbuff;
631 psrcbuff++;
632 psramaddress++;
633 }
634
635 /* Update the SRAM controller state */
636 hsram->State = HAL_SRAM_STATE_READY;
637
638 /* Process unlocked */
639 __HAL_UNLOCK(hsram);
640 }
641 else
642 {
643 return HAL_ERROR;
644 }
645
646 return HAL_OK;
647 }
648
649 /**
650 * @brief Reads a Words data from the SRAM memory using DMA transfer.
651 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
652 * the configuration information for SRAM module.
653 * @param pAddress Pointer to read start address
654 * @param pDstBuffer Pointer to destination buffer
655 * @param BufferSize Size of the buffer to read from memory
656 * @retval HAL status
657 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)658 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
659 uint32_t BufferSize)
660 {
661 HAL_StatusTypeDef status;
662 HAL_SRAM_StateTypeDef state = hsram->State;
663
664 /* Check the SRAM controller state */
665 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
666 {
667 /* Process Locked */
668 __HAL_LOCK(hsram);
669
670 /* Update the SRAM controller state */
671 hsram->State = HAL_SRAM_STATE_BUSY;
672
673 /* Configure DMA user callbacks */
674 if (state == HAL_SRAM_STATE_READY)
675 {
676 hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
677 }
678 else
679 {
680 hsram->hmdma->XferCpltCallback = SRAM_DMACpltProt;
681 }
682 hsram->hmdma->XferErrorCallback = SRAM_DMAError;
683
684 /* Enable the DMA Stream */
685 status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
686
687 /* Process unlocked */
688 __HAL_UNLOCK(hsram);
689 }
690 else
691 {
692 status = HAL_ERROR;
693 }
694
695 return status;
696 }
697
698 /**
699 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
700 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
701 * the configuration information for SRAM module.
702 * @param pAddress Pointer to write start address
703 * @param pSrcBuffer Pointer to source buffer to write
704 * @param BufferSize Size of the buffer to write to memory
705 * @retval HAL status
706 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)707 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
708 uint32_t BufferSize)
709 {
710 HAL_StatusTypeDef status;
711
712 /* Check the SRAM controller state */
713 if (hsram->State == HAL_SRAM_STATE_READY)
714 {
715 /* Process Locked */
716 __HAL_LOCK(hsram);
717
718 /* Update the SRAM controller state */
719 hsram->State = HAL_SRAM_STATE_BUSY;
720
721 /* Configure DMA user callbacks */
722 hsram->hmdma->XferCpltCallback = SRAM_DMACplt;
723 hsram->hmdma->XferErrorCallback = SRAM_DMAError;
724
725 /* Enable the DMA Stream */
726 status = HAL_MDMA_Start_IT(hsram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
727
728 /* Process unlocked */
729 __HAL_UNLOCK(hsram);
730 }
731 else
732 {
733 status = HAL_ERROR;
734 }
735
736 return status;
737 }
738
739 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
740 /**
741 * @brief Register a User SRAM Callback
742 * To be used to override the weak predefined callback
743 * @param hsram : SRAM handle
744 * @param CallbackId : ID of the callback to be registered
745 * This parameter can be one of the following values:
746 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
747 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
748 * @param pCallback : pointer to the Callback function
749 * @retval status
750 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)751 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
752 pSRAM_CallbackTypeDef pCallback)
753 {
754 HAL_StatusTypeDef status = HAL_OK;
755 HAL_SRAM_StateTypeDef state;
756
757 if (pCallback == NULL)
758 {
759 return HAL_ERROR;
760 }
761
762 state = hsram->State;
763 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
764 {
765 switch (CallbackId)
766 {
767 case HAL_SRAM_MSP_INIT_CB_ID :
768 hsram->MspInitCallback = pCallback;
769 break;
770 case HAL_SRAM_MSP_DEINIT_CB_ID :
771 hsram->MspDeInitCallback = pCallback;
772 break;
773 default :
774 /* update return status */
775 status = HAL_ERROR;
776 break;
777 }
778 }
779 else
780 {
781 /* update return status */
782 status = HAL_ERROR;
783 }
784
785 return status;
786 }
787
788 /**
789 * @brief Unregister a User SRAM Callback
790 * SRAM Callback is redirected to the weak predefined callback
791 * @param hsram : SRAM handle
792 * @param CallbackId : ID of the callback to be unregistered
793 * This parameter can be one of the following values:
794 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
795 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
796 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
797 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
798 * @retval status
799 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)800 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
801 {
802 HAL_StatusTypeDef status = HAL_OK;
803 HAL_SRAM_StateTypeDef state;
804
805 state = hsram->State;
806 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
807 {
808 switch (CallbackId)
809 {
810 case HAL_SRAM_MSP_INIT_CB_ID :
811 hsram->MspInitCallback = HAL_SRAM_MspInit;
812 break;
813 case HAL_SRAM_MSP_DEINIT_CB_ID :
814 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
815 break;
816 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
817 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
818 break;
819 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
820 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
821 break;
822 default :
823 /* update return status */
824 status = HAL_ERROR;
825 break;
826 }
827 }
828 else if (state == HAL_SRAM_STATE_RESET)
829 {
830 switch (CallbackId)
831 {
832 case HAL_SRAM_MSP_INIT_CB_ID :
833 hsram->MspInitCallback = HAL_SRAM_MspInit;
834 break;
835 case HAL_SRAM_MSP_DEINIT_CB_ID :
836 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
837 break;
838 default :
839 /* update return status */
840 status = HAL_ERROR;
841 break;
842 }
843 }
844 else
845 {
846 /* update return status */
847 status = HAL_ERROR;
848 }
849
850 return status;
851 }
852
853 /**
854 * @brief Register a User SRAM Callback for DMA transfers
855 * To be used to override the weak predefined callback
856 * @param hsram : SRAM handle
857 * @param CallbackId : ID of the callback to be registered
858 * This parameter can be one of the following values:
859 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
860 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
861 * @param pCallback : pointer to the Callback function
862 * @retval status
863 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)864 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
865 pSRAM_DmaCallbackTypeDef pCallback)
866 {
867 HAL_StatusTypeDef status = HAL_OK;
868 HAL_SRAM_StateTypeDef state;
869
870 if (pCallback == NULL)
871 {
872 return HAL_ERROR;
873 }
874
875 /* Process locked */
876 __HAL_LOCK(hsram);
877
878 state = hsram->State;
879 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
880 {
881 switch (CallbackId)
882 {
883 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
884 hsram->DmaXferCpltCallback = pCallback;
885 break;
886 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
887 hsram->DmaXferErrorCallback = pCallback;
888 break;
889 default :
890 /* update return status */
891 status = HAL_ERROR;
892 break;
893 }
894 }
895 else
896 {
897 /* update return status */
898 status = HAL_ERROR;
899 }
900
901 /* Release Lock */
902 __HAL_UNLOCK(hsram);
903 return status;
904 }
905 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
906
907 /**
908 * @}
909 */
910
911 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
912 * @brief Control functions
913 *
914 @verbatim
915 ==============================================================================
916 ##### SRAM Control functions #####
917 ==============================================================================
918 [..]
919 This subsection provides a set of functions allowing to control dynamically
920 the SRAM interface.
921
922 @endverbatim
923 * @{
924 */
925
926 /**
927 * @brief Enables dynamically SRAM write operation.
928 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
929 * the configuration information for SRAM module.
930 * @retval HAL status
931 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)932 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
933 {
934 /* Check the SRAM controller state */
935 if (hsram->State == HAL_SRAM_STATE_PROTECTED)
936 {
937 /* Process Locked */
938 __HAL_LOCK(hsram);
939
940 /* Update the SRAM controller state */
941 hsram->State = HAL_SRAM_STATE_BUSY;
942
943 /* Enable write operation */
944 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
945
946 /* Update the SRAM controller state */
947 hsram->State = HAL_SRAM_STATE_READY;
948
949 /* Process unlocked */
950 __HAL_UNLOCK(hsram);
951 }
952 else
953 {
954 return HAL_ERROR;
955 }
956
957 return HAL_OK;
958 }
959
960 /**
961 * @brief Disables dynamically SRAM write operation.
962 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
963 * the configuration information for SRAM module.
964 * @retval HAL status
965 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)966 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
967 {
968 /* Check the SRAM controller state */
969 if (hsram->State == HAL_SRAM_STATE_READY)
970 {
971 /* Process Locked */
972 __HAL_LOCK(hsram);
973
974 /* Update the SRAM controller state */
975 hsram->State = HAL_SRAM_STATE_BUSY;
976
977 /* Disable write operation */
978 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
979
980 /* Update the SRAM controller state */
981 hsram->State = HAL_SRAM_STATE_PROTECTED;
982
983 /* Process unlocked */
984 __HAL_UNLOCK(hsram);
985 }
986 else
987 {
988 return HAL_ERROR;
989 }
990
991 return HAL_OK;
992 }
993
994 /**
995 * @}
996 */
997
998 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
999 * @brief Peripheral State functions
1000 *
1001 @verbatim
1002 ==============================================================================
1003 ##### SRAM State functions #####
1004 ==============================================================================
1005 [..]
1006 This subsection permits to get in run-time the status of the SRAM controller
1007 and the data flow.
1008
1009 @endverbatim
1010 * @{
1011 */
1012
1013 /**
1014 * @brief Returns the SRAM controller state
1015 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1016 * the configuration information for SRAM module.
1017 * @retval HAL state
1018 */
HAL_SRAM_GetState(const SRAM_HandleTypeDef * hsram)1019 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
1020 {
1021 return hsram->State;
1022 }
1023
1024 /**
1025 * @}
1026 */
1027
1028 /**
1029 * @}
1030 */
1031
1032 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
1033 * @{
1034 */
1035
1036 /**
1037 * @brief MDMA SRAM process complete callback.
1038 * @param hmdma : MDMA handle
1039 * @retval None
1040 */
SRAM_DMACplt(MDMA_HandleTypeDef * hmdma)1041 static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
1042 {
1043 /* Derogation MISRAC2012-Rule-11.5 */
1044 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent);
1045
1046 /* Disable the MDMA channel */
1047 __HAL_MDMA_DISABLE(hmdma);
1048
1049 /* Update the SRAM controller state */
1050 hsram->State = HAL_SRAM_STATE_READY;
1051
1052 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1053 hsram->DmaXferCpltCallback(hmdma);
1054 #else
1055 HAL_SRAM_DMA_XferCpltCallback(hmdma);
1056 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1057 }
1058
1059 /**
1060 * @brief MDMA SRAM process complete callback.
1061 * @param hmdma : MDMA handle
1062 * @retval None
1063 */
SRAM_DMACpltProt(MDMA_HandleTypeDef * hmdma)1064 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
1065 {
1066 /* Derogation MISRAC2012-Rule-11.5 */
1067 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent);
1068
1069 /* Disable the MDMA channel */
1070 __HAL_MDMA_DISABLE(hmdma);
1071
1072 /* Update the SRAM controller state */
1073 hsram->State = HAL_SRAM_STATE_PROTECTED;
1074
1075 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1076 hsram->DmaXferCpltCallback(hmdma);
1077 #else
1078 HAL_SRAM_DMA_XferCpltCallback(hmdma);
1079 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1080 }
1081
1082 /**
1083 * @brief MDMA SRAM error callback.
1084 * @param hmdma : MDMA handle
1085 * @retval None
1086 */
SRAM_DMAError(MDMA_HandleTypeDef * hmdma)1087 static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
1088 {
1089 /* Derogation MISRAC2012-Rule-11.5 */
1090 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent);
1091
1092 /* Disable the MDMA channel */
1093 __HAL_MDMA_DISABLE(hmdma);
1094
1095 /* Update the SRAM controller state */
1096 hsram->State = HAL_SRAM_STATE_ERROR;
1097
1098 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1099 hsram->DmaXferErrorCallback(hmdma);
1100 #else
1101 HAL_SRAM_DMA_XferErrorCallback(hmdma);
1102 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1103 }
1104
1105 /**
1106 * @}
1107 */
1108
1109 /**
1110 * @}
1111 */
1112
1113 #endif /* HAL_SRAM_MODULE_ENABLED */
1114
1115 /**
1116 * @}
1117 */
1118
1119
