1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_swpmi.h
4 * @author MCD Application Team
5 * @brief Header file of SWPMI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_SWPMI_H
21 #define STM32H7xx_LL_SWPMI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34
35 /** @defgroup SWPMI_LL SWPMI
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 #if defined(USE_FULL_LL_DRIVER)
44 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
45 * @{
46 */
47 /**
48 * @}
49 */
50 #endif /*USE_FULL_LL_DRIVER*/
51
52 /* Exported types ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
55 * @{
56 */
57
58 /**
59 * @brief SWPMI Init structures definition
60 */
61 typedef struct
62 {
63 uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class.
64 This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
65
66 This feature can be modified afterwards using unitary
67 function @ref LL_SWPMI_SetVoltageClass. */
68
69 uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler.
70 This parameter must be a number between Min_Data=0
71 and Max_Data=255U.
72
73 The value can be calculated thanks to helper
74 macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
75
76 This feature can be modified afterwards using unitary
77 function @ref LL_SWPMI_SetBitRatePrescaler. */
78
79 uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode.
80 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
81
82 This feature can be modified afterwards using
83 unitary function @ref LL_SWPMI_SetTransmissionMode. */
84
85 uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
86 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
87
88 This feature can be modified afterwards using
89 unitary function @ref LL_SWPMI_SetReceptionMode. */
90 } LL_SWPMI_InitTypeDef;
91
92 /**
93 * @}
94 */
95 #endif /* USE_FULL_LL_DRIVER */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
99 * @{
100 */
101
102 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
103 * @brief Flags defines which can be used with LL_SWPMI_WriteReg function
104 * @{
105 */
106 #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */
107 #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */
108 #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */
109 #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */
110 #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
111 #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */
112 #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */
113 /**
114 * @}
115 */
116
117 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
118 * @brief Flags defines which can be used with LL_SWPMI_ReadReg function
119 * @{
120 */
121 #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */
122 #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */
123 #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */
124 #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */
125 #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */
126 #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */
127 #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */
128 #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */
129 #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */
130 #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */
131 #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */
132 /**
133 * @}
134 */
135
136 /** @defgroup SWPMI_LL_EC_IT IT Defines
137 * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions
138 * @{
139 */
140 #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */
141 #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */
142 #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */
143 #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */
144 #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
145 #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */
146 #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */
147 #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */
148 #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */
149 /**
150 * @}
151 */
152
153 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
154 * @{
155 */
156 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */
157 #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */
158 /**
159 * @}
160 */
161
162 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
163 * @{
164 */
165 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */
166 #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */
167 /**
168 * @}
169 */
170
171 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
172 * @{
173 */
174 #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */
175 #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
176 /**
177 * @}
178 */
179
180 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
181 * @{
182 */
183 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */
184 #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */
185 /**
186 * @}
187 */
188
189 /**
190 * @}
191 */
192
193 /* Exported macro ------------------------------------------------------------*/
194 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
195 * @{
196 */
197
198 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
199 * @{
200 */
201
202 /**
203 * @brief Write a value in SWPMI register
204 * @param __INSTANCE__ SWPMI Instance
205 * @param __REG__ Register to be written
206 * @param __VALUE__ Value to be written in the register
207 * @retval None
208 */
209 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
210
211 /**
212 * @brief Read a value in SWPMI register
213 * @param __INSTANCE__ SWPMI Instance
214 * @param __REG__ Register to be read
215 * @retval Register value
216 */
217 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
218 /**
219 * @}
220 */
221
222 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
223 * @{
224 */
225
226 /**
227 * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
228 * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
229 * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
230 * @param __FSWPCLK__ PCLK or HSI frequency (in Hz)
231 * @retval Bitrate prescaler (BRR register)
232 */
233 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
234
235 /**
236 * @}
237 */
238
239 /**
240 * @}
241 */
242
243 /* Exported functions --------------------------------------------------------*/
244 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
245 * @{
246 */
247
248 /** @defgroup SWPMI_LL_EF_Configuration Configuration
249 * @{
250 */
251
252 /**
253 * @brief Set Reception buffering mode
254 * @note If Multi software buffer mode is chosen, RXDMA bits must also be set.
255 * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode
256 * @param SWPMIx SWPMI Instance
257 * @param RxBufferingMode This parameter can be one of the following values:
258 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
259 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
260 * @retval None
261 */
LL_SWPMI_SetReceptionMode(SWPMI_TypeDef * SWPMIx,uint32_t RxBufferingMode)262 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
263 {
264 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
265 }
266
267 /**
268 * @brief Get Reception buffering mode
269 * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode
270 * @param SWPMIx SWPMI Instance
271 * @retval Returned value can be one of the following values:
272 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
273 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
274 */
LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef * SWPMIx)275 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef *SWPMIx)
276 {
277 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
278 }
279
280 /**
281 * @brief Set Transmission buffering mode
282 * @note If Multi software buffer mode is chosen, TXDMA bits must also be set.
283 * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode
284 * @param SWPMIx SWPMI Instance
285 * @param TxBufferingMode This parameter can be one of the following values:
286 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
287 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
288 * @retval None
289 */
LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef * SWPMIx,uint32_t TxBufferingMode)290 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
291 {
292 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
293 }
294
295 /**
296 * @brief Get Transmission buffering mode
297 * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode
298 * @param SWPMIx SWPMI Instance
299 * @retval Returned value can be one of the following values:
300 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
301 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
302 */
LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef * SWPMIx)303 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef *SWPMIx)
304 {
305 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
306 }
307
308 /**
309 * @brief Enable loopback mode
310 * @rmtoll CR LPBK LL_SWPMI_EnableLoopback
311 * @param SWPMIx SWPMI Instance
312 * @retval None
313 */
LL_SWPMI_EnableLoopback(SWPMI_TypeDef * SWPMIx)314 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
315 {
316 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
317 }
318
319 /**
320 * @brief Disable loopback mode
321 * @rmtoll CR LPBK LL_SWPMI_DisableLoopback
322 * @param SWPMIx SWPMI Instance
323 * @retval None
324 */
LL_SWPMI_DisableLoopback(SWPMI_TypeDef * SWPMIx)325 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
326 {
327 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
328 }
329
330 /**
331 * @brief Enable SWPMI transceiver
332 * @note SWPMI_IO pin is controlled by SWPMI
333 * @rmtoll CR SWPEN LL_SWPMI_EnableTransceiver
334 * @param SWPMIx SWPMI Instance
335 * @retval None
336 */
LL_SWPMI_EnableTransceiver(SWPMI_TypeDef * SWPMIx)337 __STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)
338 {
339 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
340 }
341
342 /**
343 * @brief Disable SWPMI transceiver
344 * @note SWPMI_IO pin is controlled by GPIO controller
345 * @rmtoll CR SWPEN LL_SWPMI_DisableTransceiver
346 * @param SWPMIx SWPMI Instance
347 * @retval None
348 */
LL_SWPMI_DisableTransceiver(SWPMI_TypeDef * SWPMIx)349 __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)
350 {
351 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);
352 }
353
354 /**
355 * @brief Check if SWPMI transceiver is enabled
356 * @rmtoll CR SWPEN LL_SWPMI_IsEnabledTransceiver
357 * @param SWPMIx SWPMI Instance
358 * @retval State of bit (1 or 0).
359 */
LL_SWPMI_IsEnabledTransceiver(const SWPMI_TypeDef * SWPMIx)360 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(const SWPMI_TypeDef *SWPMIx)
361 {
362 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL);
363 }
364
365 /**
366 * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
367 * @note SWP bus stays in the ACTIVATED state as long as there is a communication
368 * with the slave, either in transmission or in reception. The SWP bus switches back
369 * to the SUSPENDED state as soon as there is no more transmission or reception
370 * activity, after 7 idle bits.
371 * @rmtoll CR SWPACT LL_SWPMI_Activate
372 * @param SWPMIx SWPMI Instance
373 * @retval None
374 */
LL_SWPMI_Activate(SWPMI_TypeDef * SWPMIx)375 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
376 {
377 /* In order to activate SWP again, the software must clear DEACT bit*/
378 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
379
380 /* Set SWACT bit */
381 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
382 }
383
384 /**
385 * @brief Check if Single wire protocol bus is in ACTIVATED state.
386 * @rmtoll CR SWPACT LL_SWPMI_Activate
387 * @param SWPMIx SWPMI Instance
388 * @retval State of bit (1 or 0).
389 */
LL_SWPMI_IsActivated(const SWPMI_TypeDef * SWPMIx)390 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(const SWPMI_TypeDef *SWPMIx)
391 {
392 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);
393 }
394
395 /**
396 * @brief Deactivate immediately Single wire protocol bus (immediate transition to
397 * DEACTIVATED state)
398 * @rmtoll CR SWPACT LL_SWPMI_Deactivate
399 * @param SWPMIx SWPMI Instance
400 * @retval None
401 */
LL_SWPMI_Deactivate(SWPMI_TypeDef * SWPMIx)402 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
403 {
404 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
405 }
406
407 /**
408 * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
409 * state if no resume from slave)
410 * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation
411 * @param SWPMIx SWPMI Instance
412 * @retval None
413 */
LL_SWPMI_RequestDeactivation(SWPMI_TypeDef * SWPMIx)414 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
415 {
416 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
417 }
418
419 /**
420 * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
421 * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler
422 * @param SWPMIx SWPMI Instance
423 * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=255U
424 * @retval None
425 */
LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef * SWPMIx,uint32_t BitRatePrescaler)426 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
427 {
428 WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
429 }
430
431 /**
432 * @brief Get Bitrate prescaler
433 * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler
434 * @param SWPMIx SWPMI Instance
435 * @retval A number between Min_Data=0 and Max_Data=255U
436 */
LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef * SWPMIx)437 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef *SWPMIx)
438 {
439 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
440 }
441
442 /**
443 * @brief Set SWP Voltage Class
444 * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass
445 * @param SWPMIx SWPMI Instance
446 * @param VoltageClass This parameter can be one of the following values:
447 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
448 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
449 * @retval None
450 */
LL_SWPMI_SetVoltageClass(SWPMI_TypeDef * SWPMIx,uint32_t VoltageClass)451 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
452 {
453 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
454 }
455
456 /**
457 * @brief Get SWP Voltage Class
458 * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass
459 * @param SWPMIx SWPMI Instance
460 * @retval Returned value can be one of the following values:
461 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
462 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
463 */
LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef * SWPMIx)464 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef *SWPMIx)
465 {
466 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
467 }
468
469 /**
470 * @}
471 */
472
473 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
474 * @{
475 */
476
477 /**
478 * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR.
479 * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF
480 * @param SWPMIx SWPMI Instance
481 * @retval State of bit (1 or 0).
482 */
LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef * SWPMIx)483 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef *SWPMIx)
484 {
485 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);
486 }
487
488 /**
489 * @brief Check if Frame transmission buffer has been emptied
490 * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE
491 * @param SWPMIx SWPMI Instance
492 * @retval State of bit (1 or 0).
493 */
LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef * SWPMIx)494 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef *SWPMIx)
495 {
496 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);
497 }
498
499 /**
500 * @brief Check if CRC error in reception has been detected
501 * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER
502 * @param SWPMIx SWPMI Instance
503 * @retval State of bit (1 or 0).
504 */
LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef * SWPMIx)505 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef *SWPMIx)
506 {
507 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);
508 }
509
510 /**
511 * @brief Check if Overrun in reception has been detected
512 * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR
513 * @param SWPMIx SWPMI Instance
514 * @retval State of bit (1 or 0).
515 */
LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef * SWPMIx)516 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef *SWPMIx)
517 {
518 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);
519 }
520
521 /**
522 * @brief Check if underrun error in transmission has been detected
523 * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR
524 * @param SWPMIx SWPMI Instance
525 * @retval State of bit (1 or 0).
526 */
LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef * SWPMIx)527 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef *SWPMIx)
528 {
529 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);
530 }
531
532 /**
533 * @brief Check if Receive data register not empty (it means that Received data is ready
534 * to be read in the SWPMI_RDR register)
535 * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE
536 * @param SWPMIx SWPMI Instance
537 * @retval State of bit (1 or 0).
538 */
LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef * SWPMIx)539 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef *SWPMIx)
540 {
541 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);
542 }
543
544 /**
545 * @brief Check if Transmit data register is empty (it means that Data written in transmit
546 * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
547 * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE
548 * @param SWPMIx SWPMI Instance
549 * @retval State of bit (1 or 0).
550 */
LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef * SWPMIx)551 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef *SWPMIx)
552 {
553 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);
554 }
555
556 /**
557 * @brief Check if Both transmission and reception are completed and SWP is switched to
558 * the SUSPENDED state
559 * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC
560 * @param SWPMIx SWPMI Instance
561 * @retval State of bit (1 or 0).
562 */
LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef * SWPMIx)563 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef *SWPMIx)
564 {
565 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);
566 }
567
568 /**
569 * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
570 * state
571 * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR
572 * @param SWPMIx SWPMI Instance
573 * @retval State of bit (1 or 0).
574 */
LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef * SWPMIx)575 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef *SWPMIx)
576 {
577 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);
578 }
579
580 /**
581 * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state
582 * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP
583 * @param SWPMIx SWPMI Instance
584 * @retval State of bit (1 or 0).
585 */
LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef * SWPMIx)586 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef *SWPMIx)
587 {
588 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);
589 }
590
591 /**
592 * @brief Check if SWP bus is in DEACTIVATED state
593 * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT
594 * @param SWPMIx SWPMI Instance
595 * @retval State of bit (1 or 0).
596 */
LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef * SWPMIx)597 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef *SWPMIx)
598 {
599 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);
600 }
601
602 /**
603 * @brief Check if SWPMI transceiver is ready
604 * @rmtoll ISR RDYF LL_SWPMI_IsActiveFlag_RDYF
605 * @param SWPMIx SWPMI Instance
606 * @retval State of bit (1 or 0).
607 */
LL_SWPMI_IsActiveFlag_RDYF(const SWPMI_TypeDef * SWPMIx)608 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(const SWPMI_TypeDef *SWPMIx)
609 {
610 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL);
611 }
612
613 /**
614 * @brief Clear receive buffer full flag
615 * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF
616 * @param SWPMIx SWPMI Instance
617 * @retval None
618 */
LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef * SWPMIx)619 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
620 {
621 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
622 }
623
624 /**
625 * @brief Clear transmit buffer empty flag
626 * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE
627 * @param SWPMIx SWPMI Instance
628 * @retval None
629 */
LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef * SWPMIx)630 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
631 {
632 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
633 }
634
635 /**
636 * @brief Clear receive CRC error flag
637 * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER
638 * @param SWPMIx SWPMI Instance
639 * @retval None
640 */
LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef * SWPMIx)641 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
642 {
643 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
644 }
645
646 /**
647 * @brief Clear receive overrun error flag
648 * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR
649 * @param SWPMIx SWPMI Instance
650 * @retval None
651 */
LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef * SWPMIx)652 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
653 {
654 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
655 }
656
657 /**
658 * @brief Clear transmit underrun error flag
659 * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR
660 * @param SWPMIx SWPMI Instance
661 * @retval None
662 */
LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef * SWPMIx)663 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
664 {
665 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
666 }
667
668 /**
669 * @brief Clear transfer complete flag
670 * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC
671 * @param SWPMIx SWPMI Instance
672 * @retval None
673 */
LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef * SWPMIx)674 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
675 {
676 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
677 }
678
679 /**
680 * @brief Clear slave resume flag
681 * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR
682 * @param SWPMIx SWPMI Instance
683 * @retval None
684 */
LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef * SWPMIx)685 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
686 {
687 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
688 }
689
690 /**
691 * @brief Clear SWPMI transceiver ready flag
692 * @rmtoll ISR CRDYF LL_SWPMI_ClearFlag_RDY
693 * @param SWPMIx SWPMI Instance
694 * @retval None
695 */
LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef * SWPMIx)696 __STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)
697 {
698 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF);
699 }
700
701 /**
702 * @}
703 */
704
705 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
706 * @{
707 */
708
709 /**
710 * @brief Enable SWPMI transceiver ready interrupt
711 * @rmtoll IER RDYIE LL_SWPMI_EnableIT_RDY
712 * @param SWPMIx SWPMI Instance
713 * @retval None
714 */
LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef * SWPMIx)715 __STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)
716 {
717 SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
718 }
719
720 /**
721 * @brief Enable Slave resume interrupt
722 * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR
723 * @param SWPMIx SWPMI Instance
724 * @retval None
725 */
LL_SWPMI_EnableIT_SR(SWPMI_TypeDef * SWPMIx)726 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
727 {
728 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
729 }
730
731 /**
732 * @brief Enable Transmit complete interrupt
733 * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC
734 * @param SWPMIx SWPMI Instance
735 * @retval None
736 */
LL_SWPMI_EnableIT_TC(SWPMI_TypeDef * SWPMIx)737 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
738 {
739 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
740 }
741
742 /**
743 * @brief Enable Transmit interrupt
744 * @rmtoll IER TIE LL_SWPMI_EnableIT_TX
745 * @param SWPMIx SWPMI Instance
746 * @retval None
747 */
LL_SWPMI_EnableIT_TX(SWPMI_TypeDef * SWPMIx)748 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
749 {
750 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
751 }
752
753 /**
754 * @brief Enable Receive interrupt
755 * @rmtoll IER RIE LL_SWPMI_EnableIT_RX
756 * @param SWPMIx SWPMI Instance
757 * @retval None
758 */
LL_SWPMI_EnableIT_RX(SWPMI_TypeDef * SWPMIx)759 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
760 {
761 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
762 }
763
764 /**
765 * @brief Enable Transmit underrun error interrupt
766 * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR
767 * @param SWPMIx SWPMI Instance
768 * @retval None
769 */
LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef * SWPMIx)770 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
771 {
772 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
773 }
774
775 /**
776 * @brief Enable Receive overrun error interrupt
777 * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR
778 * @param SWPMIx SWPMI Instance
779 * @retval None
780 */
LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef * SWPMIx)781 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
782 {
783 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
784 }
785
786 /**
787 * @brief Enable Receive CRC error interrupt
788 * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER
789 * @param SWPMIx SWPMI Instance
790 * @retval None
791 */
LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef * SWPMIx)792 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
793 {
794 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
795 }
796
797 /**
798 * @brief Enable Transmit buffer empty interrupt
799 * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE
800 * @param SWPMIx SWPMI Instance
801 * @retval None
802 */
LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef * SWPMIx)803 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
804 {
805 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
806 }
807
808 /**
809 * @brief Enable Receive buffer full interrupt
810 * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF
811 * @param SWPMIx SWPMI Instance
812 * @retval None
813 */
LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef * SWPMIx)814 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
815 {
816 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
817 }
818
819 /**
820 * @brief Disable SWPMI transceiver ready interrupt
821 * @rmtoll IER RDYIE LL_SWPMI_DisableIT_RDY
822 * @param SWPMIx SWPMI Instance
823 * @retval None
824 */
LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef * SWPMIx)825 __STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)
826 {
827 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);
828 }
829
830 /**
831 * @brief Disable Slave resume interrupt
832 * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR
833 * @param SWPMIx SWPMI Instance
834 * @retval None
835 */
LL_SWPMI_DisableIT_SR(SWPMI_TypeDef * SWPMIx)836 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
837 {
838 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
839 }
840
841 /**
842 * @brief Disable Transmit complete interrupt
843 * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC
844 * @param SWPMIx SWPMI Instance
845 * @retval None
846 */
LL_SWPMI_DisableIT_TC(SWPMI_TypeDef * SWPMIx)847 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
848 {
849 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
850 }
851
852 /**
853 * @brief Disable Transmit interrupt
854 * @rmtoll IER TIE LL_SWPMI_DisableIT_TX
855 * @param SWPMIx SWPMI Instance
856 * @retval None
857 */
LL_SWPMI_DisableIT_TX(SWPMI_TypeDef * SWPMIx)858 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
859 {
860 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
861 }
862
863 /**
864 * @brief Disable Receive interrupt
865 * @rmtoll IER RIE LL_SWPMI_DisableIT_RX
866 * @param SWPMIx SWPMI Instance
867 * @retval None
868 */
LL_SWPMI_DisableIT_RX(SWPMI_TypeDef * SWPMIx)869 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
870 {
871 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
872 }
873
874 /**
875 * @brief Disable Transmit underrun error interrupt
876 * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR
877 * @param SWPMIx SWPMI Instance
878 * @retval None
879 */
LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef * SWPMIx)880 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
881 {
882 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
883 }
884
885 /**
886 * @brief Disable Receive overrun error interrupt
887 * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR
888 * @param SWPMIx SWPMI Instance
889 * @retval None
890 */
LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef * SWPMIx)891 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
892 {
893 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
894 }
895
896 /**
897 * @brief Disable Receive CRC error interrupt
898 * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER
899 * @param SWPMIx SWPMI Instance
900 * @retval None
901 */
LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef * SWPMIx)902 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
903 {
904 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
905 }
906
907 /**
908 * @brief Disable Transmit buffer empty interrupt
909 * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE
910 * @param SWPMIx SWPMI Instance
911 * @retval None
912 */
LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef * SWPMIx)913 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
914 {
915 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
916 }
917
918 /**
919 * @brief Disable Receive buffer full interrupt
920 * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF
921 * @param SWPMIx SWPMI Instance
922 * @retval None
923 */
LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef * SWPMIx)924 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
925 {
926 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
927 }
928
929 /**
930 * @brief Check if SWPMI transceiver ready interrupt is enabled
931 * @rmtoll IER RDYIE LL_SWPMI_IsEnabledIT_RDY
932 * @param SWPMIx SWPMI Instance
933 * @retval State of bit (1 or 0).
934 */
LL_SWPMI_IsEnabledIT_RDY(const SWPMI_TypeDef * SWPMIx)935 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(const SWPMI_TypeDef *SWPMIx)
936 {
937 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL);
938 }
939
940 /**
941 * @brief Check if Slave resume interrupt is enabled
942 * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR
943 * @param SWPMIx SWPMI Instance
944 * @retval State of bit (1 or 0).
945 */
LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef * SWPMIx)946 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef *SWPMIx)
947 {
948 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);
949 }
950
951 /**
952 * @brief Check if Transmit complete interrupt is enabled
953 * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC
954 * @param SWPMIx SWPMI Instance
955 * @retval State of bit (1 or 0).
956 */
LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef * SWPMIx)957 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef *SWPMIx)
958 {
959 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);
960 }
961
962 /**
963 * @brief Check if Transmit interrupt is enabled
964 * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX
965 * @param SWPMIx SWPMI Instance
966 * @retval State of bit (1 or 0).
967 */
LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef * SWPMIx)968 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef *SWPMIx)
969 {
970 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);
971 }
972
973 /**
974 * @brief Check if Receive interrupt is enabled
975 * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX
976 * @param SWPMIx SWPMI Instance
977 * @retval State of bit (1 or 0).
978 */
LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef * SWPMIx)979 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef *SWPMIx)
980 {
981 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);
982 }
983
984 /**
985 * @brief Check if Transmit underrun error interrupt is enabled
986 * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR
987 * @param SWPMIx SWPMI Instance
988 * @retval State of bit (1 or 0).
989 */
LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef * SWPMIx)990 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef *SWPMIx)
991 {
992 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);
993 }
994
995 /**
996 * @brief Check if Receive overrun error interrupt is enabled
997 * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR
998 * @param SWPMIx SWPMI Instance
999 * @retval State of bit (1 or 0).
1000 */
LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef * SWPMIx)1001 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef *SWPMIx)
1002 {
1003 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);
1004 }
1005
1006 /**
1007 * @brief Check if Receive CRC error interrupt is enabled
1008 * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER
1009 * @param SWPMIx SWPMI Instance
1010 * @retval State of bit (1 or 0).
1011 */
LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef * SWPMIx)1012 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef *SWPMIx)
1013 {
1014 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);
1015 }
1016
1017 /**
1018 * @brief Check if Transmit buffer empty interrupt is enabled
1019 * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE
1020 * @param SWPMIx SWPMI Instance
1021 * @retval State of bit (1 or 0).
1022 */
LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef * SWPMIx)1023 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef *SWPMIx)
1024 {
1025 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);
1026 }
1027
1028 /**
1029 * @brief Check if Receive buffer full interrupt is enabled
1030 * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF
1031 * @param SWPMIx SWPMI Instance
1032 * @retval State of bit (1 or 0).
1033 */
LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef * SWPMIx)1034 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef *SWPMIx)
1035 {
1036 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);
1037 }
1038
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
1044 * @{
1045 */
1046
1047 /**
1048 * @brief Enable DMA mode for reception
1049 * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX
1050 * @param SWPMIx SWPMI Instance
1051 * @retval None
1052 */
LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef * SWPMIx)1053 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1054 {
1055 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1056 }
1057
1058 /**
1059 * @brief Disable DMA mode for reception
1060 * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX
1061 * @param SWPMIx SWPMI Instance
1062 * @retval None
1063 */
LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef * SWPMIx)1064 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
1065 {
1066 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
1067 }
1068
1069 /**
1070 * @brief Check if DMA mode for reception is enabled
1071 * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX
1072 * @param SWPMIx SWPMI Instance
1073 * @retval State of bit (1 or 0).
1074 */
LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef * SWPMIx)1075 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef *SWPMIx)
1076 {
1077 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);
1078 }
1079
1080 /**
1081 * @brief Enable DMA mode for transmission
1082 * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX
1083 * @param SWPMIx SWPMI Instance
1084 * @retval None
1085 */
LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef * SWPMIx)1086 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1087 {
1088 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1089 }
1090
1091 /**
1092 * @brief Disable DMA mode for transmission
1093 * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX
1094 * @param SWPMIx SWPMI Instance
1095 * @retval None
1096 */
LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef * SWPMIx)1097 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
1098 {
1099 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
1100 }
1101
1102 /**
1103 * @brief Check if DMA mode for transmission is enabled
1104 * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX
1105 * @param SWPMIx SWPMI Instance
1106 * @retval State of bit (1 or 0).
1107 */
LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef * SWPMIx)1108 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef *SWPMIx)
1109 {
1110 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);
1111 }
1112
1113 /**
1114 * @brief Get the data register address used for DMA transfer
1115 * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n
1116 * RDR RD LL_SWPMI_DMA_GetRegAddr
1117 * @param SWPMIx SWPMI Instance
1118 * @param Direction This parameter can be one of the following values:
1119 * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
1120 * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
1121 * @retval Address of data register
1122 */
LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef * SWPMIx,uint32_t Direction)1123 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef *SWPMIx, uint32_t Direction)
1124 {
1125 uint32_t data_reg_addr;
1126
1127 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
1128 {
1129 /* return address of TDR register */
1130 data_reg_addr = (uint32_t) &(SWPMIx->TDR);
1131 }
1132 else
1133 {
1134 /* return address of RDR register */
1135 data_reg_addr = (uint32_t) &(SWPMIx->RDR);
1136 }
1137
1138 return data_reg_addr;
1139 }
1140
1141 /**
1142 * @}
1143 */
1144
1145 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
1146 * @{
1147 */
1148
1149 /**
1150 * @brief Retrieve number of data bytes present in payload of received frame
1151 * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength
1152 * @param SWPMIx SWPMI Instance
1153 * @retval Value between Min_Data=0x00 and Max_Data=0x1F
1154 */
LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef * SWPMIx)1155 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef *SWPMIx)
1156 {
1157 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
1158 }
1159
1160 /**
1161 * @brief Transmit Data Register
1162 * @rmtoll TDR TD LL_SWPMI_TransmitData32
1163 * @param SWPMIx SWPMI Instance
1164 * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1165 * @retval None
1166 */
LL_SWPMI_TransmitData32(SWPMI_TypeDef * SWPMIx,uint32_t TxData)1167 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
1168 {
1169 WRITE_REG(SWPMIx->TDR, TxData);
1170 }
1171
1172 /**
1173 * @brief Receive Data Register
1174 * @rmtoll RDR RD LL_SWPMI_ReceiveData32
1175 * @param SWPMIx SWPMI Instance
1176 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1177 */
LL_SWPMI_ReceiveData32(SWPMI_TypeDef * SWPMIx)1178 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
1179 {
1180 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
1181 }
1182
1183 /**
1184 * @brief Enable SWP Transceiver Bypass
1185 * @note The external interface for SWPMI is SWPMI_IO
1186 * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
1187 * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass
1188 * @param SWPMIx SWPMI Instance
1189 * @retval None
1190 */
LL_SWPMI_EnableTXBypass(SWPMI_TypeDef * SWPMIx)1191 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
1192 {
1193 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1194 }
1195
1196 /**
1197 * @brief Disable SWP Transceiver Bypass
1198 * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
1199 * function on GPIOs. This configuration is selected to connect an external transceiver
1200 * @note In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared
1201 * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass
1202 * @param SWPMIx SWPMI Instance
1203 * @retval None
1204 */
LL_SWPMI_DisableTXBypass(SWPMI_TypeDef * SWPMIx)1205 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
1206 {
1207 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
1208 }
1209
1210 /**
1211 * @}
1212 */
1213
1214 #if defined(USE_FULL_LL_DRIVER)
1215 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
1216 * @{
1217 */
1218
1219 ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx);
1220 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1221 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
1222
1223 /**
1224 * @}
1225 */
1226 #endif /*USE_FULL_LL_DRIVER*/
1227
1228 /**
1229 * @}
1230 */
1231
1232 /**
1233 * @}
1234 */
1235
1236
1237 /**
1238 * @}
1239 */
1240
1241 #ifdef __cplusplus
1242 }
1243 #endif
1244
1245 #endif /* STM32H7xx_LL_SWPMI_H */
1246
