1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rng.h
4 * @author MCD Application Team
5 * @brief Header file of RNG LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_RNG_H
21 #define STM32H7xx_LL_RNG_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (RNG)
35
36 /** @defgroup RNG_LL RNG
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private defines -----------------------------------------------------------*/
42 /** @defgroup RNG_LL_Private_Defines RNG Private Defines
43 * @{
44 */
45 /* Health test control register information to use in CCM algorithm */
46 #define LL_RNG_HTCFG 0x17590ABCU /*!< Magic number */
47 /**
48 * @}
49 */
50 /* Private variables ---------------------------------------------------------*/
51 /* Private constants ---------------------------------------------------------*/
52 /* Private macros ------------------------------------------------------------*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
57 * @{
58 */
59
60
61 /**
62 * @brief LL RNG Init Structure Definition
63 */
64 typedef struct
65 {
66 uint32_t ClockErrorDetection; /*!< Clock error detection.
67 This parameter can be one value of @ref RNG_LL_CED.
68 This parameter can be modified using unitary
69 functions @ref LL_RNG_EnableClkErrorDetect(). */
70 } LL_RNG_InitTypeDef;
71
72 /**
73 * @}
74 */
75 #endif /* USE_FULL_LL_DRIVER */
76 /* Exported constants --------------------------------------------------------*/
77 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
78 * @{
79 */
80
81 /** @defgroup RNG_LL_CED Clock Error Detection
82 * @{
83 */
84 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
85 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
86 /**
87 * @}
88 */
89
90 #if defined(RNG_CR_CONDRST)
91 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
92 * programmable divider acting on the incoming RNG clock
93 * @{
94 */
95 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
96 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
97 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
98 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
99 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
100 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
101 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
102 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
103 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
104 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
105 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
106 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
107 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
108 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
109 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
110 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
111 /**
112 * @}
113 */
114
115 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration
116 * @{
117 */
118 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/
119 #define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */
120
121 /**
122 * @}
123 */
124
125 #endif /* RNG_CR_CONDRST */
126 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
127 * @brief Flags defines which can be used with LL_RNG_ReadReg function
128 * @{
129 */
130 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
131 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
132 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
133 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
134 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
135 /**
136 * @}
137 */
138
139 /** @defgroup RNG_LL_EC_IT IT Defines
140 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
141 * @{
142 */
143 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
144 /**
145 * @}
146 */
147
148 /**
149 * @}
150 */
151
152 /* Exported macro ------------------------------------------------------------*/
153 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
154 * @{
155 */
156
157 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
158 * @{
159 */
160
161 /**
162 * @brief Write a value in RNG register
163 * @param __INSTANCE__ RNG Instance
164 * @param __REG__ Register to be written
165 * @param __VALUE__ Value to be written in the register
166 * @retval None
167 */
168 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
169
170 /**
171 * @brief Read a value in RNG register
172 * @param __INSTANCE__ RNG Instance
173 * @param __REG__ Register to be read
174 * @retval Register value
175 */
176 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
177 /**
178 * @}
179 */
180
181 /**
182 * @}
183 */
184
185
186 /* Exported functions --------------------------------------------------------*/
187 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
188 * @{
189 */
190 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
191 * @{
192 */
193
194 /**
195 * @brief Enable Random Number Generation
196 * @rmtoll CR RNGEN LL_RNG_Enable
197 * @param RNGx RNG Instance
198 * @retval None
199 */
LL_RNG_Enable(RNG_TypeDef * RNGx)200 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
201 {
202 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
203 }
204
205 /**
206 * @brief Disable Random Number Generation
207 * @rmtoll CR RNGEN LL_RNG_Disable
208 * @param RNGx RNG Instance
209 * @retval None
210 */
LL_RNG_Disable(RNG_TypeDef * RNGx)211 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
212 {
213 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
214 }
215
216 /**
217 * @brief Check if Random Number Generator is enabled
218 * @rmtoll CR RNGEN LL_RNG_IsEnabled
219 * @param RNGx RNG Instance
220 * @retval State of bit (1 or 0).
221 */
LL_RNG_IsEnabled(const RNG_TypeDef * RNGx)222 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
223 {
224 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
225 }
226
227 /**
228 * @brief Enable Clock Error Detection
229 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect
230 * @param RNGx RNG Instance
231 * @retval None
232 */
LL_RNG_EnableClkErrorDetect(RNG_TypeDef * RNGx)233 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
234 {
235 #if defined(RNG_CR_CONDRST)
236 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
237 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
238 #else
239 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
240 #endif /* RNG_CR_CONDRST*/
241 }
242
243 /**
244 * @brief Disable RNG Clock Error Detection
245 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect
246 * @param RNGx RNG Instance
247 * @retval None
248 */
LL_RNG_DisableClkErrorDetect(RNG_TypeDef * RNGx)249 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
250 {
251 #if defined(RNG_CR_CONDRST)
252 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
253 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
254 #else
255 SET_BIT(RNGx->CR, RNG_CR_CED);
256 #endif /* RNG_CR_CONDRST*/
257 }
258
259 /**
260 * @brief Check if RNG Clock Error Detection is enabled
261 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
262 * @param RNGx RNG Instance
263 * @retval State of bit (1 or 0).
264 */
LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef * RNGx)265 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
266 {
267 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
268 }
269
270 #if defined(RNG_CR_CONDRST)
271 /**
272 * @brief Set RNG Conditioning Soft Reset bit
273 * @rmtoll CR CONDRST LL_RNG_EnableCondReset
274 * @param RNGx RNG Instance
275 * @retval None
276 */
LL_RNG_EnableCondReset(RNG_TypeDef * RNGx)277 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
278 {
279 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
280 }
281
282 /**
283 * @brief Reset RNG Conditioning Soft Reset bit
284 * @rmtoll CR CONDRST LL_RNG_DisableCondReset
285 * @param RNGx RNG Instance
286 * @retval None
287 */
LL_RNG_DisableCondReset(RNG_TypeDef * RNGx)288 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
289 {
290 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
291 }
292
293 /**
294 * @brief Check if RNG Conditioning Soft Reset bit is set
295 * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset
296 * @param RNGx RNG Instance
297 * @retval State of bit (1 or 0).
298 */
LL_RNG_IsEnabledCondReset(const RNG_TypeDef * RNGx)299 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
300 {
301 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
302 }
303
304 /**
305 * @brief Enable RNG Config Lock
306 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock
307 * @param RNGx RNG Instance
308 * @retval None
309 */
LL_RNG_ConfigLock(RNG_TypeDef * RNGx)310 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
311 {
312 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
313 }
314
315 /**
316 * @brief Check if RNG Config Lock is enabled
317 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked
318 * @param RNGx RNG Instance
319 * @retval State of bit (1 or 0).
320 */
LL_RNG_IsConfigLocked(const RNG_TypeDef * RNGx)321 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
322 {
323 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
324 }
325
326 /**
327 * @brief Enable NIST Compliance
328 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance
329 * @param RNGx RNG Instance
330 * @retval None
331 */
LL_RNG_EnableNistCompliance(RNG_TypeDef * RNGx)332 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
333 {
334 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
335 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
336 }
337
338 /**
339 * @brief Disable NIST Compliance
340 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance
341 * @param RNGx RNG Instance
342 * @retval None
343 */
LL_RNG_DisableNistCompliance(RNG_TypeDef * RNGx)344 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
345 {
346 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
347 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
348 }
349
350 /**
351 * @brief Check if NIST Compliance is enabled
352 * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance
353 * @param RNGx RNG Instance
354 * @retval State of bit (1 or 0).
355 */
LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef * RNGx)356 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
357 {
358 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
359 }
360
361 /**
362 * @brief Set RNG Config1 Configuration field value
363 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1
364 * @param RNGx RNG Instance
365 * @param Config1 Value between 0 and 0x3F
366 * @retval None
367 */
LL_RNG_SetConfig1(RNG_TypeDef * RNGx,uint32_t Config1)368 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
369 {
370 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
371 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
372 }
373
374 /**
375 * @brief Get RNG Config1 Configuration field value
376 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1
377 * @param RNGx RNG Instance
378 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
379 */
LL_RNG_GetConfig1(const RNG_TypeDef * RNGx)380 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
381 {
382 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
383 }
384
385 /**
386 * @brief Set RNG Config2 Configuration field value
387 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2
388 * @param RNGx RNG Instance
389 * @param Config2 Value between 0 and 0x7
390 * @retval None
391 */
LL_RNG_SetConfig2(RNG_TypeDef * RNGx,uint32_t Config2)392 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
393 {
394 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
395 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
396 }
397
398 /**
399 * @brief Get RNG Config2 Configuration field value
400 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2
401 * @param RNGx RNG Instance
402 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
403 */
LL_RNG_GetConfig2(const RNG_TypeDef * RNGx)404 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
405 {
406 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
407 }
408
409 /**
410 * @brief Set RNG Config3 Configuration field value
411 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3
412 * @param RNGx RNG Instance
413 * @param Config3 Value between 0 and 0xF
414 * @retval None
415 */
LL_RNG_SetConfig3(RNG_TypeDef * RNGx,uint32_t Config3)416 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
417 {
418 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
419 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
420 }
421
422 /**
423 * @brief Get RNG Config3 Configuration field value
424 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3
425 * @param RNGx RNG Instance
426 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
427 */
LL_RNG_GetConfig3(const RNG_TypeDef * RNGx)428 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
429 {
430 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
431 }
432
433 /**
434 * @brief Set RNG Clock divider factor
435 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider
436 * @param RNGx RNG Instance
437 * @param Divider can be one of the following values:
438 * @arg @ref LL_RNG_CLKDIV_BY_1
439 * @arg @ref LL_RNG_CLKDIV_BY_2
440 * @arg @ref LL_RNG_CLKDIV_BY_4
441 * @arg @ref LL_RNG_CLKDIV_BY_8
442 * @arg @ref LL_RNG_CLKDIV_BY_16
443 * @arg @ref LL_RNG_CLKDIV_BY_32
444 * @arg @ref LL_RNG_CLKDIV_BY_64
445 * @arg @ref LL_RNG_CLKDIV_BY_128
446 * @arg @ref LL_RNG_CLKDIV_BY_256
447 * @arg @ref LL_RNG_CLKDIV_BY_512
448 * @arg @ref LL_RNG_CLKDIV_BY_1024
449 * @arg @ref LL_RNG_CLKDIV_BY_2048
450 * @arg @ref LL_RNG_CLKDIV_BY_4096
451 * @arg @ref LL_RNG_CLKDIV_BY_8192
452 * @arg @ref LL_RNG_CLKDIV_BY_16384
453 * @arg @ref LL_RNG_CLKDIV_BY_32768
454 * @retval None
455 */
LL_RNG_SetClockDivider(RNG_TypeDef * RNGx,uint32_t Divider)456 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
457 {
458 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
459 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
460 }
461
462 /**
463 * @brief Get RNG Clock divider factor
464 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider
465 * @param RNGx RNG Instance
466 * @retval Returned value can be one of the following values:
467 * @arg @ref LL_RNG_CLKDIV_BY_1
468 * @arg @ref LL_RNG_CLKDIV_BY_2
469 * @arg @ref LL_RNG_CLKDIV_BY_4
470 * @arg @ref LL_RNG_CLKDIV_BY_8
471 * @arg @ref LL_RNG_CLKDIV_BY_16
472 * @arg @ref LL_RNG_CLKDIV_BY_32
473 * @arg @ref LL_RNG_CLKDIV_BY_64
474 * @arg @ref LL_RNG_CLKDIV_BY_128
475 * @arg @ref LL_RNG_CLKDIV_BY_256
476 * @arg @ref LL_RNG_CLKDIV_BY_512
477 * @arg @ref LL_RNG_CLKDIV_BY_1024
478 * @arg @ref LL_RNG_CLKDIV_BY_2048
479 * @arg @ref LL_RNG_CLKDIV_BY_4096
480 * @arg @ref LL_RNG_CLKDIV_BY_8192
481 * @arg @ref LL_RNG_CLKDIV_BY_16384
482 * @arg @ref LL_RNG_CLKDIV_BY_32768
483 */
LL_RNG_GetClockDivider(const RNG_TypeDef * RNGx)484 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
485 {
486 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
487 }
488 #endif /* RNG_CR_CONDRST */
489 /**
490 * @}
491 */
492
493 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
494 * @{
495 */
496
497 /**
498 * @brief Indicate if the RNG Data ready Flag is set or not
499 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
500 * @param RNGx RNG Instance
501 * @retval State of bit (1 or 0).
502 */
LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef * RNGx)503 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
504 {
505 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
506 }
507
508 /**
509 * @brief Indicate if the Clock Error Current Status Flag is set or not
510 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
511 * @param RNGx RNG Instance
512 * @retval State of bit (1 or 0).
513 */
LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef * RNGx)514 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
515 {
516 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
517 }
518
519 /**
520 * @brief Indicate if the Seed Error Current Status Flag is set or not
521 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
522 * @param RNGx RNG Instance
523 * @retval State of bit (1 or 0).
524 */
LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef * RNGx)525 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
526 {
527 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
528 }
529
530 /**
531 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not
532 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
533 * @param RNGx RNG Instance
534 * @retval State of bit (1 or 0).
535 */
LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef * RNGx)536 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
537 {
538 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
539 }
540
541 /**
542 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not
543 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
544 * @param RNGx RNG Instance
545 * @retval State of bit (1 or 0).
546 */
LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef * RNGx)547 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
548 {
549 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
550 }
551
552 /**
553 * @brief Clear Clock Error interrupt Status (CEIS) Flag
554 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
555 * @param RNGx RNG Instance
556 * @retval None
557 */
LL_RNG_ClearFlag_CEIS(RNG_TypeDef * RNGx)558 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
559 {
560 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
561 }
562
563 /**
564 * @brief Clear Seed Error interrupt Status (SEIS) Flag
565 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
566 * @param RNGx RNG Instance
567 * @retval None
568 */
LL_RNG_ClearFlag_SEIS(RNG_TypeDef * RNGx)569 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
570 {
571 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
572 }
573
574 /**
575 * @}
576 */
577
578 /** @defgroup RNG_LL_EF_IT_Management IT Management
579 * @{
580 */
581
582 /**
583 * @brief Enable Random Number Generator Interrupt
584 * (applies for either Seed error, Clock Error or Data ready interrupts)
585 * @rmtoll CR IE LL_RNG_EnableIT
586 * @param RNGx RNG Instance
587 * @retval None
588 */
LL_RNG_EnableIT(RNG_TypeDef * RNGx)589 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
590 {
591 SET_BIT(RNGx->CR, RNG_CR_IE);
592 }
593
594 /**
595 * @brief Disable Random Number Generator Interrupt
596 * (applies for either Seed error, Clock Error or Data ready interrupts)
597 * @rmtoll CR IE LL_RNG_DisableIT
598 * @param RNGx RNG Instance
599 * @retval None
600 */
LL_RNG_DisableIT(RNG_TypeDef * RNGx)601 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
602 {
603 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
604 }
605
606 /**
607 * @brief Check if Random Number Generator Interrupt is enabled
608 * (applies for either Seed error, Clock Error or Data ready interrupts)
609 * @rmtoll CR IE LL_RNG_IsEnabledIT
610 * @param RNGx RNG Instance
611 * @retval State of bit (1 or 0).
612 */
LL_RNG_IsEnabledIT(const RNG_TypeDef * RNGx)613 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
614 {
615 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
616 }
617
618 /**
619 * @}
620 */
621
622 /** @defgroup RNG_LL_EF_Data_Management Data Management
623 * @{
624 */
625
626 /**
627 * @brief Return32-bit Random Number value
628 * @rmtoll DR RNDATA LL_RNG_ReadRandData32
629 * @param RNGx RNG Instance
630 * @retval Generated 32-bit random value
631 */
LL_RNG_ReadRandData32(const RNG_TypeDef * RNGx)632 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
633 {
634 return (uint32_t)(READ_REG(RNGx->DR));
635 }
636
637 /**
638 * @}
639 */
640
641 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
642 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
643 * @{
644 */
645
646 /**
647 * @brief Set RNG Health Test Control
648 * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig
649 * @param RNGx RNG Instance
650 * @param HTCFG can be values of 32 bits
651 * @retval None
652 */
LL_RNG_SetHealthConfig(RNG_TypeDef * RNGx,uint32_t HTCFG)653 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
654 {
655 /*!< magic number must be written immediately before to RNG_HTCRG */
656 WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
657
658 WRITE_REG(RNGx->HTCR, HTCFG);
659 }
660
661 /**
662 * @brief Get RNG Health Test Control
663 * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig
664 * @param RNGx RNG Instance
665 * @retval Return 32-bit RNG Health Test configuration
666 */
LL_RNG_GetHealthConfig(RNG_TypeDef * RNGx)667 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
668 {
669 /*!< magic number must be written immediately before reading RNG_HTCRG */
670 WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
671
672 return (uint32_t)READ_REG(RNGx->HTCR);
673 }
674
675 /**
676 * @}
677 */
678 #endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */
679 #if defined(USE_FULL_LL_DRIVER)
680 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
681 * @{
682 */
683 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct);
684 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
685 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
686
687 /**
688 * @}
689 */
690 #endif /* USE_FULL_LL_DRIVER */
691
692 /**
693 * @}
694 */
695
696 /**
697 * @}
698 */
699
700 #endif /* RNG */
701
702 /**
703 * @}
704 */
705
706 #ifdef __cplusplus
707 }
708 #endif
709
710 #endif /* __STM32H7xx_LL_RNG_H */
711
712
