1 /**
2   ******************************************************************************
3   * @file    stm32h7xx_ll_dac.h
4   * @author  MCD Application Team
5   * @brief   Header file of DAC LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2017 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_DAC_H
21 #define STM32H7xx_LL_DAC_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29 
30 /** @addtogroup STM32H7xx_LL_Driver
31   * @{
32   */
33 
34 #if defined(DAC1) || defined(DAC2)
35 
36 /** @defgroup DAC_LL DAC
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45   * @{
46   */
47 
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */
51 /* - channel bits position into register SWTRIG                               */
52 /* - channel register offset of data holding register DHRx                    */
53 /* - channel register offset of data output register DORx                     */
54 /* - channel register offset of sample-and-hold sample time register SHSRx    */
55 #define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers
56                                                 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers
58                                                 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60 
61 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64 
65 #define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
67                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
68 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
69                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
70 
71 #define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
72                                                                   DHR12Rx channel 1 (shifted left of 28 bits)   */
73 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
74                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
75 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
76                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
77 
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK\
82                                         | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83 
84 #define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
85 
86 #define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus
87                                                                   DORx channel 2 (shifted left of 5 bits)    */
88 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89 
90 #define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus
92                                                                   SHSRx channel 2 (shifted left of 6 bits)    */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94 
95 
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97                                                                    DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted
99                                                                    to position 0                                    */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted
101                                                                    to position 0                                    */
102 
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           28UL  /* Position of bits register offset of DHR12Rx
104                                                                    channel 1 or 2 versus DHR12Rx channel 1
105                                                                    (shifted left of 28 bits)                   */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx
107                                                                    channel 1 or 2 versus DHR12Rx channel 1
108                                                                    (shifted left of 20 bits)                   */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx
110                                                                    channel 1 or 2 versus DHR12Rx channel 1
111                                                                    (shifted left of 24 bits)                   */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS               5UL  /* Position of bits register offset of DORx
113                                                                    channel 1 or 2 versus DORx channel 1
114                                                                    (shifted left of 5 bits)                    */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS              6UL  /* Position of bits register offset of SHSRx
116                                                                    channel 1 or 2 versus SHSRx channel 1
117                                                                    (shifted left of 6 bits)                    */
118 
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos
123 
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS                  4095UL   /* Full-scale digital value with a resolution of 12
126                                                               bits (voltage range determined by analog voltage
127                                                               references Vref+ and Vref-, refer to reference manual) */
128 
129 /**
130   * @}
131   */
132 
133 
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136   * @{
137   */
138 
139 /**
140   * @brief  Driver macro reserved for internal use: set a pointer to
141   *         a register from a register basis from which an offset
142   *         is applied.
143   * @param  __REG__ Register basis from which the offset is applied.
144   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145   * @retval Pointer to register address
146   */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
148   ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149 
150 /**
151   * @}
152   */
153 
154 
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158   * @{
159   */
160 
161 /**
162   * @brief  Structure definition of some features of DAC instance.
163   */
164 typedef struct
165 {
166   uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel:
167                                              internal (SW start) or from external peripheral
168                                              (timer event, external interrupt line).
169                                              This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170 
171                                              This feature can be modified afterwards using unitary
172                                              function @ref LL_DAC_SetTriggerSource(). */
173 
174   uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
175                                              This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176 
177                                              This feature can be modified afterwards using unitary
178                                              function @ref LL_DAC_SetWaveAutoGeneration(). */
179 
180   uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
181                                              If waveform automatic generation mode is set to noise, this parameter
182                                              can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183                                              If waveform automatic generation mode is set to triangle,
184                                              this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185                                              @note If waveform automatic generation mode is disabled,
186                                               this parameter is discarded.
187 
188                                              This feature can be modified afterwards using unitary
189                                              function @ref LL_DAC_SetWaveNoiseLFSR(),
190                                              @ref LL_DAC_SetWaveTriangleAmplitude()
191                                              depending on the wave automatic generation selected. */
192 
193   uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
194                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195 
196                                              This feature can be modified afterwards using unitary
197                                              function @ref LL_DAC_SetOutputBuffer(). */
198 
199   uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
200                                              This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201 
202                                              This feature can be modified afterwards using unitary
203                                              function @ref LL_DAC_SetOutputConnection(). */
204 
205   uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC
206                                              channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207 
208                                              This feature can be modified afterwards using unitary
209                                              function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211 
212 /**
213   * @}
214   */
215 #endif /* USE_FULL_LL_DRIVER */
216 
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219   * @{
220   */
221 
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223   * @brief    Flags defines which can be used with LL_DAC_ReadReg function
224   * @{
225   */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
230 
231 /* DAC channel 2 flags */
232 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
233 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
234 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
235 
236 /**
237   * @}
238   */
239 
240 /** @defgroup DAC_LL_EC_IT DAC interruptions
241   * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
242   * @{
243   */
244 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
245 
246 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
247 
248 /**
249   * @}
250   */
251 
252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
253   * @{
254   */
255 #define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
256 #define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
257 /**
258   * @}
259   */
260 
261 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
262   * @{
263   */
264 #define LL_DAC_MODE_NORMAL_OPERATION       0x00000000UL            /*!< DAC channel in mode normal operation */
265 #define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
266 /**
267   * @}
268   */
269 
270 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
271   * @{
272   */
273 #define LL_DAC_TRIG_SOFTWARE               0x00000000U                                                         /*!< DAC channel conversion trigger internal (SW start) */
274 #define LL_DAC_TRIG_EXT_TIM1_TRGO          (                                                   DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
275 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (                                  DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
276 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
277 #define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
278 #define LL_DAC_TRIG_EXT_TIM6_TRGO          (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
279 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
280 #define LL_DAC_TRIG_EXT_TIM8_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
281 #define LL_DAC_TRIG_EXT_TIM15_TRGO         (DAC_CR_TSEL1_3                                                   ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
282 #if defined (HRTIM1)
283 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1        (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
284 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
285 #endif /* HRTIM1 */
286 #define LL_DAC_TRIG_EXT_LPTIM1_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
287 #define LL_DAC_TRIG_EXT_LPTIM2_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_2                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
288 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
289 #if defined(TIM23)
290 #define LL_DAC_TRIG_EXT_TIM23_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
291 #endif /* TIM23 */
292 #if defined(TIM24)
293 #define LL_DAC_TRIG_EXT_TIM24_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
294 #endif /* TIM24 */
295 #if defined (DAC2)
296 #define LL_DAC_TRIG_EXT_LPTIM3_OUT         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
297 #endif /* DAC2 */
298 /**
299   * @}
300   */
301 
302 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
303   * @{
304   */
305 #define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */
306 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
307 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
308 /**
309   * @}
310   */
311 
312 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
313   * @{
314   */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
324 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
325 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
326 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
327 /**
328   * @}
329   */
330 
331 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
332   * @{
333   */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
336 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
337 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
338 #define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
339 #define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
340 #define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
341 #define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
342 #define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
343 #define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
344 #define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
345 #define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
346 /**
347   * @}
348   */
349 
350 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
351   * @{
352   */
353 #define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000UL            /*!< The selected DAC channel output is on mode normal. */
354 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
355 /**
356   * @}
357   */
358 
359 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
360   * @{
361   */
362 #define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
363 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
364 /**
365   * @}
366   */
367 
368 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
369   * @{
370   */
371 #define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000UL            /*!< The selected DAC channel output is connected to external pin */
372 #define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
373 /**
374   * @}
375   */
376 
377 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming
378   * @{
379   */
380 #define LL_DAC_TRIGGER_SOFTWARE            (LL_DAC_TRIG_SOFTWARE)
381 #define LL_DAC_TRIGGER_TIM2_TRGO           (LL_DAC_TRIG_EXT_TIM2_TRGO)
382 #define LL_DAC_TRIGGER_TIM4_TRGO           (LL_DAC_TRIG_EXT_TIM4_TRGO)
383 #define LL_DAC_TRIGGER_TIM6_TRGO           (LL_DAC_TRIG_EXT_TIM6_TRGO)
384 #define LL_DAC_TRIGGER_TIM7_TRGO           (LL_DAC_TRIG_EXT_TIM7_TRGO)
385 #define LL_DAC_TRIGGER_TIM8_TRGO           (LL_DAC_TRIG_EXT_TIM8_TRGO)
386 #define LL_DAC_TRIGGER_EXT_IT9             (LL_DAC_TRIG_EXT_EXTI_LINE9)
387 
388 #define LL_DAC_WAVEGENERATION_NONE         (LL_DAC_WAVE_AUTO_GENERATION_NONE)
389 #define LL_DAC_WAVEGENERATION_NOISE        (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
390 #define LL_DAC_WAVEGENERATION_TRIANGLE     (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
391 
392 #define LL_DAC_CONNECT_GPIO                (LL_DAC_OUTPUT_CONNECT_GPIO)
393 #define LL_DAC_CONNECT_INTERNAL            (LL_DAC_OUTPUT_CONNECT_INTERNAL)
394 /**
395   * @}
396   */
397 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
398   * @{
399   */
400 #define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */
401 #define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */
402 /**
403   * @}
404   */
405 
406 /** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
407   * @{
408   */
409 /* List of DAC registers intended to be used (most commonly) with             */
410 /* DMA transfer.                                                              */
411 /* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
412 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
413 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
414 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
415 /**
416   * @}
417   */
418 
419 /** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
420   * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,
421   *         not timeout values.
422   *         For details on delays values, refer to descriptions in source code
423   *         above each literal definition.
424   * @{
425   */
426 
427 /* Delay for DAC channel voltage settling time from DAC channel startup       */
428 /* (transition from disable to enable).                                       */
429 /* Note: DAC channel startup time depends on board application environment:   */
430 /*       impedance connected to DAC channel output.                           */
431 /*       The delay below is specified under conditions:                       */
432 /*        - voltage maximum transition (lowest to highest value)              */
433 /*        - until voltage reaches final value +-1LSB                          */
434 /*        - DAC channel output buffer enabled                                 */
435 /*        - load impedance of 5kOhm (min), 50pF (max)                         */
436 /* Literal set to maximum value (refer to device datasheet,                   */
437 /* parameter "tWAKEUP").                                                      */
438 /* Unit: us                                                                   */
439 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8UL  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
440 
441 /* Delay for DAC channel voltage settling time.                               */
442 /* Note: DAC channel startup time depends on board application environment:   */
443 /*       impedance connected to DAC channel output.                           */
444 /*       The delay below is specified under conditions:                       */
445 /*        - voltage maximum transition (lowest to highest value)              */
446 /*        - until voltage reaches final value +-1LSB                          */
447 /*        - DAC channel output buffer enabled                                 */
448 /*        - load impedance of 5kOhm min, 50pF max                             */
449 /* Literal set to maximum value (refer to device datasheet,                   */
450 /* parameter "tSETTLING").                                                    */
451 /* Unit: us                                                                   */
452 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     3UL /*!< Delay for DAC channel voltage settling time */
453 
454 /**
455   * @}
456   */
457 
458 /**
459   * @}
460   */
461 
462 /* Exported macro ------------------------------------------------------------*/
463 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
464   * @{
465   */
466 
467 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
468   * @{
469   */
470 
471 /**
472   * @brief  Write a value in DAC register
473   * @param  __INSTANCE__ DAC Instance
474   * @param  __REG__ Register to be written
475   * @param  __VALUE__ Value to be written in the register
476   * @retval None
477   */
478 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
479 
480 /**
481   * @brief  Read a value in DAC register
482   * @param  __INSTANCE__ DAC Instance
483   * @param  __REG__ Register to be read
484   * @retval Register value
485   */
486 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
487 
488 /**
489   * @}
490   */
491 
492 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
493   * @{
494   */
495 
496 /**
497   * @brief  Helper macro to get DAC channel number in decimal format
498   *         from literals LL_DAC_CHANNEL_x.
499   *         Example:
500   *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
501   *            will return decimal number "1".
502   * @note   The input can be a value from functions where a channel
503   *         number is returned.
504   * @param  __CHANNEL__ This parameter can be one of the following values:
505   *         @arg @ref LL_DAC_CHANNEL_1
506   *         @arg @ref LL_DAC_CHANNEL_2
507   * @retval 1...2
508   */
509 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
510   ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
511 
512 /**
513   * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
514   *         from number in decimal format.
515   *         Example:
516   *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
517   *           will return a data equivalent to "LL_DAC_CHANNEL_1".
518   * @note  If the input parameter does not correspond to a DAC channel,
519   *        this macro returns value '0'.
520   * @param  __DECIMAL_NB__ 1...2
521   * @retval Returned value can be one of the following values:
522   *         @arg @ref LL_DAC_CHANNEL_1
523   *         @arg @ref LL_DAC_CHANNEL_2
524   */
525 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
526   (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1  ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
527 
528 /**
529   * @brief  Helper macro to define the DAC conversion data full-scale digital
530   *         value corresponding to the selected DAC resolution.
531   * @note   DAC conversion data full-scale corresponds to voltage range
532   *         determined by analog voltage references Vref+ and Vref-
533   *         (refer to reference manual).
534   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
535   *         @arg @ref LL_DAC_RESOLUTION_12B
536   *         @arg @ref LL_DAC_RESOLUTION_8B
537   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
538   */
539 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
540   ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
541 
542 /**
543   * @brief  Helper macro to calculate the DAC conversion data (unit: digital
544   *         value) corresponding to a voltage (unit: mVolt).
545   * @note   This helper macro is intended to provide input data in voltage
546   *         rather than digital value,
547   *         to be used with LL DAC functions such as
548   *         @ref LL_DAC_ConvertData12RightAligned().
549   * @note   Analog reference voltage (Vref+) must be either known from
550   *         user board environment or can be calculated using ADC measurement
551   *         and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
552   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
553   * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
554   *                         (unit: mVolt).
555   * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
556   *         @arg @ref LL_DAC_RESOLUTION_12B
557   *         @arg @ref LL_DAC_RESOLUTION_8B
558   * @retval DAC conversion data (unit: digital value)
559   */
560 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)     \
561   ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                                      \
562    / (__VREFANALOG_VOLTAGE__)                                                                          \
563   )
564 
565 /**
566   * @}
567   */
568 
569 /**
570   * @}
571   */
572 
573 
574 /* Exported functions --------------------------------------------------------*/
575 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
576   * @{
577   */
578 
579 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
580   * @{
581   */
582 
583 /**
584   * @brief  Set the operating mode for the selected DAC channel:
585   *         calibration or normal operating mode.
586   * @rmtoll CR       CEN1           LL_DAC_SetMode\n
587   *         CR       CEN2           LL_DAC_SetMode
588   * @param  DACx DAC instance
589   * @param  DAC_Channel This parameter can be one of the following values:
590   *         @arg @ref LL_DAC_CHANNEL_1
591   *         @arg @ref LL_DAC_CHANNEL_2
592   * @param  ChannelMode This parameter can be one of the following values:
593   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
594   *         @arg @ref LL_DAC_MODE_CALIBRATION
595   * @retval None
596   */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)597 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
598 {
599   MODIFY_REG(DACx->CR,
600              DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
601              ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
602 }
603 
604 /**
605   * @brief  Get the operating mode for the selected DAC channel:
606   *         calibration or normal operating mode.
607   * @rmtoll CR       CEN1           LL_DAC_GetMode\n
608   *         CR       CEN2           LL_DAC_GetMode
609   * @param  DACx DAC instance
610   * @param  DAC_Channel This parameter can be one of the following values:
611   *         @arg @ref LL_DAC_CHANNEL_1
612   *         @arg @ref LL_DAC_CHANNEL_2
613   * @retval Returned value can be one of the following values:
614   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
615   *         @arg @ref LL_DAC_MODE_CALIBRATION
616   */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)617 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
618 {
619   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
620                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
621                    );
622 }
623 
624 /**
625   * @brief  Set the offset trimming value for the selected DAC channel.
626   *         Trimming has an impact when output buffer is enabled
627   *         and is intended to replace factory calibration default values.
628   * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
629   *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
630   * @param  DACx DAC instance
631   * @param  DAC_Channel This parameter can be one of the following values:
632   *         @arg @ref LL_DAC_CHANNEL_1
633   *         @arg @ref LL_DAC_CHANNEL_2
634   * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
635   * @retval None
636   */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)637 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
638 {
639   MODIFY_REG(DACx->CCR,
640              DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
641              TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
642 }
643 
644 /**
645   * @brief  Get the offset trimming value for the selected DAC channel.
646   *         Trimming has an impact when output buffer is enabled
647   *         and is intended to replace factory calibration default values.
648   * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
649   *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
650   * @param  DACx DAC instance
651   * @param  DAC_Channel This parameter can be one of the following values:
652   *         @arg @ref LL_DAC_CHANNEL_1
653   *         @arg @ref LL_DAC_CHANNEL_2
654   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
655   */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)656 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
657 {
658   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
659                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
660                    );
661 }
662 
663 /**
664   * @brief  Set the conversion trigger source for the selected DAC channel.
665   * @note   For conversion trigger source to be effective, DAC trigger
666   *         must be enabled using function @ref LL_DAC_EnableTrigger().
667   * @note   To set conversion trigger source, DAC channel must be disabled.
668   *         Otherwise, the setting is discarded.
669   * @note   Availability of parameters of trigger sources from timer
670   *         depends on timers availability on the selected device.
671   * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
672   *         CR       TSEL2          LL_DAC_SetTriggerSource
673   * @param  DACx DAC instance
674   * @param  DAC_Channel This parameter can be one of the following values:
675   *         @arg @ref LL_DAC_CHANNEL_1
676   *         @arg @ref LL_DAC_CHANNEL_2
677   * @param  TriggerSource This parameter can be one of the following values:
678   *         @arg @ref LL_DAC_TRIG_SOFTWARE
679   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
680   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
681   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
682   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
683   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
684   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
685   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
686   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
687   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1    (1)
688   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2    (1)
689   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
690   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
691   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT     (2)
692   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
693   *         @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO     (3)
694   *         @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO     (4)
695   *
696   *         (1) On this STM32 series, parameter not available on all devices.
697   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
698   *         (2) On this STM32 series, parameter only available on DAC2.
699   *         (3) On this STM32 series, parameter not available on all devices.
700   *          Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
701   *         (4) On this STM32 series, parameter not available on all devices.
702   *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
703   * @retval None
704   */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)705 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
706 {
707   MODIFY_REG(DACx->CR,
708              DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
709              TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
710 }
711 
712 /**
713   * @brief  Get the conversion trigger source for the selected DAC channel.
714   * @note   For conversion trigger source to be effective, DAC trigger
715   *         must be enabled using function @ref LL_DAC_EnableTrigger().
716   * @note   Availability of parameters of trigger sources from timer
717   *         depends on timers availability on the selected device.
718   * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
719   *         CR       TSEL2          LL_DAC_GetTriggerSource
720   * @param  DACx DAC instance
721   * @param  DAC_Channel This parameter can be one of the following values:
722   *         @arg @ref LL_DAC_CHANNEL_1
723   *         @arg @ref LL_DAC_CHANNEL_2
724   * @retval Returned value can be one of the following values:
725   *         @arg @ref LL_DAC_TRIG_SOFTWARE
726   *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
727   *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
728   *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
729   *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
730   *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
731   *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
732   *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
733   *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
734   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1    (1)
735   *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2    (1)
736   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
737   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
738   *         @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT     (2)
739   *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
740   *         @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO     (3)
741   *         @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO     (4)
742   *
743   *         (1) On this STM32 series, parameter not available on all devices.
744   *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
745   *         (2) On this STM32 series, parameter only available on DAC2.
746   *         (3) On this STM32 series, parameter not available on all devices.
747   *          Only available if TIM23 feature is supported (refer to device datasheet for supported features list)
748   *         (4) On this STM32 series, parameter not available on all devices.
749   *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
750   */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)751 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
752 {
753   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
754                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
755                    );
756 }
757 
758 /**
759   * @brief  Set the waveform automatic generation mode
760   *         for the selected DAC channel.
761   * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
762   *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
763   * @param  DACx DAC instance
764   * @param  DAC_Channel This parameter can be one of the following values:
765   *         @arg @ref LL_DAC_CHANNEL_1
766   *         @arg @ref LL_DAC_CHANNEL_2
767   * @param  WaveAutoGeneration This parameter can be one of the following values:
768   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
769   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
770   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
771   * @retval None
772   */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)773 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
774 {
775   MODIFY_REG(DACx->CR,
776              DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
777              WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
778 }
779 
780 /**
781   * @brief  Get the waveform automatic generation mode
782   *         for the selected DAC channel.
783   * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
784   *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
785   * @param  DACx DAC instance
786   * @param  DAC_Channel This parameter can be one of the following values:
787   *         @arg @ref LL_DAC_CHANNEL_1
788   *         @arg @ref LL_DAC_CHANNEL_2
789   * @retval Returned value can be one of the following values:
790   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
791   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
792   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
793   */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)794 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
795 {
796   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
797                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
798                    );
799 }
800 
801 /**
802   * @brief  Set the noise waveform generation for the selected DAC channel:
803   *         Noise mode and parameters LFSR (linear feedback shift register).
804   * @note   For wave generation to be effective, DAC channel
805   *         wave generation mode must be enabled using
806   *         function @ref LL_DAC_SetWaveAutoGeneration().
807   * @note   This setting can be set when the selected DAC channel is disabled
808   *         (otherwise, the setting operation is ignored).
809   * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
810   *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
811   * @param  DACx DAC instance
812   * @param  DAC_Channel This parameter can be one of the following values:
813   *         @arg @ref LL_DAC_CHANNEL_1
814   *         @arg @ref LL_DAC_CHANNEL_2
815   * @param  NoiseLFSRMask This parameter can be one of the following values:
816   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
817   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
818   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
819   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
820   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
821   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
822   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
823   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
824   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
825   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
826   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
827   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
828   * @retval None
829   */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)830 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
831 {
832   MODIFY_REG(DACx->CR,
833              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
834              NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
835 }
836 
837 /**
838   * @brief  Get the noise waveform generation for the selected DAC channel:
839   *         Noise mode and parameters LFSR (linear feedback shift register).
840   * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
841   *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
842   * @param  DACx DAC instance
843   * @param  DAC_Channel This parameter can be one of the following values:
844   *         @arg @ref LL_DAC_CHANNEL_1
845   *         @arg @ref LL_DAC_CHANNEL_2
846   * @retval Returned value can be one of the following values:
847   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
848   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
849   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
850   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
851   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
852   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
853   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
854   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
855   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
856   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
857   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
858   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
859   */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)860 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
861 {
862   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
863                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
864                    );
865 }
866 
867 /**
868   * @brief  Set the triangle waveform generation for the selected DAC channel:
869   *         triangle mode and amplitude.
870   * @note   For wave generation to be effective, DAC channel
871   *         wave generation mode must be enabled using
872   *         function @ref LL_DAC_SetWaveAutoGeneration().
873   * @note   This setting can be set when the selected DAC channel is disabled
874   *         (otherwise, the setting operation is ignored).
875   * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
876   *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
877   * @param  DACx DAC instance
878   * @param  DAC_Channel This parameter can be one of the following values:
879   *         @arg @ref LL_DAC_CHANNEL_1
880   *         @arg @ref LL_DAC_CHANNEL_2
881   * @param  TriangleAmplitude This parameter can be one of the following values:
882   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
883   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
884   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
885   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
886   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
887   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
888   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
889   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
890   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
891   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
892   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
893   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
894   * @retval None
895   */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)896 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
897                                                      uint32_t TriangleAmplitude)
898 {
899   MODIFY_REG(DACx->CR,
900              DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
901              TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
902 }
903 
904 /**
905   * @brief  Get the triangle waveform generation for the selected DAC channel:
906   *         triangle mode and amplitude.
907   * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
908   *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
909   * @param  DACx DAC instance
910   * @param  DAC_Channel This parameter can be one of the following values:
911   *         @arg @ref LL_DAC_CHANNEL_1
912   *         @arg @ref LL_DAC_CHANNEL_2
913   * @retval Returned value can be one of the following values:
914   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
915   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
916   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
917   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
918   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
919   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
920   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
921   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
922   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
923   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
924   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
925   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
926   */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)927 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
928 {
929   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
930                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
931                    );
932 }
933 
934 /**
935   * @brief  Set the output for the selected DAC channel.
936   * @note   This function set several features:
937   *         - mode normal or sample-and-hold
938   *         - buffer
939   *         - connection to GPIO or internal path.
940   *         These features can also be set individually using
941   *         dedicated functions:
942   *         - @ref LL_DAC_SetOutputBuffer()
943   *         - @ref LL_DAC_SetOutputMode()
944   *         - @ref LL_DAC_SetOutputConnection()
945   * @note   On this STM32 series, output connection depends on output mode
946   *         (normal or sample and hold) and output buffer state.
947   *         - if output connection is set to internal path and output buffer
948   *           is enabled (whatever output mode):
949   *           output connection is also connected to GPIO pin
950   *           (both connections to GPIO pin and internal path).
951   *         - if output connection is set to GPIO pin, output buffer
952   *           is disabled, output mode set to sample and hold:
953   *           output connection is also connected to internal path
954   *           (both connections to GPIO pin and internal path).
955   * @note   Mode sample-and-hold requires an external capacitor
956   *         to be connected between DAC channel output and ground.
957   *         Capacitor value depends on load on DAC channel output and
958   *         sample-and-hold timings configured.
959   *         As indication, capacitor typical value is 100nF
960   *         (refer to device datasheet, parameter "CSH").
961   * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
962   *         CR       MODE2          LL_DAC_ConfigOutput
963   * @param  DACx DAC instance
964   * @param  DAC_Channel This parameter can be one of the following values:
965   *         @arg @ref LL_DAC_CHANNEL_1
966   *         @arg @ref LL_DAC_CHANNEL_2
967   * @param  OutputMode This parameter can be one of the following values:
968   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
969   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
970   * @param  OutputBuffer This parameter can be one of the following values:
971   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
972   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
973   * @param  OutputConnection This parameter can be one of the following values:
974   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
975   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
976   * @retval None
977   */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)978 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
979                                          uint32_t OutputBuffer, uint32_t OutputConnection)
980 {
981   MODIFY_REG(DACx->MCR,
982              (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
983              (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
984 }
985 
986 /**
987   * @brief  Set the output mode normal or sample-and-hold
988   *         for the selected DAC channel.
989   * @note   Mode sample-and-hold requires an external capacitor
990   *         to be connected between DAC channel output and ground.
991   *         Capacitor value depends on load on DAC channel output and
992   *         sample-and-hold timings configured.
993   *         As indication, capacitor typical value is 100nF
994   *         (refer to device datasheet, parameter "CSH").
995   * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
996   *         CR       MODE2          LL_DAC_SetOutputMode
997   * @param  DACx DAC instance
998   * @param  DAC_Channel This parameter can be one of the following values:
999   *         @arg @ref LL_DAC_CHANNEL_1
1000   *         @arg @ref LL_DAC_CHANNEL_2
1001   * @param  OutputMode This parameter can be one of the following values:
1002   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1003   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1004   * @retval None
1005   */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)1006 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1007 {
1008   MODIFY_REG(DACx->MCR,
1009              (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1010              OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1011 }
1012 
1013 /**
1014   * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
1015   * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
1016   *         CR       MODE2          LL_DAC_GetOutputMode
1017   * @param  DACx DAC instance
1018   * @param  DAC_Channel This parameter can be one of the following values:
1019   *         @arg @ref LL_DAC_CHANNEL_1
1020   *         @arg @ref LL_DAC_CHANNEL_2
1021   * @retval Returned value can be one of the following values:
1022   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1023   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1024   */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1025 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1026 {
1027   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1028                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1029                    );
1030 }
1031 
1032 /**
1033   * @brief  Set the output buffer for the selected DAC channel.
1034   * @note   On this STM32 series, when buffer is enabled, its offset can be
1035   *         trimmed: factory calibration default values can be
1036   *         replaced by user trimming values, using function
1037   *         @ref LL_DAC_SetTrimmingValue().
1038   * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
1039   *         CR       MODE2          LL_DAC_SetOutputBuffer
1040   * @param  DACx DAC instance
1041   * @param  DAC_Channel This parameter can be one of the following values:
1042   *         @arg @ref LL_DAC_CHANNEL_1
1043   *         @arg @ref LL_DAC_CHANNEL_2
1044   * @param  OutputBuffer This parameter can be one of the following values:
1045   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1046   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1047   * @retval None
1048   */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)1049 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1050 {
1051   MODIFY_REG(DACx->MCR,
1052              (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1053              OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1054 }
1055 
1056 /**
1057   * @brief  Get the output buffer state for the selected DAC channel.
1058   * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
1059   *         CR       MODE2          LL_DAC_GetOutputBuffer
1060   * @param  DACx DAC instance
1061   * @param  DAC_Channel This parameter can be one of the following values:
1062   *         @arg @ref LL_DAC_CHANNEL_1
1063   *         @arg @ref LL_DAC_CHANNEL_2
1064   * @retval Returned value can be one of the following values:
1065   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1066   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1067   */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1068 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1069 {
1070   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1071                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1072                    );
1073 }
1074 
1075 /**
1076   * @brief  Set the output connection for the selected DAC channel.
1077   * @note   On this STM32 series, output connection depends on output mode (normal or
1078   *         sample and hold) and output buffer state.
1079   *         - if output connection is set to internal path and output buffer
1080   *           is enabled (whatever output mode):
1081   *           output connection is also connected to GPIO pin
1082   *           (both connections to GPIO pin and internal path).
1083   *         - if output connection is set to GPIO pin, output buffer
1084   *           is disabled, output mode set to sample and hold:
1085   *           output connection is also connected to internal path
1086   *           (both connections to GPIO pin and internal path).
1087   * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
1088   *         CR       MODE2          LL_DAC_SetOutputConnection
1089   * @param  DACx DAC instance
1090   * @param  DAC_Channel This parameter can be one of the following values:
1091   *         @arg @ref LL_DAC_CHANNEL_1
1092   *         @arg @ref LL_DAC_CHANNEL_2
1093   * @param  OutputConnection This parameter can be one of the following values:
1094   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1095   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1096   * @retval None
1097   */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1098 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1099 {
1100   MODIFY_REG(DACx->MCR,
1101              (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1102              OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1103 }
1104 
1105 /**
1106   * @brief  Get the output connection for the selected DAC channel.
1107   * @note   On this STM32 series, output connection depends on output mode (normal or
1108   *         sample and hold) and output buffer state.
1109   *         - if output connection is set to internal path and output buffer
1110   *           is enabled (whatever output mode):
1111   *           output connection is also connected to GPIO pin
1112   *           (both connections to GPIO pin and internal path).
1113   *         - if output connection is set to GPIO pin, output buffer
1114   *           is disabled, output mode set to sample and hold:
1115   *           output connection is also connected to internal path
1116   *           (both connections to GPIO pin and internal path).
1117   * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
1118   *         CR       MODE2          LL_DAC_GetOutputConnection
1119   * @param  DACx DAC instance
1120   * @param  DAC_Channel This parameter can be one of the following values:
1121   *         @arg @ref LL_DAC_CHANNEL_1
1122   *         @arg @ref LL_DAC_CHANNEL_2
1123   * @retval Returned value can be one of the following values:
1124   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1125   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1126   */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1127 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1128 {
1129   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1130                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1131                    );
1132 }
1133 
1134 /**
1135   * @brief  Set the sample-and-hold timing for the selected DAC channel:
1136   *         sample time
1137   * @note   Sample time must be set when DAC channel is disabled
1138   *         or during DAC operation when DAC channel flag BWSTx is reset,
1139   *         otherwise the setting is ignored.
1140   *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1141   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
1142   *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
1143   * @param  DACx DAC instance
1144   * @param  DAC_Channel This parameter can be one of the following values:
1145   *         @arg @ref LL_DAC_CHANNEL_1
1146   *         @arg @ref LL_DAC_CHANNEL_2
1147   * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1148   * @retval None
1149   */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1150 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1151 {
1152   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1153                                              & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1154 
1155   MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1156 }
1157 
1158 /**
1159   * @brief  Get the sample-and-hold timing for the selected DAC channel:
1160   *         sample time
1161   * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
1162   *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
1163   * @param  DACx DAC instance
1164   * @param  DAC_Channel This parameter can be one of the following values:
1165   *         @arg @ref LL_DAC_CHANNEL_1
1166   *         @arg @ref LL_DAC_CHANNEL_2
1167   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1168   */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1169 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1170 {
1171   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1172                                                    & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1173 
1174   return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1175 }
1176 
1177 /**
1178   * @brief  Set the sample-and-hold timing for the selected DAC channel:
1179   *         hold time
1180   * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
1181   *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
1182   * @param  DACx DAC instance
1183   * @param  DAC_Channel This parameter can be one of the following values:
1184   *         @arg @ref LL_DAC_CHANNEL_1
1185   *         @arg @ref LL_DAC_CHANNEL_2
1186   * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1187   * @retval None
1188   */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1189 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1190 {
1191   MODIFY_REG(DACx->SHHR,
1192              DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1193              HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1194 }
1195 
1196 /**
1197   * @brief  Get the sample-and-hold timing for the selected DAC channel:
1198   *         hold time
1199   * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
1200   *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
1201   * @param  DACx DAC instance
1202   * @param  DAC_Channel This parameter can be one of the following values:
1203   *         @arg @ref LL_DAC_CHANNEL_1
1204   *         @arg @ref LL_DAC_CHANNEL_2
1205   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1206   */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1207 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1208 {
1209   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1210                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1211                    );
1212 }
1213 
1214 /**
1215   * @brief  Set the sample-and-hold timing for the selected DAC channel:
1216   *         refresh time
1217   * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
1218   *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
1219   * @param  DACx DAC instance
1220   * @param  DAC_Channel This parameter can be one of the following values:
1221   *         @arg @ref LL_DAC_CHANNEL_1
1222   *         @arg @ref LL_DAC_CHANNEL_2
1223   * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1224   * @retval None
1225   */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1226 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1227 {
1228   MODIFY_REG(DACx->SHRR,
1229              DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1230              RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1231 }
1232 
1233 /**
1234   * @brief  Get the sample-and-hold timing for the selected DAC channel:
1235   *         refresh time
1236   * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
1237   *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
1238   * @param  DACx DAC instance
1239   * @param  DAC_Channel This parameter can be one of the following values:
1240   *         @arg @ref LL_DAC_CHANNEL_1
1241   *         @arg @ref LL_DAC_CHANNEL_2
1242   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1243   */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1244 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1245 {
1246   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1247                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1248                    );
1249 }
1250 
1251 /**
1252   * @}
1253   */
1254 
1255 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1256   * @{
1257   */
1258 
1259 /**
1260   * @brief  Enable DAC DMA transfer request of the selected channel.
1261   * @note   To configure DMA source address (peripheral address),
1262   *         use function @ref LL_DAC_DMA_GetRegAddr().
1263   * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
1264   *         CR       DMAEN2         LL_DAC_EnableDMAReq
1265   * @param  DACx DAC instance
1266   * @param  DAC_Channel This parameter can be one of the following values:
1267   *         @arg @ref LL_DAC_CHANNEL_1
1268   *         @arg @ref LL_DAC_CHANNEL_2
1269   * @retval None
1270   */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1271 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1272 {
1273   SET_BIT(DACx->CR,
1274           DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1275 }
1276 
1277 /**
1278   * @brief  Disable DAC DMA transfer request of the selected channel.
1279   * @note   To configure DMA source address (peripheral address),
1280   *         use function @ref LL_DAC_DMA_GetRegAddr().
1281   * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
1282   *         CR       DMAEN2         LL_DAC_DisableDMAReq
1283   * @param  DACx DAC instance
1284   * @param  DAC_Channel This parameter can be one of the following values:
1285   *         @arg @ref LL_DAC_CHANNEL_1
1286   *         @arg @ref LL_DAC_CHANNEL_2
1287   * @retval None
1288   */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1289 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1290 {
1291   CLEAR_BIT(DACx->CR,
1292             DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1293 }
1294 
1295 /**
1296   * @brief  Get DAC DMA transfer request state of the selected channel.
1297   *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1298   * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
1299   *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
1300   * @param  DACx DAC instance
1301   * @param  DAC_Channel This parameter can be one of the following values:
1302   *         @arg @ref LL_DAC_CHANNEL_1
1303   *         @arg @ref LL_DAC_CHANNEL_2
1304   * @retval State of bit (1 or 0).
1305   */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1306 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1307 {
1308   return ((READ_BIT(DACx->CR,
1309                     DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1310            == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1311 }
1312 
1313 /**
1314   * @brief  Function to help to configure DMA transfer to DAC: retrieve the
1315   *         DAC register address from DAC instance and a list of DAC registers
1316   *         intended to be used (most commonly) with DMA transfer.
1317   * @note   These DAC registers are data holding registers:
1318   *         when DAC conversion is requested, DAC generates a DMA transfer
1319   *         request to have data available in DAC data holding registers.
1320   * @note   This macro is intended to be used with LL DMA driver, refer to
1321   *         function "LL_DMA_ConfigAddresses()".
1322   *         Example:
1323   *           LL_DMA_ConfigAddresses(DMA1,
1324   *                                  LL_DMA_CHANNEL_1,
1325   *                                  (uint32_t)&< array or variable >,
1326   *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1327   *                                  LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1328   *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1329   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
1330   *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
1331   *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
1332   *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
1333   *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
1334   *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
1335   * @param  DACx DAC instance
1336   * @param  DAC_Channel This parameter can be one of the following values:
1337   *         @arg @ref LL_DAC_CHANNEL_1
1338   *         @arg @ref LL_DAC_CHANNEL_2
1339   * @param  Register This parameter can be one of the following values:
1340   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1341   *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1342   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1343   * @retval DAC register address
1344   */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1345 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1346 {
1347   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
1348   /* DAC channel selected.                                                    */
1349   return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1350                                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1351 }
1352 /**
1353   * @}
1354   */
1355 
1356 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1357   * @{
1358   */
1359 
1360 /**
1361   * @brief  Enable DAC selected channel.
1362   * @rmtoll CR       EN1            LL_DAC_Enable\n
1363   *         CR       EN2            LL_DAC_Enable
1364   * @note   After enable from off state, DAC channel requires a delay
1365   *         for output voltage to reach accuracy +/- 1 LSB.
1366   *         Refer to device datasheet, parameter "tWAKEUP".
1367   * @param  DACx DAC instance
1368   * @param  DAC_Channel This parameter can be one of the following values:
1369   *         @arg @ref LL_DAC_CHANNEL_1
1370   *         @arg @ref LL_DAC_CHANNEL_2
1371   * @retval None
1372   */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1373 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1374 {
1375   SET_BIT(DACx->CR,
1376           DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1377 }
1378 
1379 /**
1380   * @brief  Disable DAC selected channel.
1381   * @rmtoll CR       EN1            LL_DAC_Disable\n
1382   *         CR       EN2            LL_DAC_Disable
1383   * @param  DACx DAC instance
1384   * @param  DAC_Channel This parameter can be one of the following values:
1385   *         @arg @ref LL_DAC_CHANNEL_1
1386   *         @arg @ref LL_DAC_CHANNEL_2
1387   * @retval None
1388   */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1389 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1390 {
1391   CLEAR_BIT(DACx->CR,
1392             DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1393 }
1394 
1395 /**
1396   * @brief  Get DAC enable state of the selected channel.
1397   *         (0: DAC channel is disabled, 1: DAC channel is enabled)
1398   * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
1399   *         CR       EN2            LL_DAC_IsEnabled
1400   * @param  DACx DAC instance
1401   * @param  DAC_Channel This parameter can be one of the following values:
1402   *         @arg @ref LL_DAC_CHANNEL_1
1403   *         @arg @ref LL_DAC_CHANNEL_2
1404   * @retval State of bit (1 or 0).
1405   */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1406 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1407 {
1408   return ((READ_BIT(DACx->CR,
1409                     DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1410            == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1411 }
1412 
1413 /**
1414   * @brief  Enable DAC trigger of the selected channel.
1415   * @note   - If DAC trigger is disabled, DAC conversion is performed
1416   *           automatically once the data holding register is updated,
1417   *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1418   *           @ref LL_DAC_ConvertData12RightAligned(), ...
1419   *         - If DAC trigger is enabled, DAC conversion is performed
1420   *           only when a hardware of software trigger event is occurring.
1421   *           Select trigger source using
1422   *           function @ref LL_DAC_SetTriggerSource().
1423   * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
1424   *         CR       TEN2           LL_DAC_EnableTrigger
1425   * @param  DACx DAC instance
1426   * @param  DAC_Channel This parameter can be one of the following values:
1427   *         @arg @ref LL_DAC_CHANNEL_1
1428   *         @arg @ref LL_DAC_CHANNEL_2
1429   * @retval None
1430   */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1431 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1432 {
1433   SET_BIT(DACx->CR,
1434           DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1435 }
1436 
1437 /**
1438   * @brief  Disable DAC trigger of the selected channel.
1439   * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
1440   *         CR       TEN2           LL_DAC_DisableTrigger
1441   * @param  DACx DAC instance
1442   * @param  DAC_Channel This parameter can be one of the following values:
1443   *         @arg @ref LL_DAC_CHANNEL_1
1444   *         @arg @ref LL_DAC_CHANNEL_2
1445   * @retval None
1446   */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1447 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1448 {
1449   CLEAR_BIT(DACx->CR,
1450             DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1451 }
1452 
1453 /**
1454   * @brief  Get DAC trigger state of the selected channel.
1455   *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1456   * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
1457   *         CR       TEN2           LL_DAC_IsTriggerEnabled
1458   * @param  DACx DAC instance
1459   * @param  DAC_Channel This parameter can be one of the following values:
1460   *         @arg @ref LL_DAC_CHANNEL_1
1461   *         @arg @ref LL_DAC_CHANNEL_2
1462   * @retval State of bit (1 or 0).
1463   */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1464 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1465 {
1466   return ((READ_BIT(DACx->CR,
1467                     DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1468            == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1469 }
1470 
1471 /**
1472   * @brief  Trig DAC conversion by software for the selected DAC channel.
1473   * @note   Preliminarily, DAC trigger must be set to software trigger
1474   *         using function
1475   *           @ref LL_DAC_Init()
1476   *           @ref LL_DAC_SetTriggerSource()
1477   *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
1478   *         and DAC trigger must be enabled using
1479   *         function @ref LL_DAC_EnableTrigger().
1480   * @note   For devices featuring DAC with 2 channels: this function
1481   *         can perform a SW start of both DAC channels simultaneously.
1482   *         Two channels can be selected as parameter.
1483   *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1484   * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
1485   *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
1486   * @param  DACx DAC instance
1487   * @param  DAC_Channel  This parameter can a combination of the following values:
1488   *         @arg @ref LL_DAC_CHANNEL_1
1489   *         @arg @ref LL_DAC_CHANNEL_2
1490   * @retval None
1491   */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1492 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1493 {
1494   SET_BIT(DACx->SWTRIGR,
1495           (DAC_Channel & DAC_SWTR_CHX_MASK));
1496 }
1497 
1498 /**
1499   * @brief  Set the data to be loaded in the data holding register
1500   *         in format 12 bits left alignment (LSB aligned on bit 0),
1501   *         for the selected DAC channel.
1502   * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
1503   *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
1504   * @param  DACx DAC instance
1505   * @param  DAC_Channel This parameter can be one of the following values:
1506   *         @arg @ref LL_DAC_CHANNEL_1
1507   *         @arg @ref LL_DAC_CHANNEL_2
1508   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
1509   * @retval None
1510   */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1511 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1512 {
1513   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1514                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1515 
1516   MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1517 }
1518 
1519 /**
1520   * @brief  Set the data to be loaded in the data holding register
1521   *         in format 12 bits left alignment (MSB aligned on bit 15),
1522   *         for the selected DAC channel.
1523   * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
1524   *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
1525   * @param  DACx DAC instance
1526   * @param  DAC_Channel This parameter can be one of the following values:
1527   *         @arg @ref LL_DAC_CHANNEL_1
1528   *         @arg @ref LL_DAC_CHANNEL_2
1529   * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
1530   * @retval None
1531   */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1532 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1533 {
1534   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1535                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1536 
1537   MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1538 }
1539 
1540 /**
1541   * @brief  Set the data to be loaded in the data holding register
1542   *         in format 8 bits left alignment (LSB aligned on bit 0),
1543   *         for the selected DAC channel.
1544   * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
1545   *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
1546   * @param  DACx DAC instance
1547   * @param  DAC_Channel This parameter can be one of the following values:
1548   *         @arg @ref LL_DAC_CHANNEL_1
1549   *         @arg @ref LL_DAC_CHANNEL_2
1550   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
1551   * @retval None
1552   */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1553 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1554 {
1555   __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1556                                              & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1557 
1558   MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1559 }
1560 
1561 
1562 /**
1563   * @brief  Set the data to be loaded in the data holding register
1564   *         in format 12 bits left alignment (LSB aligned on bit 0),
1565   *         for both DAC channels.
1566   * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
1567   *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
1568   * @param  DACx DAC instance
1569   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1570   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1571   * @retval None
1572   */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1573 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1574                                                           uint32_t DataChannel2)
1575 {
1576   MODIFY_REG(DACx->DHR12RD,
1577              (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1578              ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1579 }
1580 
1581 /**
1582   * @brief  Set the data to be loaded in the data holding register
1583   *         in format 12 bits left alignment (MSB aligned on bit 15),
1584   *         for both DAC channels.
1585   * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
1586   *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
1587   * @param  DACx DAC instance
1588   * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1589   * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1590   * @retval None
1591   */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1592 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1593                                                          uint32_t DataChannel2)
1594 {
1595   /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
1596   /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
1597   /*       the 4 LSB must be taken into account for the shift value.          */
1598   MODIFY_REG(DACx->DHR12LD,
1599              (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1600              ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1601 }
1602 
1603 /**
1604   * @brief  Set the data to be loaded in the data holding register
1605   *         in format 8 bits left alignment (LSB aligned on bit 0),
1606   *         for both DAC channels.
1607   * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
1608   *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
1609   * @param  DACx DAC instance
1610   * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1611   * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1612   * @retval None
1613   */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1614 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1615                                                          uint32_t DataChannel2)
1616 {
1617   MODIFY_REG(DACx->DHR8RD,
1618              (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1619              ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1620 }
1621 
1622 
1623 /**
1624   * @brief  Retrieve output data currently generated for the selected DAC channel.
1625   * @note   Whatever alignment and resolution settings
1626   *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1627   *         @ref LL_DAC_ConvertData12RightAligned(), ...),
1628   *         output data format is 12 bits right aligned (LSB aligned on bit 0).
1629   * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
1630   *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
1631   * @param  DACx DAC instance
1632   * @param  DAC_Channel This parameter can be one of the following values:
1633   *         @arg @ref LL_DAC_CHANNEL_1
1634   *         @arg @ref LL_DAC_CHANNEL_2
1635   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1636   */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1637 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1638 {
1639   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1640                                                    & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1641 
1642   return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1643 }
1644 
1645 /**
1646   * @}
1647   */
1648 
1649 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1650   * @{
1651   */
1652 
1653 /**
1654   * @brief  Get DAC calibration offset flag for DAC channel 1
1655   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
1656   * @param  DACx DAC instance
1657   * @retval State of bit (1 or 0).
1658   */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1659 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1660 {
1661   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1662 }
1663 
1664 
1665 /**
1666   * @brief  Get DAC calibration offset flag for DAC channel 2
1667   * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
1668   * @param  DACx DAC instance
1669   * @retval State of bit (1 or 0).
1670   */
LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef * DACx)1671 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
1672 {
1673   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1674 }
1675 
1676 
1677 /**
1678   * @brief  Get DAC busy writing sample time flag for DAC channel 1
1679   * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
1680   * @param  DACx DAC instance
1681   * @retval State of bit (1 or 0).
1682   */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1683 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1684 {
1685   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1686 }
1687 
1688 /**
1689   * @brief  Get DAC busy writing sample time flag for DAC channel 2
1690   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
1691   * @param  DACx DAC instance
1692   * @retval State of bit (1 or 0).
1693   */
LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef * DACx)1694 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
1695 {
1696   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1697 }
1698 
1699 
1700 /**
1701   * @brief  Get DAC underrun flag for DAC channel 1
1702   * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
1703   * @param  DACx DAC instance
1704   * @retval State of bit (1 or 0).
1705   */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1706 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1707 {
1708   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1709 }
1710 
1711 
1712 /**
1713   * @brief  Get DAC underrun flag for DAC channel 2
1714   * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
1715   * @param  DACx DAC instance
1716   * @retval State of bit (1 or 0).
1717   */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1718 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1719 {
1720   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1721 }
1722 
1723 
1724 /**
1725   * @brief  Clear DAC underrun flag for DAC channel 1
1726   * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
1727   * @param  DACx DAC instance
1728   * @retval None
1729   */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1730 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1731 {
1732   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1733 }
1734 
1735 
1736 /**
1737   * @brief  Clear DAC underrun flag for DAC channel 2
1738   * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
1739   * @param  DACx DAC instance
1740   * @retval None
1741   */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1742 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1743 {
1744   WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1745 }
1746 
1747 
1748 /**
1749   * @}
1750   */
1751 
1752 /** @defgroup DAC_LL_EF_IT_Management IT management
1753   * @{
1754   */
1755 
1756 /**
1757   * @brief  Enable DMA underrun interrupt for DAC channel 1
1758   * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
1759   * @param  DACx DAC instance
1760   * @retval None
1761   */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1762 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1763 {
1764   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1765 }
1766 
1767 
1768 /**
1769   * @brief  Enable DMA underrun interrupt for DAC channel 2
1770   * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
1771   * @param  DACx DAC instance
1772   * @retval None
1773   */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1774 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1775 {
1776   SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1777 }
1778 
1779 
1780 /**
1781   * @brief  Disable DMA underrun interrupt for DAC channel 1
1782   * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
1783   * @param  DACx DAC instance
1784   * @retval None
1785   */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1786 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1787 {
1788   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1789 }
1790 
1791 
1792 /**
1793   * @brief  Disable DMA underrun interrupt for DAC channel 2
1794   * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
1795   * @param  DACx DAC instance
1796   * @retval None
1797   */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1798 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1799 {
1800   CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1801 }
1802 
1803 
1804 /**
1805   * @brief  Get DMA underrun interrupt for DAC channel 1
1806   * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
1807   * @param  DACx DAC instance
1808   * @retval State of bit (1 or 0).
1809   */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1810 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1811 {
1812   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1813 }
1814 
1815 
1816 /**
1817   * @brief  Get DMA underrun interrupt for DAC channel 2
1818   * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
1819   * @param  DACx DAC instance
1820   * @retval State of bit (1 or 0).
1821   */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)1822 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1823 {
1824   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1825 }
1826 
1827 
1828 /**
1829   * @}
1830   */
1831 
1832 #if defined(USE_FULL_LL_DRIVER)
1833 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1834   * @{
1835   */
1836 
1837 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1838 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1839 void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1840 
1841 /**
1842   * @}
1843   */
1844 #endif /* USE_FULL_LL_DRIVER */
1845 
1846 /**
1847   * @}
1848   */
1849 
1850 /**
1851   * @}
1852   */
1853 
1854 #endif /* DAC1 || DAC2 */
1855 
1856 /**
1857   * @}
1858   */
1859 
1860 #ifdef __cplusplus
1861 }
1862 #endif
1863 
1864 #endif /* STM32H7xx_LL_DAC_H */
1865