1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_OSPI_H 21 #define STM32H7xx_HAL_OSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7xx_hal_def.h" 29 30 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 31 32 /** @addtogroup STM32H7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup OSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup OSPI_Exported_Types OSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief OSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 51 indicating that data are available in reception or free place 52 is available in transmission. 53 This parameter can be a value between 1 and 32 */ 54 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 55 quad mode on two different devices to increase the throughput. 56 This parameter can be a value of @ref OSPI_DualQuad */ 57 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 58 This parameter can be a value of @ref OSPI_MemoryType */ 59 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 60 it corresponds to the number of address bits required to access 61 the external device. 62 This parameter can be a value between 1 and 32 */ 63 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 64 must remain high between commands. 65 This parameter can be a value between 1 and 8 */ 66 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 67 This parameter can be a value of @ref OSPI_FreeRunningClock */ 68 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 69 This parameter can be a value of @ref OSPI_ClockMode */ 70 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 71 This parameter can be a value of @ref OSPI_WrapSize */ 72 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 73 the external clock based on the AHB clock. 74 This parameter can be a value between 1 and 256 */ 75 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 76 to take in account external signal delays. 77 This parameter can be a value of @ref OSPI_SampleShifting */ 78 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 79 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 80 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 81 defines the boundary of bytes to release the chip select. 82 This parameter can be a value between 0 and 31 */ 83 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 84 by the delay block. 85 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 86 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 87 released every MaxTran+1 bytes when the other OctoSPI request the access 88 to the bus. 89 This parameter can be a value between 0 and 255 */ 90 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 91 Refresh+1 clock cycles. 92 This parameter can be a value between 0 and 0xFFFFFFFF */ 93 } OSPI_InitTypeDef; 94 95 /** 96 * @brief HAL OSPI Handle Structure definition 97 */ 98 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 99 typedef struct __OSPI_HandleTypeDef 100 #else 101 typedef struct 102 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 103 { 104 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 105 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 106 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 107 __IO uint32_t XferSize; /*!< Number of data to transfer */ 108 __IO uint32_t XferCount; /*!< Counter of data transferred */ 109 MDMA_HandleTypeDef *hmdma; /*!< Handle of the MDMA channel used for the transfer */ 110 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 111 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 112 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 113 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 114 void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi); 115 void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 116 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 117 void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 118 void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 119 void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 120 void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 121 void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 122 void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi); 123 void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi); 124 125 void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi); 126 void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi); 127 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 128 } OSPI_HandleTypeDef; 129 130 /** 131 * @brief HAL OSPI Regular Command Structure definition 132 */ 133 typedef struct 134 { 135 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 136 to the registers for the write operation (these registers are only 137 used for memory-mapped mode). 138 This parameter can be a value of @ref OSPI_OperationType */ 139 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 140 applies only if Dualquad is disabled in the initialization structure). 141 This parameter can be a value of @ref OSPI_FlashID */ 142 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 143 This parameter can be a value between 0 and 0xFFFFFFFF */ 144 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 145 This parameter can be a value of @ref OSPI_InstructionMode */ 146 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 147 This parameter can be a value of @ref OSPI_InstructionSize */ 148 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 149 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 150 uint32_t Address; /*!< It contains the address to be sent to the device. 151 This parameter can be a value between 0 and 0xFFFFFFFF */ 152 uint32_t AddressMode; /*!< It indicates the mode of the address. 153 This parameter can be a value of @ref OSPI_AddressMode */ 154 uint32_t AddressSize; /*!< It indicates the size of the address. 155 This parameter can be a value of @ref OSPI_AddressSize */ 156 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 157 This parameter can be a value of @ref OSPI_AddressDtrMode */ 158 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 159 This parameter can be a value between 0 and 0xFFFFFFFF */ 160 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 161 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 162 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 163 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 164 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 165 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 166 uint32_t DataMode; /*!< It indicates the mode of the data. 167 This parameter can be a value of @ref OSPI_DataMode */ 168 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 169 This field is only used for indirect mode. 170 This parameter can be a value between 1 and 0xFFFFFFFF */ 171 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 172 This parameter can be a value of @ref OSPI_DataDtrMode */ 173 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 174 This parameter can be a value between 0 and 31 */ 175 uint32_t DQSMode; /*!< It enables or not the data strobe management. 176 This parameter can be a value of @ref OSPI_DQSMode */ 177 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 178 This parameter can be a value of @ref OSPI_SIOOMode */ 179 } OSPI_RegularCmdTypeDef; 180 181 /** 182 * @brief HAL OSPI Hyperbus Configuration Structure definition 183 */ 184 typedef struct 185 { 186 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 187 This parameter can be a value between 0 and 255 */ 188 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 189 This parameter can be a value between 0 and 255 */ 190 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 191 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 192 uint32_t LatencyMode; /*!< It configures the latency mode. 193 This parameter can be a value of @ref OSPI_LatencyMode */ 194 } OSPI_HyperbusCfgTypeDef; 195 196 /** 197 * @brief HAL OSPI Hyperbus Command Structure definition 198 */ 199 typedef struct 200 { 201 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 202 This parameter can be a value of @ref OSPI_AddressSpace */ 203 uint32_t Address; /*!< It contains the address to be sent tot he device. 204 This parameter can be a value between 0 and 0xFFFFFFFF */ 205 uint32_t AddressSize; /*!< It indicates the size of the address. 206 This parameter can be a value of @ref OSPI_AddressSize */ 207 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 208 This field is only used for indirect mode. 209 This parameter can be a value between 1 and 0xFFFFFFFF 210 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 211 uint32_t DQSMode; /*!< It enables or not the data strobe management. 212 This parameter can be a value of @ref OSPI_DQSMode */ 213 } OSPI_HyperbusCmdTypeDef; 214 215 /** 216 * @brief HAL OSPI Auto Polling mode configuration structure definition 217 */ 218 typedef struct 219 { 220 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 221 This parameter can be any value between 0 and 0xFFFFFFFF */ 222 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 223 This parameter can be any value between 0 and 0xFFFFFFFF */ 224 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 225 This parameter can be a value of @ref OSPI_MatchMode */ 226 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 227 This parameter can be a value of @ref OSPI_AutomaticStop */ 228 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 229 This parameter can be any value between 0 and 0xFFFF */ 230 } OSPI_AutoPollingTypeDef; 231 232 /** 233 * @brief HAL OSPI Memory Mapped mode configuration structure definition 234 */ 235 typedef struct 236 { 237 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 238 This parameter can be a value of @ref OSPI_TimeOutActivation */ 239 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 240 This parameter can be any value between 0 and 0xFFFF */ 241 } OSPI_MemoryMappedTypeDef; 242 243 /** 244 * @brief HAL OSPI IO Manager Configuration structure definition 245 */ 246 typedef struct 247 { 248 uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. 249 This parameter can be a value between 1 and 8 */ 250 uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. 251 This parameter can be a value between 0 and 8, 0 means that signal not used */ 252 uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. 253 This parameter can be a value between 1 and 8 */ 254 uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 255 This parameter can be a value of @ref OSPIM_IOPort */ 256 uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 257 This parameter can be a value of @ref OSPIM_IOPort */ 258 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected 259 if some signals are multiplexed in the OSPI IO Manager with the other OSPI. 260 This parameter can be a value between 1 and 256 */ 261 } OSPIM_CfgTypeDef; 262 263 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 264 /** 265 * @brief HAL OSPI Callback ID enumeration definition 266 */ 267 typedef enum 268 { 269 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 270 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 271 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 272 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 273 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 274 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 275 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 276 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 277 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 278 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 279 280 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 281 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 282 } HAL_OSPI_CallbackIDTypeDef; 283 284 /** 285 * @brief HAL OSPI Callback pointer definition 286 */ 287 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 288 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 289 /** 290 * @} 291 */ 292 293 /* Exported constants --------------------------------------------------------*/ 294 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 295 * @{ 296 */ 297 298 /** @defgroup OSPI_State OSPI State 299 * @{ 300 */ 301 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 302 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 303 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 304 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 305 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 306 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 307 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 308 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 309 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 310 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 311 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 312 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 313 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 314 /** 315 * @} 316 */ 317 318 /** @defgroup OSPI_ErrorCode OSPI Error Code 319 * @{ 320 */ 321 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 322 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 323 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 324 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 325 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 326 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 327 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 328 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 329 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 330 /** 331 * @} 332 */ 333 334 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 335 * @{ 336 */ 337 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 338 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 339 /** 340 * @} 341 */ 342 343 /** @defgroup OSPI_MemoryType OSPI Memory Type 344 * @{ 345 */ 346 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 347 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 348 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 349 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 350 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 356 * @{ 357 */ 358 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 359 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup OSPI_ClockMode OSPI Clock Mode 365 * @{ 366 */ 367 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 368 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 369 /** 370 * @} 371 */ 372 373 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 374 * @{ 375 */ 376 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 377 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 378 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 379 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 380 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 381 /** 382 * @} 383 */ 384 385 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 386 * @{ 387 */ 388 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 389 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 395 * @{ 396 */ 397 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 398 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 399 /** 400 * @} 401 */ 402 403 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 404 * @{ 405 */ 406 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 407 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup OSPI_OperationType OSPI Operation Type 413 * @{ 414 */ 415 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 416 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 417 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 418 #define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup OSPI_FlashID OSPI Flash Id 424 * @{ 425 */ 426 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 427 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 428 /** 429 * @} 430 */ 431 432 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 433 * @{ 434 */ 435 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 436 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 437 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 438 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 439 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 440 /** 441 * @} 442 */ 443 444 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 445 * @{ 446 */ 447 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 448 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 449 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 450 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 451 /** 452 * @} 453 */ 454 455 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 456 * @{ 457 */ 458 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 459 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup OSPI_AddressMode OSPI Address Mode 465 * @{ 466 */ 467 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 468 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 469 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 470 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 471 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 472 /** 473 * @} 474 */ 475 476 /** @defgroup OSPI_AddressSize OSPI Address Size 477 * @{ 478 */ 479 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 480 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 481 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 482 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 483 /** 484 * @} 485 */ 486 487 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 488 * @{ 489 */ 490 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 491 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 492 /** 493 * @} 494 */ 495 496 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 497 * @{ 498 */ 499 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 500 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 501 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 502 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 503 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 504 /** 505 * @} 506 */ 507 508 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 509 * @{ 510 */ 511 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 512 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 513 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 514 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 515 /** 516 * @} 517 */ 518 519 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 520 * @{ 521 */ 522 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 523 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup OSPI_DataMode OSPI Data Mode 529 * @{ 530 */ 531 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 532 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 533 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 534 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 535 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 541 * @{ 542 */ 543 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 544 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 545 /** 546 * @} 547 */ 548 549 /** @defgroup OSPI_DQSMode OSPI DQS Mode 550 * @{ 551 */ 552 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 553 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 554 /** 555 * @} 556 */ 557 558 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 559 * @{ 560 */ 561 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 562 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 563 /** 564 * @} 565 */ 566 567 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 568 * @{ 569 */ 570 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 571 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 577 * @{ 578 */ 579 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 580 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 586 * @{ 587 */ 588 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 589 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup OSPI_MatchMode OSPI Match Mode 595 * @{ 596 */ 597 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 598 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 599 /** 600 * @} 601 */ 602 603 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 604 * @{ 605 */ 606 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 607 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 613 * @{ 614 */ 615 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 616 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 617 /** 618 * @} 619 */ 620 621 /** @defgroup OSPI_Flags OSPI Flags 622 * @{ 623 */ 624 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 625 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 626 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 627 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 628 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 629 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 630 /** 631 * @} 632 */ 633 634 /** @defgroup OSPI_Interrupts OSPI Interrupts 635 * @{ 636 */ 637 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 638 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 639 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 640 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 641 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 642 /** 643 * @} 644 */ 645 646 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 647 * @{ 648 */ 649 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 650 /** 651 * @} 652 */ 653 654 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port 655 * @{ 656 */ 657 #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ 658 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 659 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 660 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 661 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 662 #define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */ 663 #define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */ 664 #define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */ 665 #define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */ 666 #define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */ 667 #define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */ 668 #define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */ 669 #define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */ 670 #define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */ 671 #define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */ 672 #define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */ 673 #define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */ 674 /** 675 * @} 676 */ 677 /** 678 * @} 679 */ 680 681 /* Exported macros -----------------------------------------------------------*/ 682 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 683 * @{ 684 */ 685 /** @brief Reset OSPI handle state. 686 * @param __HANDLE__ specifies the OSPI Handle. 687 * @retval None 688 */ 689 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 690 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 691 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 692 (__HANDLE__)->MspInitCallback = NULL; \ 693 (__HANDLE__)->MspDeInitCallback = NULL; \ 694 } while(0) 695 #else 696 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 697 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 698 699 /** @brief Enable the OSPI peripheral. 700 * @param __HANDLE__ specifies the OSPI Handle. 701 * @retval None 702 */ 703 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 704 705 /** @brief Disable the OSPI peripheral. 706 * @param __HANDLE__ specifies the OSPI Handle. 707 * @retval None 708 */ 709 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 710 711 /** @brief Enable the specified OSPI interrupt. 712 * @param __HANDLE__ specifies the OSPI Handle. 713 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 714 * This parameter can be one of the following values: 715 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 716 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 717 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 718 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 719 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 720 * @retval None 721 */ 722 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 723 724 725 /** @brief Disable the specified OSPI interrupt. 726 * @param __HANDLE__ specifies the OSPI Handle. 727 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 728 * This parameter can be one of the following values: 729 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 730 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 731 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 732 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 733 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 734 * @retval None 735 */ 736 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 737 738 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 739 * @param __HANDLE__ specifies the OSPI Handle. 740 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 741 * This parameter can be one of the following values: 742 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 743 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 744 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 745 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 746 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 747 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 748 */ 749 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 750 == (__INTERRUPT__)) 751 752 /** 753 * @brief Check whether the selected OSPI flag is set or not. 754 * @param __HANDLE__ specifies the OSPI Handle. 755 * @param __FLAG__ specifies the OSPI flag to check. 756 * This parameter can be one of the following values: 757 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 758 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 759 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 760 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 761 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 762 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 763 * @retval None 764 */ 765 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 766 != 0U) ? SET : RESET) 767 768 /** @brief Clears the specified OSPI's flag status. 769 * @param __HANDLE__ specifies the OSPI Handle. 770 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 771 * This parameter can be one of the following values: 772 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 773 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 774 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 775 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 776 * @retval None 777 */ 778 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 779 780 /** 781 * @} 782 */ 783 784 /* Exported functions --------------------------------------------------------*/ 785 /** @addtogroup OSPI_Exported_Functions 786 * @{ 787 */ 788 789 /* Initialization/de-initialization functions ********************************/ 790 /** @addtogroup OSPI_Exported_Functions_Group1 791 * @{ 792 */ 793 HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); 794 void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi); 795 HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi); 796 void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi); 797 798 /** 799 * @} 800 */ 801 802 /* IO operation functions *****************************************************/ 803 /** @addtogroup OSPI_Exported_Functions_Group2 804 * @{ 805 */ 806 /* OSPI IRQ handler function */ 807 void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi); 808 809 /* OSPI command configuration functions */ 810 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 811 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 812 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 813 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 814 815 /* OSPI indirect mode functions */ 816 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 817 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 818 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 819 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 820 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 821 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 822 823 /* OSPI status flag polling mode functions */ 824 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 825 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 826 827 /* OSPI memory-mapped mode functions */ 828 HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 829 830 /* Callback functions in non-blocking modes ***********************************/ 831 void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi); 832 void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi); 833 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 834 835 /* OSPI indirect mode functions */ 836 void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi); 837 void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi); 838 void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi); 839 void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi); 840 void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi); 841 842 /* OSPI status flag polling mode functions */ 843 void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi); 844 845 /* OSPI memory-mapped mode functions */ 846 void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi); 847 848 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 849 /* OSPI callback registering/unregistering */ 850 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, 851 pOSPI_CallbackTypeDef pCallback); 852 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 853 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 854 /** 855 * @} 856 */ 857 858 /* Peripheral Control and State functions ************************************/ 859 /** @addtogroup OSPI_Exported_Functions_Group3 860 * @{ 861 */ 862 HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); 863 HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi); 864 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold); 865 uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi); 866 HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout); 867 uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi); 868 uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); 869 870 /** 871 * @} 872 */ 873 874 /* OSPI IO Manager configuration function ************************************/ 875 /** @addtogroup OSPI_Exported_Functions_Group4 876 * @{ 877 */ 878 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 879 880 /** 881 * @} 882 */ 883 884 /** 885 * @} 886 */ 887 /* End of exported functions -------------------------------------------------*/ 888 889 /* Private macros ------------------------------------------------------------*/ 890 /** 891 @cond 0 892 */ 893 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 894 895 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 896 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 897 898 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 899 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 900 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 901 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 902 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 903 904 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 905 906 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 907 908 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 909 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 910 911 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 912 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 913 914 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 915 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 916 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 917 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 918 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 919 920 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 921 922 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 923 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 924 925 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 926 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 927 928 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 929 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 930 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \ 931 ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG)) 932 933 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 934 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 935 936 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 937 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 938 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 939 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 940 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 941 942 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 943 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 944 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 945 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 946 947 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 948 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 949 950 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 951 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 952 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 953 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 954 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 955 956 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 957 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 958 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 959 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 960 961 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 962 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 963 964 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 965 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 966 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 967 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 968 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 969 970 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 971 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 972 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 973 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 974 975 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 976 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 977 978 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 979 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 980 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 981 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 982 ((MODE) == HAL_OSPI_DATA_8_LINES)) 983 984 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 985 986 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 987 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 988 989 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 990 991 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 992 ((MODE) == HAL_OSPI_DQS_ENABLE)) 993 994 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 995 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 996 997 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 998 999 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 1000 1001 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 1002 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 1003 1004 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 1005 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 1006 1007 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 1008 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 1009 1010 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 1011 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 1012 1013 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 1014 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 1015 1016 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 1017 1018 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1019 1020 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 1021 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 1022 1023 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1024 1025 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 1026 1027 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ 1028 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) 1029 1030 #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 1031 1032 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 1033 1034 #define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) 1035 1036 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ 1037 ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 1038 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 1039 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 1040 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ 1041 ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \ 1042 ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \ 1043 ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \ 1044 ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \ 1045 ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \ 1046 ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \ 1047 ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \ 1048 ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \ 1049 ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \ 1050 ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \ 1051 ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \ 1052 ((PORT) == HAL_OSPIM_IOPORT_8_HIGH)) 1053 1054 #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 1055 /** 1056 @endcond 1057 */ 1058 1059 /* End of private macros -----------------------------------------------------*/ 1060 1061 /** 1062 * @} 1063 */ 1064 1065 /** 1066 * @} 1067 */ 1068 1069 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1070 1071 #ifdef __cplusplus 1072 } 1073 #endif 1074 1075 #endif /* STM32H7xx_HAL_OSPI_H */ 1076
