1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal_lptim.c
4 * @author MCD Application Team
5 * @brief LPTIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Low Power Timer (LPTIM) peripheral:
8 * + Initialization and de-initialization functions.
9 * + Start/Stop operation functions in polling mode.
10 * + Start/Stop operation functions in interrupt mode.
11 * + Reading operation functions.
12 * + Peripheral State functions.
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2022 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The LPTIM HAL driver can be used as follows:
31
32 (#)Initialize the LPTIM low level resources by implementing the
33 HAL_LPTIM_MspInit():
34 (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE().
35 (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()):
36 (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority().
37 (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ().
38 (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler().
39
40 (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function
41 configures mainly:
42 (++) The instance: LPTIM1, LPTIM2, LPTIM3, LPTIM4 or LPTIM5.
43 (++) Clock: the counter clock.
44 (+++) Source : it can be either the ULPTIM input (IN1) or one of
45 the internal clock; (APB, LSE or LSI).
46 (+++) Prescaler: select the clock divider.
47 (++) UltraLowPowerClock : To be used only if the ULPTIM is selected
48 as counter clock source.
49 (+++) Polarity: polarity of the active edge for the counter unit
50 if the ULPTIM input is selected.
51 (+++) SampleTime: clock sampling time to configure the clock glitch
52 filter.
53 (++) Trigger: How the counter start.
54 (+++) Source: trigger can be software or one of the hardware triggers.
55 (+++) ActiveEdge : only for hardware trigger.
56 (+++) SampleTime : trigger sampling time to configure the trigger
57 glitch filter.
58 (++) OutputPolarity : 2 opposite polarities are possible.
59 (++) UpdateMode: specifies whether the update of the autoreload and
60 the compare values is done immediately or after the end of current
61 period.
62 (++) Input1Source: Source selected for input1 (GPIO or comparator output).
63 (++) Input2Source: Source selected for input2 (GPIO or comparator output).
64 Input2 is used only for encoder feature so is used only for LPTIM1 instance.
65
66 (#)Six modes are available:
67
68 (++) PWM Mode: To generate a PWM signal with specified period and pulse,
69 call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption
70 mode.
71
72 (++) One Pulse Mode: To generate pulse with specified width in response
73 to a stimulus, call HAL_LPTIM_OnePulse_Start() or
74 HAL_LPTIM_OnePulse_Start_IT() for interruption mode.
75
76 (++) Set once Mode: In this mode, the output changes the level (from
77 low level to high level if the output polarity is configured high, else
78 the opposite) when a compare match occurs. To start this mode, call
79 HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for
80 interruption mode.
81
82 (++) Encoder Mode: To use the encoder interface call
83 HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for
84 interruption mode. Only available for LPTIM1 instance.
85
86 (++) Time out Mode: an active edge on one selected trigger input rests
87 the counter. The first trigger event will start the timer, any
88 successive trigger event will reset the counter and the timer will
89 restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or
90 HAL_LPTIM_TimeOut_Start_IT() for interruption mode.
91
92 (++) Counter Mode: counter can be used to count external events on
93 the LPTIM Input1 or it can be used to count internal clock cycles.
94 To start this mode, call HAL_LPTIM_Counter_Start() or
95 HAL_LPTIM_Counter_Start_IT() for interruption mode.
96
97
98 (#) User can stop any process by calling the corresponding API:
99 HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is
100 already started in interruption mode.
101
102 (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit().
103
104 *** Callback registration ***
105 =============================================
106 [..]
107 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
108 allows the user to configure dynamically the driver callbacks.
109 [..]
110 Use Function HAL_LPTIM_RegisterCallback() to register a callback.
111 HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
112 the Callback ID and a pointer to the user callback function.
113 [..]
114 Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
115 default weak function.
116 HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
117 and the Callback ID.
118 [..]
119 These functions allow to register/unregister following callbacks:
120
121 (+) MspInitCallback : LPTIM Base Msp Init Callback.
122 (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback.
123 (+) CompareMatchCallback : Compare match Callback.
124 (+) AutoReloadMatchCallback : Auto-reload match Callback.
125 (+) TriggerCallback : External trigger event detection Callback.
126 (+) CompareWriteCallback : Compare register write complete Callback.
127 (+) AutoReloadWriteCallback : Auto-reload register write complete Callback.
128 (+) DirectionUpCallback : Up-counting direction change Callback.
129 (+) DirectionDownCallback : Down-counting direction change Callback.
130 (+) UpdateEventCallback : Update event detection Callback.
131 (+) RepCounterWriteCallback : Repetition counter register write complete Callback.
132
133 [..]
134 By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
135 all interrupt callbacks are set to the corresponding weak functions:
136 examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
137
138 [..]
139 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
140 functionalities in the Init/DeInit only when these callbacks are null
141 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
142 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
143
144 [..]
145 Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
146 Exception done MspInit/MspDeInit that can be registered/unregistered
147 in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
148 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
149 In that case first register the MspInit/MspDeInit user callbacks
150 using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
151
152 [..]
153 When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
154 not defined, the callback registration feature is not available and all callbacks
155 are set to the corresponding weak functions.
156
157 @endverbatim
158 ******************************************************************************
159 */
160
161 /* Includes ------------------------------------------------------------------*/
162 #include "stm32h7rsxx_hal.h"
163
164 /** @addtogroup STM32H7RSxx_HAL_Driver
165 * @{
166 */
167
168 /** @defgroup LPTIM LPTIM
169 * @brief LPTIM HAL module driver.
170 * @{
171 */
172
173 #ifdef HAL_LPTIM_MODULE_ENABLED
174
175 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
176
177 /* Private typedef -----------------------------------------------------------*/
178 /* Private define ------------------------------------------------------------*/
179 /** @addtogroup LPTIM_Private_Constants
180 * @{
181 */
182 #define TIMEOUT 1000UL /* Timeout is 1s */
183 /**
184 * @}
185 */
186
187 /* Private macro -------------------------------------------------------------*/
188 /** @addtogroup LPTIM_Private_Macros
189 * @{
190 */
191 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
192 (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\
193 ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() :\
194 ((__INSTANCE__) == LPTIM3) ? __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT() :\
195 ((__INSTANCE__) == LPTIM4) ? __HAL_LPTIM_LPTIM4_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM5_EXTI_ENABLE_IT())
196
197 #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
198 (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\
199 ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() :\
200 ((__INSTANCE__) == LPTIM3) ? __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() :\
201 ((__INSTANCE__) == LPTIM4) ? __HAL_LPTIM_LPTIM4_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM5_EXTI_DISABLE_IT())
202 /**
203 * @}
204 */
205
206 /* Private variables ---------------------------------------------------------*/
207 /* Private function prototypes -----------------------------------------------*/
208 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
209 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig);
210 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
211 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig);
212 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
213 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
214 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
215 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
216 void LPTIM_DMAError(DMA_HandleTypeDef *hdma);
217 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
218 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
219 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma);
220 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma);
221 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
222 uint32_t length);
223
224 /* Exported functions --------------------------------------------------------*/
225
226 /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
227 * @{
228 */
229
230 /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
231 * @brief Initialization and Configuration functions.
232 *
233 @verbatim
234 ==============================================================================
235 ##### Initialization and de-initialization functions #####
236 ==============================================================================
237 [..] This section provides functions allowing to:
238 (+) Initialize the LPTIM according to the specified parameters in the
239 LPTIM_InitTypeDef and initialize the associated handle.
240 (+) DeInitialize the LPTIM peripheral.
241 (+) Initialize the LPTIM MSP.
242 (+) DeInitialize the LPTIM MSP.
243
244 @endverbatim
245 * @{
246 */
247
248 /**
249 * @brief Initialize the LPTIM according to the specified parameters in the
250 * LPTIM_InitTypeDef and initialize the associated handle.
251 * @param hlptim LPTIM handle
252 * @retval HAL status
253 */
HAL_LPTIM_Init(LPTIM_HandleTypeDef * hlptim)254 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
255 {
256 uint32_t tmpcfgr;
257
258 /* Check the LPTIM handle allocation */
259 if (hlptim == NULL)
260 {
261 return HAL_ERROR;
262 }
263
264 /* Check the parameters */
265 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
266 assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period));
267
268 assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
269 assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
270 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
271 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
272 {
273 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
274 assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
275 }
276 assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
277 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
278 {
279 assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
280 assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
281 }
282 assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
283 assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
284 assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter));
285
286 if (hlptim->State == HAL_LPTIM_STATE_RESET)
287 {
288 /* Allocate lock resource and initialize it */
289 hlptim->Lock = HAL_UNLOCKED;
290
291 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
292 /* Reset interrupt callbacks to legacy weak callbacks */
293 LPTIM_ResetCallback(hlptim);
294
295 if (hlptim->MspInitCallback == NULL)
296 {
297 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
298 }
299
300 /* Init the low level hardware : GPIO, CLOCK, NVIC */
301 hlptim->MspInitCallback(hlptim);
302 #else
303 /* Init the low level hardware : GPIO, CLOCK, NVIC */
304 HAL_LPTIM_MspInit(hlptim);
305 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
306 }
307
308 /* Change the LPTIM state */
309 hlptim->State = HAL_LPTIM_STATE_BUSY;
310
311 /* Enable the Peripheral */
312 __HAL_LPTIM_ENABLE(hlptim);
313
314 /* Clear flag */
315 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
316
317 /* Set the repetition counter */
318 __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter);
319
320 /* Wait for the completion of the write operation to the LPTIM_RCR register */
321 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT)
322 {
323 return HAL_TIMEOUT;
324 }
325
326
327 /* Clear flag */
328 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
329
330 /* Set LPTIM Period */
331 __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period);
332
333 /* Wait for the completion of the write operation to the LPTIM_ARR register */
334 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
335 {
336 return HAL_TIMEOUT;
337 }
338
339 /* Disable the Peripheral */
340 __HAL_LPTIM_DISABLE(hlptim);
341
342 /* Get the LPTIMx CFGR value */
343 tmpcfgr = hlptim->Instance->CFGR;
344
345 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
346 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
347 {
348 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
349 }
350 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
351 {
352 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
353 }
354
355 /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
356 tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
357 LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
358
359 /* Set initialization parameters */
360 tmpcfgr |= (hlptim->Init.Clock.Source |
361 hlptim->Init.Clock.Prescaler |
362 hlptim->Init.UpdateMode |
363 hlptim->Init.CounterSource);
364
365 /* Glitch filters for internal triggers and external inputs are configured
366 * only if an internal clock source is provided to the LPTIM
367 */
368 if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
369 {
370 tmpcfgr |= (hlptim->Init.Trigger.SampleTime |
371 hlptim->Init.UltraLowPowerClock.SampleTime);
372 }
373
374 /* Configure LPTIM external clock polarity and digital filter */
375 if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
376 || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
377 {
378 tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
379 hlptim->Init.UltraLowPowerClock.SampleTime);
380 }
381
382 /* Configure LPTIM external trigger */
383 if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
384 {
385 /* Enable External trigger and set the trigger source */
386 tmpcfgr |= (hlptim->Init.Trigger.Source |
387 hlptim->Init.Trigger.ActiveEdge |
388 hlptim->Init.Trigger.SampleTime);
389 }
390
391 /* Write to LPTIMx CFGR */
392 hlptim->Instance->CFGR = tmpcfgr;
393
394 /* Configure LPTIM input sources */
395 if ((hlptim->Instance == LPTIM1) || (hlptim->Instance == LPTIM2))
396 {
397 /* Check LPTIM Input1 and Input2 sources */
398 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
399 assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source));
400
401 /* Configure LPTIM Input1 and Input2 sources */
402 hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source);
403 }
404 else
405 {
406 if (hlptim->Instance == LPTIM3)
407 {
408 /* Check LPTIM3 Input1 source */
409 assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
410
411 /* Configure LPTIM3 Input1 source */
412 hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
413 }
414 }
415
416 /* Initialize the LPTIM channels state */
417 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY);
418
419 /* Change the LPTIM state */
420 hlptim->State = HAL_LPTIM_STATE_READY;
421
422 /* Return function status */
423 return HAL_OK;
424 }
425
426 /**
427 * @brief DeInitialize the LPTIM peripheral.
428 * @param hlptim LPTIM handle
429 * @retval HAL status
430 */
HAL_LPTIM_DeInit(LPTIM_HandleTypeDef * hlptim)431 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
432 {
433 /* Check the LPTIM handle allocation */
434 if (hlptim == NULL)
435 {
436 return HAL_ERROR;
437 }
438
439 /* Change the LPTIM state */
440 hlptim->State = HAL_LPTIM_STATE_BUSY;
441
442 __HAL_LPTIM_ENABLE(hlptim);
443 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
444 {
445 hlptim->Instance->CCMR1 = 0;
446 }
447
448 /* Clear flag */
449 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
450
451 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0);
452 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
453 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
454 {
455 return HAL_TIMEOUT;
456 }
457
458 if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance))
459 {
460 /* Clear flag */
461 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
462
463 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0);
464 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
465 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT)
466 {
467 return HAL_TIMEOUT;
468 }
469 }
470
471 /* Clear flag */
472 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
473
474 __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0);
475
476 /* Wait for the completion of the write operation to the LPTIM_ARR register */
477 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
478 {
479 return HAL_TIMEOUT;
480 }
481
482 /* Disable the LPTIM Peripheral Clock */
483 __HAL_LPTIM_DISABLE(hlptim);
484
485 hlptim->Instance->CFGR = 0;
486 hlptim->Instance->CFGR2 = 0;
487
488 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
489 if (hlptim->MspDeInitCallback == NULL)
490 {
491 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
492 }
493
494 /* DeInit the low level hardware: CLOCK, NVIC.*/
495 hlptim->MspDeInitCallback(hlptim);
496 #else
497 /* DeInit the low level hardware: CLOCK, NVIC.*/
498 HAL_LPTIM_MspDeInit(hlptim);
499 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
500
501 /* Change the LPTIM channels state */
502 LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET);
503
504 /* Change the LPTIM state */
505 hlptim->State = HAL_LPTIM_STATE_RESET;
506
507 /* Release Lock */
508 __HAL_UNLOCK(hlptim);
509
510 /* Return function status */
511 return HAL_OK;
512 }
513
514 /**
515 * @brief Initialize the LPTIM MSP.
516 * @param hlptim LPTIM handle
517 * @retval None
518 */
HAL_LPTIM_MspInit(LPTIM_HandleTypeDef * hlptim)519 __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
520 {
521 /* Prevent unused argument(s) compilation warning */
522 UNUSED(hlptim);
523
524 /* NOTE : This function should not be modified, when the callback is needed,
525 the HAL_LPTIM_MspInit could be implemented in the user file
526 */
527 }
528
529 /**
530 * @brief DeInitialize LPTIM MSP.
531 * @param hlptim LPTIM handle
532 * @retval None
533 */
HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef * hlptim)534 __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
535 {
536 /* Prevent unused argument(s) compilation warning */
537 UNUSED(hlptim);
538
539 /* NOTE : This function should not be modified, when the callback is needed,
540 the HAL_LPTIM_MspDeInit could be implemented in the user file
541 */
542 }
543
544 /**
545 * @}
546 */
547
548 /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
549 * @brief Start-Stop operation functions.
550 *
551 @verbatim
552 ==============================================================================
553 ##### LPTIM Start Stop operation functions #####
554 ==============================================================================
555 [..] This section provides functions allowing to:
556 (+) Start the PWM mode.
557 (+) Stop the PWM mode.
558 (+) Start the One pulse mode.
559 (+) Stop the One pulse mode.
560 (+) Start the Set once mode.
561 (+) Stop the Set once mode.
562 (+) Start the Encoder mode.
563 (+) Stop the Encoder mode.
564 (+) Start the Timeout mode.
565 (+) Stop the Timeout mode.
566 (+) Start the Counter mode.
567 (+) Stop the Counter mode.
568
569
570 @endverbatim
571 * @{
572 */
573
574 /**
575 * @brief Start the LPTIM PWM generation.
576 * @param hlptim LPTIM handle
577 * @param Channel LPTIM Channel to be enabled
578 * This parameter can be one of the following values:
579 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
580 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
581 * @retval HAL status
582 */
HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)583 HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
584 {
585 /* Check the parameters */
586 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
587
588 /* Check LPTIM channel state */
589 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
590 {
591 return HAL_ERROR;
592 }
593
594 /* Set the LPTIM state */
595 hlptim->State = HAL_LPTIM_STATE_BUSY;
596
597 /* Set the LPTIM channel state */
598 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
599
600 /* Reset WAVE bit to set PWM mode */
601 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
602
603 /* Enable the Peripheral */
604 __HAL_LPTIM_ENABLE(hlptim);
605
606 /* Enable LPTIM signal on the corresponding output pin */
607 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
608
609 /* Start timer in continuous mode */
610 __HAL_LPTIM_START_CONTINUOUS(hlptim);
611
612 /* Change the LPTIM state */
613 hlptim->State = HAL_LPTIM_STATE_READY;
614
615 /* Return function status */
616 return HAL_OK;
617 }
618
619 /**
620 * @brief Stop the LPTIM PWM generation.
621 * @param hlptim LPTIM handle
622 * @param Channel LPTIM Channel to be disabled
623 * This parameter can be one of the following values:
624 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
625 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
626 * @retval HAL status
627 */
HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)628 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
629 {
630 /* Check the parameters */
631 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
632
633 /* Change the LPTIM state */
634 hlptim->State = HAL_LPTIM_STATE_BUSY;
635
636 /* Disable LPTIM signal from the corresponding output pin */
637 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
638
639 /* Disable the Peripheral */
640 __HAL_LPTIM_DISABLE(hlptim);
641
642 /* Set the LPTIM channel state */
643 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
644
645 /* Set the LPTIM state */
646 hlptim->State = HAL_LPTIM_STATE_READY;
647
648 /* Return function status */
649 return HAL_OK;
650 }
651
652 /**
653 * @brief Start the LPTIM PWM generation in interrupt mode.
654 * @param hlptim LPTIM handle
655 * @param Channel LPTIM Channel to be enabled
656 * This parameter can be one of the following values:
657 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
658 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
659 * @retval HAL status
660 */
HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)661 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
662 {
663 /* Check the parameters */
664 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
665
666 /* Check LPTIM channel state */
667 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
668 {
669 return HAL_ERROR;
670 }
671
672 /* Set the LPTIM state */
673 hlptim->State = HAL_LPTIM_STATE_BUSY;
674
675 /* Set the LPTIM channel state */
676 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
677
678 /* Reset WAVE bit to set PWM mode */
679 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
680
681 /* Enable the Peripheral */
682 __HAL_LPTIM_ENABLE(hlptim);
683 /* Clear flag */
684 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
685
686 switch (Channel)
687 {
688 case LPTIM_CHANNEL_1:
689 /* Enable interrupt */
690 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
691 LPTIM_IT_UPDATE);
692 break;
693 case LPTIM_CHANNEL_2:
694 /* Enable interrupt */
695 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
696 LPTIM_IT_UPDATE);
697 break;
698 default:
699 break;
700 }
701
702 /* Wait for the completion of the write operation to the LPTIM_DIER register */
703 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
704 {
705 return HAL_TIMEOUT;
706 }
707
708 /* If external trigger source is used, then enable external trigger interrupt */
709 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
710 {
711 /* Clear flag */
712 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
713
714 /* Enable external trigger interrupt */
715 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
716
717 /* Wait for the completion of the write operation to the LPTIM_DIER register */
718 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
719 {
720 return HAL_TIMEOUT;
721 }
722 }
723
724 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
725
726 /* Start timer in continuous mode */
727 __HAL_LPTIM_START_CONTINUOUS(hlptim);
728
729 /* Change the LPTIM state */
730 hlptim->State = HAL_LPTIM_STATE_READY;
731
732 /* Return function status */
733 return HAL_OK;
734 }
735
736 /**
737 * @brief Stop the LPTIM PWM generation in interrupt mode.
738 * @param hlptim LPTIM handle
739 * @param Channel LPTIM Channel to be disabled
740 * This parameter can be one of the following values:
741 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
742 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
743 * @retval HAL status
744 */
HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)745 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
746 {
747 /* Check the parameters */
748 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
749
750 /* Change the LPTIM state */
751 hlptim->State = HAL_LPTIM_STATE_BUSY;
752
753 /* Disable LPTIM signal from the corresponding output pin */
754 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
755
756 /* Disable the Peripheral */
757 __HAL_LPTIM_DISABLE(hlptim);
758
759 /* Enable the Peripheral */
760 __HAL_LPTIM_ENABLE(hlptim);
761
762 /* Clear flag */
763 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
764
765 switch (Channel)
766 {
767 case LPTIM_CHANNEL_1:
768 /* Disable interrupt */
769 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
770 LPTIM_IT_UPDATE);
771 break;
772 case LPTIM_CHANNEL_2:
773 /* Disable interrupt */
774 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
775 LPTIM_IT_UPDATE);
776 break;
777 default:
778 break;
779 }
780
781 /* Wait for the completion of the write operation to the LPTIM_DIER register */
782 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
783 {
784 return HAL_TIMEOUT;
785 }
786
787 /* If external trigger source is used, then enable external trigger interrupt */
788 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
789 {
790 /* Clear flag */
791 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
792
793 /* Enable external trigger interrupt */
794 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
795
796 /* Wait for the completion of the write operation to the LPTIM_DIER register */
797 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
798 {
799 return HAL_TIMEOUT;
800 }
801 }
802
803 /* Disable the Peripheral */
804 __HAL_LPTIM_DISABLE(hlptim);
805
806 /* Set the LPTIM channel state */
807 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
808
809 /* Set the LPTIM state */
810 hlptim->State = HAL_LPTIM_STATE_READY;
811
812 /* Return function status */
813 return HAL_OK;
814 }
815
816 /**
817 * @brief Start the LPTIM PWM generation in DMA mode.
818 * @param hlptim LPTIM handle
819 * @param Channel LPTIM Channel to be enabled
820 * This parameter can be one of the following values:
821 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
822 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
823 * @param pData The destination Buffer address
824 * @param Length The length of data to be transferred from LPTIM peripheral to memory
825 * @retval HAL status
826 */
HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,const uint32_t * pData,uint32_t Length)827 HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData,
828 uint32_t Length)
829 {
830 DMA_HandleTypeDef *hdma;
831
832 /* Check the parameters */
833 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
834 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
835
836 if ((pData == NULL) || (Length == 0U))
837 {
838 return HAL_ERROR;
839 }
840
841 /* Check LPTIM channel state */
842 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
843 {
844 return HAL_ERROR;
845 }
846
847 /* Set the LPTIM state */
848 hlptim->State = HAL_LPTIM_STATE_BUSY;
849
850 /* Set the LPTIM channel state */
851 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
852
853 /* Reset WAVE bit to set PWM mode */
854 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
855
856 /* Enable the Peripheral */
857 __HAL_LPTIM_ENABLE(hlptim);
858
859 /* Enable update event DMA request */
860 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
861
862 /* Wait for the completion of the write operation to the LPTIM_DIER register */
863 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
864 {
865 return HAL_TIMEOUT;
866 }
867
868 switch (Channel)
869 {
870 case LPTIM_CHANNEL_1:
871 /* Set the DMA update event callbacks */
872 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
873 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
874
875 /* Set the DMA error callback */
876 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
877
878 /* Enable the DMA Channel */
879 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
880 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK)
881 {
882 /* Return error status */
883 return HAL_ERROR;
884 }
885 break;
886 case LPTIM_CHANNEL_2:
887 /* Set the DMA update event callbacks */
888 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt;
889 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt;
890
891 /* Set the DMA error callback */
892 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
893
894 /* Enable the DMA Channel */
895 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
896 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK)
897 {
898 /* Return error status */
899 return HAL_ERROR;
900 }
901 break;
902 default:
903 break;
904 }
905
906 /* Enable LPTIM signal on the corresponding output pin */
907 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
908
909 /* Start timer in continuous mode */
910 __HAL_LPTIM_START_CONTINUOUS(hlptim);
911
912 /* Change the LPTIM state */
913 hlptim->State = HAL_LPTIM_STATE_READY;
914
915 /* Return function status */
916 return HAL_OK;
917 }
918
919 /**
920 * @brief Stop the LPTIM PWM generation in DMA mode.
921 * @param hlptim LPTIM handle
922 * @param Channel LPTIM Channel to be disabled
923 * This parameter can be one of the following values:
924 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
925 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
926 * @retval HAL status
927 */
HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)928 HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
929 {
930 /* Check the parameters */
931 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
932 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
933
934 /* Change the LPTIM state */
935 hlptim->State = HAL_LPTIM_STATE_BUSY;
936
937 /* Disable update event DMA request */
938 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE);
939
940 switch (Channel)
941 {
942 case LPTIM_CHANNEL_1:
943 /* Disable update event DMA request */
944 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
945 break;
946 case LPTIM_CHANNEL_2:
947 /* Disable update event DMA request */
948 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
949 break;
950 default:
951 break;
952 }
953
954 /* Disable LPTIM signal from the corresponding output pin */
955 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
956
957 /* Disable the Peripheral */
958 __HAL_LPTIM_DISABLE(hlptim);
959
960 /* Set the LPTIM channel state */
961 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
962
963 /* Set the LPTIM state */
964 hlptim->State = HAL_LPTIM_STATE_READY;
965
966 /* Return function status */
967 return HAL_OK;
968 }
969
970 /**
971 * @brief Start the LPTIM One pulse generation.
972 * @param hlptim LPTIM handle
973 * @param Channel LPTIM Channel to be enabled
974 * This parameter can be one of the following values:
975 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
976 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
977 * @retval HAL status
978 */
HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)979 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
980 {
981 /* Check the parameters */
982 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
983
984 /* Check LPTIM channel state */
985 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
986 {
987 return HAL_ERROR;
988 }
989
990 /* Set the LPTIM state */
991 hlptim->State = HAL_LPTIM_STATE_BUSY;
992
993 /* Set the LPTIM channel state */
994 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
995
996 /* Reset WAVE bit to set one pulse mode */
997 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
998
999 /* Enable the Peripheral */
1000 __HAL_LPTIM_ENABLE(hlptim);
1001
1002 /* Enable LPTIM signal on the corresponding output pin */
1003 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1004
1005 /* Start timer in single (one shot) mode */
1006 __HAL_LPTIM_START_SINGLE(hlptim);
1007
1008 /* Change the LPTIM state */
1009 hlptim->State = HAL_LPTIM_STATE_READY;
1010
1011 /* Return function status */
1012 return HAL_OK;
1013 }
1014
1015 /**
1016 * @brief Stop the LPTIM One pulse generation.
1017 * @param hlptim LPTIM handle
1018 * @param Channel LPTIM Channel to be disabled
1019 * This parameter can be one of the following values:
1020 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1021 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1022 * @retval HAL status
1023 */
HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1024 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1025 {
1026 /* Check the parameters */
1027 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1028
1029 /* Set the LPTIM state */
1030 hlptim->State = HAL_LPTIM_STATE_BUSY;
1031
1032 /* Disable LPTIM signal on the corresponding output pin */
1033 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1034
1035 /* Disable the Peripheral */
1036 __HAL_LPTIM_DISABLE(hlptim);
1037
1038 /* Set the LPTIM channel state */
1039 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1040
1041 /* Set the LPTIM state */
1042 hlptim->State = HAL_LPTIM_STATE_READY;
1043
1044 /* Return function status */
1045 return HAL_OK;
1046 }
1047
1048 /**
1049 * @brief Start the LPTIM One pulse generation in interrupt mode.
1050 * @param hlptim LPTIM handle
1051 * @param Channel LPTIM Channel to be enabled
1052 * This parameter can be one of the following values:
1053 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1054 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1055 * @retval HAL status
1056 */
HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1057 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1058 {
1059 /* Check the parameters */
1060 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1061
1062 /* Check LPTIM channel state */
1063 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1064 {
1065 return HAL_ERROR;
1066 }
1067
1068 /* Set the LPTIM state */
1069 hlptim->State = HAL_LPTIM_STATE_BUSY;
1070
1071 /* Set the LPTIM channel state */
1072 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1073
1074 /* Reset WAVE bit to set one pulse mode */
1075 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
1076
1077 /* Enable the Peripheral */
1078 __HAL_LPTIM_ENABLE(hlptim);
1079
1080 /* Clear flag */
1081 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1082
1083 switch (Channel)
1084 {
1085 case LPTIM_CHANNEL_1:
1086 /* Enable interrupt */
1087 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1088 LPTIM_IT_UPDATE);
1089 break;
1090 case LPTIM_CHANNEL_2:
1091 /* Enable interrupt */
1092 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1093 LPTIM_IT_UPDATE);
1094 break;
1095 default:
1096 break;
1097 }
1098
1099 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1100 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1101 {
1102 return HAL_TIMEOUT;
1103 }
1104
1105 /* If external trigger source is used, then enable external trigger interrupt */
1106 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1107 {
1108 /* Clear flag */
1109 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1110 /* Enable external trigger interrupt */
1111 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1112 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1113 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1114 {
1115 return HAL_TIMEOUT;
1116 }
1117 }
1118
1119 /* Enable LPTIM signal on the corresponding output pin */
1120 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1121
1122 /* Start timer in single (one shot) mode */
1123 __HAL_LPTIM_START_SINGLE(hlptim);
1124
1125 /* Change the LPTIM state */
1126 hlptim->State = HAL_LPTIM_STATE_READY;
1127
1128 /* Return function status */
1129 return HAL_OK;
1130 }
1131
1132 /**
1133 * @brief Stop the LPTIM One pulse generation in interrupt mode.
1134 * @param hlptim LPTIM handle
1135 * @param Channel LPTIM Channel to be disabled
1136 * This parameter can be one of the following values:
1137 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1138 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1139 * @retval HAL status
1140 */
HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1141 HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1142 {
1143 /* Check the parameters */
1144 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1145
1146 /* Set the LPTIM state */
1147 hlptim->State = HAL_LPTIM_STATE_BUSY;
1148
1149 /* Disable LPTIM signal on the corresponding output pin */
1150 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1151
1152 /* Disable the Peripheral */
1153 __HAL_LPTIM_DISABLE(hlptim);
1154
1155
1156 /* Enable the Peripheral */
1157 __HAL_LPTIM_ENABLE(hlptim);
1158
1159 /* Clear flag */
1160 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1161
1162 switch (Channel)
1163 {
1164 case LPTIM_CHANNEL_1:
1165 /* Disable interrupt */
1166 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1167 LPTIM_IT_UPDATE);
1168 break;
1169 case LPTIM_CHANNEL_2:
1170 /* Disable interrupt */
1171 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK |
1172 LPTIM_IT_UPDATE);
1173 break;
1174 default:
1175 break;
1176 }
1177
1178 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1179 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1180 {
1181 return HAL_TIMEOUT;
1182 }
1183
1184 /* If external trigger source is used, then enable external trigger interrupt */
1185 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1186 {
1187 /* Clear flag */
1188 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1189 /* Enable external trigger interrupt */
1190 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1191 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1192 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1193 {
1194 return HAL_TIMEOUT;
1195 }
1196 }
1197
1198 /* Disable the Peripheral */
1199 __HAL_LPTIM_DISABLE(hlptim);
1200
1201 /* Set the LPTIM channel state */
1202 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1203
1204 /* Set the LPTIM state */
1205 hlptim->State = HAL_LPTIM_STATE_READY;
1206
1207 /* Return function status */
1208 return HAL_OK;
1209 }
1210
1211 /**
1212 * @brief Start the LPTIM in Set once mode.
1213 * @param hlptim LPTIM handle
1214 * @param Channel LPTIM Channel to be enabled
1215 * This parameter can be one of the following values:
1216 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1217 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1218 * @retval HAL status
1219 */
HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1220 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1221 {
1222 /* Check the parameters */
1223 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1224
1225 /* Check LPTIM channel state */
1226 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1227 {
1228 return HAL_ERROR;
1229 }
1230
1231 /* Set the LPTIM state */
1232 hlptim->State = HAL_LPTIM_STATE_BUSY;
1233
1234 /* Set the LPTIM channel state */
1235 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1236
1237 /* Set WAVE bit to enable the set once mode */
1238 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1239
1240 /* Enable the Peripheral */
1241 __HAL_LPTIM_ENABLE(hlptim);
1242
1243 /* Enable LPTIM signal on the corresponding output pin */
1244 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1245
1246 /* Start timer in single (one shot) mode */
1247 __HAL_LPTIM_START_SINGLE(hlptim);
1248
1249 /* Change the LPTIM state */
1250 hlptim->State = HAL_LPTIM_STATE_READY;
1251
1252 /* Return function status */
1253 return HAL_OK;
1254 }
1255
1256 /**
1257 * @brief Stop the LPTIM Set once mode.
1258 * @param hlptim LPTIM handle
1259 * @param Channel LPTIM Channel to be disabled
1260 * This parameter can be one of the following values:
1261 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1262 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1263 * @retval HAL status
1264 */
HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1265 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1266 {
1267 /* Check the parameters */
1268 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1269
1270 /* Set the LPTIM state */
1271 hlptim->State = HAL_LPTIM_STATE_BUSY;
1272
1273 /* Disable LPTIM signal on the corresponding output pin */
1274 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1275
1276 /* Disable the Peripheral */
1277 __HAL_LPTIM_DISABLE(hlptim);
1278
1279 /* Set the LPTIM channel state */
1280 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1281
1282 /* Set the LPTIM state */
1283 hlptim->State = HAL_LPTIM_STATE_READY;
1284
1285 /* Return function status */
1286 return HAL_OK;
1287 }
1288
1289 /**
1290 * @brief Start the LPTIM Set once mode in interrupt mode.
1291 * @param hlptim LPTIM handle
1292 * @param Channel LPTIM Channel to be enabled
1293 * This parameter can be one of the following values:
1294 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1295 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1296 * @retval HAL status
1297 */
HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1298 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1299 {
1300 /* Check the parameters */
1301 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1302
1303 /* Check LPTIM channel state */
1304 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1305 {
1306 return HAL_ERROR;
1307 }
1308
1309 /* Set the LPTIM state */
1310 hlptim->State = HAL_LPTIM_STATE_BUSY;
1311
1312 /* Set the LPTIM channel state */
1313 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1314
1315 /* Set WAVE bit to enable the set once mode */
1316 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
1317
1318 /* Enable the Peripheral */
1319 __HAL_LPTIM_ENABLE(hlptim);
1320
1321 /* Clear flag */
1322 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1323
1324 switch (Channel)
1325 {
1326 case LPTIM_CHANNEL_1:
1327 /* Enable interrupt */
1328 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1329 break;
1330 case LPTIM_CHANNEL_2:
1331 /* Enable interrupt */
1332 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE);
1333 break;
1334 default:
1335 break;
1336 }
1337
1338 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1339 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1340 {
1341 return HAL_TIMEOUT;
1342 }
1343
1344 /* If external trigger source is used, then enable external trigger interrupt */
1345 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1346 {
1347 /* Clear flag */
1348 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1349 /* Enable external trigger interrupt */
1350 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1351 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1352 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1353 {
1354 return HAL_TIMEOUT;
1355 }
1356 }
1357
1358 /* Enable LPTIM signal on the corresponding output pin */
1359 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1360
1361 /* Start timer in single (one shot) mode */
1362 __HAL_LPTIM_START_SINGLE(hlptim);
1363
1364 /* Change the LPTIM state */
1365 hlptim->State = HAL_LPTIM_STATE_READY;
1366
1367 /* Return function status */
1368 return HAL_OK;
1369 }
1370
1371 /**
1372 * @brief Stop the LPTIM Set once mode in interrupt mode.
1373 * @param hlptim LPTIM handle
1374 * @param Channel LPTIM Channel to be disabled
1375 * This parameter can be one of the following values:
1376 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
1377 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
1378 * @retval HAL status
1379 */
HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1380 HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1381 {
1382 /* Check the parameters */
1383 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1384
1385 /* Set the LPTIM state */
1386 hlptim->State = HAL_LPTIM_STATE_BUSY;
1387
1388 /* Disable LPTIM signal on the corresponding output pin */
1389 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
1390
1391 /* Disable the Peripheral */
1392 __HAL_LPTIM_DISABLE(hlptim);
1393
1394 /* Enable the Peripheral */
1395 __HAL_LPTIM_ENABLE(hlptim);
1396
1397 /* Clear flag */
1398 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1399
1400 switch (Channel)
1401 {
1402 case LPTIM_CHANNEL_1:
1403 /* Disable interrupt */
1404 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1405 break;
1406 case LPTIM_CHANNEL_2:
1407 /* Disable interrupt */
1408 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM);
1409 break;
1410 default:
1411 break;
1412 }
1413
1414 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1415 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1416 {
1417 return HAL_TIMEOUT;
1418 }
1419
1420 /* If external trigger source is used, then enable external trigger interrupt */
1421 if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE)
1422 {
1423 /* Clear flag */
1424 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1425 /* Enable external trigger interrupt */
1426 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
1427
1428 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1429 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1430 {
1431 return HAL_TIMEOUT;
1432 }
1433 }
1434
1435 /* Disable the Peripheral */
1436 __HAL_LPTIM_DISABLE(hlptim);
1437
1438 /* Set the LPTIM channel state */
1439 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
1440
1441 /* Set the LPTIM state */
1442 hlptim->State = HAL_LPTIM_STATE_READY;
1443
1444 /* Return function status */
1445 return HAL_OK;
1446 }
1447
1448 /**
1449 * @brief Start the Encoder interface.
1450 * @param hlptim LPTIM handle
1451 * @retval HAL status
1452 */
HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef * hlptim)1453 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim)
1454 {
1455 uint32_t tmpcfgr;
1456
1457 /* Check the parameters */
1458 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1459 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1460 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1461 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1462
1463 /* Set the LPTIM state */
1464 hlptim->State = HAL_LPTIM_STATE_BUSY;
1465
1466 /* Get the LPTIMx CFGR value */
1467 tmpcfgr = hlptim->Instance->CFGR;
1468
1469 /* Clear CKPOL bits */
1470 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1471
1472 /* Set Input polarity */
1473 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1474
1475 /* Write to LPTIMx CFGR */
1476 hlptim->Instance->CFGR = tmpcfgr;
1477
1478 /* Set ENC bit to enable the encoder interface */
1479 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1480
1481 /* Enable the Peripheral */
1482 __HAL_LPTIM_ENABLE(hlptim);
1483
1484 /* Start timer in continuous mode */
1485 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1486
1487 /* Change the LPTIM state */
1488 hlptim->State = HAL_LPTIM_STATE_READY;
1489
1490 /* Return function status */
1491 return HAL_OK;
1492 }
1493
1494 /**
1495 * @brief Stop the Encoder interface.
1496 * @param hlptim LPTIM handle
1497 * @retval HAL status
1498 */
HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef * hlptim)1499 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
1500 {
1501 /* Check the parameters */
1502 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1503
1504 /* Set the LPTIM state */
1505 hlptim->State = HAL_LPTIM_STATE_BUSY;
1506
1507 /* Disable the Peripheral */
1508 __HAL_LPTIM_DISABLE(hlptim);
1509
1510 /* Reset ENC bit to disable the encoder interface */
1511 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1512
1513 /* Change the LPTIM state */
1514 hlptim->State = HAL_LPTIM_STATE_READY;
1515
1516 /* Return function status */
1517 return HAL_OK;
1518 }
1519
1520 /**
1521 * @brief Start the Encoder interface in interrupt mode.
1522 * @param hlptim LPTIM handle
1523 * @retval HAL status
1524 */
HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef * hlptim)1525 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim)
1526 {
1527 uint32_t tmpcfgr;
1528
1529 /* Check the parameters */
1530 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1531 assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC);
1532 assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1);
1533 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
1534
1535 /* Set the LPTIM state */
1536 hlptim->State = HAL_LPTIM_STATE_BUSY;
1537
1538 /* Configure edge sensitivity for encoder mode */
1539 /* Get the LPTIMx CFGR value */
1540 tmpcfgr = hlptim->Instance->CFGR;
1541
1542 /* Clear CKPOL bits */
1543 tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL);
1544
1545 /* Set Input polarity */
1546 tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity;
1547
1548 /* Write to LPTIMx CFGR */
1549 hlptim->Instance->CFGR = tmpcfgr;
1550
1551 /* Set ENC bit to enable the encoder interface */
1552 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
1553
1554 /* Enable the Peripheral */
1555 __HAL_LPTIM_ENABLE(hlptim);
1556
1557 /* Clear flag */
1558 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1559
1560 /* Enable "switch to up/down direction" interrupt */
1561 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1562
1563 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1564 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1565 {
1566 return HAL_TIMEOUT;
1567 }
1568
1569
1570 /* Start timer in continuous mode */
1571 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1572
1573 /* Change the LPTIM state */
1574 hlptim->State = HAL_LPTIM_STATE_READY;
1575
1576 /* Return function status */
1577 return HAL_OK;
1578 }
1579
1580 /**
1581 * @brief Stop the Encoder interface in interrupt mode.
1582 * @param hlptim LPTIM handle
1583 * @retval HAL status
1584 */
HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef * hlptim)1585 HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1586 {
1587 /* Check the parameters */
1588 assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance));
1589
1590 /* Set the LPTIM state */
1591 hlptim->State = HAL_LPTIM_STATE_BUSY;
1592
1593 /* Disable the Peripheral */
1594 __HAL_LPTIM_DISABLE(hlptim);
1595
1596 /* Reset ENC bit to disable the encoder interface */
1597 hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
1598 /* Enable the Peripheral */
1599 __HAL_LPTIM_ENABLE(hlptim);
1600
1601 /* Clear flag */
1602 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1603
1604 /* Disable "switch to down/up direction" interrupt */
1605 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN);
1606
1607 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1608 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1609 {
1610 return HAL_TIMEOUT;
1611 }
1612
1613 /* Disable the Peripheral */
1614 __HAL_LPTIM_DISABLE(hlptim);
1615
1616 /* Change the LPTIM state */
1617 hlptim->State = HAL_LPTIM_STATE_READY;
1618
1619 /* Return function status */
1620 return HAL_OK;
1621 }
1622
1623 /**
1624 * @brief Start the Timeout function.
1625 * @note The first trigger event will start the timer, any successive
1626 * trigger event will reset the counter and the timer restarts.
1627 * @param hlptim LPTIM handle
1628 * @param Timeout Specifies the TimeOut value to reset the counter.
1629 * This parameter must be a value between 0x0000 and 0xFFFF.
1630 * @retval HAL status
1631 */
HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1632 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1633 {
1634 /* Check the parameters */
1635 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1636 assert_param(IS_LPTIM_PULSE(Timeout));
1637
1638 /* Set the LPTIM state */
1639 hlptim->State = HAL_LPTIM_STATE_BUSY;
1640
1641 /* Set TIMOUT bit to enable the timeout function */
1642 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1643
1644 /* Enable the Peripheral */
1645 __HAL_LPTIM_ENABLE(hlptim);
1646
1647 /* Clear flag */
1648 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1649
1650 /* Load the Timeout value in the compare register */
1651 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1652
1653 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1654 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1655 {
1656 return HAL_TIMEOUT;
1657 }
1658
1659 /* Start timer in continuous mode */
1660 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1661
1662 /* Change the LPTIM state */
1663 hlptim->State = HAL_LPTIM_STATE_READY;
1664
1665 /* Return function status */
1666 return HAL_OK;
1667 }
1668
1669 /**
1670 * @brief Stop the Timeout function.
1671 * @param hlptim LPTIM handle
1672 * @retval HAL status
1673 */
HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef * hlptim)1674 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
1675 {
1676 /* Check the parameters */
1677 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1678
1679 /* Set the LPTIM state */
1680 hlptim->State = HAL_LPTIM_STATE_BUSY;
1681
1682 /* Disable the Peripheral */
1683 __HAL_LPTIM_DISABLE(hlptim);
1684
1685 /* Reset TIMOUT bit to enable the timeout function */
1686 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1687
1688 /* Change the LPTIM state */
1689 hlptim->State = HAL_LPTIM_STATE_READY;
1690
1691 /* Return function status */
1692 return HAL_OK;
1693 }
1694
1695 /**
1696 * @brief Start the Timeout function in interrupt mode.
1697 * @note The first trigger event will start the timer, any successive
1698 * trigger event will reset the counter and the timer restarts.
1699 * @param hlptim LPTIM handle
1700 * @param Timeout Specifies the TimeOut value to reset the counter.
1701 * This parameter must be a value between 0x0000 and 0xFFFF.
1702 * @retval HAL status
1703 */
HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Timeout)1704 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout)
1705 {
1706 /* Check the parameters */
1707 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1708 assert_param(IS_LPTIM_PULSE(Timeout));
1709
1710 /* Set the LPTIM state */
1711 hlptim->State = HAL_LPTIM_STATE_BUSY;
1712
1713 /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
1714 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
1715
1716 /* Set TIMOUT bit to enable the timeout function */
1717 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
1718
1719 /* Enable the Peripheral */
1720 __HAL_LPTIM_ENABLE(hlptim);
1721
1722 /* Clear flag */
1723 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1724
1725 /* Enable Compare match CH1 interrupt */
1726 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
1727
1728 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1729 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1730 {
1731 return HAL_TIMEOUT;
1732 }
1733
1734 /* Clear flag */
1735 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
1736
1737 /* Load the Timeout value in the compare register */
1738 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout);
1739
1740 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
1741 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
1742 {
1743 return HAL_TIMEOUT;
1744 }
1745
1746 /* Start timer in continuous mode */
1747 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1748
1749 /* Change the LPTIM state */
1750 hlptim->State = HAL_LPTIM_STATE_READY;
1751
1752 /* Return function status */
1753 return HAL_OK;
1754 }
1755
1756 /**
1757 * @brief Stop the Timeout function in interrupt mode.
1758 * @param hlptim LPTIM handle
1759 * @retval HAL status
1760 */
HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef * hlptim)1761 HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1762 {
1763 /* Check the parameters */
1764 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1765
1766
1767 /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
1768 __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
1769
1770 /* Set the LPTIM state */
1771 hlptim->State = HAL_LPTIM_STATE_BUSY;
1772
1773 /* Disable the Peripheral */
1774 __HAL_LPTIM_DISABLE(hlptim);
1775
1776 /* Reset TIMOUT bit to enable the timeout function */
1777 hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
1778
1779 /* Enable the Peripheral */
1780 __HAL_LPTIM_ENABLE(hlptim);
1781
1782 /* Clear flag */
1783 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1784
1785 /* Disable Compare match CH1 interrupt */
1786 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
1787
1788 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1789 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1790 {
1791 return HAL_TIMEOUT;
1792 }
1793
1794 /* Disable the Peripheral */
1795 __HAL_LPTIM_DISABLE(hlptim);
1796
1797 /* Change the LPTIM state */
1798 hlptim->State = HAL_LPTIM_STATE_READY;
1799
1800 /* Return function status */
1801 return HAL_OK;
1802 }
1803
1804 /**
1805 * @brief Start the Counter mode.
1806 * @param hlptim LPTIM handle
1807 * @retval HAL status
1808 */
HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef * hlptim)1809 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim)
1810 {
1811 /* Check the parameters */
1812 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1813
1814 /* Set the LPTIM state */
1815 hlptim->State = HAL_LPTIM_STATE_BUSY;
1816
1817 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1818 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1819 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1820 {
1821 /* Check if clock is prescaled */
1822 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1823 /* Set clock prescaler to 0 */
1824 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1825 }
1826
1827 /* Enable the Peripheral */
1828 __HAL_LPTIM_ENABLE(hlptim);
1829
1830 /* Start timer in continuous mode */
1831 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1832
1833 /* Change the LPTIM state */
1834 hlptim->State = HAL_LPTIM_STATE_READY;
1835
1836 /* Return function status */
1837 return HAL_OK;
1838 }
1839
1840 /**
1841 * @brief Stop the Counter mode.
1842 * @param hlptim LPTIM handle
1843 * @retval HAL status
1844 */
HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef * hlptim)1845 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
1846 {
1847 /* Check the parameters */
1848 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1849
1850 /* Set the LPTIM state */
1851 hlptim->State = HAL_LPTIM_STATE_BUSY;
1852
1853 /* Disable the Peripheral */
1854 __HAL_LPTIM_DISABLE(hlptim);
1855
1856 /* Change the LPTIM state */
1857 hlptim->State = HAL_LPTIM_STATE_READY;
1858
1859 /* Return function status */
1860 return HAL_OK;
1861 }
1862
1863 /**
1864 * @brief Start the Counter mode in interrupt mode.
1865 * @param hlptim LPTIM handle
1866 * @retval HAL status
1867 */
HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef * hlptim)1868 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim)
1869 {
1870 /* Check the parameters */
1871 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1872
1873 /* Set the LPTIM state */
1874 hlptim->State = HAL_LPTIM_STATE_BUSY;
1875
1876 /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
1877 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
1878
1879 /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
1880 if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
1881 && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
1882 {
1883 /* Check if clock is prescaled */
1884 assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
1885 /* Set clock prescaler to 0 */
1886 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
1887 }
1888
1889 /* Enable the Peripheral */
1890 __HAL_LPTIM_ENABLE(hlptim);
1891
1892 /* Clear flag */
1893 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1894
1895 /* Enable interrupt */
1896 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1897
1898 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1899 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1900 {
1901 return HAL_TIMEOUT;
1902 }
1903
1904 /* Start timer in continuous mode */
1905 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1906
1907 /* Change the LPTIM state */
1908 hlptim->State = HAL_LPTIM_STATE_READY;
1909
1910 /* Return function status */
1911 return HAL_OK;
1912 }
1913
1914 /**
1915 * @brief Stop the Counter mode in interrupt mode.
1916 * @param hlptim LPTIM handle
1917 * @retval HAL status
1918 */
HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef * hlptim)1919 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
1920 {
1921 /* Check the parameters */
1922 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
1923
1924
1925 /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
1926 __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(hlptim->Instance);
1927
1928 /* Set the LPTIM state */
1929 hlptim->State = HAL_LPTIM_STATE_BUSY;
1930
1931 /* Disable the Peripheral */
1932 __HAL_LPTIM_DISABLE(hlptim);
1933
1934
1935 /* Enable the Peripheral */
1936 __HAL_LPTIM_ENABLE(hlptim);
1937
1938 /* Clear flag */
1939 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK);
1940
1941 /* Disable interrupt */
1942 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE);
1943
1944 /* Wait for the completion of the write operation to the LPTIM_DIER register */
1945 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
1946 {
1947 return HAL_TIMEOUT;
1948 }
1949
1950 /* Disable the Peripheral */
1951 __HAL_LPTIM_DISABLE(hlptim);
1952
1953 /* Change the LPTIM state */
1954 hlptim->State = HAL_LPTIM_STATE_READY;
1955
1956 /* Return function status */
1957 return HAL_OK;
1958 }
1959
1960 /**
1961 * @brief Starts the LPTIM Input Capture measurement.
1962 * @param hlptim LPTIM Input Capture handle
1963 * @param Channel LPTIM Channels to be enabled
1964 * This parameter can be one of the following values:
1965 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
1966 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
1967 * @retval HAL status
1968 */
HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)1969 HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
1970 {
1971 /* Check the parameters */
1972 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
1973 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
1974
1975 /* Check LPTIM channel state */
1976 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
1977 {
1978 return HAL_ERROR;
1979 }
1980
1981 /* Set the LPTIM state */
1982 hlptim->State = HAL_LPTIM_STATE_BUSY;
1983
1984 /* Set the LPTIM channel state */
1985 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
1986
1987 /* Enable the Peripheral */
1988 __HAL_LPTIM_ENABLE(hlptim);
1989
1990 /* Start timer in continuous mode */
1991 __HAL_LPTIM_START_CONTINUOUS(hlptim);
1992
1993 /* Enable capture */
1994 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
1995
1996 /* Change the LPTIM state */
1997 hlptim->State = HAL_LPTIM_STATE_READY;
1998
1999 /* Return function status */
2000 return HAL_OK;
2001 }
2002
2003 /**
2004 * @brief Stops the LPTIM Input Capture measurement.
2005 * @param hlptim LPTIM Input Capture handle
2006 * @param Channel LPTIM Channels to be disabled
2007 * This parameter can be one of the following values:
2008 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2009 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2010 * @retval HAL status
2011 */
HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2012 HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2013 {
2014 /* Check the parameters */
2015 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2016 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2017
2018 /* Set the LPTIM state */
2019 hlptim->State = HAL_LPTIM_STATE_BUSY;
2020
2021 /* Disable capture */
2022 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2023
2024 /* Disable the Peripheral */
2025 __HAL_LPTIM_DISABLE(hlptim);
2026
2027 /* Set the LPTIM channel state */
2028 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2029
2030 /* Set the LPTIM state */
2031 hlptim->State = HAL_LPTIM_STATE_READY;
2032
2033 /* Return function status */
2034 return HAL_OK;
2035 }
2036
2037 /**
2038 * @brief Starts the LPTIM Input Capture measurement in interrupt mode.
2039 * @param hlptim LPTIM Input Capture handle
2040 * @param Channel LPTIM Channels to be enabled
2041 * This parameter can be one of the following values:
2042 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2043 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2044 * @retval HAL status
2045 */
HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2046 HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2047 {
2048 /* Check the parameters */
2049 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2050 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2051
2052 /* Check LPTIM channel state */
2053 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2054 {
2055 return HAL_ERROR;
2056 }
2057
2058 /* Set the LPTIM state */
2059 hlptim->State = HAL_LPTIM_STATE_BUSY;
2060
2061 /* Set the LPTIM channel state */
2062 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2063
2064 /* Enable the Peripheral */
2065 __HAL_LPTIM_ENABLE(hlptim);
2066
2067 switch (Channel)
2068 {
2069 case LPTIM_CHANNEL_1:
2070 /* Enable Capture/Compare 1 interrupt */
2071 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1);
2072 break;
2073 case LPTIM_CHANNEL_2:
2074 /* Disable Capture/Compare 2 interrupt */
2075 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2);
2076 break;
2077 default:
2078 break;
2079 }
2080
2081 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2082 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2083 {
2084 return HAL_TIMEOUT;
2085 }
2086
2087 /* Start timer in continuous mode */
2088 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2089
2090 /* Enable capture */
2091 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2092
2093 /* Set the LPTIM state */
2094 hlptim->State = HAL_LPTIM_STATE_READY;
2095
2096 /* Return function status */
2097 return HAL_OK;
2098 }
2099
2100 /**
2101 * @brief Stops the LPTIM Input Capture measurement in interrupt mode.
2102 * @param hlptim LPTIM Input Capture handle
2103 * @param Channel LPTIM Channels to be disabled
2104 * This parameter can be one of the following values:
2105 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2106 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2107 * @retval HAL status
2108 */
HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2109 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2110 {
2111 /* Check the parameters */
2112 assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance));
2113 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2114
2115 /* Set the LPTIM state */
2116 hlptim->State = HAL_LPTIM_STATE_BUSY;
2117
2118 switch (Channel)
2119 {
2120 case LPTIM_CHANNEL_1:
2121 /* Disable Capture/Compare 1 interrupt */
2122 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1);
2123 break;
2124 case LPTIM_CHANNEL_2:
2125 /* Disable Capture/Compare 2 interrupt */
2126 __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2);
2127 break;
2128 default:
2129 return HAL_ERROR;
2130 break;
2131 }
2132 /* Disable capture */
2133 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2134
2135 /* Disable the Peripheral */
2136 __HAL_LPTIM_DISABLE(hlptim);
2137
2138 /* Set the LPTIM channel state */
2139 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2140
2141 /* Set the LPTIM state */
2142 hlptim->State = HAL_LPTIM_STATE_READY;
2143
2144 /* Return function status */
2145 return HAL_OK;
2146 }
2147
2148 /**
2149 * @brief Starts the LPTIM Input Capture measurement in DMA mode.
2150 * @param hlptim LPTIM Input Capture handle
2151 * @param Channel LPTIM Channels to be enabled
2152 * This parameter can be one of the following values:
2153 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2154 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2155 * @param pData The destination Buffer address
2156 * @param Length The length of data to be transferred from LPTIM peripheral to memory
2157 * @retval HAL status
2158 */
HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel,uint32_t * pData,uint32_t Length)2159 HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData,
2160 uint32_t Length)
2161 {
2162 DMA_HandleTypeDef *hdma;
2163
2164 /* Check the parameters */
2165 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2166 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2167
2168 if ((pData == NULL) || (Length == 0U))
2169 {
2170 return HAL_ERROR;
2171 }
2172
2173 /* Check LPTIM channel state */
2174 if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY)
2175 {
2176 return HAL_ERROR;
2177 }
2178
2179 /* Set the LPTIM state */
2180 hlptim->State = HAL_LPTIM_STATE_BUSY;
2181
2182 /* Set the LPTIM channel state */
2183 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY);
2184
2185 /* Enable the Peripheral */
2186 __HAL_LPTIM_ENABLE(hlptim);
2187
2188 switch (Channel)
2189 {
2190 case LPTIM_CHANNEL_1:
2191 /* Set the DMA capture callbacks */
2192 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt;
2193 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2194
2195 /* Set the DMA error callback */
2196 hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError;
2197
2198 /* Enable the DMA Channel */
2199 hdma = hlptim->hdma[LPTIM_DMA_ID_CC1];
2200 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2201 {
2202 /* Return error status */
2203 return HAL_ERROR;
2204 }
2205
2206 /* Enable Capture/Compare 1 DMA request */
2207 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1);
2208 break;
2209
2210 case LPTIM_CHANNEL_2:
2211 /* Set the DMA capture callbacks */
2212 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt;
2213 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt;
2214
2215 /* Set the DMA error callback */
2216 hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError;
2217
2218 /* Enable the DMA Channel */
2219 hdma = hlptim->hdma[LPTIM_DMA_ID_CC2];
2220 if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2221 {
2222 /* Return error status */
2223 return HAL_ERROR;
2224 }
2225
2226 /* Enable Capture/Compare 2 DMA request */
2227 __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2);
2228 break;
2229
2230 default:
2231 break;
2232 }
2233
2234 /* Wait for the completion of the write operation to the LPTIM_DIER register */
2235 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT)
2236 {
2237 return HAL_TIMEOUT;
2238 }
2239
2240 /* Start timer in continuous mode */
2241 __HAL_LPTIM_START_CONTINUOUS(hlptim);
2242
2243 /* Enable capture */
2244 __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel);
2245
2246 /* Set the LPTIM state */
2247 hlptim->State = HAL_LPTIM_STATE_READY;
2248
2249 /* Return function status */
2250 return HAL_OK;
2251 }
2252
2253 /**
2254 * @brief Stops the LPTIM Input Capture measurement in DMA mode.
2255 * @param hlptim LPTIM Input Capture handle
2256 * @param Channel LPTIM Channels to be disabled
2257 * This parameter can be one of the following values:
2258 * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected
2259 * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected
2260 * @retval HAL status
2261 */
HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2262 HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2263 {
2264 /* Check the parameters */
2265 assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance));
2266 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2267
2268 /* Set the LPTIM state */
2269 hlptim->State = HAL_LPTIM_STATE_BUSY;
2270
2271 switch (Channel)
2272 {
2273 case LPTIM_CHANNEL_1:
2274 /* Disable Capture/Compare 1 DMA request */
2275 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1);
2276 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]);
2277 break;
2278
2279 case LPTIM_CHANNEL_2:
2280 /* Disable Capture/Compare 2 DMA request */
2281 __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2);
2282 (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]);
2283 break;
2284 default:
2285 return HAL_ERROR;
2286 break;
2287 }
2288
2289 /* Disable capture */
2290 __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel);
2291
2292 /* Disable the Peripheral */
2293 __HAL_LPTIM_DISABLE(hlptim);
2294
2295 /* Set the LPTIM channel state */
2296 LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY);
2297
2298 /* Set the LPTIM state */
2299 hlptim->State = HAL_LPTIM_STATE_READY;
2300
2301 /* Return function status */
2302 return HAL_OK;
2303 }
2304 /**
2305 * @}
2306 */
2307
2308 /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
2309 * @brief Read operation functions.
2310 *
2311 @verbatim
2312 ==============================================================================
2313 ##### LPTIM Read operation functions #####
2314 ==============================================================================
2315 [..] This section provides LPTIM Reading functions.
2316 (+) Read the counter value.
2317 (+) Read the period (Auto-reload) value.
2318 (+) Read the pulse (Compare)value.
2319 @endverbatim
2320 * @{
2321 */
2322
2323 /**
2324 * @brief Return the current counter value.
2325 * @param hlptim LPTIM handle
2326 * @retval Counter value.
2327 */
HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef * hlptim)2328 uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
2329 {
2330 /* Check the parameters */
2331 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2332
2333 return (hlptim->Instance->CNT);
2334 }
2335
2336 /**
2337 * @brief Return the current Autoreload (Period) value.
2338 * @param hlptim LPTIM handle
2339 * @retval Autoreload value.
2340 */
HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef * hlptim)2341 uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
2342 {
2343 /* Check the parameters */
2344 assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
2345
2346 return (hlptim->Instance->ARR);
2347 }
2348
2349 /**
2350 * @brief Return the current Compare (Pulse) value.
2351 * @param hlptim LPTIM handle
2352 * @param Channel LPTIM Channel to be selected
2353 * This parameter can be one of the following values:
2354 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2355 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2356 * @retval Compare value.
2357 */
HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2358 uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2359 {
2360 uint32_t tmpccr;
2361
2362 /* Check the parameters */
2363 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2364
2365 switch (Channel)
2366 {
2367 case LPTIM_CHANNEL_1:
2368 tmpccr = hlptim->Instance->CCR1;
2369 break;
2370 case LPTIM_CHANNEL_2:
2371 tmpccr = hlptim->Instance->CCR2;
2372 break;
2373 default:
2374 tmpccr = 0;
2375 break;
2376 }
2377 return tmpccr;
2378 }
2379
2380 /**
2381 * @brief LPTimer Input Capture Get Offset(in counter step unit)
2382 * @note The real capture value corresponding to the input capture trigger can be calculated using
2383 * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset
2384 * The Offset value is depending on the glitch filter value for the channel
2385 * and the value of the prescaler for the kernel clock.
2386 * Please check Errata Sheet V1_8 for more details under "variable latency
2387 * on input capture channel" section.
2388 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
2389 * the configuration information for LPTIM module.
2390 * @param Channel This parameter can be one of the following values:
2391 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2392 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2393 * @retval The offset value
2394 */
HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef * hlptim,uint32_t Channel)2395 uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel)
2396 {
2397
2398 uint8_t offset ;
2399 uint32_t prescaler;
2400 uint32_t filter ;
2401
2402 /* Get prescaler value */
2403 prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance);
2404
2405 /* Get filter value */
2406 filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel);
2407
2408 /* Get offset value */
2409 offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter);
2410
2411 /* return offset value */
2412 return offset;
2413 }
2414
2415 /**
2416 * @}
2417 */
2418 /** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function
2419 * @brief Config channel
2420 *
2421 @verbatim
2422 ==============================================================================
2423 ##### LPTIM Config function #####
2424 ==============================================================================
2425 [..] This section provides LPTIM Config function.
2426 (+) Configure channel: Output Compare mode, Period, Polarity.
2427 @endverbatim
2428 * @{
2429 */
2430
2431 /**
2432 * @brief
2433 * @param hlptim LPTIM handle
2434 * @param sConfig The output configuration structure
2435 * @param Channel LPTIM Channel to be configured
2436 * This parameter can be one of the following values:
2437 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2438 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2439 * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed
2440 * after a delay that must be greater or equal than the value of
2441 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2442 * division factor (1, 2, 4, ..., 128). Any successive call violating
2443 * this delay, leads to unpredictable results.
2444 * @retval HAL status
2445 */
HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig,uint32_t Channel)2446 HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig,
2447 uint32_t Channel)
2448 {
2449 HAL_StatusTypeDef status;
2450 /* Check the parameters */
2451 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2452 assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity));
2453 assert_param(IS_LPTIM_PULSE(sConfig->Pulse));
2454
2455 hlptim->State = HAL_LPTIM_STATE_BUSY;
2456
2457 switch (Channel)
2458 {
2459 case LPTIM_CHANNEL_1:
2460 {
2461 /* Check the parameters */
2462 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2463
2464 /* Configure the LPTIM Channel 1 in Output Compare */
2465 status = LPTIM_OC1_SetConfig(hlptim, sConfig);
2466 if (status != HAL_OK)
2467 {
2468 return status;
2469 }
2470 break;
2471 }
2472 case LPTIM_CHANNEL_2:
2473 {
2474 /* Check the parameters */
2475 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2476
2477 /* Configure the LPTIM Channel 2 in Output Compare */
2478 status = LPTIM_OC2_SetConfig(hlptim, sConfig);
2479 if (status != HAL_OK)
2480 {
2481 return status;
2482 }
2483 break;
2484 }
2485 default:
2486 break;
2487 }
2488
2489 /* Change the LPTIM state */
2490 hlptim->State = HAL_LPTIM_STATE_READY;
2491
2492 /* Return function status */
2493 return HAL_OK;
2494 }
2495
2496 /**
2497 * @brief
2498 * @param hlptim LPTIM handle
2499 * @param sConfig The input configuration structure
2500 * @param Channel LPTIM Channel to be configured
2501 * This parameter can be one of the following values:
2502 * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected
2503 * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected
2504 * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed
2505 * after a delay that must be greater or equal than the value of
2506 * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal
2507 * division factor (1, 2, 4, ..., 128). Any successive call violating
2508 * this delay, leads to unpredictable results.
2509 * @retval HAL status
2510 */
HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig,uint32_t Channel)2511 HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig,
2512 uint32_t Channel)
2513 {
2514 /* Check the parameters */
2515 assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel));
2516 assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler));
2517 assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity));
2518 assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter));
2519
2520 hlptim->State = HAL_LPTIM_STATE_BUSY;
2521
2522 switch (Channel)
2523 {
2524 case LPTIM_CHANNEL_1:
2525 {
2526 /* Check the parameters */
2527 assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance));
2528 assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2529
2530 /* Configure the LPTIM Channel 1 in Input Capture */
2531 LPTIM_IC1_SetConfig(hlptim, sConfig);
2532 break;
2533 }
2534 case LPTIM_CHANNEL_2:
2535 {
2536 /* Check the parameters */
2537 assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance));
2538 assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource));
2539
2540 /* Configure the LPTIM Channel 2 in Input Capture */
2541 LPTIM_IC2_SetConfig(hlptim, sConfig);
2542 break;
2543 }
2544 default:
2545 break;
2546 }
2547
2548 /* Change the LPTIM state */
2549 hlptim->State = HAL_LPTIM_STATE_READY;
2550 /* Return function status */
2551 return HAL_OK;
2552 }
2553 /**
2554 * @}
2555 */
2556
2557 /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
2558 * @brief LPTIM IRQ handler.
2559 *
2560 @verbatim
2561 ==============================================================================
2562 ##### LPTIM IRQ handler and callbacks #####
2563 ==============================================================================
2564 [..] This section provides LPTIM IRQ handler and callback functions called within
2565 the IRQ handler:
2566 (+) LPTIM interrupt request handler
2567 (+) Compare match Callback
2568 (+) Auto-reload match Callback
2569 (+) External trigger event detection Callback
2570 (+) Compare register write complete Callback
2571 (+) Auto-reload register write complete Callback
2572 (+) Up-counting direction change Callback
2573 (+) Down-counting direction change Callback
2574
2575 @endverbatim
2576 * @{
2577 */
2578
2579 /**
2580 * @brief Handle LPTIM interrupt request.
2581 * @param hlptim LPTIM handle
2582 * @retval None
2583 */
HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef * hlptim)2584 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
2585 {
2586 /* Capture Compare 1 interrupt */
2587 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET)
2588 {
2589 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET)
2590 {
2591 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1);
2592 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2593
2594 /* Input capture event */
2595 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U)
2596 {
2597 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2598 hlptim->IC_CaptureCallback(hlptim);
2599 #else
2600 HAL_LPTIM_IC_CaptureCallback(hlptim);
2601 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2602 }
2603 /* Output compare event */
2604 else
2605 {
2606 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2607 hlptim->CompareMatchCallback(hlptim);
2608 #else
2609 HAL_LPTIM_CompareMatchCallback(hlptim);
2610 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2611 }
2612 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2613 }
2614 }
2615
2616 /* Capture Compare 2 interrupt */
2617 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET)
2618 {
2619 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET)
2620 {
2621 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2);
2622 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2623
2624 /* Input capture event */
2625 if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U)
2626 {
2627 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2628 hlptim->IC_CaptureCallback(hlptim);
2629 #else
2630 HAL_LPTIM_IC_CaptureCallback(hlptim);
2631 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2632 }
2633 /* Output compare event */
2634 else
2635 {
2636 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2637 hlptim->CompareMatchCallback(hlptim);
2638 #else
2639 HAL_LPTIM_CompareMatchCallback(hlptim);
2640 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2641 }
2642 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2643 }
2644 }
2645
2646 /* Over Capture 1 interrupt */
2647 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET)
2648 {
2649 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET)
2650 {
2651 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O);
2652 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2653
2654 /* Over capture event */
2655 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2656 hlptim->IC_OverCaptureCallback(hlptim);
2657 #else
2658 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2659 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2660 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2661 }
2662 }
2663
2664 /* Over Capture 2 interrupt */
2665 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET)
2666 {
2667 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET)
2668 {
2669 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O);
2670 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2671
2672 /* Over capture event */
2673 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2674 hlptim->IC_OverCaptureCallback(hlptim);
2675 #else
2676 HAL_LPTIM_IC_OverCaptureCallback(hlptim);
2677 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2678 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
2679 }
2680 }
2681
2682 /* Autoreload match interrupt */
2683 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET)
2684 {
2685 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET)
2686 {
2687 /* Clear Autoreload match flag */
2688 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
2689
2690 /* Autoreload match Callback */
2691 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2692 hlptim->AutoReloadMatchCallback(hlptim);
2693 #else
2694 HAL_LPTIM_AutoReloadMatchCallback(hlptim);
2695 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2696 }
2697 }
2698
2699 /* Trigger detected interrupt */
2700 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET)
2701 {
2702 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET)
2703 {
2704 /* Clear Trigger detected flag */
2705 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
2706
2707 /* Trigger detected callback */
2708 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2709 hlptim->TriggerCallback(hlptim);
2710 #else
2711 HAL_LPTIM_TriggerCallback(hlptim);
2712 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2713 }
2714 }
2715
2716 /* Compare write interrupt */
2717 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET)
2718 {
2719 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET)
2720 {
2721 /* Clear Compare write flag */
2722 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
2723 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
2724 /* Compare write Callback */
2725 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2726 hlptim->CompareWriteCallback(hlptim);
2727 #else
2728 HAL_LPTIM_CompareWriteCallback(hlptim);
2729 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2730 }
2731 }
2732
2733 /* Compare write interrupt */
2734 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET)
2735 {
2736 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET)
2737 {
2738 /* Clear Compare write flag */
2739 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
2740 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
2741 /* Compare write Callback */
2742 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2743 hlptim->CompareWriteCallback(hlptim);
2744 #else
2745 HAL_LPTIM_CompareWriteCallback(hlptim);
2746 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2747 }
2748 }
2749
2750 /* Autoreload write interrupt */
2751 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET)
2752 {
2753 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET)
2754 {
2755 /* Clear Autoreload write flag */
2756 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
2757
2758 /* Autoreload write Callback */
2759 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2760 hlptim->AutoReloadWriteCallback(hlptim);
2761 #else
2762 HAL_LPTIM_AutoReloadWriteCallback(hlptim);
2763 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2764 }
2765 }
2766
2767 /* Direction counter changed from Down to Up interrupt */
2768 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET)
2769 {
2770 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET)
2771 {
2772 /* Clear Direction counter changed from Down to Up flag */
2773 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
2774
2775 /* Direction counter changed from Down to Up Callback */
2776 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2777 hlptim->DirectionUpCallback(hlptim);
2778 #else
2779 HAL_LPTIM_DirectionUpCallback(hlptim);
2780 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2781 }
2782 }
2783
2784 /* Direction counter changed from Up to Down interrupt */
2785 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET)
2786 {
2787 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET)
2788 {
2789 /* Clear Direction counter changed from Up to Down flag */
2790 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
2791
2792 /* Direction counter changed from Up to Down Callback */
2793 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2794 hlptim->DirectionDownCallback(hlptim);
2795 #else
2796 HAL_LPTIM_DirectionDownCallback(hlptim);
2797 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2798 }
2799 }
2800
2801 /* Repetition counter underflowed (or contains zero) and the LPTIM counter
2802 overflowed */
2803 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
2804 {
2805 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
2806 {
2807 /* Clear update event flag */
2808 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
2809
2810 /* Update event Callback */
2811 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2812 hlptim->UpdateEventCallback(hlptim);
2813 #else
2814 HAL_LPTIM_UpdateEventCallback(hlptim);
2815 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2816 }
2817 }
2818
2819 /* Successful APB bus write to repetition counter register */
2820 if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
2821 {
2822 if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
2823 {
2824 /* Clear successful APB bus write to repetition counter flag */
2825 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
2826
2827 /* Successful APB bus write to repetition counter Callback */
2828 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
2829 hlptim->RepCounterWriteCallback(hlptim);
2830 #else
2831 HAL_LPTIM_RepCounterWriteCallback(hlptim);
2832 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
2833 }
2834 }
2835 }
2836
2837 /**
2838 * @brief Compare match callback in non-blocking mode.
2839 * @param hlptim LPTIM handle
2840 * @retval None
2841 */
HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef * hlptim)2842 __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
2843 {
2844 /* Prevent unused argument(s) compilation warning */
2845 UNUSED(hlptim);
2846
2847 /* NOTE : This function should not be modified, when the callback is needed,
2848 the HAL_LPTIM_CompareMatchCallback could be implemented in the user file
2849 */
2850 }
2851
2852 /**
2853 * @brief Autoreload match callback in non-blocking mode.
2854 * @param hlptim LPTIM handle
2855 * @retval None
2856 */
HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef * hlptim)2857 __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
2858 {
2859 /* Prevent unused argument(s) compilation warning */
2860 UNUSED(hlptim);
2861
2862 /* NOTE : This function should not be modified, when the callback is needed,
2863 the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file
2864 */
2865 }
2866
2867 /**
2868 * @brief Trigger detected callback in non-blocking mode.
2869 * @param hlptim LPTIM handle
2870 * @retval None
2871 */
HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef * hlptim)2872 __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
2873 {
2874 /* Prevent unused argument(s) compilation warning */
2875 UNUSED(hlptim);
2876
2877 /* NOTE : This function should not be modified, when the callback is needed,
2878 the HAL_LPTIM_TriggerCallback could be implemented in the user file
2879 */
2880 }
2881
2882 /**
2883 * @brief Compare write callback in non-blocking mode.
2884 * @param hlptim LPTIM handle
2885 * @retval None
2886 */
HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef * hlptim)2887 __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
2888 {
2889 /* Prevent unused argument(s) compilation warning */
2890 UNUSED(hlptim);
2891
2892 /* NOTE : This function should not be modified, when the callback is needed,
2893 the HAL_LPTIM_CompareWriteCallback could be implemented in the user file
2894 */
2895 }
2896
2897 /**
2898 * @brief Autoreload write callback in non-blocking mode.
2899 * @param hlptim LPTIM handle
2900 * @retval None
2901 */
HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef * hlptim)2902 __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
2903 {
2904 /* Prevent unused argument(s) compilation warning */
2905 UNUSED(hlptim);
2906
2907 /* NOTE : This function should not be modified, when the callback is needed,
2908 the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file
2909 */
2910 }
2911
2912 /**
2913 * @brief Direction counter changed from Down to Up callback in non-blocking mode.
2914 * @param hlptim LPTIM handle
2915 * @retval None
2916 */
HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef * hlptim)2917 __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
2918 {
2919 /* Prevent unused argument(s) compilation warning */
2920 UNUSED(hlptim);
2921
2922 /* NOTE : This function should not be modified, when the callback is needed,
2923 the HAL_LPTIM_DirectionUpCallback could be implemented in the user file
2924 */
2925 }
2926
2927 /**
2928 * @brief Direction counter changed from Up to Down callback in non-blocking mode.
2929 * @param hlptim LPTIM handle
2930 * @retval None
2931 */
HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef * hlptim)2932 __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
2933 {
2934 /* Prevent unused argument(s) compilation warning */
2935 UNUSED(hlptim);
2936
2937 /* NOTE : This function should not be modified, when the callback is needed,
2938 the HAL_LPTIM_DirectionDownCallback could be implemented in the user file
2939 */
2940 }
2941
2942 /**
2943 * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode.
2944 * @param hlptim LPTIM handle
2945 * @retval None
2946 */
HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef * hlptim)2947 __weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim)
2948 {
2949 /* Prevent unused argument(s) compilation warning */
2950 UNUSED(hlptim);
2951
2952 /* NOTE : This function should not be modified, when the callback is needed,
2953 the HAL_LPTIM_UpdateEventCallback could be implemented in the user file
2954 */
2955 }
2956
2957 /**
2958 * @brief Successful APB bus write to repetition counter register callback in non-blocking mode.
2959 * @param hlptim LPTIM handle
2960 * @retval None
2961 */
HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef * hlptim)2962 __weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim)
2963 {
2964 /* Prevent unused argument(s) compilation warning */
2965 UNUSED(hlptim);
2966
2967 /* NOTE : This function should not be modified, when the callback is needed,
2968 the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file
2969 */
2970 }
2971
2972 /**
2973 * @brief Input Capture callback in non-blocking mode
2974 * @param hlptim LPTIM handle
2975 * @retval None
2976 */
HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef * hlptim)2977 __weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim)
2978 {
2979 /* Prevent unused argument(s) compilation warning */
2980 UNUSED(hlptim);
2981
2982 /* NOTE : This function should not be modified, when the callback is needed,
2983 the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file
2984 */
2985 }
2986
2987 /**
2988 * @brief Over Capture callback in non-blocking mode
2989 * @param hlptim LPTIM handle
2990 * @retval None
2991 */
HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef * hlptim)2992 __weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim)
2993 {
2994 /* Prevent unused argument(s) compilation warning */
2995 UNUSED(hlptim);
2996
2997 /* NOTE : This function should not be modified, when the callback is needed,
2998 the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file
2999 */
3000 }
3001
3002 /**
3003 * @brief Input Capture half complete callback in non-blocking mode
3004 * @param hlptim LPTIM IC handle
3005 * @retval None
3006 */
HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)3007 __weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
3008 {
3009 /* Prevent unused argument(s) compilation warning */
3010 UNUSED(hlptim);
3011
3012 /* NOTE : This function should not be modified, when the callback is needed,
3013 the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file
3014 */
3015 }
3016
3017 /**
3018 * @brief Update event half complete callback in non-blocking mode
3019 * @param hlptim LPTIM handle
3020 * @retval None
3021 */
HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef * hlptim)3022 __weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim)
3023 {
3024 /* Prevent unused argument(s) compilation warning */
3025 UNUSED(hlptim);
3026
3027 /* NOTE : This function should not be modified, when the callback is needed,
3028 the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file
3029 */
3030 }
3031
3032 /**
3033 * @brief Error callback in non-blocking mode
3034 * @param hlptim LPTIM handle
3035 * @retval None
3036 */
HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef * hlptim)3037 __weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim)
3038 {
3039 /* Prevent unused argument(s) compilation warning */
3040 UNUSED(hlptim);
3041
3042 /* NOTE : This function should not be modified, when the callback is needed,
3043 the HAL_LPTIM_ErrorCallback could be implemented in the user file
3044 */
3045 }
3046
3047
3048 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3049 /**
3050 * @brief Register a User LPTIM callback to be used instead of the weak predefined callback
3051 * @param hlptim LPTIM handle
3052 * @param CallbackID ID of the callback to be registered
3053 * This parameter can be one of the following values:
3054 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3055 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3056 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3057 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3058 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3059 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3060 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3061 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3062 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3063 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3064 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3065 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3066 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3067 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3068 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3069 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3070 * @param pCallback pointer to the callback function
3071 * @retval status
3072 */
HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID,pLPTIM_CallbackTypeDef pCallback)3073 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
3074 HAL_LPTIM_CallbackIDTypeDef CallbackID,
3075 pLPTIM_CallbackTypeDef pCallback)
3076 {
3077 HAL_StatusTypeDef status = HAL_OK;
3078
3079 if (pCallback == NULL)
3080 {
3081 return HAL_ERROR;
3082 }
3083
3084 if (hlptim->State == HAL_LPTIM_STATE_READY)
3085 {
3086 switch (CallbackID)
3087 {
3088 case HAL_LPTIM_MSPINIT_CB_ID :
3089 hlptim->MspInitCallback = pCallback;
3090 break;
3091
3092 case HAL_LPTIM_MSPDEINIT_CB_ID :
3093 hlptim->MspDeInitCallback = pCallback;
3094 break;
3095
3096 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3097 hlptim->CompareMatchCallback = pCallback;
3098 break;
3099
3100 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3101 hlptim->AutoReloadMatchCallback = pCallback;
3102 break;
3103
3104 case HAL_LPTIM_TRIGGER_CB_ID :
3105 hlptim->TriggerCallback = pCallback;
3106 break;
3107
3108 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3109 hlptim->CompareWriteCallback = pCallback;
3110 break;
3111
3112 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3113 hlptim->AutoReloadWriteCallback = pCallback;
3114 break;
3115
3116 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3117 hlptim->DirectionUpCallback = pCallback;
3118 break;
3119
3120 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3121 hlptim->DirectionDownCallback = pCallback;
3122 break;
3123
3124 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3125 hlptim->UpdateEventCallback = pCallback;
3126 break;
3127
3128 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3129 hlptim->RepCounterWriteCallback = pCallback;
3130 break;
3131
3132 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3133 hlptim->UpdateEventHalfCpltCallback = pCallback;
3134 break;
3135
3136 case HAL_LPTIM_ERROR_CB_ID :
3137 hlptim->ErrorCallback = pCallback;
3138 break;
3139
3140 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3141 hlptim->IC_CaptureCallback = pCallback;
3142 break;
3143
3144 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3145 hlptim->IC_CaptureHalfCpltCallback = pCallback;
3146 break;
3147
3148 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3149 hlptim->IC_OverCaptureCallback = pCallback;
3150 break;
3151
3152 default :
3153 /* Return error status */
3154 status = HAL_ERROR;
3155 break;
3156 }
3157 }
3158 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3159 {
3160 switch (CallbackID)
3161 {
3162 case HAL_LPTIM_MSPINIT_CB_ID :
3163 hlptim->MspInitCallback = pCallback;
3164 break;
3165
3166 case HAL_LPTIM_MSPDEINIT_CB_ID :
3167 hlptim->MspDeInitCallback = pCallback;
3168 break;
3169
3170 default :
3171 /* Return error status */
3172 status = HAL_ERROR;
3173 break;
3174 }
3175 }
3176 else
3177 {
3178 /* Return error status */
3179 status = HAL_ERROR;
3180 }
3181
3182 return status;
3183 }
3184
3185 /**
3186 * @brief Unregister a LPTIM callback
3187 * LLPTIM callback is redirected to the weak predefined callback
3188 * @param hlptim LPTIM handle
3189 * @param CallbackID ID of the callback to be unregistered
3190 * This parameter can be one of the following values:
3191 * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID
3192 * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID
3193 * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID
3194 * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID
3195 * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID
3196 * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID
3197 * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID
3198 * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID
3199 * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID
3200 * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID
3201 * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID
3202 * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID
3203 * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID
3204 * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID
3205 * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
3206 * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID
3207 * @retval status
3208 */
HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef * hlptim,HAL_LPTIM_CallbackIDTypeDef CallbackID)3209 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
3210 HAL_LPTIM_CallbackIDTypeDef CallbackID)
3211 {
3212 HAL_StatusTypeDef status = HAL_OK;
3213
3214 if (hlptim->State == HAL_LPTIM_STATE_READY)
3215 {
3216 switch (CallbackID)
3217 {
3218 case HAL_LPTIM_MSPINIT_CB_ID :
3219 /* Legacy weak MspInit Callback */
3220 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3221 break;
3222
3223 case HAL_LPTIM_MSPDEINIT_CB_ID :
3224 /* Legacy weak Msp DeInit Callback */
3225 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3226 break;
3227
3228 case HAL_LPTIM_COMPARE_MATCH_CB_ID :
3229 /* Legacy weak Compare match Callback */
3230 hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3231 break;
3232
3233 case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
3234 /* Legacy weak Auto-reload match Callback */
3235 hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3236 break;
3237
3238 case HAL_LPTIM_TRIGGER_CB_ID :
3239 /* Legacy weak External trigger event detection Callback */
3240 hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3241 break;
3242
3243 case HAL_LPTIM_COMPARE_WRITE_CB_ID :
3244 /* Legacy weak Compare register write complete Callback */
3245 hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3246 break;
3247
3248 case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
3249 /* Legacy weak Auto-reload register write complete Callback */
3250 hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3251 break;
3252
3253 case HAL_LPTIM_DIRECTION_UP_CB_ID :
3254 /* Legacy weak Up-counting direction change Callback */
3255 hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3256 break;
3257
3258 case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
3259 /* Legacy weak Down-counting direction change Callback */
3260 hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3261 break;
3262
3263 case HAL_LPTIM_UPDATE_EVENT_CB_ID :
3264 /* Legacy weak Update event detection Callback */
3265 hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3266 break;
3267
3268 case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID :
3269 /* Legacy weak Repetition counter register write complete Callback */
3270 hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3271 break;
3272
3273 case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID :
3274 /* Legacy weak Update event half complete detection Callback */
3275 hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3276 break;
3277
3278 case HAL_LPTIM_ERROR_CB_ID :
3279 /* Legacy weak error Callback */
3280 hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3281 break;
3282
3283 case HAL_LPTIM_IC_CAPTURE_CB_ID :
3284 /* Legacy weak IC Capture Callback */
3285 hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3286 break;
3287
3288 case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID :
3289 /* Legacy weak IC Capture half complete Callback */
3290 hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3291 break;
3292
3293 case HAL_LPTIM_OVER_CAPTURE_CB_ID :
3294 /* Legacy weak IC over capture Callback */
3295 hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3296 break;
3297
3298 default :
3299 /* Return error status */
3300 status = HAL_ERROR;
3301 break;
3302 }
3303 }
3304 else if (hlptim->State == HAL_LPTIM_STATE_RESET)
3305 {
3306 switch (CallbackID)
3307 {
3308 case HAL_LPTIM_MSPINIT_CB_ID :
3309 /* Legacy weak MspInit Callback */
3310 hlptim->MspInitCallback = HAL_LPTIM_MspInit;
3311 break;
3312
3313 case HAL_LPTIM_MSPDEINIT_CB_ID :
3314 /* Legacy weak Msp DeInit Callback */
3315 hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
3316 break;
3317
3318 default :
3319 /* Return error status */
3320 status = HAL_ERROR;
3321 break;
3322 }
3323 }
3324 else
3325 {
3326 /* Return error status */
3327 status = HAL_ERROR;
3328 }
3329
3330 return status;
3331 }
3332 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3333
3334 /**
3335 * @}
3336 */
3337
3338 /** @defgroup LPTIM_Group5 Peripheral State functions
3339 * @brief Peripheral State functions.
3340 *
3341 @verbatim
3342 ==============================================================================
3343 ##### Peripheral State functions #####
3344 ==============================================================================
3345 [..]
3346 This subsection permits to get in run-time the status of the peripheral.
3347
3348 @endverbatim
3349 * @{
3350 */
3351
3352 /**
3353 * @brief Return the LPTIM handle state.
3354 * @param hlptim LPTIM handle
3355 * @retval HAL state
3356 */
HAL_LPTIM_GetState(const LPTIM_HandleTypeDef * hlptim)3357 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
3358 {
3359 /* Return LPTIM handle state */
3360 return hlptim->State;
3361 }
3362
3363 /**
3364 * @}
3365 */
3366
3367
3368 /**
3369 * @}
3370 */
3371
3372 /* Private functions ---------------------------------------------------------*/
3373
3374 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
3375 * @{
3376 */
3377 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3378 /**
3379 * @brief Reset interrupt callbacks to the legacy weak callbacks.
3380 * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains
3381 * the configuration information for LPTIM module.
3382 * @retval None
3383 */
LPTIM_ResetCallback(LPTIM_HandleTypeDef * lptim)3384 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
3385 {
3386 /* Reset the LPTIM callback to the legacy weak callbacks */
3387 lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
3388 lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
3389 lptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
3390 lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
3391 lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
3392 lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
3393 lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
3394 lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback;
3395 lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback;
3396 lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback;
3397 lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback;
3398 lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback;
3399 lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback;
3400 lptim->ErrorCallback = HAL_LPTIM_ErrorCallback;
3401 }
3402 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3403
3404 /**
3405 * @brief LPTimer Wait for flag set
3406 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3407 * the configuration information for LPTIM module.
3408 * @param flag The lptim flag
3409 * @retval HAL status
3410 */
LPTIM_WaitForFlag(const LPTIM_HandleTypeDef * hlptim,uint32_t flag)3411 static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
3412 {
3413 HAL_StatusTypeDef result = HAL_OK;
3414 uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
3415 do
3416 {
3417 count--;
3418 if (count == 0UL)
3419 {
3420 result = HAL_TIMEOUT;
3421 }
3422 } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
3423
3424 return result;
3425 }
3426
3427 /**
3428 * @brief LPTIM DMA error callback
3429 * @param hdma pointer to DMA handle.
3430 * @retval None
3431 */
LPTIM_DMAError(DMA_HandleTypeDef * hdma)3432 void LPTIM_DMAError(DMA_HandleTypeDef *hdma)
3433 {
3434 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3435
3436 hlptim->State = HAL_LPTIM_STATE_READY;
3437
3438 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3439 hlptim->ErrorCallback(hlptim);
3440 #else
3441 HAL_LPTIM_ErrorCallback(hlptim);
3442 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3443 }
3444
3445 /**
3446 * @brief LPTIM DMA Capture complete callback.
3447 * @param hdma pointer to DMA handle.
3448 * @retval None
3449 */
LPTIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)3450 void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
3451 {
3452 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3453
3454 hlptim->State = HAL_LPTIM_STATE_READY;
3455
3456 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3457 {
3458 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3459 }
3460 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3461 {
3462 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3463 }
3464 else
3465 {
3466 /* nothing to do */
3467 }
3468
3469 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3470 hlptim->IC_CaptureCallback(hlptim);
3471 #else
3472 HAL_LPTIM_IC_CaptureCallback(hlptim);
3473 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3474
3475 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3476 }
3477
3478 /**
3479 * @brief LPTIM DMA Capture half complete callback.
3480 * @param hdma pointer to DMA handle.
3481 * @retval None
3482 */
LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)3483 void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
3484 {
3485 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3486
3487 hlptim->State = HAL_LPTIM_STATE_READY;
3488
3489 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3490 {
3491 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3492 }
3493 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3494 {
3495 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3496 }
3497 else
3498 {
3499 /* nothing to do */
3500 }
3501
3502 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3503 hlptim->IC_CaptureHalfCpltCallback(hlptim);
3504 #else
3505 HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim);
3506 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3507
3508 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3509 }
3510
3511 /**
3512 * @brief LPTIM DMA Update event complete callback.
3513 * @param hdma pointer to DMA handle.
3514 * @retval None
3515 */
LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef * hdma)3516 void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma)
3517 {
3518 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3519
3520 hlptim->State = HAL_LPTIM_STATE_READY;
3521
3522 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3523 {
3524 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3525 }
3526 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3527 {
3528 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3529 }
3530 else
3531 {
3532 /* nothing to do */
3533 }
3534
3535 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3536 hlptim->UpdateEventCallback(hlptim);
3537 #else
3538 HAL_LPTIM_UpdateEventCallback(hlptim);
3539 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3540
3541 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3542 }
3543
3544 /**
3545 * @brief LPTIM DMA Capture half complete callback.
3546 * @param hdma pointer to DMA handle.
3547 * @retval None
3548 */
LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef * hdma)3549 void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma)
3550 {
3551 LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3552
3553 hlptim->State = HAL_LPTIM_STATE_READY;
3554
3555 if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1])
3556 {
3557 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1;
3558 }
3559 else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2])
3560 {
3561 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2;
3562 }
3563 else
3564 {
3565 /* nothing to do */
3566 }
3567
3568 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
3569 hlptim->UpdateEventHalfCpltCallback(hlptim);
3570 #else
3571 HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim);
3572 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
3573
3574 hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED;
3575 }
3576 /**
3577 * @brief LPTimer Output Compare 1 configuration
3578 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3579 * the configuration information for LPTIM module.
3580 * @param sConfig The output configuration structure
3581 * @retval None
3582 */
LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3583 static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3584 {
3585 uint32_t tmpccmr1;
3586 uint32_t tmpcfgr;
3587
3588 tmpccmr1 = hlptim->Instance->CCMR1;
3589 tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk);
3590
3591 if ((hlptim->Instance == LPTIM4) || (hlptim->Instance == LPTIM5))
3592 {
3593 tmpcfgr = hlptim->Instance->CFGR;
3594 tmpcfgr &= ~LPTIM_CFGR_WAVPOL_Msk;
3595 tmpcfgr |= sConfig->OCPolarity << LPTIM_CFGR_WAVPOL_Pos;
3596
3597 /* Write to CFGR register */
3598 hlptim->Instance->CFGR = tmpcfgr;
3599 }
3600 else
3601 {
3602 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos;
3603 }
3604
3605 /* Enable the Peripheral */
3606 __HAL_LPTIM_ENABLE(hlptim);
3607
3608 /* Clear flag */
3609 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK);
3610
3611 /* Write to CCR1 register */
3612 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse);
3613
3614 /* Wait for the completion of the write operation to the LPTIM_CCR1 register */
3615 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT)
3616 {
3617 return HAL_TIMEOUT;
3618 }
3619
3620 /* Disable the Peripheral */
3621 __HAL_LPTIM_DISABLE(hlptim);
3622
3623 /* Write to CCMR1 register */
3624 hlptim->Instance->CCMR1 = tmpccmr1;
3625
3626 return HAL_OK;
3627 }
3628
3629 /**
3630 * @brief LPTimer Output Compare 2 configuration
3631 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3632 * the configuration information for LPTIM module.
3633 * @param sConfig The output configuration structure
3634 * @retval None
3635 */
LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_OC_ConfigTypeDef * sConfig)3636 static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig)
3637 {
3638 uint32_t tmpccmr1;
3639
3640 tmpccmr1 = hlptim->Instance->CCMR1;
3641 tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk);
3642 tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos;
3643
3644 /* Enable the Peripheral */
3645 __HAL_LPTIM_ENABLE(hlptim);
3646
3647 /* Clear flag */
3648 __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK);
3649
3650 /* Write to CCR2 register */
3651 __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse);
3652
3653 /* Wait for the completion of the write operation to the LPTIM_CCR2 register */
3654 if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK)
3655 {
3656 return HAL_TIMEOUT;
3657 }
3658
3659 /* Disable the Peripheral */
3660 __HAL_LPTIM_DISABLE(hlptim);
3661
3662 /* Write to CCMR1 register */
3663 hlptim->Instance->CCMR1 = tmpccmr1;
3664
3665 return HAL_OK;
3666 }
3667
3668 /**
3669 * @brief LPTimer Input Capture 1 configuration
3670 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3671 * the configuration information for LPTIM module.
3672 * @param sConfig The input configuration structure
3673 * @retval None
3674 */
LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3675 static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3676 {
3677 uint32_t tmpccmr1;
3678 uint32_t tmpcfgr2;
3679
3680 tmpccmr1 = hlptim->Instance->CCMR1;
3681 tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk);
3682 tmpccmr1 |= sConfig->ICPrescaler |
3683 sConfig->ICPolarity |
3684 sConfig->ICFilter |
3685 LPTIM_CCMR1_CC1SEL;
3686
3687 tmpcfgr2 = hlptim->Instance->CFGR2;
3688 tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk);
3689 tmpcfgr2 |= sConfig->ICInputSource;
3690
3691 /* Write to CCMR1 register */
3692 hlptim->Instance->CCMR1 = tmpccmr1;
3693
3694 /* Write to CFGR2 register */
3695 hlptim->Instance->CFGR2 = tmpcfgr2;
3696 }
3697
3698 /**
3699 * @brief LPTimer Input Capture 2 configuration
3700 * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
3701 * the configuration information for LPTIM module.
3702 * @param sConfig The input configuration structure
3703 * @retval None
3704 */
LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef * hlptim,const LPTIM_IC_ConfigTypeDef * sConfig)3705 static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig)
3706 {
3707 uint32_t tmpccmr1;
3708 uint32_t tmpcfgr2;
3709
3710 tmpccmr1 = hlptim->Instance->CCMR1;
3711 tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk);
3712 tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) |
3713 (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) |
3714 (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) |
3715 LPTIM_CCMR1_CC2SEL;
3716
3717 tmpcfgr2 = hlptim->Instance->CFGR2;
3718 tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk);
3719 tmpcfgr2 |= sConfig->ICInputSource;
3720
3721 /* Write to CCMR1 register */
3722 hlptim->Instance->CCMR1 = tmpccmr1;
3723
3724 /* Write to CFGR2 register */
3725 hlptim->Instance->CFGR2 = tmpcfgr2;
3726 }
3727
3728 /**
3729 * @brief Start the DMA data transfer.
3730 * @param hdma DMA handle
3731 * @param src The source memory Buffer address.
3732 * @param dst The destination memory Buffer address.
3733 * @param length The size of a source block transfer in byte.
3734 * @retval HAL status
3735 */
LPTIM_DMA_Start_IT(DMA_HandleTypeDef * hdma,uint32_t src,uint32_t dst,uint32_t length)3736 HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst,
3737 uint32_t length)
3738 {
3739 HAL_StatusTypeDef status;
3740
3741 /* Enable the DMA channel */
3742 if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3743 {
3744 if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U))
3745 {
3746 /* Enable the DMA channel */
3747 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length;
3748 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src;
3749 hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst;
3750
3751 status = HAL_DMAEx_List_Start_IT(hdma);
3752 }
3753 else
3754 {
3755 status = HAL_ERROR;
3756 }
3757 }
3758 else
3759 {
3760 status = HAL_DMA_Start_IT(hdma, src, dst, length);
3761 }
3762
3763 return status;
3764 }
3765 /**
3766 * @}
3767 */
3768 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
3769
3770 #endif /* HAL_LPTIM_MODULE_ENABLED */
3771 /**
3772 * @}
3773 */
3774
3775 /**
3776 * @}
3777 */
3778
