1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32H7RSxx_LL_UTILS_H
33 #define STM32H7RSxx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32h7rsxx.h"
41 #include "stm32h7rsxx_ll_system.h"
42 #include "stm32h7rsxx_ll_bus.h"
43 #include "stm32h7rsxx_ll_rcc.h"
44
45 /** @addtogroup STM32H7RSxx_LL_Driver
46 * @{
47 */
48
49 /** @defgroup UTILS_LL UTILS
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
58 * @{
59 */
60
61 /* Max delay can be used in LL_mDelay */
62 #define LL_MAX_DELAY 0xFFFFFFFFU
63
64 /**
65 * @brief Unique device ID register base address
66 */
67 #define UID_BASE_ADDRESS UID_BASE
68
69 /**
70 * @brief Flash size data register base address
71 */
72 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
73
74 /**
75 * @brief Package data register base address
76 */
77 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
78
79 /**
80 * @}
81 */
82
83 /* Private macros ------------------------------------------------------------*/
84 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
85 * @{
86 */
87 /**
88 * @}
89 */
90 /* Exported types ------------------------------------------------------------*/
91 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
92 * @{
93 */
94 /**
95 * @brief UTILS PLL structure definition
96 */
97 typedef struct
98 {
99 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
100 This parameter must be a number between Min_Data = 0 and Max_Data = 63
101
102 This feature can be modified afterwards using unitary function
103 @ref LL_RCC_PLL1_SetM(). */
104
105 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
106 This parameter must be a number between Min_Data = 4 and Max_Data = 512
107
108 This feature can be modified afterwards using unitary function
109 @ref LL_RCC_PLL1_SetN(). */
110
111 uint32_t PLLP; /*!< Division for the main system clock.
112 This parameter must be a number between Min_Data = 2 and Max_Data = 128
113 odd division factors are not allowed
114
115 This feature can be modified afterwards using unitary function
116 @ref LL_RCC_PLL1_SetP(). */
117
118 uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO.
119 This parameter can be a value between 0 and 8191
120
121 This feature can be modified afterwards using unitary function
122 @ref LL_RCC_PLL1_SetFRACN(). */
123
124 uint32_t VCO_Input; /*!< PLL clock Input range.
125 This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
126
127 This feature can be modified afterwards using unitary function
128 @ref LL_RCC_PLL1_SetVCOInputRange(). */
129
130 uint32_t VCO_Output; /*!< PLL clock Output range.
131 This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
132
133 This feature can be modified afterwards using unitary function
134 @ref LL_RCC_PLL1_SetVCOOutputRange(). */
135
136 } LL_UTILS_PLLInitTypeDef;
137
138 /**
139 * @brief UTILS System, AHB and APB buses clock configuration structure definition
140 */
141 typedef struct
142 {
143 uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
144 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
145
146 This feature can be modified afterwards using unitary function
147 @ref LL_RCC_SetSysPrescaler(). */
148
149 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
150 This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
151
152 This feature can be modified afterwards using unitary function
153 @ref LL_RCC_SetAHBPrescaler(). */
154
155 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
156 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
157
158 This feature can be modified afterwards using unitary function
159 @ref LL_RCC_SetAPB1Prescaler(). */
160
161 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
162 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
163
164 This feature can be modified afterwards using unitary function
165 @ref LL_RCC_SetAPB2Prescaler(). */
166
167 uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
168 This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
169
170 This feature can be modified afterwards using unitary function
171 @ref LL_RCC_SetAPB4Prescaler(). */
172
173 uint32_t APB5CLKDivider; /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AHB clock (HCLK).
174 This parameter can be a value of @ref RCC_LL_EC_APB5_DIV
175
176 This feature can be modified afterwards using unitary function
177 @ref LL_RCC_SetAPB5Prescaler(). */
178
179 } LL_UTILS_ClkInitTypeDef;
180
181 /**
182 * @}
183 */
184
185 /* Exported constants --------------------------------------------------------*/
186 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
187 * @{
188 */
189
190 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
191 * @{
192 */
193 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
194 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
195 /**
196 * @}
197 */
198
199 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
200 * @{
201 */
202 #define LL_UTILS_PACKAGETYPE_VFQFPN68_GP 0U /*!< VFQFPN68 GP package type */
203 #define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS_GP 1U /*!< TFBGA100 SMPS GP package type */
204 #define LL_UTILS_PACKAGETYPE_LQFP100_GP 2U /*!< LQFP100 GP package type */
205 #define LL_UTILS_PACKAGETYPE_LQFP144_GP 3U /*!< LQFP144 GP package type */
206 #define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GP 4U /*!< UFBGA144 SMPS GP package type */
207 #define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GFX 5U /*!< UFBGA144 SMPS GFX package type */
208 #define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GFX 6U /*!< UFBGA169 SMPS GFX package type */
209 #define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GP 7U /*!< UFBGA169 SMPS GP package type */
210 #define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GP 8U /*!< UFBGA176+25 SMPS GP package type */
211 #define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GP 9U /*!< LQFP176 SMPS GP package type */
212 #define LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GFX 10U /*!< LQFP176 SMPS GFX package type */
213 #define LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GFX 11U /*!< UFBGA176+25 SMPS GFX package type */
214 #define LL_UTILS_PACKAGETYPE_TFBGA225_OCTO 12U /*!< TFBGA225 OCTO package type */
215 #define LL_UTILS_PACKAGETYPE_TFBGA225_HEXA 13U /*!< TFBGA225 HEXA package type */
216 #define LL_UTILS_PACKAGETYPE_WLCSP_SMPS_GP 14U /*!< WLCSP SMPS GP package type */
217 /**
218 * @}
219 */
220
221 /**
222 * @}
223 */
224
225 /* Exported macro ------------------------------------------------------------*/
226
227 /* Exported functions --------------------------------------------------------*/
228 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
229 * @{
230 */
231
232 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
233 * @{
234 */
235
236 /**
237 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
238 * @note The read address belongs to an area which may contain virgin data generating
239 * double ECC error (as never programmed). Thus, in case of cache activation
240 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
241 * through the MPU.
242 * @retval UID[31:0]
243 */
LL_GetUID_Word0(void)244 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
245 {
246 return (uint32_t)(READ_REG(*((__IO uint32_t *)UID_BASE_ADDRESS)));
247 }
248
249 /**
250 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
251 * @note The read address belongs to an area which may contain virgin data generating
252 * double ECC error (as never programmed). Thus, in case of cache activation
253 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
254 * through the MPU.
255 * @retval UID[63:32]
256 */
LL_GetUID_Word1(void)257 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
258 {
259 return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 4U))));
260 }
261
262 /**
263 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
264 * @note The read address belongs to an area which may contain virgin data generating
265 * double ECC error (as never programmed). Thus, in case of cache activation
266 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
267 * through the MPU.
268 * @retval UID[95:64]
269 */
LL_GetUID_Word2(void)270 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
271 {
272 return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U))));
273 }
274
275 /**
276 * @brief Get Flash memory size
277 * @note This bitfield indicates the size of the device Flash memory expressed in
278 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
279 * @note The read address belongs to an area which may contain virgin data generating
280 * double ECC error (as never programmed). Thus, in case of cache activation
281 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
282 * through the MPU.
283 * @retval FLASH_SIZE[15:0]: Flash memory size
284 */
LL_GetFlashSize(void)285 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
286 {
287 return (uint32_t)((READ_REG(*((__IO uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF0000UL) >> 16UL);
288 }
289
290 /**
291 * @brief Get Package type
292 * @note The read address belongs to an area which may contain virgin data generating
293 * double ECC error (as never programmed). Thus, in case of cache activation
294 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
295 * through the MPU.
296 * @retval Returned value can be one of the following values:
297 * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_GP
298 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS_GP
299 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_GP
300 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_GP
301 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GP
302 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS_GFX
303 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GFX
304 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS_GP
305 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GP
306 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GP
307 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS_GFX
308 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_25_SMPS_GFX
309 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225_OCTO
310 * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225_HEXA
311 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP_SMPS_GP
312 */
LL_GetPackageType(void)313 __STATIC_INLINE uint32_t LL_GetPackageType(void)
314 {
315 return (uint32_t)(READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0FUL);
316 }
317
318 /**
319 * @}
320 */
321
322 /** @defgroup UTILS_LL_EF_DELAY DELAY
323 * @{
324 */
325
326 /**
327 * @brief This function configures the Cortex-M SysTick source of the time base.
328 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
329 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
330 * configuration by calling this function, for a delay use rather osDelay RTOS service.
331 * @param Ticks Number of ticks
332 * @retval None
333 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)334 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
335 {
336 if (Ticks > 0U)
337 {
338 /* Configure the SysTick to have interrupt in 1ms time base */
339 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
340 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
341 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
342 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
343 }
344 }
345
346 void LL_Init1msTick(uint32_t CPU_Frequency);
347 void LL_mDelay(uint32_t Delay);
348
349 /**
350 * @}
351 */
352
353 /** @defgroup UTILS_EF_SYSTEM SYSTEM
354 * @{
355 */
356
357 void LL_SetSystemCoreClock(uint32_t CPU_Frequency);
358 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
359 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
360 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
361 ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
362 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
363 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
364 uint32_t HSEBypass,
365 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
366 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
367
368 /**
369 * @}
370 */
371
372 /**
373 * @}
374 */
375
376 /**
377 * @}
378 */
379
380 /**
381 * @}
382 */
383
384 #ifdef __cplusplus
385 }
386 #endif
387
388 #endif /* STM32H7RSxx_LL_UTILS_H */
389
