1 /**
2   ******************************************************************************
3   * @file    stm32h7rsxx_ll_i3c.h
4   * @author  MCD Application Team
5   * @brief   Header file of I3C LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2022 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_LL_I3C_H
21 #define STM32H7RSxx_LL_I3C_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29 
30 /** @addtogroup STM32H7RSxx_LL_Driver
31   * @{
32   */
33 
34 #if defined (I3C1)
35 
36 /** @defgroup I3C_LL I3C
37   * @{
38   */
39 
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 
43 /* Private constants ---------------------------------------------------------*/
44 
45 /* Private macros ------------------------------------------------------------*/
46 /** @defgroup I3C_LL_Private_Macros I3C Private Macros
47   * @{
48   */
49 #if !defined(UNUSED)
50 #define UNUSED(x) ((void)(x))
51 #endif /* !UNUSED */
52 /**
53   * @}
54   */
55 
56 /* Exported types ------------------------------------------------------------*/
57 /** @defgroup I3C_LL_ES_CONTROLLER_BUS_CONFIG_STRUCTURE_DEFINITION I3C Controller Bus Configuration Structure definition
58   * @brief    I3C LL Controller Bus Configuration Structure definition
59   * @{
60   */
61 typedef struct
62 {
63   uint32_t SDAHoldTime;         /*!< Specifies the I3C SDA hold time.
64                                      This parameter must be a value of @ref I3C_LL_EC_SDA_HOLD_TIME                   */
65 
66   uint32_t WaitTime;            /*!< Specifies the time that the main and the new controllers should wait before
67                                      issuing a start.
68                                      This parameter must be a value of @ref I3C_LL_EC_OWN_ACTIVITY_STATE              */
69 
70   uint8_t SCLPPLowDuration;     /*!< Specifies the I3C SCL low duration in number of kernel clock cycles
71                                      in I3C push-pull phases.
72                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
73 
74   uint8_t SCLI3CHighDuration;   /*!< Specifies the I3C SCL high duration in number of kernel clock cycles,
75                                      used for I3C messages for I3C open-drain and push pull phases.
76                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
77 
78   uint8_t SCLODLowDuration;     /*!< Specifies the I3C SCL low duration in number of kernel clock cycles in
79                                      open-drain phases, used for legacy I2C commands and for I3C open-drain phases.
80                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
81 
82   uint8_t SCLI2CHighDuration;   /*!< Specifies the I3C SCL high duration in number of kernel clock cycles, used
83                                      for legacy I2C commands.
84                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
85 
86   uint8_t BusFreeDuration;      /*!< Specifies the I3C controller duration in number of kernel clock cycles, after
87                                      a stop and before a start.
88                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
89 
90   uint8_t BusIdleDuration;      /*!< Specifies the I3C controller duration in number of kernel clock cycles to be
91                                      elapsed, after that both SDA and SCL are continuously high and stable
92                                      before issuing a hot-join event.
93                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
94 } LL_I3C_CtrlBusConfTypeDef;
95 /**
96   * @}
97   */
98 
99 /** @defgroup I3C_LL_ES_TARGET_BUS_CONFIG_STRUCTURE_DEFINITION I3C Target Bus Configuration Structure definition
100   * @brief    I3C LL Target Bus Configuration Structure definition
101   * @{
102   */
103 typedef struct
104 {
105   uint8_t BusAvailableDuration; /*!< Specifies the I3C target duration in number of kernel clock cycles, when
106                                      the SDA and the SCL are high for at least taval.
107                                      This parameter must be a number between Min_Data=0 and Max_Data=0xFF.            */
108 } LL_I3C_TgtBusConfTypeDef;
109 /**
110   * @}
111   */
112 #if defined(USE_FULL_LL_DRIVER)
113 
114 /** @defgroup I3C_LL_ES_INIT I3C Exported Init structure
115   * @brief    I3C LL Init Structure definition
116   * @{
117   */
118 typedef struct
119 {
120   LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration
121                                                         when Controller mode                                          */
122 
123   LL_I3C_TgtBusConfTypeDef  TgtBusCharacteristic;  /*!< Specifies the I3C target bus characteristic configuration
124                                                         when Target mode                                              */
125 
126 } LL_I3C_InitTypeDef;
127 /**
128   * @}
129   */
130 #endif /* USE_FULL_LL_DRIVER */
131 
132 /* Exported constants --------------------------------------------------------*/
133 /** @defgroup I3C_LL_Exported_Constants I3C Exported Constants
134   * @{
135   */
136 
137 /** @defgroup I3C_LL_EC_GET_FLAG Get Flags Defines
138   * @brief    Flags defines which can be used with LL_I3C_ReadReg function
139   * @{
140   */
141 #define LL_I3C_EVR_CFEF                    I3C_EVR_CFEF
142 #define LL_I3C_EVR_TXFEF                   I3C_EVR_TXFEF
143 #define LL_I3C_EVR_CFNFF                   I3C_EVR_CFNFF
144 #define LL_I3C_EVR_SFNEF                   I3C_EVR_SFNEF
145 #define LL_I3C_EVR_TXFNFF                  I3C_EVR_TXFNFF
146 #define LL_I3C_EVR_RXFNEF                  I3C_EVR_RXFNEF
147 #define LL_I3C_EVR_RXLASTF                 I3C_EVR_RXLASTF
148 #define LL_I3C_EVR_TXLASTF                 I3C_EVR_TXLASTF
149 #define LL_I3C_EVR_FCF                     I3C_EVR_FCF
150 #define LL_I3C_EVR_RXTGTENDF               I3C_EVR_RXTGTENDF
151 #define LL_I3C_EVR_ERRF                    I3C_EVR_ERRF
152 #define LL_I3C_EVR_IBIF                    I3C_EVR_IBIF
153 #define LL_I3C_EVR_IBIENDF                 I3C_EVR_IBIENDF
154 #define LL_I3C_EVR_CRF                     I3C_EVR_CRF
155 #define LL_I3C_EVR_CRUPDF                  I3C_EVR_CRUPDF
156 #define LL_I3C_EVR_HJF                     I3C_EVR_HJF
157 #define LL_I3C_EVR_WKPF                    I3C_EVR_WKPF
158 #define LL_I3C_EVR_GETF                    I3C_EVR_GETF
159 #define LL_I3C_EVR_STAF                    I3C_EVR_STAF
160 #define LL_I3C_EVR_DAUPDF                  I3C_EVR_DAUPDF
161 #define LL_I3C_EVR_MWLUPDF                 I3C_EVR_MWLUPDF
162 #define LL_I3C_EVR_MRLUPDF                 I3C_EVR_MRLUPDF
163 #define LL_I3C_EVR_RSTF                    I3C_EVR_RSTF
164 #define LL_I3C_EVR_ASUPDF                  I3C_EVR_ASUPDF
165 #define LL_I3C_EVR_INTUPDF                 I3C_EVR_INTUPDF
166 #define LL_I3C_EVR_DEFF                    I3C_EVR_DEFF
167 #define LL_I3C_EVR_GRPF                    I3C_EVR_GRPF
168 #define LL_I3C_SER_PERR                    I3C_SER_PERR
169 #define LL_I3C_SER_STALL                   I3C_SER_STALL
170 #define LL_I3C_SER_DOVR                    I3C_SER_DOVR
171 #define LL_I3C_SER_COVR                    I3C_SER_COVR
172 #define LL_I3C_SER_ANACK                   I3C_SER_ANACK
173 #define LL_I3C_SER_DNACK                   I3C_SER_DNACK
174 #define LL_I3C_SER_DERR                    I3C_SER_DERR
175 /**
176   * @}
177   */
178 
179 /** @defgroup I3C_LL_EC_IT IT Defines
180   * @brief    IT defines which can be used with LL_I3C_ReadReg and  LL_I3C_WriteReg functions
181   * @{
182   */
183 #define LL_I3C_IER_CFNFIE                  I3C_IER_CFNFIE
184 #define LL_I3C_IER_SFNEIE                  I3C_IER_SFNEIE
185 #define LL_I3C_IER_TXFNFIE                 I3C_IER_TXFNFIE
186 #define LL_I3C_IER_RXFNEIE                 I3C_IER_RXFNEIE
187 #define LL_I3C_IER_FCIE                    I3C_IER_FCIE
188 #define LL_I3C_IER_RXTGTENDIE              I3C_IER_RXTGTENDIE
189 #define LL_I3C_IER_ERRIE                   I3C_IER_ERRIE
190 #define LL_I3C_IER_IBIIE                   I3C_IER_IBIIE
191 #define LL_I3C_IER_IBIENDIE                I3C_IER_IBIENDIE
192 #define LL_I3C_IER_CRIE                    I3C_IER_CRIE
193 #define LL_I3C_IER_CRUPDIE                 I3C_IER_CRUPDIE
194 #define LL_I3C_IER_HJIE                    I3C_IER_HJIE
195 #define LL_I3C_IER_WKPIE                   I3C_IER_WKPIE
196 #define LL_I3C_IER_GETIE                   I3C_IER_GETIE
197 #define LL_I3C_IER_STAIE                   I3C_IER_STAIE
198 #define LL_I3C_IER_DAUPDIE                 I3C_IER_DAUPDIE
199 #define LL_I3C_IER_MWLUPDIE                I3C_IER_MWLUPDIE
200 #define LL_I3C_IER_MRLUPDIE                I3C_IER_MRLUPDIE
201 #define LL_I3C_IER_RSTIE                   I3C_IER_RSTIE
202 #define LL_I3C_IER_ASUPDIE                 I3C_IER_ASUPDIE
203 #define LL_I3C_IER_INTUPDIE                I3C_IER_INTUPDIE
204 #define LL_I3C_IER_DEFIE                   I3C_IER_DEFIE
205 #define LL_I3C_IER_GRPIE                   I3C_IER_GRPIE
206 /**
207   * @}
208   */
209 
210 /** @defgroup I3C_LL_EC_MODE MODE
211   * @{
212   */
213 #define LL_I3C_MODE_CONTROLLER              I3C_CFGR_CRINIT         /*!< I3C Controller mode */
214 #define LL_I3C_MODE_TARGET                  0x00000000U             /*!< I3C Target (Controller capable) mode */
215 /**
216   * @}
217   */
218 
219 /** @defgroup I3C_LL_EC_DMA_REG_DATA DMA Register Data
220   * @{
221   */
222 #define LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE   0x00000000U              /*!< Get address of data register used
223                                                                           for transmission in Byte */
224 #define LL_I3C_DMA_REG_DATA_RECEIVE_BYTE    0x00000001U              /*!< Get address of data register used
225                                                                           for reception in Byte */
226 #define LL_I3C_DMA_REG_DATA_TRANSMIT_WORD   0x00000002U              /*!< Get address of data register used for
227                                                                           transmission in Word */
228 #define LL_I3C_DMA_REG_DATA_RECEIVE_WORD    0x00000003U              /*!< Get address of data register used
229                                                                           for reception in Word */
230 #define LL_I3C_DMA_REG_STATUS               0x00000004U              /*!< Get address of status register used
231                                                                           for transfer status in Word */
232 #define LL_I3C_DMA_REG_CONTROL              0x00000005U              /*!< Get address of control register used
233                                                                           for transfer control in Word */
234 /**
235   * @}
236   */
237 
238 /** @defgroup I3C_LL_EC_RX_THRESHOLD RX THRESHOLD
239   * @{
240   */
241 #define LL_I3C_RXFIFO_THRESHOLD_1_4         0x00000000U
242 /*!< Rx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */
243 #define LL_I3C_RXFIFO_THRESHOLD_4_4         I3C_CFGR_RXTHRES
244 /*!< Rx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */
245 /**
246   * @}
247   */
248 
249 /** @defgroup I3C_LL_EC_TX_THRESHOLD TX THRESHOLD
250   * @{
251   */
252 #define LL_I3C_TXFIFO_THRESHOLD_1_4         0x00000000U
253 /*!< Tx Fifo Threshold is 1 byte in a Fifo depth of 4 bytes */
254 #define LL_I3C_TXFIFO_THRESHOLD_4_4         I3C_CFGR_TXTHRES
255 /*!< Tx Fifo Threshold is 4 bytes in a Fifo depth of 4 bytes */
256 /**
257   * @}
258   */
259 
260 /** @defgroup I3C_LL_EC_PAYLOAD PAYLOAD
261   * @{
262   */
263 #define LL_I3C_PAYLOAD_EMPTY               0x00000000U
264 /*!< Empty payload, no additional data after IBI acknowledge */
265 #define LL_I3C_PAYLOAD_1_BYTE              I3C_MAXRLR_IBIP_0
266 /*!< One additional data byte after IBI acknowledge */
267 #define LL_I3C_PAYLOAD_2_BYTES             I3C_MAXRLR_IBIP_1
268 /*!< Two additional data bytes after IBI acknowledge */
269 #define LL_I3C_PAYLOAD_3_BYTES             (I3C_MAXRLR_IBIP_1 | I3C_MAXRLR_IBIP_0)
270 /*!< Three additional data bytes after IBI acknowledge */
271 #define LL_I3C_PAYLOAD_4_BYTES             I3C_MAXRLR_IBIP_2
272 /*!< Four additional data bytes after IBI acknowledge */
273 /**
274   * @}
275   */
276 
277 /** @defgroup I3C_LL_EC_SDA_HOLD_TIME SDA HOLD TIME 0
278   * @{
279   */
280 #define LL_I3C_SDA_HOLD_TIME_0_5           0x00000000U               /*!< SDA hold time is 0.5 x ti3cclk */
281 #define LL_I3C_SDA_HOLD_TIME_1_5           I3C_TIMINGR1_SDA_HD       /*!< SDA hold time is 1.5 x ti3cclk */
282 /**
283   * @}
284   */
285 
286 /** @defgroup I3C_LL_EC_OWN_ACTIVITY_STATE OWN ACTIVITY STATE
287   * @{
288   */
289 #define LL_I3C_OWN_ACTIVITY_STATE_0        0x00000000U
290 /*!< Own Controller Activity state 0 */
291 #define LL_I3C_OWN_ACTIVITY_STATE_1        I3C_TIMINGR1_ASNCR_0
292 /*!< Own Controller Activity state 1 */
293 #define LL_I3C_OWN_ACTIVITY_STATE_2        I3C_TIMINGR1_ASNCR_1
294 /*!< Own Controller Activity state 2 */
295 #define LL_I3C_OWN_ACTIVITY_STATE_3        (I3C_TIMINGR1_ASNCR_1 | I3C_TIMINGR1_ASNCR_0)
296 /*!< Own Controller Activity state 3 */
297 /**
298   * @}
299   */
300 
301 /** @defgroup I3C_LL_EC_DEVICE_ROLE_AS DEVICE ROLE AS
302   * @{
303   */
304 #define LL_I3C_DEVICE_ROLE_AS_TARGET        0x00000000U              /*!< I3C Target */
305 #define LL_I3C_DEVICE_ROLE_AS_CONTROLLER    I3C_BCR_BCR6             /*!< I3C Controller */
306 /**
307   * @}
308   */
309 
310 /** @defgroup I3C_LL_EC_IBI_NO_ADDITIONAL IBI NO ADDITIONAL
311   * @{
312   */
313 #define LL_I3C_IBI_NO_ADDITIONAL_DATA      0x00000000U               /*!< No data byte follows the accepted IBI */
314 #define LL_I3C_IBI_ADDITIONAL_DATA         I3C_BCR_BCR2              /*!< A Mandatory Data Byte (MDB)
315                                                                           follows the accepted IBI */
316 /**
317   * @}
318   */
319 
320 /** @defgroup I3C_LL_EC_MAX_DATA_SPEED_LIMITATION MAX DATA SPEED LIMITATION
321   * @{
322   */
323 #define LL_I3C_NO_DATA_SPEED_LIMITATION    0x00000000U               /*!< No max data speed limitation */
324 #define LL_I3C_MAX_DATA_SPEED_LIMITATION   I3C_BCR_BCR0              /*!< Max data speed limitation */
325 /**
326   * @}
327   */
328 
329 /** @defgroup I3C_LL_EC_IBI_MDB_READ_NOTIFICATION IBI MDB READ NOTIFICATION
330   * @{
331   */
332 #define LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION  0x00000000U
333 /*!< No support of pending read notification via the IBI MDB[7:0] value */
334 #define LL_I3C_MDB_PENDING_READ_NOTIFICATION     I3C_GETCAPR_CAPPEND
335 /*!< Support of pending read notification via the IBI MDB[7:0] value    */
336 /**
337   * @}
338   */
339 
340 /** @defgroup I3C_LL_EC_HANDOFF_GRP_ADDR_NOT HANDOFF GRP ADDR NOT
341   * @{
342   */
343 #define LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED 0x00000000U            /*!< Group Address Handoff is not supported */
344 #define LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED     I3C_CRCAPR_CAPGRP      /*!< Group Address Handoff is supported     */
345 /**
346   * @}
347   */
348 
349 /** @defgroup I3C_LL_EC_HANDOFF HANDOFF
350   * @{
351   */
352 #define LL_I3C_HANDOFF_NOT_DELAYED         0x00000000U
353 /*!< Additional time to process controllership handoff is not needed */
354 #define LL_I3C_HANDOFF_DELAYED             I3C_CRCAPR_CAPDHOFF
355 /*!< Additional time to process controllership handoff is needed */
356 /**
357   * @}
358   */
359 
360 /** @defgroup I3C_LL_EC_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE
361   * @{
362   */
363 #define LL_I3C_HANDOFF_ACTIVITY_STATE_0    0x00000000U
364 /*!< Indicates that will act according to Activity State 0 after controllership handoff */
365 #define LL_I3C_HANDOFF_ACTIVITY_STATE_1    I3C_GETMXDSR_HOFFAS_0
366 /*!< Indicates that will act according to Activity State 1 after controllership handoff */
367 #define LL_I3C_HANDOFF_ACTIVITY_STATE_2    I3C_GETMXDSR_HOFFAS_1
368 /*!< Indicates that will act according to Activity State 2 after controllership handoff */
369 #define LL_I3C_HANDOFF_ACTIVITY_STATE_3    (I3C_GETMXDSR_HOFFAS_1 | I3C_GETMXDSR_HOFFAS_0)
370 /*!< Indicates that will act according to Activity State 3 after controllership handoff */
371 /**
372   * @}
373   */
374 
375 /** @defgroup I3C_LL_EC_GETMXDS_FORMAT GETMXDS FORMAT
376   * @{
377   */
378 #define LL_I3C_GETMXDS_FORMAT_1            0x00000000U
379 /*!< GETMXDS CCC Format 1 is used, no MaxRdTurn field in response */
380 #define LL_I3C_GETMXDS_FORMAT_2_LSB        I3C_GETMXDSR_FMT_0
381 /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, LSB = RDTURN[7:0] */
382 #define LL_I3C_GETMXDS_FORMAT_2_MID        I3C_GETMXDSR_FMT_1
383 /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, Middle byte = RDTURN[7:0] */
384 #define LL_I3C_GETMXDS_FORMAT_2_MSB        (I3C_GETMXDSR_FMT_1 | I3C_GETMXDSR_FMT_0)
385 /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field in response, MSB = RDTURN[7:0] */
386 /**
387   * @}
388   */
389 
390 /** @defgroup I3C_LL_EC_GETMXDS_TSCO GETMXDS TSCO
391   * @{
392   */
393 #define LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS     0x00000000U         /*!< clock-to-data turnaround time tSCO <= 12ns */
394 #define LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS  I3C_GETMXDSR_TSCO   /*!< clock-to-data turnaround time tSCO > 12ns  */
395 /**
396   * @}
397   */
398 
399 /** @defgroup I3C_LL_EC_BUS_ACTIVITY_STATE BUS ACTIVITY STATE
400   * @{
401   */
402 #define LL_I3C_BUS_ACTIVITY_STATE_0        0x00000000U
403 /*!< Controller on the Bus Activity State 0 */
404 #define LL_I3C_BUS_ACTIVITY_STATE_1        I3C_DEVR0_AS_0
405 /*!< Controller on the Bus Activity State 1 */
406 #define LL_I3C_BUS_ACTIVITY_STATE_2        I3C_DEVR0_AS_1
407 /*!< Controller on the Bus Activity State 2 */
408 #define LL_I3C_BUS_ACTIVITY_STATE_3        (I3C_DEVR0_AS_1 | I3C_DEVR0_AS_0)
409 /*!< Controller on the Bus Activity State 3 */
410 /**
411   * @}
412   */
413 
414 /** @defgroup I3C_LL_EC_RESET_ACTION RESET ACTION
415   * @{
416   */
417 #define LL_I3C_RESET_ACTION_NONE           0x00000000U
418 /*!< No Reset Action Required */
419 #define LL_I3C_RESET_ACTION_PARTIAL        I3C_DEVR0_RSTACT_0
420 /*!< Reset of some internal registers of the peripheral*/
421 #define LL_I3C_RESET_ACTION_FULL           I3C_DEVR0_RSTACT_1
422 /*!< Reset all internal registers of the peripheral */
423 /**
424   * @}
425   */
426 
427 /** @defgroup I3C_LL_EC_DIRECTION DIRECTION
428   * @{
429   */
430 #define LL_I3C_DIRECTION_WRITE             0x00000000U               /*!< Write transfer      */
431 #define LL_I3C_DIRECTION_READ              I3C_CR_RNW                /*!< Read transfer       */
432 /**
433   * @}
434   */
435 
436 /** @defgroup I3C_LL_EC_GENERATE GENERATE
437   * @{
438   */
439 #define LL_I3C_GENERATE_STOP               I3C_CR_MEND
440 /*!< Generate Stop condition after sending a message */
441 #define LL_I3C_GENERATE_RESTART            0x00000000U
442 /*!< Generate Restart condition after sending a message */
443 /**
444   * @}
445   */
446 
447 /** @defgroup I3C_LL_EC_CONTROLLER_MTYPE CONTROLLER MTYPE
448   * @{
449   */
450 #define LL_I3C_CONTROLLER_MTYPE_RELEASE        0x00000000U
451 /*!< SCL output clock stops running until next instruction executed       */
452 #define LL_I3C_CONTROLLER_MTYPE_HEADER         I3C_CR_MTYPE_0
453 /*!< Header Message */
454 #define LL_I3C_CONTROLLER_MTYPE_PRIVATE        I3C_CR_MTYPE_1
455 /*!< Private Message Type */
456 #define LL_I3C_CONTROLLER_MTYPE_DIRECT         (I3C_CR_MTYPE_1 | I3C_CR_MTYPE_0)
457 /*!< Direct Message Type */
458 #define LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C     I3C_CR_MTYPE_2
459 /*!< Legacy I2C Message Type */
460 #define LL_I3C_CONTROLLER_MTYPE_CCC            (I3C_CR_MTYPE_2 | I3C_CR_MTYPE_1)
461 /*!< Common Command Code */
462 /**
463   * @}
464   */
465 
466 /** @defgroup I3C_LL_EC_TARGET_MTYPE_HOT TARGET MTYPE HOT
467   * @{
468   */
469 #define LL_I3C_TARGET_MTYPE_HOT_JOIN            I3C_CR_MTYPE_3                     /*!< Hot Join*/
470 #define LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_0)  /*!< Controller-role Request */
471 #define LL_I3C_TARGET_MTYPE_IBI                 (I3C_CR_MTYPE_3 | I3C_CR_MTYPE_1)  /*!< In Band Interrupt (IBI) */
472 /**
473   * @}
474   */
475 
476 /** @defgroup I3C_LL_EC_MESSAGE MESSAGE
477   * @{
478   */
479 #define LL_I3C_MESSAGE_ERROR               0x00000000U               /*!< An error has been detected in the message */
480 #define LL_I3C_MESSAGE_SUCCESS             I3C_SR_OK                 /*!< The message ended with success       */
481 /**
482   * @}
483   */
484 
485 /** @defgroup I3C_LL_EC_MESSAGE_DIRECTION MESSAGE DIRECTION
486   * @{
487   */
488 #define LL_I3C_MESSAGE_DIRECTION_WRITE     0x00000000U               /*!< Write data or command      */
489 #define LL_I3C_MESSAGE_DIRECTION_READ      I3C_SR_DIR                /*!< Read data       */
490 /**
491   * @}
492   */
493 
494 /** @defgroup I3C_LL_EC_CONTROLLER_ERROR CONTROLLER ERROR
495   * @{
496   */
497 #define LL_I3C_CONTROLLER_ERROR_CE0        0x00000000U
498 /*!< Controller detected an illegally formatted CCC    */
499 #define LL_I3C_CONTROLLER_ERROR_CE1        I3C_SER_CODERR_0
500 /*!< Controller detected that transmitted data on the bus is different than expected    */
501 #define LL_I3C_CONTROLLER_ERROR_CE2        I3C_SER_CODERR_1
502 /*!< Controller detected that broadcast address 7'h7E has been nacked    */
503 #define LL_I3C_CONTROLLER_ERROR_CE3        (I3C_SER_CODERR_1 | I3C_SER_CODERR_0)
504 /*!< Controller detected that new Controller did not drive the bus after Controller-role handoff    */
505 /**
506   * @}
507   */
508 
509 /** @defgroup I3C_LL_EC_TARGET_ERROR TARGET ERROR
510   * @{
511   */
512 #define LL_I3C_TARGET_ERROR_TE0            I3C_SER_CODERR_3
513 /*!< Target detected an invalid broadcast address    */
514 #define LL_I3C_TARGET_ERROR_TE1            (I3C_SER_CODERR_3  | I3C_SER_CODERR_0)
515 /*!< Target detected an invalid CCC Code    */
516 #define LL_I3C_TARGET_ERROR_TE2            (I3C_SER_CODERR_3  | I3C_SER_CODERR_1)
517 /*!< Target detected an invalid write data    */
518 #define LL_I3C_TARGET_ERROR_TE3            (I3C_SER_CODERR_3  | I3C_SER_CODERR_1 | I3C_SER_CODERR_0)
519 /*!< Target detected an invalid assigned address during Dynamic Address Assignment procedure    */
520 #define LL_I3C_TARGET_ERROR_TE4            (I3C_SER_CODERR_3  | I3C_SER_CODERR_2)
521 /*!< Target detected 7'h7E missing after Restart during Dynamic Address Assignment procedure    */
522 #define LL_I3C_TARGET_ERROR_TE5            (I3C_SER_CODERR_3  | I3C_SER_CODERR_2 | I3C_SER_CODERR_0)
523 /*!< Target detected an illegally formatted CCC     */
524 #define LL_I3C_TARGET_ERROR_TE6            (I3C_SER_CODERR_3  | I3C_SER_CODERR_2 | I3C_SER_CODERR_1)
525 /*!< Target detected that transmitted data on the bus is different than expected     */
526 /**
527   * @}
528   */
529 
530 /** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD
531   * @{
532   */
533 #define LL_I3C_BCR_IN_PAYLOAD_SHIFT        48  /*!< BCR field in target payload */
534 /**
535   * @}
536   */
537 
538 /** @defgroup I3C_LL_EC_IBI_CAPABILITY IBI CAPABILITY
539   * @{
540   */
541 #define LL_I3C_IBI_CAPABILITY              I3C_DEVRX_IBIACK
542 /*!< Controller acknowledge Target In Band Interrupt capable */
543 #define LL_I3C_IBI_NO_CAPABILITY           0x00000000U
544 /*!< Controller no acknowledge Target In Band Interrupt capable */
545 /**
546   * @}
547   */
548 
549 /** @defgroup I3C_LL_EC_IBI_ADDITIONAL_DATA IBI ADDITIONAL DATA
550   * @{
551   */
552 #define LL_I3C_IBI_DATA_ENABLE             I3C_DEVRX_IBIDEN
553 /*!< A mandatory data byte follows the IBI acknowledgement */
554 #define LL_I3C_IBI_DATA_DISABLE            0x00000000U
555 /*!< No mandatory data byte follows the IBI acknowledgement */
556 /**
557   * @}
558   */
559 
560 /** @defgroup I3C_LL_EC_CR_CAPABILITY CR CAPABILITY
561   * @{
562   */
563 #define LL_I3C_CR_CAPABILITY               I3C_DEVRX_CRACK
564 /*!< Controller acknowledge Target Controller Role capable */
565 #define LL_I3C_CR_NO_CAPABILITY            0x00000000U
566 /*!< Controller no acknowledge Target Controller Role capable */
567 /**
568   * @}
569   */
570 
571 /**
572   * @}
573   */
574 
575 /* Exported macro ------------------------------------------------------------*/
576 /** @defgroup I3C_LL_Exported_Macros I3C Exported Macros
577   * @{
578   */
579 
580 /** @defgroup I3C_LL_EM_WRITE_READ Common Write and read registers Macros
581   * @{
582   */
583 
584 /** @brief  Get Bus Characterics in payload (64bits) receive during ENTDAA procedure.
585   * @param  __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
586   *         This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF.
587   * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF.
588   */
589 #define LL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> LL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \
590                                      I3C_BCR_BCR)
591 
592 /** @brief  Check IBI request capabilities.
593   * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
594   *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
595   * @retval Value of @ref I3C_LL_EC_IBI_CAPABILITY.
596   */
597 #define LL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \
598                                          ? LL_I3C_IBI_CAPABILITY : LL_I3C_IBI_NO_CAPABILITY)
599 
600 /** @brief  Check IBI additional data byte capabilities.
601   * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
602   *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
603   * @retval Value of @ref I3C_LL_EC_IBI_ADDITIONAL_DATA.
604   */
605 #define LL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \
606                                          ? LL_I3C_IBI_DATA_ENABLE : LL_I3C_IBI_DATA_DISABLE)
607 
608 /** @brief  Check Controller role request capabilities.
609   * @param  __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure.
610   *         This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF.
611   * @retval Value of @ref I3C_LL_EC_CR_CAPABILITY.
612   */
613 #define LL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \
614                                         ? LL_I3C_CR_CAPABILITY : LL_I3C_CR_NO_CAPABILITY)
615 
616 /**
617   * @brief  Write a value in I3C register
618   * @param  __INSTANCE__ I3C Instance
619   * @param  __REG__ Register to be written
620   * @param  __VALUE__ Value to be written in the register
621   * @retval None
622   */
623 #define LL_I3C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
624 
625 /**
626   * @brief  Read a value in I3C register
627   * @param  __INSTANCE__ I3C Instance
628   * @param  __REG__ Register to be read
629   * @retval Register value
630   */
631 #define LL_I3C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
632 /**
633   * @}
634   */
635 
636 /**
637   * @}
638   */
639 
640 /* Exported functions --------------------------------------------------------*/
641 /** @defgroup I3C_LL_Exported_Functions I3C Exported Functions
642   * @{
643   */
644 
645 /** @defgroup I3C_LL_EF_Configuration Configuration
646   * @{
647   */
648 
649 /**
650   * @brief  Enable I3C peripheral (EN = 1).
651   * @rmtoll CFGR      EN            LL_I3C_Enable
652   * @param  I3Cx I3C Instance.
653   * @retval None
654   */
LL_I3C_Enable(I3C_TypeDef * I3Cx)655 __STATIC_INLINE void LL_I3C_Enable(I3C_TypeDef *I3Cx)
656 {
657   SET_BIT(I3Cx->CFGR, I3C_CFGR_EN);
658 }
659 
660 /**
661   * @brief  Disable I3C peripheral (EN = 0).
662   * @note   Controller mode: before clearing EN, all possible target requests must be disabled using DISEC CCC.
663   *         Target mode: software is not expected clearing EN unless a partial reset of the IP is needed
664   * @rmtoll CFGR      EN            LL_I3C_Disable
665   * @param  I3Cx I3C Instance.
666   * @retval None
667   */
LL_I3C_Disable(I3C_TypeDef * I3Cx)668 __STATIC_INLINE void LL_I3C_Disable(I3C_TypeDef *I3Cx)
669 {
670   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EN);
671 }
672 
673 /**
674   * @brief  Check if the I3C peripheral is enabled or disabled.
675   * @rmtoll CFGR      EN            LL_I3C_IsEnabled
676   * @param  I3Cx I3C Instance.
677   * @retval State of bit (1 or 0).
678   */
LL_I3C_IsEnabled(const I3C_TypeDef * I3Cx)679 __STATIC_INLINE uint32_t LL_I3C_IsEnabled(const I3C_TypeDef *I3Cx)
680 {
681   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EN) == (I3C_CFGR_EN)) ? 1UL : 0UL);
682 }
683 
684 /**
685   * @brief  Check if Reset action is required or not required.
686   * @note   This bit indicates if Reset Action field has been updated by HW upon reception
687   *         of RSTACT during current frame.
688   * @rmtoll DEVR0        RSTVAL        LL_I3C_IsEnabledReset
689   * @param  I3Cx I3C Instance.
690   * @retval State of bit (1 or 0).
691   */
LL_I3C_IsEnabledReset(const I3C_TypeDef * I3Cx)692 __STATIC_INLINE uint32_t LL_I3C_IsEnabledReset(const I3C_TypeDef *I3Cx)
693 {
694   return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTVAL) == (I3C_DEVR0_RSTVAL)) ? 1UL : 0UL);
695 }
696 
697 /**
698   * @brief  Configure peripheral mode.
699   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
700   * @rmtoll CFGR      CRINIT       LL_I3C_SetMode
701   * @param  I3Cx I3C Instance.
702   * @param  PeripheralMode This parameter can be one of the following values:
703   *         @arg @ref LL_I3C_MODE_CONTROLLER
704   *         @arg @ref LL_I3C_MODE_TARGET
705   * @retval None
706   */
LL_I3C_SetMode(I3C_TypeDef * I3Cx,uint32_t PeripheralMode)707 __STATIC_INLINE void LL_I3C_SetMode(I3C_TypeDef *I3Cx, uint32_t PeripheralMode)
708 {
709   MODIFY_REG(I3Cx->CFGR, I3C_CFGR_CRINIT, PeripheralMode);
710 }
711 
712 /**
713   * @brief  Get peripheral mode.
714   * @rmtoll CFGR      CRINIT       LL_I3C_GetMode
715   * @param  I3Cx I3C Instance.
716   * @retval Returned value can be one of the following values:
717   *         @arg @ref LL_I3C_MODE_CONTROLLER
718   *         @arg @ref LL_I3C_MODE_TARGET
719   */
LL_I3C_GetMode(const I3C_TypeDef * I3Cx)720 __STATIC_INLINE uint32_t LL_I3C_GetMode(const I3C_TypeDef *I3Cx)
721 {
722   return (uint32_t)((READ_BIT(I3Cx->CFGR, I3C_CFGR_CRINIT) == (I3C_CFGR_CRINIT)) ? 1UL : 0UL);
723 }
724 
725 /**
726   * @brief  An arbitration header (7'h7E) is sent after Start in case of legacy I2C or I3C private transfers.
727   * @note   This bit can be modified only when there is no frame ongoing
728   * @rmtoll CFGR      NOARBH        LL_I3C_EnableArbitrationHeader
729   * @param  I3Cx I3C Instance.
730   * @retval None
731   */
LL_I3C_EnableArbitrationHeader(I3C_TypeDef * I3Cx)732 __STATIC_INLINE void LL_I3C_EnableArbitrationHeader(I3C_TypeDef *I3Cx)
733 {
734   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH);
735 }
736 
737 /**
738   * @brief  Target address is sent directly after a Start in case of legacy I2C or I3C private transfers.
739   * @note   This bit can be modified only when there is no frame ongoing
740   * @rmtoll CFGR      NOARBH        LL_I3C_DisableArbitrationHeader
741   * @param  I3Cx I3C Instance.
742   * @retval None
743   */
LL_I3C_DisableArbitrationHeader(I3C_TypeDef * I3Cx)744 __STATIC_INLINE void LL_I3C_DisableArbitrationHeader(I3C_TypeDef *I3Cx)
745 {
746   SET_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH);
747 }
748 
749 /**
750   * @brief  Check if the arbitration header is enabled of disabled.
751   * @rmtoll CFGR      NOARBH        LL_I3C_IsEnabledArbitrationHeader
752   * @param  I3Cx I3C Instance.
753   * @retval State of bit (1 or 0).
754   */
LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef * I3Cx)755 __STATIC_INLINE uint32_t LL_I3C_IsEnabledArbitrationHeader(const I3C_TypeDef *I3Cx)
756 {
757   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_NOARBH) == (I3C_CFGR_NOARBH)) ? 0UL : 1UL);
758 }
759 
760 /**
761   * @brief  A Reset Pattern is inserted before the STOP at the end of a frame when the last CCC
762   *         of the frame was RSTACT CCC.
763   * @note   This bit can be modified only when there is no frame ongoing
764   * @rmtoll CFGR      RSTPTRN       LL_I3C_EnableResetPattern
765   * @param  I3Cx I3C Instance.
766   * @retval None
767   */
LL_I3C_EnableResetPattern(I3C_TypeDef * I3Cx)768 __STATIC_INLINE void LL_I3C_EnableResetPattern(I3C_TypeDef *I3Cx)
769 {
770   SET_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN);
771 }
772 
773 /**
774   * @brief  A single STOP is emitted at the end of a frame.
775   * @note   This bit can be modified only when there is no frame ongoing
776   * @rmtoll CFGR      RSTPTRN       LL_I3C_DisableResetPattern
777   * @param  I3Cx I3C Instance.
778   * @retval None
779   */
LL_I3C_DisableResetPattern(I3C_TypeDef * I3Cx)780 __STATIC_INLINE void LL_I3C_DisableResetPattern(I3C_TypeDef *I3Cx)
781 {
782   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN);
783 }
784 
785 /**
786   * @brief  Check if Reset Pattern is enabled of disabled.
787   * @rmtoll CFGR      RSTPTRN       LL_I3C_IsEnabledResetPattern
788   * @param  I3Cx I3C Instance.
789   * @retval State of bit (1 or 0).
790   */
LL_I3C_IsEnabledResetPattern(const I3C_TypeDef * I3Cx)791 __STATIC_INLINE uint32_t LL_I3C_IsEnabledResetPattern(const I3C_TypeDef *I3Cx)
792 {
793   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RSTPTRN) == (I3C_CFGR_RSTPTRN)) ? 1UL : 0UL);
794 }
795 
796 /**
797   * @brief  An Exit Pattern is sent after header (MTYPE = header) to program an escalation fault.
798   * @note   This bit can be modified only when there is no frame ongoing
799   * @rmtoll CFGR      EXITPTRN      LL_I3C_EnableExitPattern
800   * @param  I3Cx I3C Instance.
801   * @retval None
802   */
LL_I3C_EnableExitPattern(I3C_TypeDef * I3Cx)803 __STATIC_INLINE void LL_I3C_EnableExitPattern(I3C_TypeDef *I3Cx)
804 {
805   SET_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN);
806 }
807 
808 /**
809   * @brief  An Exit Pattern is not sent after header (MTYPE = header).
810   * @note   This bit can be modified only when there is no frame ongoing
811   * @rmtoll CFGR      EXITPTRN      LL_I3C_DisableExitPattern
812   * @param  I3Cx I3C Instance.
813   * @retval None
814   */
LL_I3C_DisableExitPattern(I3C_TypeDef * I3Cx)815 __STATIC_INLINE void LL_I3C_DisableExitPattern(I3C_TypeDef *I3Cx)
816 {
817   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN);
818 }
819 
820 /**
821   * @brief  Check if Exit Pattern is enabled or disabled.
822   * @rmtoll CFGR      EXITPTRN      LL_I3C_IsEnabledExitPattern
823   * @param  I3Cx I3C Instance.
824   * @retval State of bit (1 or 0).
825   */
LL_I3C_IsEnabledExitPattern(const I3C_TypeDef * I3Cx)826 __STATIC_INLINE uint32_t LL_I3C_IsEnabledExitPattern(const I3C_TypeDef *I3Cx)
827 {
828   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_EXITPTRN) == (I3C_CFGR_EXITPTRN)) ? 1UL : 0UL);
829 }
830 
831 /**
832   * @brief  High Keeper is enabled and will be used in place of standard Open drain Pull Up device
833   *         during handoff procedures.
834   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
835   * @rmtoll CFGR      HKSDAEN       LL_I3C_EnableHighKeeperSDA
836   * @param  I3Cx I3C Instance.
837   * @retval None
838   */
LL_I3C_EnableHighKeeperSDA(I3C_TypeDef * I3Cx)839 __STATIC_INLINE void LL_I3C_EnableHighKeeperSDA(I3C_TypeDef *I3Cx)
840 {
841   SET_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN);
842 }
843 
844 /**
845   * @brief  High Keeper is disabled.
846   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
847   * @rmtoll CFGR      HKSDAEN       LL_I3C_DisableHighKeeperSDA
848   * @param  I3Cx I3C Instance.
849   * @retval None
850   */
LL_I3C_DisableHighKeeperSDA(I3C_TypeDef * I3Cx)851 __STATIC_INLINE void LL_I3C_DisableHighKeeperSDA(I3C_TypeDef *I3Cx)
852 {
853   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN);
854 }
855 
856 /**
857   * @brief  Check if High Keeper is enabled or disabled.
858   * @rmtoll CFGR      HKSDAEN       LL_I3C_IsEnabledHighKeeperSDA
859   * @param  I3Cx I3C Instance.
860   * @retval State of bit (1 or 0).
861   */
LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef * I3Cx)862 __STATIC_INLINE uint32_t LL_I3C_IsEnabledHighKeeperSDA(const I3C_TypeDef *I3Cx)
863 {
864   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HKSDAEN) == (I3C_CFGR_HKSDAEN)) ? 1UL : 0UL);
865 }
866 
867 /**
868   * @brief  Hot Join Request is Acked. Current frame on the bus is continued.
869   *         An Hot Join interrupt is sent through HJF flag.
870   * @note   This bit can be used when I3C is acting as a Controller.
871   * @rmtoll CFGR      HJACK         LL_I3C_EnableHJAck
872   * @param  I3Cx I3C Instance.
873   * @retval None
874   */
LL_I3C_EnableHJAck(I3C_TypeDef * I3Cx)875 __STATIC_INLINE void LL_I3C_EnableHJAck(I3C_TypeDef *I3Cx)
876 {
877   SET_BIT(I3Cx->CFGR, I3C_CFGR_HJACK);
878 }
879 
880 /**
881   * @brief  Hot Join Request is Nacked. Current frame on the bus is continued.
882   *         No Hot Join interrupt is generated.
883   * @note   This bit can be used when I3C is acting as a Controller.
884   * @rmtoll CFGR      HJACK         LL_I3C_DisableHJAck
885   * @param  I3Cx I3C Instance.
886   * @retval None
887   */
LL_I3C_DisableHJAck(I3C_TypeDef * I3Cx)888 __STATIC_INLINE void LL_I3C_DisableHJAck(I3C_TypeDef *I3Cx)
889 {
890   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_HJACK);
891 }
892 
893 /**
894   * @brief  Check if Hot Join Request Acknowledgement is enabled or disabled.
895   * @rmtoll CFGR      HJACK         LL_I3C_IsEnabledHJAck
896   * @param  I3Cx I3C Instance.
897   * @retval State of bit (1 or 0).
898   */
LL_I3C_IsEnabledHJAck(const I3C_TypeDef * I3Cx)899 __STATIC_INLINE uint32_t LL_I3C_IsEnabledHJAck(const I3C_TypeDef *I3Cx)
900 {
901   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_HJACK) == (I3C_CFGR_HJACK)) ? 1UL : 0UL);
902 }
903 
904 /**
905   * @brief  Get the data register address used for DMA transfer
906   * @rmtoll TDR          TDB0         LL_I3C_DMA_GetRegAddr\n
907   *         TDWR         TDWR          LL_I3C_DMA_GetRegAddr\n
908   *         RDR          RXRB0         LL_I3C_DMA_GetRegAddr\n
909   *         RDWR         RDWR          LL_I3C_DMA_GetRegAddr\n
910   *         SR           SR            LL_I3C_DMA_GetRegAddr\n
911   *         CR           CR            LL_I3C_DMA_GetRegAddr
912   * @param  I3Cx I3C Instance
913   * @param  Direction This parameter can be one of the following values:
914   *         @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE
915   *         @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_BYTE
916   *         @arg @ref LL_I3C_DMA_REG_DATA_TRANSMIT_WORD
917   *         @arg @ref LL_I3C_DMA_REG_DATA_RECEIVE_WORD
918   *         @arg @ref LL_I3C_DMA_REG_STATUS
919   *         @arg @ref LL_I3C_DMA_REG_CONTROL
920   * @retval Address of data register
921   */
LL_I3C_DMA_GetRegAddr(const I3C_TypeDef * I3Cx,uint32_t Direction)922 __STATIC_INLINE uint32_t LL_I3C_DMA_GetRegAddr(const I3C_TypeDef *I3Cx, uint32_t Direction)
923 {
924   register uint32_t data_reg_addr;
925 
926   if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE)
927   {
928     /* return address of TDR register */
929     data_reg_addr = (uint32_t) &(I3Cx->TDR);
930   }
931   else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_BYTE)
932   {
933     /* return address of RDR register */
934     data_reg_addr = (uint32_t) &(I3Cx->RDR);
935   }
936   else if (Direction == LL_I3C_DMA_REG_DATA_TRANSMIT_WORD)
937   {
938     /* return address of TDWR register */
939     data_reg_addr = (uint32_t) &(I3Cx->TDWR);
940   }
941   else if (Direction == LL_I3C_DMA_REG_DATA_RECEIVE_WORD)
942   {
943     /* return address of RDWR register */
944     data_reg_addr = (uint32_t) &(I3Cx->RDWR);
945   }
946   else if (Direction == LL_I3C_DMA_REG_STATUS)
947   {
948     /* return address of SR register */
949     data_reg_addr = (uint32_t) &(I3Cx->SR);
950   }
951   else
952   {
953     /* return address of CR register */
954     data_reg_addr = (uint32_t) &(I3Cx->CR);
955   }
956 
957   return data_reg_addr;
958 }
959 
960 /**
961   * @brief  Enable DMA FIFO reception requests.
962   * @rmtoll CFGR      RXDMAEN       LL_I3C_EnableDMAReq_RX
963   * @param  I3Cx I3C Instance.
964   * @retval None
965   */
LL_I3C_EnableDMAReq_RX(I3C_TypeDef * I3Cx)966 __STATIC_INLINE void LL_I3C_EnableDMAReq_RX(I3C_TypeDef *I3Cx)
967 {
968   SET_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN);
969 }
970 
971 /**
972   * @brief  Disable DMA FIFO reception requests.
973   * @rmtoll CFGR      RXDMAEN       LL_I3C_DisableDMAReq_RX
974   * @param  I3Cx I3C Instance.
975   * @retval None
976   */
LL_I3C_DisableDMAReq_RX(I3C_TypeDef * I3Cx)977 __STATIC_INLINE void LL_I3C_DisableDMAReq_RX(I3C_TypeDef *I3Cx)
978 {
979   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN);
980 }
981 
982 /**
983   * @brief  Check if DMA FIFO reception requests are enabled or disabled.
984   * @rmtoll CFGR      RXDMAEN       LL_I3C_IsEnabledDMAReq_RX
985   * @param  I3Cx I3C Instance.
986   * @retval State of bit (1 or 0).
987   */
LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef * I3Cx)988 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_RX(const I3C_TypeDef *I3Cx)
989 {
990   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_RXDMAEN) == (I3C_CFGR_RXDMAEN)) ? 1UL : 0UL);
991 }
992 
993 /**
994   * @brief  Set the Receive FIFO Threshold level.
995   * @rmtoll CFGR      RXTHRES       LL_I3C_SetRxFIFOThreshold
996   * @param  I3Cx I3C Instance.
997   * @param  RxFIFOThreshold This parameter can be one of the following values:
998   *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4
999   *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4
1000   * @retval None
1001   */
LL_I3C_SetRxFIFOThreshold(I3C_TypeDef * I3Cx,uint32_t RxFIFOThreshold)1002 __STATIC_INLINE void LL_I3C_SetRxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t RxFIFOThreshold)
1003 {
1004   MODIFY_REG(I3Cx->CFGR, I3C_CFGR_RXTHRES, RxFIFOThreshold);
1005 }
1006 
1007 /**
1008   * @brief  Get the Receive FIFO Threshold level.
1009   * @rmtoll CFGR      RXTHRES       LL_I3C_GetRxFIFOThreshold
1010   * @param  I3Cx I3C Instance.
1011   * @retval Returned value can be one of the following values:
1012   *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_1_4
1013   *         @arg @ref LL_I3C_RXFIFO_THRESHOLD_4_4
1014   */
LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef * I3Cx)1015 __STATIC_INLINE uint32_t LL_I3C_GetRxFIFOThreshold(const I3C_TypeDef *I3Cx)
1016 {
1017   return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_RXTHRES));
1018 }
1019 
1020 /**
1021   * @brief  Enable DMA FIFO transmission requests.
1022   * @rmtoll CFGR      TXDMAEN       LL_I3C_EnableDMAReq_TX
1023   * @param  I3Cx I3C Instance.
1024   * @retval None
1025   */
LL_I3C_EnableDMAReq_TX(I3C_TypeDef * I3Cx)1026 __STATIC_INLINE void LL_I3C_EnableDMAReq_TX(I3C_TypeDef *I3Cx)
1027 {
1028   SET_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN);
1029 }
1030 
1031 /**
1032   * @brief  Disable DMA FIFO transmission requests.
1033   * @rmtoll CFGR      TXDMAEN       LL_I3C_DisableDMAReq_TX
1034   * @param  I3Cx I3C Instance.
1035   * @retval None
1036   */
LL_I3C_DisableDMAReq_TX(I3C_TypeDef * I3Cx)1037 __STATIC_INLINE void LL_I3C_DisableDMAReq_TX(I3C_TypeDef *I3Cx)
1038 {
1039   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN);
1040 }
1041 
1042 /**
1043   * @brief  Check if DMA FIFO transmission requests are enabled or disabled.
1044   * @rmtoll CFGR      TXDMAEN       LL_I3C_IsEnabledDMAReq_TX
1045   * @param  I3Cx I3C Instance.
1046   * @retval State of bit (1 or 0).
1047   */
LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef * I3Cx)1048 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_TX(const I3C_TypeDef *I3Cx)
1049 {
1050   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TXDMAEN) == (I3C_CFGR_TXDMAEN)) ? 1UL : 0UL);
1051 }
1052 
1053 /**
1054   * @brief  Set the Transmit FIFO Threshold level.
1055   * @rmtoll CFGR      TXTHRES       LL_I3C_SetTxFIFOThreshold
1056   * @param  I3Cx I3C Instance.
1057   * @param  TxFIFOThreshold This parameter can be one of the following values:
1058   *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4
1059   *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4
1060   * @retval None
1061   */
LL_I3C_SetTxFIFOThreshold(I3C_TypeDef * I3Cx,uint32_t TxFIFOThreshold)1062 __STATIC_INLINE void LL_I3C_SetTxFIFOThreshold(I3C_TypeDef *I3Cx, uint32_t TxFIFOThreshold)
1063 {
1064   MODIFY_REG(I3Cx->CFGR, I3C_CFGR_TXTHRES, TxFIFOThreshold);
1065 }
1066 
1067 /**
1068   * @brief  Get the Transmit FIFO Threshold level.
1069   * @rmtoll CFGR      TXTHRES       LL_I3C_GetTxFIFOThreshold
1070   * @param  I3Cx I3C Instance.
1071   * @retval Returned value can be one of the following values:
1072   *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_1_4
1073   *         @arg @ref LL_I3C_TXFIFO_THRESHOLD_4_4
1074   * @retval State of bit (1 or 0).
1075   */
LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef * I3Cx)1076 __STATIC_INLINE uint32_t LL_I3C_GetTxFIFOThreshold(const I3C_TypeDef *I3Cx)
1077 {
1078   return (uint32_t)(READ_BIT(I3Cx->CFGR, I3C_CFGR_TXTHRES));
1079 }
1080 
1081 /**
1082   * @brief  Enable DMA FIFO Status requests.
1083   * @rmtoll CFGR      SDMAEN        LL_I3C_EnableDMAReq_Status
1084   * @param  I3Cx I3C Instance.
1085   * @retval None
1086   */
LL_I3C_EnableDMAReq_Status(I3C_TypeDef * I3Cx)1087 __STATIC_INLINE void LL_I3C_EnableDMAReq_Status(I3C_TypeDef *I3Cx)
1088 {
1089   SET_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN);
1090 }
1091 
1092 /**
1093   * @brief  Disable DMA FIFO Status requests.
1094   * @rmtoll CFGR      SDMAEN        LL_I3C_DisableDMAReq_Status
1095   * @param  I3Cx I3C Instance.
1096   * @retval None
1097   */
LL_I3C_DisableDMAReq_Status(I3C_TypeDef * I3Cx)1098 __STATIC_INLINE void LL_I3C_DisableDMAReq_Status(I3C_TypeDef *I3Cx)
1099 {
1100   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN);
1101 }
1102 
1103 /**
1104   * @brief  Check if DMA FIFO Status requests are enabled or disabled.
1105   * @rmtoll CFGR      SDMAEN        LL_I3C_IsEnabledDMAReq_Status
1106   * @param  I3Cx I3C Instance.
1107   * @retval State of bit (1 or 0).
1108   */
LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef * I3Cx)1109 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Status(const I3C_TypeDef *I3Cx)
1110 {
1111   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SDMAEN) == (I3C_CFGR_SDMAEN)) ? 1UL : 0UL);
1112 }
1113 
1114 /**
1115   * @brief  Enable the Status FIFO.
1116   * @note   Not applicable in target mode. Status FIFO always disabled in target mode.
1117   * @rmtoll CFGR      SMODE         LL_I3C_EnableStatusFIFO
1118   * @param  I3Cx I3C Instance.
1119   * @retval None
1120   */
LL_I3C_EnableStatusFIFO(I3C_TypeDef * I3Cx)1121 __STATIC_INLINE void LL_I3C_EnableStatusFIFO(I3C_TypeDef *I3Cx)
1122 {
1123   SET_BIT(I3Cx->CFGR, I3C_CFGR_SMODE);
1124 }
1125 
1126 /**
1127   * @brief  Disable the Status FIFO Threshold.
1128   * @rmtoll CFGR      SMODE         LL_I3C_DisableStatusFIFO
1129   * @param  I3Cx I3C Instance.
1130   * @retval None
1131   */
LL_I3C_DisableStatusFIFO(I3C_TypeDef * I3Cx)1132 __STATIC_INLINE void LL_I3C_DisableStatusFIFO(I3C_TypeDef *I3Cx)
1133 {
1134   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_SMODE);
1135 }
1136 
1137 /**
1138   * @brief  Check if the Status FIFO Threshold is enabled or disabled.
1139   * @rmtoll CFGR      SMODE         LL_I3C_IsEnabledStatusFIFO
1140   * @param  I3Cx I3C Instance.
1141   * @retval State of bit (1 or 0).
1142   */
LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef * I3Cx)1143 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStatusFIFO(const I3C_TypeDef *I3Cx)
1144 {
1145   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_SMODE) == (I3C_CFGR_SMODE)) ? 1UL : 0UL);
1146 }
1147 
1148 /**
1149   * @brief  Enable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus.
1150   * @note   Not applicable in target mode. Control FIFO always disabled in target mode.
1151   * @rmtoll CFGR      TMODE         LL_I3C_EnableControlFIFO
1152   * @param  I3Cx I3C Instance.
1153   * @retval None
1154   */
LL_I3C_EnableControlFIFO(I3C_TypeDef * I3Cx)1155 __STATIC_INLINE void LL_I3C_EnableControlFIFO(I3C_TypeDef *I3Cx)
1156 {
1157   SET_BIT(I3Cx->CFGR, I3C_CFGR_TMODE);
1158 }
1159 
1160 /**
1161   * @brief  Disable the Control and Transmit FIFO preloaded before starting a transfer on I3C bus.
1162   * @rmtoll CFGR      TMODE         LL_I3C_DisableControlFIFO
1163   * @param  I3Cx I3C Instance.
1164   * @retval None
1165   */
LL_I3C_DisableControlFIFO(I3C_TypeDef * I3Cx)1166 __STATIC_INLINE void LL_I3C_DisableControlFIFO(I3C_TypeDef *I3Cx)
1167 {
1168   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_TMODE);
1169 }
1170 
1171 /**
1172   * @brief  Check if the Control and Transmit FIFO preloaded is enabled or disabled.
1173   * @rmtoll CFGR      TMODE         LL_I3C_IsEnabledControlFIFO
1174   * @param  I3Cx I3C Instance.
1175   * @retval State of bit (1 or 0).
1176   */
LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef * I3Cx)1177 __STATIC_INLINE uint32_t LL_I3C_IsEnabledControlFIFO(const I3C_TypeDef *I3Cx)
1178 {
1179   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_TMODE) == (I3C_CFGR_TMODE)) ? 1UL : 0UL);
1180 }
1181 
1182 /**
1183   * @brief  Enable DMA FIFO Control word transfer requests.
1184   * @rmtoll CFGR      CDMAEN        LL_I3C_EnableDMAReq_Control
1185   * @param  I3Cx I3C Instance.
1186   * @retval None
1187   */
LL_I3C_EnableDMAReq_Control(I3C_TypeDef * I3Cx)1188 __STATIC_INLINE void LL_I3C_EnableDMAReq_Control(I3C_TypeDef *I3Cx)
1189 {
1190   SET_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN);
1191 }
1192 
1193 /**
1194   * @brief  Disable DMA FIFO Control word transfer requests.
1195   * @rmtoll CFGR      CDMAEN        LL_I3C_DisableDMAReq_Control
1196   * @param  I3Cx I3C Instance.
1197   * @retval None
1198   */
LL_I3C_DisableDMAReq_Control(I3C_TypeDef * I3Cx)1199 __STATIC_INLINE void LL_I3C_DisableDMAReq_Control(I3C_TypeDef *I3Cx)
1200 {
1201   CLEAR_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN);
1202 }
1203 
1204 /**
1205   * @brief  Check if DMA FIFO Control word transfer requests are enabled or disabled.
1206   * @rmtoll CFGR      CDMAEN        LL_I3C_IsEnabledDMAReq_Control
1207   * @param  I3Cx I3C Instance.
1208   * @retval State of bit (1 or 0).
1209   */
LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef * I3Cx)1210 __STATIC_INLINE uint32_t LL_I3C_IsEnabledDMAReq_Control(const I3C_TypeDef *I3Cx)
1211 {
1212   return ((READ_BIT(I3Cx->CFGR, I3C_CFGR_CDMAEN) == (I3C_CFGR_CDMAEN)) ? 1UL : 0UL);
1213 }
1214 
1215 /**
1216   * @brief  Set Own Dynamic Address as Valid.
1217   * @rmtoll DEVR0        DAVAL         LL_I3C_EnableOwnDynAddress
1218   * @param  I3Cx I3C Instance.
1219   * @retval None
1220   */
LL_I3C_EnableOwnDynAddress(I3C_TypeDef * I3Cx)1221 __STATIC_INLINE void LL_I3C_EnableOwnDynAddress(I3C_TypeDef *I3Cx)
1222 {
1223   SET_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL);
1224 }
1225 
1226 /**
1227   * @brief  Set Own Dynamic Address as Not-Valid.
1228   * @rmtoll DEVR0        DAVAL         LL_I3C_DisableOwnDynAddress
1229   * @param  I3Cx I3C Instance.
1230   * @retval None
1231   */
LL_I3C_DisableOwnDynAddress(I3C_TypeDef * I3Cx)1232 __STATIC_INLINE void LL_I3C_DisableOwnDynAddress(I3C_TypeDef *I3Cx)
1233 {
1234   CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL);
1235 }
1236 
1237 /**
1238   * @brief  Check if Own Dynamic address is Valid or Not-Valid.
1239   * @rmtoll DEVR0        DAVAL         LL_I3C_IsEnabledOwnDynAddress
1240   * @param  I3Cx I3C Instance.
1241   * @retval State of bit (1 or 0).
1242   */
LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef * I3Cx)1243 __STATIC_INLINE uint32_t LL_I3C_IsEnabledOwnDynAddress(const I3C_TypeDef *I3Cx)
1244 {
1245   return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DAVAL) == (I3C_DEVR0_DAVAL)) ? 1UL : 0UL);
1246 }
1247 
1248 /**
1249   * @brief  Configure Own Dynamic Address.
1250   * @note   This bit can be programmed in controller mode or during Dynamic Address procedure from current controller.
1251   * @rmtoll DEVR0        DA            LL_I3C_SetOwnDynamicAddress
1252   * @param  I3Cx I3C Instance.
1253   * @param  OwnDynamicAddress This parameter must be a value between Min_Data=0 and Max_Data=0x7F
1254   * @retval None
1255   */
LL_I3C_SetOwnDynamicAddress(I3C_TypeDef * I3Cx,uint32_t OwnDynamicAddress)1256 __STATIC_INLINE void LL_I3C_SetOwnDynamicAddress(I3C_TypeDef *I3Cx, uint32_t OwnDynamicAddress)
1257 {
1258   MODIFY_REG(I3Cx->DEVR0, I3C_DEVR0_DA, (OwnDynamicAddress << I3C_DEVR0_DA_Pos));
1259 }
1260 
1261 /**
1262   * @brief  Get Own Dynamic Address.
1263   * @rmtoll DEVR0        DA            LL_I3C_GetOwnDynamicAddress
1264   * @param  I3Cx I3C Instance.
1265   * @retval Value between Min_Data=0 and Max_Data=0x7F
1266   */
LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef * I3Cx)1267 __STATIC_INLINE uint8_t LL_I3C_GetOwnDynamicAddress(const I3C_TypeDef *I3Cx)
1268 {
1269   return (uint8_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_DA) >> I3C_DEVR0_DA_Pos);
1270 }
1271 
1272 /**
1273   * @brief  Set IBI procedure allowed (when the I3C is acting as target).
1274   * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1275   * @rmtoll DEVR0        IBIEN         LL_I3C_EnableIBI
1276   * @param  I3Cx I3C Instance.
1277   * @retval None
1278   */
LL_I3C_EnableIBI(I3C_TypeDef * I3Cx)1279 __STATIC_INLINE void LL_I3C_EnableIBI(I3C_TypeDef *I3Cx)
1280 {
1281   SET_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN);
1282 }
1283 
1284 /**
1285   * @brief  Set IBI procedure not-allowed (when the I3C is acting as target).
1286   * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1287   * @rmtoll DEVR0        IBIEN         LL_I3C_DisableIBI
1288   * @param  I3Cx I3C Instance.
1289   * @retval None
1290   */
LL_I3C_DisableIBI(I3C_TypeDef * I3Cx)1291 __STATIC_INLINE void LL_I3C_DisableIBI(I3C_TypeDef *I3Cx)
1292 {
1293   CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN);
1294 }
1295 
1296 /**
1297   * @brief  Check if IBI procedure is allowed or not allowed.
1298   * @rmtoll DEVR0        IBIEN         LL_I3C_IsEnabledIBI
1299   * @param  I3Cx I3C Instance.
1300   * @retval State of bit (1 or 0).
1301   */
LL_I3C_IsEnabledIBI(const I3C_TypeDef * I3Cx)1302 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIBI(const I3C_TypeDef *I3Cx)
1303 {
1304   return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_IBIEN) == (I3C_DEVR0_IBIEN)) ? 1UL : 0UL);
1305 }
1306 
1307 /**
1308   * @brief  Set Controller-role Request allowed (when the I3C is acting as target).
1309   * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1310   * @rmtoll DEVR0        CREN          LL_I3C_EnableControllerRoleReq
1311   * @param  I3Cx I3C Instance.
1312   * @retval None
1313   */
LL_I3C_EnableControllerRoleReq(I3C_TypeDef * I3Cx)1314 __STATIC_INLINE void LL_I3C_EnableControllerRoleReq(I3C_TypeDef *I3Cx)
1315 {
1316   SET_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN);
1317 }
1318 
1319 /**
1320   * @brief  Set Controller-role Request as not-allowed (when the I3C is acting as target).
1321   * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1322   * @rmtoll DEVR0        CREN          LL_I3C_DisableControllerRoleReq
1323   * @param  I3Cx I3C Instance.
1324   * @retval None
1325   */
LL_I3C_DisableControllerRoleReq(I3C_TypeDef * I3Cx)1326 __STATIC_INLINE void LL_I3C_DisableControllerRoleReq(I3C_TypeDef *I3Cx)
1327 {
1328   CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN);
1329 }
1330 
1331 /**
1332   * @brief  Check if Controller-role Request is allowed or not-allowed.
1333   * @rmtoll DEVR0        CREN          LL_I3C_IsEnabledControllerRoleReq
1334   * @param  I3Cx I3C Instance.
1335   * @retval State of bit (1 or 0).
1336   */
LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef * I3Cx)1337 __STATIC_INLINE uint32_t LL_I3C_IsEnabledControllerRoleReq(const I3C_TypeDef *I3Cx)
1338 {
1339   return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_CREN) == (I3C_DEVR0_CREN)) ? 1UL : 0UL);
1340 }
1341 
1342 /**
1343   * @brief  Set Hot Join allowed (when the I3C is acting as target).
1344   * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1345   * @rmtoll DEVR0        HJEN          LL_I3C_EnableHotJoin
1346   * @param  I3Cx I3C Instance.
1347   * @retval None
1348   */
LL_I3C_EnableHotJoin(I3C_TypeDef * I3Cx)1349 __STATIC_INLINE void LL_I3C_EnableHotJoin(I3C_TypeDef *I3Cx)
1350 {
1351   SET_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN);
1352 }
1353 
1354 /**
1355   * @brief  Set Hot Join as not-allowed (when the I3C is acting as target).
1356   * @note   This bit can be programmed when the I3C is disabled (EN = 0) or updated by HW upon reception of DISEC CCC.
1357   * @rmtoll DEVR0        HJEN          LL_I3C_DisableHotJoin
1358   * @param  I3Cx I3C Instance.
1359   * @retval None
1360   */
LL_I3C_DisableHotJoin(I3C_TypeDef * I3Cx)1361 __STATIC_INLINE void LL_I3C_DisableHotJoin(I3C_TypeDef *I3Cx)
1362 {
1363   CLEAR_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN);
1364 }
1365 
1366 /**
1367   * @brief  Check if Hot Join is allowed or not-allowed.
1368   * @rmtoll DEVR0        HJEN          LL_I3C_IsEnabledHotJoin
1369   * @param  I3Cx I3C Instance.
1370   * @retval State of bit (1 or 0).
1371   */
LL_I3C_IsEnabledHotJoin(const I3C_TypeDef * I3Cx)1372 __STATIC_INLINE uint32_t LL_I3C_IsEnabledHotJoin(const I3C_TypeDef *I3Cx)
1373 {
1374   return ((READ_BIT(I3Cx->DEVR0, I3C_DEVR0_HJEN) == (I3C_DEVR0_HJEN)) ? 1UL : 0UL);
1375 }
1376 
1377 /**
1378   * @brief  Configure Maximum Read Length (target mode).
1379   * @note   Those bits can be updated by HW upon reception of GETMRL CCC.
1380   * @rmtoll MAXRLR       MRL           LL_I3C_SetMaxReadLength
1381   * @param  I3Cx I3C Instance.
1382   * @param  MaxReadLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF
1383   * @retval None
1384   */
LL_I3C_SetMaxReadLength(I3C_TypeDef * I3Cx,uint16_t MaxReadLength)1385 __STATIC_INLINE void LL_I3C_SetMaxReadLength(I3C_TypeDef *I3Cx, uint16_t MaxReadLength)
1386 {
1387   MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_MRL, MaxReadLength);
1388 }
1389 
1390 /**
1391   * @brief  Return Maximum Read Length (target mode).
1392   * @rmtoll MAXRLR       MRL           LL_I3C_GetMaxReadLength
1393   * @param  I3Cx I3C Instance.
1394   * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF
1395   */
LL_I3C_GetMaxReadLength(const I3C_TypeDef * I3Cx)1396 __STATIC_INLINE uint32_t LL_I3C_GetMaxReadLength(const I3C_TypeDef *I3Cx)
1397 {
1398   return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_MRL));
1399 }
1400 
1401 /**
1402   * @brief  Configure the number of additional Mandatory Data Byte (MDB) sent to the controller
1403   *         after an acknowledge of the IBI (target mode).
1404   * @rmtoll MAXRLR       IBIP          LL_I3C_ConfigNbIBIAddData
1405   * @param  I3Cx I3C Instance.
1406   * @param  NbIBIAddData This parameter can be one of the following values:
1407   *         @arg @ref LL_I3C_PAYLOAD_EMPTY
1408   *         @arg @ref LL_I3C_PAYLOAD_1_BYTE
1409   *         @arg @ref LL_I3C_PAYLOAD_2_BYTES
1410   *         @arg @ref LL_I3C_PAYLOAD_3_BYTES
1411   *         @arg @ref LL_I3C_PAYLOAD_4_BYTES
1412   * @retval None
1413   */
LL_I3C_ConfigNbIBIAddData(I3C_TypeDef * I3Cx,uint32_t NbIBIAddData)1414 __STATIC_INLINE void LL_I3C_ConfigNbIBIAddData(I3C_TypeDef *I3Cx, uint32_t NbIBIAddData)
1415 {
1416   MODIFY_REG(I3Cx->MAXRLR, I3C_MAXRLR_IBIP, NbIBIAddData);
1417 }
1418 
1419 /**
1420   * @brief  Return the number of additional Mandatory Data Byte (MDB) sent to the controller
1421   *         after an acknowledge of the IBI (target mode).
1422   * @rmtoll MAXRLR       IBIP          LL_I3C_GetConfigNbIBIAddData
1423   * @param  I3Cx I3C Instance.
1424   * @retval Returned value can be one of the following values:
1425   *         @arg @ref LL_I3C_PAYLOAD_EMPTY
1426   *         @arg @ref LL_I3C_PAYLOAD_1_BYTE
1427   *         @arg @ref LL_I3C_PAYLOAD_2_BYTES
1428   *         @arg @ref LL_I3C_PAYLOAD_3_BYTES
1429   *         @arg @ref LL_I3C_PAYLOAD_4_BYTES
1430   */
LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef * I3Cx)1431 __STATIC_INLINE uint32_t LL_I3C_GetConfigNbIBIAddData(const I3C_TypeDef *I3Cx)
1432 {
1433   return (uint32_t)(READ_BIT(I3Cx->MAXRLR, I3C_MAXRLR_IBIP));
1434 }
1435 
1436 /**
1437   * @brief  Configure Maximum Write Length (target mode).
1438   * @note   Those bits can be updated by HW upon reception of GETMWL CCC.
1439   * @rmtoll MAXWLR       MWL           LL_I3C_SetMaxWriteLength
1440   * @param  I3Cx I3C Instance.
1441   * @param  MaxWriteLength This parameter must be a value between Min_Data=0x0 and Max_Data=0xFFFF
1442   * @retval None
1443   */
LL_I3C_SetMaxWriteLength(I3C_TypeDef * I3Cx,uint16_t MaxWriteLength)1444 __STATIC_INLINE void LL_I3C_SetMaxWriteLength(I3C_TypeDef *I3Cx, uint16_t MaxWriteLength)
1445 {
1446   MODIFY_REG(I3Cx->MAXWLR, I3C_MAXWLR_MWL, MaxWriteLength);
1447 }
1448 
1449 /**
1450   * @brief  Return Maximum Write Length (target mode).
1451   * @rmtoll MAXWLR       MWL           LL_I3C_GetMaxWriteLength
1452   * @param  I3Cx I3C Instance.
1453   * @retval Value between Min_Data=0x0 and Max_Data=0xFFFFF
1454   */
LL_I3C_GetMaxWriteLength(const I3C_TypeDef * I3Cx)1455 __STATIC_INLINE uint32_t LL_I3C_GetMaxWriteLength(const I3C_TypeDef *I3Cx)
1456 {
1457   return (uint32_t)(READ_BIT(I3Cx->MAXWLR, I3C_MAXWLR_MWL));
1458 }
1459 
1460 /**
1461   * @brief  Configure the SCL clock signal waveform.
1462   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1463   *
1464   * @note   This parameter is computed with the STM32CubeMX Tool.
1465   * @rmtoll TIMINGR0     TIMINGR0      LL_I3C_ConfigClockWaveForm
1466   * @param  I3Cx I3C Instance.
1467   * @param  ClockWaveForm This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1468   * @retval None
1469   */
LL_I3C_ConfigClockWaveForm(I3C_TypeDef * I3Cx,uint32_t ClockWaveForm)1470 __STATIC_INLINE void LL_I3C_ConfigClockWaveForm(I3C_TypeDef *I3Cx, uint32_t ClockWaveForm)
1471 {
1472   WRITE_REG(I3Cx->TIMINGR0, ClockWaveForm);
1473 }
1474 
1475 /**
1476   * @brief  Get the SCL clock signal waveform.
1477   * @rmtoll TIMINGR0     TIMINGR0      LL_I3C_GetClockWaveForm
1478   * @param  I3Cx I3C Instance.
1479   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF.
1480   */
LL_I3C_GetClockWaveForm(const I3C_TypeDef * I3Cx)1481 __STATIC_INLINE uint32_t LL_I3C_GetClockWaveForm(const I3C_TypeDef *I3Cx)
1482 {
1483   return (uint32_t)(READ_REG(I3Cx->TIMINGR0));
1484 }
1485 
1486 /**
1487   * @brief  Configure the SCL clock low period during I3C push-pull phases.
1488   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1489   *
1490   * @note   This parameter is computed with the STM32CubeMX Tool.
1491   * @rmtoll TIMINGR0     SCLL_PP       LL_I3C_SetPeriodClockLowPP
1492   * @param  I3Cx I3C Instance.
1493   * @param  PeriodClockLowPP This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1494   * @retval None
1495   */
LL_I3C_SetPeriodClockLowPP(I3C_TypeDef * I3Cx,uint32_t PeriodClockLowPP)1496 __STATIC_INLINE void LL_I3C_SetPeriodClockLowPP(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowPP)
1497 {
1498   MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP, (PeriodClockLowPP << I3C_TIMINGR0_SCLL_PP_Pos));
1499 }
1500 
1501 /**
1502   * @brief  Get the SCL clock low period during I3C push-pull phases.
1503   * @rmtoll TIMINGR0     SCLL_PP       LL_I3C_GetPeriodClockLowPP
1504   * @param  I3Cx I3C Instance.
1505   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1506   */
LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef * I3Cx)1507 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowPP(const I3C_TypeDef *I3Cx)
1508 {
1509   return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_PP) >> I3C_TIMINGR0_SCLL_PP_Pos);
1510 }
1511 
1512 /**
1513   * @brief  Configure the SCL clock High period during I3C open drain and push-pull phases.
1514   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1515   *
1516   * @note   This parameter is computed with the STM32CubeMX Tool.
1517   * @rmtoll TIMINGR0     SCLH_I3C      LL_I3C_SetPeriodClockHighI3C
1518   * @param  I3Cx I3C Instance.
1519   * @param  PeriodClockHighI3C This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1520   * @retval None
1521   */
LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef * I3Cx,uint32_t PeriodClockHighI3C)1522 __STATIC_INLINE void LL_I3C_SetPeriodClockHighI3C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI3C)
1523 {
1524   MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C, (PeriodClockHighI3C << I3C_TIMINGR0_SCLH_I3C_Pos));
1525 }
1526 
1527 /**
1528   * @brief  Get the SCL clock high period during I3C open drain and push-pull phases.
1529   * @rmtoll TIMINGR0     SCLH_I3C      LL_I3C_GetPeriodClockHighI3C
1530   * @param  I3Cx I3C Instance.
1531   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1532   */
LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef * I3Cx)1533 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI3C(const I3C_TypeDef *I3Cx)
1534 {
1535   return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I3C) >> I3C_TIMINGR0_SCLH_I3C_Pos);
1536 }
1537 
1538 /**
1539   * @brief  Configure the SCL clock low period during I3C open drain phases.
1540   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1541   *
1542   * @note   This parameter is computed with the STM32CubeMX Tool.
1543   * @rmtoll TIMINGR0     SCLL_OD       LL_I3C_SetPeriodClockLowOD
1544   * @param  I3Cx I3C Instance.
1545   * @param  PeriodClockLowOD This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1546   * @retval None
1547   */
LL_I3C_SetPeriodClockLowOD(I3C_TypeDef * I3Cx,uint32_t PeriodClockLowOD)1548 __STATIC_INLINE void LL_I3C_SetPeriodClockLowOD(I3C_TypeDef *I3Cx, uint32_t PeriodClockLowOD)
1549 {
1550   MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD, (PeriodClockLowOD << I3C_TIMINGR0_SCLL_OD_Pos));
1551 }
1552 
1553 /**
1554   * @brief  Get the SCL clock low period during I3C open phases.
1555   * @rmtoll TIMINGR0     SCLL_OD       LL_I3C_GetPeriodClockLowOD
1556   * @param  I3Cx I3C Instance.
1557   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1558   */
LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef * I3Cx)1559 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockLowOD(const I3C_TypeDef *I3Cx)
1560 {
1561   return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLL_OD) >> I3C_TIMINGR0_SCLL_OD_Pos);
1562 }
1563 
1564 /**
1565   * @brief  Configure the SCL clock High period during I2C open drain phases.
1566   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1567   *
1568   * @note   This parameter is computed with the STM32CubeMX Tool.
1569   * @rmtoll TIMINGR0     SCLH_I2C      LL_I3C_SetPeriodClockHighI2C
1570   * @param  I3Cx I3C Instance.
1571   * @param  PeriodClockHighI2C This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1572   * @retval None
1573   */
LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef * I3Cx,uint32_t PeriodClockHighI2C)1574 __STATIC_INLINE void LL_I3C_SetPeriodClockHighI2C(I3C_TypeDef *I3Cx, uint32_t PeriodClockHighI2C)
1575 {
1576   MODIFY_REG(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C, PeriodClockHighI2C << I3C_TIMINGR0_SCLH_I2C_Pos);
1577 }
1578 
1579 /**
1580   * @brief  Get the SCL clock high period during I2C open drain phases.
1581   * @rmtoll TIMINGR0     SCLH_I2C      LL_I3C_GetPeriodClockHighI2C
1582   * @param  I3Cx I3C Instance.
1583   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1584   */
LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef * I3Cx)1585 __STATIC_INLINE uint32_t LL_I3C_GetPeriodClockHighI2C(const I3C_TypeDef *I3Cx)
1586 {
1587   return (uint32_t)(READ_BIT(I3Cx->TIMINGR0, I3C_TIMINGR0_SCLH_I2C) >> I3C_TIMINGR0_SCLH_I2C_Pos);
1588 }
1589 
1590 /**
1591   * @brief  Configure the Controller additional hold time on SDA line.
1592   * @rmtoll TIMINGR1     SDA_HD        LL_I3C_SetDataHoldTime
1593   * @param  I3Cx I3C Instance.
1594   * @param  DataHoldTime This parameter can be one of the following values:
1595   *         @arg @ref LL_I3C_SDA_HOLD_TIME_0_5
1596   *         @arg @ref LL_I3C_SDA_HOLD_TIME_1_5
1597   * @retval None
1598   */
LL_I3C_SetDataHoldTime(I3C_TypeDef * I3Cx,uint32_t DataHoldTime)1599 __STATIC_INLINE void LL_I3C_SetDataHoldTime(I3C_TypeDef *I3Cx, uint32_t DataHoldTime)
1600 {
1601   MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD, DataHoldTime);
1602 }
1603 
1604 /**
1605   * @brief  Get the Controller additional hold time on SDA line.
1606   * @rmtoll TIMINGR1     SDA_HD        LL_I3C_GetDataHoldTime
1607   * @param  I3Cx I3C Instance.
1608   * @retval Returned value can be one of the following values:
1609   *         @arg @ref LL_I3C_SDA_HOLD_TIME_0_5
1610   *         @arg @ref LL_I3C_SDA_HOLD_TIME_1_5
1611   */
LL_I3C_GetDataHoldTime(const I3C_TypeDef * I3Cx)1612 __STATIC_INLINE uint32_t LL_I3C_GetDataHoldTime(const I3C_TypeDef *I3Cx)
1613 {
1614   return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_SDA_HD));
1615 }
1616 
1617 /**
1618   * @brief  Configure the Idle, Available state.
1619   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1620   *
1621   * @note   This parameter is computed with the STM32CubeMX Tool.
1622   * @rmtoll TIMINGR1     AVAL          LL_I3C_SetAvalTiming
1623   * @param  I3Cx I3C Instance.
1624   * @param  AvalTiming This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1625   * @retval None
1626   */
LL_I3C_SetAvalTiming(I3C_TypeDef * I3Cx,uint32_t AvalTiming)1627 __STATIC_INLINE void LL_I3C_SetAvalTiming(I3C_TypeDef *I3Cx, uint32_t AvalTiming)
1628 {
1629   MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (AvalTiming << I3C_TIMINGR1_AVAL_Pos));
1630 }
1631 
1632 /**
1633   * @brief  Get the Idle, Available integer value state.
1634   * @rmtoll TIMINGR1     AVAL          LL_I3C_GetAvalTiming
1635   * @param  I3Cx I3C Instance.
1636   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1637   */
LL_I3C_GetAvalTiming(const I3C_TypeDef * I3Cx)1638 __STATIC_INLINE uint32_t LL_I3C_GetAvalTiming(const I3C_TypeDef *I3Cx)
1639 {
1640   return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL) >> I3C_TIMINGR1_AVAL_Pos);
1641 }
1642 
1643 /**
1644   * @brief  Configure the Free state.
1645   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1646   *
1647   * @note   This parameter is computed with the STM32CubeMX Tool.
1648   * @rmtoll TIMINGR1     FREE          LL_I3C_SetFreeTiming
1649   * @param  I3Cx I3C Instance.
1650   * @param  FreeTiming This parameter must be a value between Min_Data=0 and Max_Data=0x3F.
1651   * @retval None
1652   */
LL_I3C_SetFreeTiming(I3C_TypeDef * I3Cx,uint32_t FreeTiming)1653 __STATIC_INLINE void LL_I3C_SetFreeTiming(I3C_TypeDef *I3Cx, uint32_t FreeTiming)
1654 {
1655   MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE, (FreeTiming << I3C_TIMINGR1_FREE_Pos));
1656 }
1657 
1658 /**
1659   * @brief  Get the Free integeter value state.
1660   * @rmtoll TIMINGR1     FREE          LL_I3C_GetFreeTiming
1661   * @param  I3Cx I3C Instance.
1662   * @retval Value between Min_Data=0 and Max_Data=0x3F.
1663   */
LL_I3C_GetFreeTiming(const I3C_TypeDef * I3Cx)1664 __STATIC_INLINE uint32_t LL_I3C_GetFreeTiming(const I3C_TypeDef *I3Cx)
1665 {
1666   return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_FREE) >> I3C_TIMINGR1_FREE_Pos);
1667 }
1668 
1669 /**
1670   * @brief  Configure the activity state of the new controller.
1671   * @note   Refer to MIPI I3C specification (https:__www.mipi.org_specifications)
1672   *         for more details related to Activity State.
1673   * @rmtoll TIMINGR1     ASNCR            LL_I3C_SetControllerActivityState
1674   * @param  I3Cx I3C Instance.
1675   * @param  ControllerActivityState This parameter can be one of the following values:
1676   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0
1677   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1
1678   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2
1679   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3
1680   * @retval None
1681   */
LL_I3C_SetControllerActivityState(I3C_TypeDef * I3Cx,uint32_t ControllerActivityState)1682 __STATIC_INLINE void LL_I3C_SetControllerActivityState(I3C_TypeDef *I3Cx, uint32_t ControllerActivityState)
1683 {
1684   MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR, ControllerActivityState);
1685 }
1686 
1687 /**
1688   * @brief  Get the activity state of the new controller.
1689   * @note   Refer to MIPI I3C specification (https:__www.mipi.org_specifications)
1690   *         for more details related to Activity State.
1691   * @rmtoll TIMINGR1     ASNCR            LL_I3C_GetControllerActivityState
1692   * @param  I3Cx I3C Instance.
1693   * @retval Returned value can be one of the following values:
1694   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_0
1695   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_1
1696   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_2
1697   *         @arg @ref LL_I3C_OWN_ACTIVITY_STATE_3
1698   */
LL_I3C_GetControllerActivityState(const I3C_TypeDef * I3Cx)1699 __STATIC_INLINE uint32_t LL_I3C_GetControllerActivityState(const I3C_TypeDef *I3Cx)
1700 {
1701   return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_ASNCR));
1702 }
1703 
1704 /**
1705   * @brief  Configure the Controller SDA Hold time, Bus Free, Activity state, Idle state.
1706   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1707   *
1708   * @note   This parameter is computed with the STM32CubeMX Tool.
1709   * @rmtoll TIMINGR1     SDA_HD        LL_I3C_SetCtrlBusCharacteristic\n
1710   *         TIMINGR1     FREE          LL_I3C_SetCtrlBusCharacteristic\n
1711   *         TIMINGR1     ASNCR         LL_I3C_SetCtrlBusCharacteristic\n
1712   *         TIMINGR1     IDLE          LL_I3C_SetCtrlBusCharacteristic
1713   * @param  I3Cx I3C Instance.
1714   * @param  CtrlBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0x107F03FF.
1715   * @retval None
1716   */
LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef * I3Cx,uint32_t CtrlBusCharacteristic)1717 __STATIC_INLINE void LL_I3C_SetCtrlBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t CtrlBusCharacteristic)
1718 {
1719   WRITE_REG(I3Cx->TIMINGR1, CtrlBusCharacteristic);
1720 }
1721 
1722 /**
1723   * @brief  Get the Controller SDA Hold time, Bus Free, Activity state, Idle state.
1724   * @rmtoll TIMINGR1     SDA_HD        LL_I3C_GetCtrlBusCharacteristic\n
1725   *         TIMINGR1     FREE          LL_I3C_GetCtrlBusCharacteristic\n
1726   *         TIMINGR1     ASNCR         LL_I3C_GetCtrlBusCharacteristic\n
1727   *         TIMINGR1     IDLE          LL_I3C_GetCtrlBusCharacteristic
1728   * @param  I3Cx I3C Instance.
1729   * @retval Value between Min_Data=0 and Max_Data=0x107F03FF.
1730   */
LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef * I3Cx)1731 __STATIC_INLINE uint32_t LL_I3C_GetCtrlBusCharacteristic(const I3C_TypeDef *I3Cx)
1732 {
1733   return (uint32_t)(READ_REG(I3Cx->TIMINGR1));
1734 }
1735 
1736 /**
1737   * @brief  Configure the Target Available state.
1738   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1739   *
1740   * @note   This parameter is computed with the STM32CubeMX Tool.
1741   * @rmtoll TIMINGR1     IDLE          LL_I3C_SetTgtBusCharacteristic
1742   * @param  I3Cx I3C Instance.
1743   * @param  TgtBusCharacteristic This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1744   * @retval None
1745   */
LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef * I3Cx,uint32_t TgtBusCharacteristic)1746 __STATIC_INLINE void LL_I3C_SetTgtBusCharacteristic(I3C_TypeDef *I3Cx, uint32_t TgtBusCharacteristic)
1747 {
1748   MODIFY_REG(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL, (TgtBusCharacteristic & I3C_TIMINGR1_AVAL));
1749 }
1750 
1751 /**
1752   * @brief  Get the Target Available state.
1753   * @rmtoll TIMINGR1     IDLE          LL_I3C_GetTgtBusCharacteristic
1754   * @param  I3Cx I3C Instance.
1755   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1756   */
LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef * I3Cx)1757 __STATIC_INLINE uint32_t LL_I3C_GetTgtBusCharacteristic(const I3C_TypeDef *I3Cx)
1758 {
1759   return (uint32_t)(READ_BIT(I3Cx->TIMINGR1, I3C_TIMINGR1_AVAL));
1760 }
1761 
1762 /**
1763   * @brief  Configure the SCL clock stalling time on I3C Bus (controller mode).
1764   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
1765   *
1766   * @note   This parameter is computed with the STM32CubeMX Tool.
1767   * @rmtoll TIMINGR2     STALL        LL_I3C_SetStallTime
1768   * @param  I3Cx I3C Instance.
1769   * @param  ControllerStallTime This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
1770   * @retval None
1771   */
LL_I3C_SetStallTime(I3C_TypeDef * I3Cx,uint32_t ControllerStallTime)1772 __STATIC_INLINE void LL_I3C_SetStallTime(I3C_TypeDef *I3Cx, uint32_t ControllerStallTime)
1773 {
1774   MODIFY_REG(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL, (ControllerStallTime << I3C_TIMINGR2_STALL_Pos));
1775 }
1776 
1777 /**
1778   * @brief  Get the SCL clock stalling time on I3C Bus (controller mode).
1779   * @rmtoll TIMINGR2     STALL        LL_I3C_GetStallTime
1780   * @param  I3Cx I3C Instance.
1781   * @retval Value between Min_Data=0 and Max_Data=0xFF.
1782   */
LL_I3C_GetStallTime(const I3C_TypeDef * I3Cx)1783 __STATIC_INLINE uint32_t LL_I3C_GetStallTime(const I3C_TypeDef *I3Cx)
1784 {
1785   return (uint32_t)(READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALL));
1786 }
1787 
1788 /**
1789   * @brief  Set stall on ACK bit (controller mode).
1790   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1791   * @rmtoll TIMINGR2     STALLA       LL_I3C_EnableStallACK
1792   * @param  I3Cx I3C Instance.
1793   * @retval None
1794   */
LL_I3C_EnableStallACK(I3C_TypeDef * I3Cx)1795 __STATIC_INLINE void LL_I3C_EnableStallACK(I3C_TypeDef *I3Cx)
1796 {
1797   SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA);
1798 }
1799 
1800 /**
1801   * @brief  Disable stall on ACK bit (controller mode).
1802   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1803   * @rmtoll TIMINGR2     STALLA       LL_I3C_DisableStallACK
1804   * @param  I3Cx I3C Instance.
1805   * @retval None
1806   */
LL_I3C_DisableStallACK(I3C_TypeDef * I3Cx)1807 __STATIC_INLINE void LL_I3C_DisableStallACK(I3C_TypeDef *I3Cx)
1808 {
1809   CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA);
1810 }
1811 
1812 /**
1813   * @brief  Check if stall on ACK bit is enabled or disabled (controller mode).
1814   * @rmtoll TIMINGR2     STALLA       LL_I3C_IsEnabledStallACK
1815   * @param  I3Cx I3C Instance.
1816   * @retval State of bit (1 or 0).
1817   */
LL_I3C_IsEnabledStallACK(const I3C_TypeDef * I3Cx)1818 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallACK(const I3C_TypeDef *I3Cx)
1819 {
1820   return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLA) == (I3C_TIMINGR2_STALLA)) ? 1UL : 0UL);
1821 }
1822 
1823 /**
1824   * @brief  Set stall on Parity bit of Command Code byte (controller mode).
1825   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1826   * @rmtoll TIMINGR2     STALLC       LL_I3C_EnableStallParityCCC
1827   * @param  I3Cx I3C Instance.
1828   * @retval None
1829   */
LL_I3C_EnableStallParityCCC(I3C_TypeDef * I3Cx)1830 __STATIC_INLINE void LL_I3C_EnableStallParityCCC(I3C_TypeDef *I3Cx)
1831 {
1832   SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC);
1833 }
1834 
1835 /**
1836   * @brief  Disable stall on Parity bit of Command Code byte (controller mode).
1837   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1838   * @rmtoll TIMINGR2     STALLC       LL_I3C_DisableStallParityCCC
1839   * @param  I3Cx I3C Instance.
1840   * @retval None
1841   */
LL_I3C_DisableStallParityCCC(I3C_TypeDef * I3Cx)1842 __STATIC_INLINE void LL_I3C_DisableStallParityCCC(I3C_TypeDef *I3Cx)
1843 {
1844   CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC);
1845 }
1846 
1847 /**
1848   * @brief  Check if stall on Parity bit of Command Code byte is enabled or disabled (controller mode).
1849   * @rmtoll TIMINGR2     STALLC       LL_I3C_IsEnabledStallParityCCC
1850   * @param  I3Cx I3C Instance.
1851   * @retval State of bit (1 or 0).
1852   */
LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef * I3Cx)1853 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityCCC(const I3C_TypeDef *I3Cx)
1854 {
1855   return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLC) == (I3C_TIMINGR2_STALLC)) ? 1UL : 0UL);
1856 }
1857 
1858 /**
1859   * @brief  Set stall on Parity bit of Data bytes (controller mode).
1860   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1861   * @rmtoll TIMINGR2     STALLD       LL_I3C_EnableStallParityData
1862   * @param  I3Cx I3C Instance.
1863   * @retval None
1864   */
LL_I3C_EnableStallParityData(I3C_TypeDef * I3Cx)1865 __STATIC_INLINE void LL_I3C_EnableStallParityData(I3C_TypeDef *I3Cx)
1866 {
1867   SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD);
1868 }
1869 
1870 /**
1871   * @brief  Disable stall on Parity bit of Data bytes (controller mode).
1872   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1873   * @rmtoll TIMINGR2     STALLD       LL_I3C_DisableStallParityData
1874   * @param  I3Cx I3C Instance.
1875   * @retval None
1876   */
LL_I3C_DisableStallParityData(I3C_TypeDef * I3Cx)1877 __STATIC_INLINE void LL_I3C_DisableStallParityData(I3C_TypeDef *I3Cx)
1878 {
1879   CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD);
1880 }
1881 
1882 /**
1883   * @brief  Check if stall on Parity bit of Data bytes is enabled or disabled (controller mode).
1884   * @rmtoll TIMINGR2     STALLD       LL_I3C_IsEnabledStallParityData
1885   * @param  I3Cx I3C Instance.
1886   * @retval State of bit (1 or 0).
1887   */
LL_I3C_IsEnabledStallParityData(const I3C_TypeDef * I3Cx)1888 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallParityData(const I3C_TypeDef *I3Cx)
1889 {
1890   return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLD) == (I3C_TIMINGR2_STALLD)) ? 1UL : 0UL);
1891 }
1892 
1893 /**
1894   * @brief  Set stall on T bit (controller mode).
1895   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1896   * @rmtoll TIMINGR2     STALLT       LL_I3C_EnableStallTbit
1897   * @param  I3Cx I3C Instance.
1898   * @retval None
1899   */
LL_I3C_EnableStallTbit(I3C_TypeDef * I3Cx)1900 __STATIC_INLINE void LL_I3C_EnableStallTbit(I3C_TypeDef *I3Cx)
1901 {
1902   SET_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT);
1903 }
1904 
1905 /**
1906   * @brief  Disable stall on T bit (controller mode).
1907   * @note   This bit can be programmed when the I3C is disabled (EN = 0).
1908   * @rmtoll TIMINGR2     STALLT       LL_I3C_DisableStallTbit
1909   * @param  I3Cx I3C Instance.
1910   * @retval None
1911   */
LL_I3C_DisableStallTbit(I3C_TypeDef * I3Cx)1912 __STATIC_INLINE void LL_I3C_DisableStallTbit(I3C_TypeDef *I3Cx)
1913 {
1914   CLEAR_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT);
1915 }
1916 
1917 /**
1918   * @brief  Check if stall on T bit is enabled or disabled (controller mode).
1919   * @rmtoll TIMINGR2     STALLT       LL_I3C_IsEnabledStallTbit
1920   * @param  I3Cx I3C Instance.
1921   * @retval State of bit (1 or 0).
1922   */
LL_I3C_IsEnabledStallTbit(const I3C_TypeDef * I3Cx)1923 __STATIC_INLINE uint32_t LL_I3C_IsEnabledStallTbit(const I3C_TypeDef *I3Cx)
1924 {
1925   return ((READ_BIT(I3Cx->TIMINGR2, I3C_TIMINGR2_STALLT) == (I3C_TIMINGR2_STALLT)) ? 1UL : 0UL);
1926 }
1927 
1928 /**
1929   * @brief  Configure the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6).
1930   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
1931   * @rmtoll BCR          BCR6          LL_I3C_SetDeviceCapabilityOnBus
1932   * @param  I3Cx I3C Instance.
1933   * @param  DeviceCapabilityOnBus This parameter can be one of the following values:
1934   *         @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET
1935   *         @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER
1936   * @retval None
1937   */
LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef * I3Cx,uint32_t DeviceCapabilityOnBus)1938 __STATIC_INLINE void LL_I3C_SetDeviceCapabilityOnBus(I3C_TypeDef *I3Cx, uint32_t DeviceCapabilityOnBus)
1939 {
1940   MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR6, DeviceCapabilityOnBus);
1941 }
1942 
1943 /**
1944   * @brief  Get the Device Capability on Bus as Target or Controller (MIPI Bus Characteristics Register BCR6).
1945   * @rmtoll BCR          BCR6          LL_I3C_GetDeviceCapabilityOnBus
1946   * @param  I3Cx I3C Instance.
1947   * @retval Returned value can be one of the following values:
1948   *         @arg @ref LL_I3C_DEVICE_ROLE_AS_TARGET
1949   *         @arg @ref LL_I3C_DEVICE_ROLE_AS_CONTROLLER
1950   */
LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef * I3Cx)1951 __STATIC_INLINE uint32_t LL_I3C_GetDeviceCapabilityOnBus(const I3C_TypeDef *I3Cx)
1952 {
1953   return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR6));
1954 }
1955 
1956 /**
1957   * @brief  Configure the Device IBI Payload (MIPI Bus Characteristics Register BCR2).
1958   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
1959   * @rmtoll BCR          BCR2          LL_I3C_SetDeviceIBIPayload
1960   * @param  I3Cx I3C Instance.
1961   * @param  DeviceIBIPayload This parameter can be one of the following values:
1962   *         @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA
1963   *         @arg @ref LL_I3C_IBI_ADDITIONAL_DATA
1964   * @retval None
1965   */
LL_I3C_SetDeviceIBIPayload(I3C_TypeDef * I3Cx,uint32_t DeviceIBIPayload)1966 __STATIC_INLINE void LL_I3C_SetDeviceIBIPayload(I3C_TypeDef *I3Cx, uint32_t DeviceIBIPayload)
1967 {
1968   MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR2, DeviceIBIPayload);
1969 }
1970 
1971 /**
1972   * @brief  Get the Device IBI Payload (MIPI Bus Characteristics Register BCR2).
1973   * @rmtoll BCR          BCR2          LL_I3C_GetDeviceIBIPayload
1974   * @param  I3Cx I3C Instance.
1975   * @retval Returned value can be one of the following values:
1976   *         @arg @ref LL_I3C_IBI_NO_ADDITIONAL_DATA
1977   *         @arg @ref LL_I3C_IBI_ADDITIONAL_DATA
1978   */
LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef * I3Cx)1979 __STATIC_INLINE uint32_t LL_I3C_GetDeviceIBIPayload(const I3C_TypeDef *I3Cx)
1980 {
1981   return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR2));
1982 }
1983 
1984 /**
1985   * @brief  Configure the Data Speed Limitation (limitation, as described by I3C_GETMXDSR).
1986   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
1987   * @rmtoll BCR          BCR0          LL_I3C_SetDataSpeedLimitation
1988   * @param  I3Cx I3C Instance.
1989   * @param  DataSpeedLimitation This parameter can be one of the following values:
1990   *         @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION
1991   *         @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION
1992   * @retval None
1993   */
LL_I3C_SetDataSpeedLimitation(I3C_TypeDef * I3Cx,uint32_t DataSpeedLimitation)1994 __STATIC_INLINE void LL_I3C_SetDataSpeedLimitation(I3C_TypeDef *I3Cx, uint32_t DataSpeedLimitation)
1995 {
1996   MODIFY_REG(I3Cx->BCR, I3C_BCR_BCR0, DataSpeedLimitation);
1997 }
1998 
1999 /**
2000   * @brief  Get  the Data Speed Limitation (limitation, as described by I3C_GETMXDSR).
2001   * @rmtoll BCR          BCR0          LL_I3C_GetDataSpeedLimitation
2002   * @param  I3Cx I3C Instance.
2003   * @retval Returned value can be one of the following values:
2004   *         @arg @ref LL_I3C_NO_DATA_SPEED_LIMITATION
2005   *         @arg @ref LL_I3C_MAX_DATA_SPEED_LIMITATION
2006   */
LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef * I3Cx)2007 __STATIC_INLINE uint32_t LL_I3C_GetDataSpeedLimitation(const I3C_TypeDef *I3Cx)
2008 {
2009   return (uint32_t)(READ_BIT(I3Cx->BCR, I3C_BCR_BCR0));
2010 }
2011 
2012 /**
2013   * @brief  Configure the Device Characteristics Register (DCR).
2014   * @note   This bit can only be programmed when the I3C is disabled (EN = 0).
2015   *
2016   * @note   Refer MIPI web site for the list of device code available.
2017   * @rmtoll DCR          DC            LL_I3C_SetDeviceCharacteristics
2018   * @param  I3Cx I3C Instance.
2019   * @param  DeviceCharacteristics This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
2020   * @retval None
2021   */
LL_I3C_SetDeviceCharacteristics(I3C_TypeDef * I3Cx,uint32_t DeviceCharacteristics)2022 __STATIC_INLINE void LL_I3C_SetDeviceCharacteristics(I3C_TypeDef *I3Cx, uint32_t DeviceCharacteristics)
2023 {
2024   MODIFY_REG(I3Cx->DCR, I3C_DCR_DCR, DeviceCharacteristics);
2025 }
2026 
2027 /**
2028   * @brief  Get the Device Characteristics Register (DCR).
2029   * @note   Refer MIPI web site to associated value with the list of device code available.
2030   * @rmtoll DCR          DCR            LL_I3C_GetDeviceCharacteristics
2031   * @param  I3Cx I3C Instance.
2032   * @retval Value between Min_Data=0 and Max_Data=0xFF.
2033   */
LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef * I3Cx)2034 __STATIC_INLINE uint32_t LL_I3C_GetDeviceCharacteristics(const I3C_TypeDef *I3Cx)
2035 {
2036   return (uint32_t)(READ_BIT(I3Cx->DCR, I3C_DCR_DCR));
2037 }
2038 
2039 /**
2040   * @brief  Configure IBI MDB support for pending read notification.
2041   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2042   * @rmtoll GETCAPR     CAPPEND          LL_I3C_SetPendingReadMDB
2043   * @param  I3Cx I3C Instance.
2044   * @param  PendingReadMDB This parameter can be one of the following values:
2045   *         @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION
2046   *         @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION
2047   * @retval None
2048   */
LL_I3C_SetPendingReadMDB(I3C_TypeDef * I3Cx,uint32_t PendingReadMDB)2049 __STATIC_INLINE void LL_I3C_SetPendingReadMDB(I3C_TypeDef *I3Cx, uint32_t PendingReadMDB)
2050 {
2051   MODIFY_REG(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND, PendingReadMDB);
2052 }
2053 
2054 /**
2055   * @brief  Get IBI MDB support for pending read notification value.
2056   * @rmtoll GETCAPR     CAPPEND          LL_I3C_GetPendingReadMDB
2057   * @param  I3Cx I3C Instance.
2058   * @retval Returned value can be one of the following values:
2059   *         @arg @ref LL_I3C_MDB_NO_PENDING_READ_NOTIFICATION
2060   *         @arg @ref LL_I3C_MDB_PENDING_READ_NOTIFICATION
2061   */
LL_I3C_GetPendingReadMDB(const I3C_TypeDef * I3Cx)2062 __STATIC_INLINE uint32_t LL_I3C_GetPendingReadMDB(const I3C_TypeDef *I3Cx)
2063 {
2064   return (uint32_t)(READ_BIT(I3Cx->GETCAPR, I3C_GETCAPR_CAPPEND));
2065 }
2066 
2067 /**
2068   * @brief  Configure the Group Management Support bit of MSTCAP1.
2069   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2070   * @rmtoll CRCAPR      CAPGRP        LL_I3C_SetGrpAddrHandoffSupport
2071   * @param  I3Cx I3C Instance.
2072   * @param  GrpAddrHandoffSupport This parameter can be one of the following values:
2073   *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED
2074   *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED
2075   * @retval None
2076   */
LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef * I3Cx,uint32_t GrpAddrHandoffSupport)2077 __STATIC_INLINE void LL_I3C_SetGrpAddrHandoffSupport(I3C_TypeDef *I3Cx, uint32_t GrpAddrHandoffSupport)
2078 {
2079   MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP, GrpAddrHandoffSupport);
2080 }
2081 
2082 /**
2083   * @brief  Get the Group Management Support bit of MSTCAP1.
2084   * @rmtoll CRCAPR      CAPGRP        LL_I3C_GetGrpAddrHandoffSupport
2085   * @param  I3Cx I3C Instance.
2086   * @retval Returned value can be one of the following values:
2087   *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_NOT_SUPPORTED
2088   *         @arg @ref LL_I3C_HANDOFF_GRP_ADDR_SUPPORTED
2089   */
LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef * I3Cx)2090 __STATIC_INLINE uint32_t LL_I3C_GetGrpAddrHandoffSupport(const I3C_TypeDef *I3Cx)
2091 {
2092   return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPGRP));
2093 }
2094 
2095 /**
2096   * @brief  Configure the Delayed Controller Handoff bit in MSTCAP2.
2097   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2098   * @rmtoll CRCAPR      CAPDHOFF      LL_I3C_SetControllerHandoffDelayed
2099   * @param  I3Cx I3C Instance.
2100   * @param  ControllerHandoffDelayed This parameter can be one of the following values:
2101   *         @arg @ref LL_I3C_HANDOFF_NOT_DELAYED
2102   *         @arg @ref LL_I3C_HANDOFF_DELAYED
2103   * @retval None
2104   */
LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef * I3Cx,uint32_t ControllerHandoffDelayed)2105 __STATIC_INLINE void LL_I3C_SetControllerHandoffDelayed(I3C_TypeDef *I3Cx, uint32_t ControllerHandoffDelayed)
2106 {
2107   MODIFY_REG(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF, ControllerHandoffDelayed);
2108 }
2109 
2110 /**
2111   * @brief  Get the Delayed Controller Handoff bit in MSTCAP2.
2112   * @rmtoll CRCAPR      CAPDHOFF      LL_I3C_GetControllerHandoffDelayed
2113   * @param  I3Cx I3C Instance.
2114   * @retval Returned value can be one of the following values:
2115   *         @arg @ref LL_I3C_HANDOFF_NOT_DELAYED
2116   *         @arg @ref LL_I3C_HANDOFF_DELAYED
2117   */
LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef * I3Cx)2118 __STATIC_INLINE uint32_t LL_I3C_GetControllerHandoffDelayed(const I3C_TypeDef *I3Cx)
2119 {
2120   return (uint32_t)(READ_BIT(I3Cx->CRCAPR, I3C_CRCAPR_CAPDHOFF));
2121 }
2122 
2123 /**
2124   * @brief  Configure the Activity State after controllership handoff.
2125   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2126   * @rmtoll GETMXDSR     HOFFAS        LL_I3C_SetHandoffActivityState
2127   * @param  I3Cx I3C Instance.
2128   * @param  HandoffActivityState This parameter can be one of the following values:
2129   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0
2130   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1
2131   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2
2132   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3
2133   * @retval None
2134   */
LL_I3C_SetHandoffActivityState(I3C_TypeDef * I3Cx,uint32_t HandoffActivityState)2135 __STATIC_INLINE void LL_I3C_SetHandoffActivityState(I3C_TypeDef *I3Cx, uint32_t HandoffActivityState)
2136 {
2137   MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS, HandoffActivityState);
2138 }
2139 
2140 /**
2141   * @brief  Get the Activity State after controllership handoff.
2142   * @rmtoll GETMXDSR     HOFFAS        LL_I3C_GetHandoffActivityState
2143   * @param  I3Cx I3C Instance.
2144   * @retval Returned value can be one of the following values:
2145   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_0
2146   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_1
2147   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_2
2148   *         @arg @ref LL_I3C_HANDOFF_ACTIVITY_STATE_3
2149   */
LL_I3C_GetHandoffActivityState(const I3C_TypeDef * I3Cx)2150 __STATIC_INLINE uint32_t LL_I3C_GetHandoffActivityState(const I3C_TypeDef *I3Cx)
2151 {
2152   return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_HOFFAS));
2153 }
2154 
2155 /**
2156   * @brief  Configure the Max Data Speed Format response for GETMXDS CCC.
2157   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2158   * @rmtoll GETMXDSR     FMT          LL_I3C_SetMaxDataSpeedFormat
2159   * @param  I3Cx I3C Instance.
2160   * @param  MaxDataSpeedFormat This parameter can be one of the following values:
2161   *         @arg @ref LL_I3C_GETMXDS_FORMAT_1
2162   *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB
2163   *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID
2164   *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB
2165   * @retval None
2166   */
LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef * I3Cx,uint32_t MaxDataSpeedFormat)2167 __STATIC_INLINE void LL_I3C_SetMaxDataSpeedFormat(I3C_TypeDef *I3Cx, uint32_t MaxDataSpeedFormat)
2168 {
2169   MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT, MaxDataSpeedFormat);
2170 }
2171 
2172 /**
2173   * @brief  Get the Max Data Speed Format response for GETMXDS CCC.
2174   * @rmtoll GETMXDSR     FMT          LL_I3C_GetMaxDataSpeedFormat
2175   * @param  I3Cx I3C Instance.
2176   * @retval Returned value can be one of the following values:
2177   *         @arg @ref LL_I3C_GETMXDS_FORMAT_1
2178   *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_LSB
2179   *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MID
2180   *         @arg @ref LL_I3C_GETMXDS_FORMAT_2_MSB
2181   */
LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef * I3Cx)2182 __STATIC_INLINE uint32_t LL_I3C_GetMaxDataSpeedFormat(const I3C_TypeDef *I3Cx)
2183 {
2184   return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_FMT));
2185 }
2186 
2187 /**
2188   * @brief  Configure the Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround.
2189   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2190   * @rmtoll GETMXDSR     RDTURN        LL_I3C_SetMiddleByteTurnAround
2191   * @param  I3Cx I3C Instance.
2192   * @param  MiddleByteTurnAround This parameter must be a value between Min_Data=0 and Max_Data=0xF.
2193   * @retval None
2194   */
LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef * I3Cx,uint32_t MiddleByteTurnAround)2195 __STATIC_INLINE void LL_I3C_SetMiddleByteTurnAround(I3C_TypeDef *I3Cx, uint32_t MiddleByteTurnAround)
2196 {
2197   MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN, (MiddleByteTurnAround << I3C_GETMXDSR_RDTURN_Pos));
2198 }
2199 
2200 /**
2201   * @brief  Get the value of Middle byte of MaxRdTurn field of GETMXDS CCC Format 2 with turnaround.
2202   * @rmtoll GETMXDSR     RDTURN        LL_I3C_GetMiddleByteTurnAround
2203   * @param  I3Cx I3C Instance.
2204   * @retval Value between Min_Data=0 and Max_Data=0xF.
2205   */
LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef * I3Cx)2206 __STATIC_INLINE uint32_t LL_I3C_GetMiddleByteTurnAround(const I3C_TypeDef *I3Cx)
2207 {
2208   return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_RDTURN));
2209 }
2210 
2211 /**
2212   * @brief  Configure clock-to-data turnaround time.
2213   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2214   * @rmtoll GETMXDSR     TSCO          LL_I3C_SetDataTurnAroundTime
2215   * @param  I3Cx I3C Instance.
2216   * @param  DataTurnAroundTime This parameter can be one of the following values:
2217   *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
2218   *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
2219   * @retval None
2220   */
LL_I3C_SetDataTurnAroundTime(I3C_TypeDef * I3Cx,uint32_t DataTurnAroundTime)2221 __STATIC_INLINE void LL_I3C_SetDataTurnAroundTime(I3C_TypeDef *I3Cx, uint32_t DataTurnAroundTime)
2222 {
2223   MODIFY_REG(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO, DataTurnAroundTime);
2224 }
2225 
2226 /**
2227   * @brief  Get clock-to-data turnaround time.
2228   * @rmtoll GETMXDSR     TSCO          LL_I3C_GetDataTurnAroundTime
2229   * @param  I3Cx I3C Instance.
2230   * @retval Returned value can be one of the following values:
2231   *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS
2232   *         @arg @ref LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS
2233   */
LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef * I3Cx)2234 __STATIC_INLINE uint32_t LL_I3C_GetDataTurnAroundTime(const I3C_TypeDef *I3Cx)
2235 {
2236   return (uint32_t)(READ_BIT(I3Cx->GETMXDSR, I3C_GETMXDSR_TSCO));
2237 }
2238 
2239 /**
2240   * @brief  Configure the MIPI Instance ID.
2241   * @note   Those bits can be programmed when the I3C is disabled (EN = 0).
2242   * @rmtoll EPIDR        MIPIID       LL_I3C_SetMIPIInstanceID
2243   * @param  I3Cx I3C Instance.
2244   * @param  MIPIInstanceID This parameter must be a value between Min_Data=0 and Max_Data=0xF.
2245   * @retval None
2246   */
LL_I3C_SetMIPIInstanceID(I3C_TypeDef * I3Cx,uint32_t MIPIInstanceID)2247 __STATIC_INLINE void LL_I3C_SetMIPIInstanceID(I3C_TypeDef *I3Cx, uint32_t MIPIInstanceID)
2248 {
2249   MODIFY_REG(I3Cx->EPIDR, I3C_EPIDR_MIPIID, (MIPIInstanceID << I3C_EPIDR_MIPIID_Pos));
2250 }
2251 
2252 /**
2253   * @brief  Get the MIPI Instance ID.
2254   * @rmtoll EPIDR        MIPIID       LL_I3C_GetMIPIInstanceID
2255   * @param  I3Cx I3C Instance.
2256   * @retval Value between Min_Data=0 and Max_Data=0xF.
2257   */
LL_I3C_GetMIPIInstanceID(const I3C_TypeDef * I3Cx)2258 __STATIC_INLINE uint32_t LL_I3C_GetMIPIInstanceID(const I3C_TypeDef *I3Cx)
2259 {
2260   return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIID) >> I3C_EPIDR_MIPIID_Pos);
2261 }
2262 
2263 /**
2264   * @brief  Get the ID type selector.
2265   * @rmtoll EPIDR        IDTSEL        LL_I3C_GetIDTypeSelector
2266   * @param  I3Cx I3C Instance.
2267   * @retval Value between Min_Data=0x0 and Max_Data=0x1
2268   */
LL_I3C_GetIDTypeSelector(const I3C_TypeDef * I3Cx)2269 __STATIC_INLINE uint32_t LL_I3C_GetIDTypeSelector(const I3C_TypeDef *I3Cx)
2270 {
2271   return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_IDTSEL) >> I3C_EPIDR_IDTSEL_Pos);
2272 }
2273 
2274 /**
2275   * @brief  Get the MIPI Manufacturer ID.
2276   * @rmtoll EPIDR        MIPIMID       LL_I3C_GetMIPIManufacturerID
2277   * @param  I3Cx I3C Instance.
2278   * @retval Value between Min_Data=0 and Max_Data=0x7FFF.
2279   */
LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef * I3Cx)2280 __STATIC_INLINE uint32_t LL_I3C_GetMIPIManufacturerID(const I3C_TypeDef *I3Cx)
2281 {
2282   return (uint32_t)(READ_BIT(I3Cx->EPIDR, I3C_EPIDR_MIPIMID) >> I3C_EPIDR_MIPIMID_Pos);
2283 }
2284 
2285 /**
2286   * @}
2287   */
2288 
2289 /** @defgroup I3C_LL_EF_Data Management
2290   * @{
2291   */
2292 
2293 /**
2294   * @brief  Request a reception Data FIFO Flush.
2295   * @rmtoll CFGR      RXFLUSH       LL_I3C_RequestRxFIFOFlush
2296   * @param  I3Cx I3C Instance.
2297   * @retval None
2298   */
LL_I3C_RequestRxFIFOFlush(I3C_TypeDef * I3Cx)2299 __STATIC_INLINE void LL_I3C_RequestRxFIFOFlush(I3C_TypeDef *I3Cx)
2300 {
2301   SET_BIT(I3Cx->CFGR, I3C_CFGR_RXFLUSH);
2302 }
2303 
2304 /**
2305   * @brief  Request a transmission Data FIFO Flush.
2306   * @rmtoll CFGR      TXFLUSH       LL_I3C_RequestTxFIFOFlush
2307   * @param  I3Cx I3C Instance.
2308   * @retval None
2309   */
LL_I3C_RequestTxFIFOFlush(I3C_TypeDef * I3Cx)2310 __STATIC_INLINE void LL_I3C_RequestTxFIFOFlush(I3C_TypeDef *I3Cx)
2311 {
2312   SET_BIT(I3Cx->CFGR, I3C_CFGR_TXFLUSH);
2313 }
2314 
2315 /**
2316   * @brief  Request a Status Data FIFO Flush.
2317   * @rmtoll CFGR      SFLUSH        LL_I3C_RequestStatusFIFOFlush
2318   * @param  I3Cx I3C Instance.
2319   * @retval None
2320   */
LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef * I3Cx)2321 __STATIC_INLINE void LL_I3C_RequestStatusFIFOFlush(I3C_TypeDef *I3Cx)
2322 {
2323   SET_BIT(I3Cx->CFGR, I3C_CFGR_SFLUSH);
2324 }
2325 
2326 /**
2327   * @brief  Get Activity state of Controller on the I3C Bus (Target only).
2328   * @rmtoll DEVR0        AS            LL_I3C_GetActivityState
2329   * @param  I3Cx I3C Instance.
2330   * @retval Returned value can be one of the following values:
2331   *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_0
2332   *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_1
2333   *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_2
2334   *         @arg @ref LL_I3C_BUS_ACTIVITY_STATE_3
2335   */
LL_I3C_GetActivityState(const I3C_TypeDef * I3Cx)2336 __STATIC_INLINE uint32_t LL_I3C_GetActivityState(const I3C_TypeDef *I3Cx)
2337 {
2338   return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_AS));
2339 }
2340 
2341 /**
2342   * @brief  Get Reset Action (Target only).
2343   * @rmtoll DEVR0        RSTACT        LL_I3C_GetResetAction
2344   * @param  I3Cx I3C Instance.
2345   * @retval Returned value can be one of the following values:
2346   *         @arg @ref LL_I3C_RESET_ACTION_NONE
2347   *         @arg @ref LL_I3C_RESET_ACTION_PARTIAL
2348   *         @arg @ref LL_I3C_RESET_ACTION_FULL
2349   */
LL_I3C_GetResetAction(const I3C_TypeDef * I3Cx)2350 __STATIC_INLINE uint32_t LL_I3C_GetResetAction(const I3C_TypeDef *I3Cx)
2351 {
2352   return (uint32_t)(READ_BIT(I3Cx->DEVR0, I3C_DEVR0_RSTACT));
2353 }
2354 
2355 /**
2356   * @brief  Request a Control word FIFO Flush.
2357   * @rmtoll CFGR      CFLUSH        LL_I3C_RequestControlFIFOFlush
2358   * @param  I3Cx I3C Instance.
2359   * @retval None
2360   */
LL_I3C_RequestControlFIFOFlush(I3C_TypeDef * I3Cx)2361 __STATIC_INLINE void LL_I3C_RequestControlFIFOFlush(I3C_TypeDef *I3Cx)
2362 {
2363   SET_BIT(I3Cx->CFGR, I3C_CFGR_CFLUSH);
2364 }
2365 
2366 /**
2367   * @brief  Request a Transfer start.
2368   * @note   After request, the current instruction in Control Register is executed on I3C Bus.
2369   * @rmtoll CFGR      TSFSET        LL_I3C_RequestTransfer
2370   * @param  I3Cx I3C Instance.
2371   * @retval None
2372   */
LL_I3C_RequestTransfer(I3C_TypeDef * I3Cx)2373 __STATIC_INLINE void LL_I3C_RequestTransfer(I3C_TypeDef *I3Cx)
2374 {
2375   SET_BIT(I3Cx->CFGR, I3C_CFGR_TSFSET);
2376 }
2377 
2378 /**
2379   * @brief  Handles I3C Message content on the I3C Bus as Controller.
2380   * @rmtoll CR           ADD           LL_I3C_ControllerHandleMessage\n
2381   *         CR           DCNT          LL_I3C_ControllerHandleMessage\n
2382   *         CR           RNW           LL_I3C_ControllerHandleMessage\n
2383   *         CR           MTYPE         LL_I3C_ControllerHandleMessage\n
2384   *         CR           MEND          LL_I3C_ControllerHandleMessage
2385   * @param  I3Cx I3C Instance.
2386   * @param  TargetAddr Specifies the target address to be programmed.
2387   *               This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
2388   * @param  TransferSize Specifies the number of bytes to be programmed.
2389   *               This parameter must be a value between Min_Data=0 and Max_Data=65535.
2390   * @param  Direction This parameter can be one of the following values:
2391   *         @arg @ref LL_I3C_DIRECTION_WRITE
2392   *         @arg @ref LL_I3C_DIRECTION_READ
2393   * @param  MessageType This parameter can be one of the following values:
2394   *         @arg @ref LL_I3C_CONTROLLER_MTYPE_RELEASE
2395   *         @arg @ref LL_I3C_CONTROLLER_MTYPE_HEADER
2396   *         @arg @ref LL_I3C_CONTROLLER_MTYPE_PRIVATE
2397   *         @arg @ref LL_I3C_CONTROLLER_MTYPE_DIRECT
2398   *         @arg @ref LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C
2399   * @param  EndMode This parameter can be one of the following values:
2400   *         @arg @ref LL_I3C_GENERATE_STOP
2401   *         @arg @ref LL_I3C_GENERATE_RESTART
2402   * @retval None
2403   */
LL_I3C_ControllerHandleMessage(I3C_TypeDef * I3Cx,uint32_t TargetAddr,uint32_t TransferSize,uint32_t Direction,uint32_t MessageType,uint32_t EndMode)2404 __STATIC_INLINE void LL_I3C_ControllerHandleMessage(I3C_TypeDef *I3Cx, uint32_t TargetAddr, uint32_t TransferSize,
2405                                                     uint32_t Direction, uint32_t MessageType, uint32_t EndMode)
2406 {
2407   WRITE_REG(I3Cx->CR, ((TargetAddr << I3C_CR_ADD_Pos) | TransferSize | Direction | MessageType | EndMode) \
2408             & (I3C_CR_ADD | I3C_CR_DCNT | I3C_CR_RNW | I3C_CR_MTYPE | I3C_CR_MEND));
2409 }
2410 
2411 /**
2412   * @brief  Handles I3C Common Command Code content on the I3C Bus as Controller.
2413   * @rmtoll CR           CCC           LL_I3C_ControllerHandleCCC\n
2414   *         CR           DCNT          LL_I3C_ControllerHandleCCC\n
2415   *         CR           MTYPE         LL_I3C_ControllerHandleCCC\n
2416   *         CR           MEND          LL_I3C_ControllerHandleCCC
2417   * @param  I3Cx I3C Instance.
2418   * @param  CCCValue Specifies the Command Code to be programmed.
2419   *               This parameter must be a value between Min_Data=0 and Max_Data=0x1FF.
2420   * @param  AddByteSize Specifies the number of CCC additional bytes to be programmed.
2421   *               This parameter must be a value between Min_Data=0 and Max_Data=65535.
2422   * @param  EndMode This parameter can be one of the following values:
2423   *         @arg @ref LL_I3C_GENERATE_STOP
2424   *         @arg @ref LL_I3C_GENERATE_RESTART
2425   * @retval None
2426   */
LL_I3C_ControllerHandleCCC(I3C_TypeDef * I3Cx,uint32_t CCCValue,uint32_t AddByteSize,uint32_t EndMode)2427 __STATIC_INLINE void LL_I3C_ControllerHandleCCC(I3C_TypeDef *I3Cx, uint32_t CCCValue,
2428                                                 uint32_t AddByteSize, uint32_t EndMode)
2429 {
2430   WRITE_REG(I3Cx->CR, ((CCCValue << I3C_CR_CCC_Pos) | AddByteSize | EndMode | LL_I3C_CONTROLLER_MTYPE_CCC) \
2431             & (I3C_CR_CCC | I3C_CR_DCNT | I3C_CR_MTYPE | I3C_CR_MEND));
2432 }
2433 
2434 /**
2435   * @brief  Handles I3C Message content on the I3C Bus as Target.
2436   * @rmtoll CR           MTYPE         LL_I3C_TargetHandleMessage\n
2437   *         CR           DCNT       LL_I3C_TargetHandleMessage
2438   * @param  I3Cx I3C Instance.
2439   * @param  MessageType This parameter can be one of the following values:
2440   *         @arg @ref LL_I3C_TARGET_MTYPE_HOT_JOIN
2441   *         @arg @ref LL_I3C_TARGET_MTYPE_CONTROLLER_ROLE_REQ
2442   *         @arg @ref LL_I3C_TARGET_MTYPE_IBI
2443   * @param  IBISize Specifies the number of IBI bytes.
2444   *               This parameter must be a value between Min_Data=0 and Max_Data=65535.
2445   * @retval None
2446   */
LL_I3C_TargetHandleMessage(I3C_TypeDef * I3Cx,uint32_t MessageType,uint32_t IBISize)2447 __STATIC_INLINE void LL_I3C_TargetHandleMessage(I3C_TypeDef *I3Cx, uint32_t MessageType, uint32_t IBISize)
2448 {
2449   WRITE_REG(I3Cx->CR, (MessageType | IBISize) & (I3C_CR_DCNT | I3C_CR_MTYPE));
2450 }
2451 
2452 /**
2453   * @}
2454   */
2455 
2456 /** @defgroup I3C_LL_EF_Data_Management Data_Management
2457   * @{
2458   */
2459 
2460 /**
2461   * @brief  Read Receive Data Byte register.
2462   * @rmtoll RDR          RDB0         LL_I3C_ReceiveData8
2463   * @param  I3Cx I3C Instance.
2464   * @retval Value between Min_Data=0 to Max_Data=0xFF
2465   */
LL_I3C_ReceiveData8(const I3C_TypeDef * I3Cx)2466 __STATIC_INLINE uint8_t LL_I3C_ReceiveData8(const I3C_TypeDef *I3Cx)
2467 {
2468   return (uint8_t)(READ_BIT(I3Cx->RDR, I3C_RDR_RDB0));
2469 }
2470 
2471 /**
2472   * @brief  Write in Transmit Data Byte Register.
2473   * @rmtoll TDR          TDB0         LL_I3C_TransmitData8
2474   * @param  I3Cx I3C Instance.
2475   * @param  Data This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
2476   * @retval None
2477   */
LL_I3C_TransmitData8(I3C_TypeDef * I3Cx,uint8_t Data)2478 __STATIC_INLINE void LL_I3C_TransmitData8(I3C_TypeDef *I3Cx, uint8_t Data)
2479 {
2480   WRITE_REG(I3Cx->TDR, Data);
2481 }
2482 
2483 /**
2484   * @brief  Read Receive Data Word register.
2485   * @note   Content of register is filled in Little Endian.
2486   *         Mean MSB correspond to last data byte received,
2487   *         LSB correspond to first data byte received.
2488   * @rmtoll RDWR         RDWR          LL_I3C_ReceiveData32
2489   * @param  I3Cx I3C Instance.
2490   * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF
2491   */
LL_I3C_ReceiveData32(const I3C_TypeDef * I3Cx)2492 __STATIC_INLINE uint32_t LL_I3C_ReceiveData32(const I3C_TypeDef *I3Cx)
2493 {
2494   return (uint32_t)(READ_REG(I3Cx->RDWR));
2495 }
2496 
2497 /**
2498   * @brief  Write in Transmit Data Word Register.
2499   * @note   Content of register is filled in Little Endian.
2500   *         Mean MSB correspond to last data byte transmitted,
2501   *         LSB correspond to first data byte transmitted.
2502   * @rmtoll TDWR         TDWR          LL_I3C_TransmitData32
2503   * @param  I3Cx I3C Instance.
2504   * @param  Data This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
2505   * @retval None
2506   */
LL_I3C_TransmitData32(I3C_TypeDef * I3Cx,uint32_t Data)2507 __STATIC_INLINE void LL_I3C_TransmitData32(I3C_TypeDef *I3Cx, uint32_t Data)
2508 {
2509   WRITE_REG(I3Cx->TDWR, Data);
2510 }
2511 
2512 /**
2513   * @brief  Configure the IBI data payload to be sent during IBI (target mode).
2514   * @note   Content of register is filled in Little Endian.
2515   *         Mean MSB correspond to last IBI data byte,
2516   *         LSB correspond to first IBI data byte.
2517   * @rmtoll IBIDR        IBIDR         LL_I3C_SetIBIPayload
2518   * @param  I3Cx I3C Instance.
2519   * @param  OwnIBIPayload This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF
2520   * @retval None
2521   */
LL_I3C_SetIBIPayload(I3C_TypeDef * I3Cx,uint32_t OwnIBIPayload)2522 __STATIC_INLINE void LL_I3C_SetIBIPayload(I3C_TypeDef *I3Cx, uint32_t OwnIBIPayload)
2523 {
2524   WRITE_REG(I3Cx->IBIDR, OwnIBIPayload);
2525 }
2526 
2527 /**
2528   * @brief  Get the own IBI data payload (target mode), or get the Target IBI received (controller mode).
2529   * @note   Content of register is filled in Little Endian.
2530   *         Mean MSB correspond to last IBI data byte,
2531   *         LSB correspond to first IBI data byte.
2532   * @rmtoll IBIDR        IBIDR         LL_I3C_GetIBIPayload
2533   * @param  I3Cx I3C Instance.
2534   * @retval Value between Min_Data=0 to Max_Data=0xFFFFFFFF
2535   */
LL_I3C_GetIBIPayload(const I3C_TypeDef * I3Cx)2536 __STATIC_INLINE uint32_t LL_I3C_GetIBIPayload(const I3C_TypeDef *I3Cx)
2537 {
2538   return (uint32_t)(READ_REG(I3Cx->IBIDR));
2539 }
2540 
2541 /**
2542   * @brief  Get the number of data bytes received when reading IBI data (controller mode).
2543   * @rmtoll RMR         IBIRDCNT     LL_I3C_GetNbIBIAddData
2544   * @param  I3Cx I3C Instance.
2545   * @retval Value between Min_Data=0 to Max_Data=0x7
2546   */
LL_I3C_GetNbIBIAddData(const I3C_TypeDef * I3Cx)2547 __STATIC_INLINE uint32_t LL_I3C_GetNbIBIAddData(const I3C_TypeDef *I3Cx)
2548 {
2549   return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_IBIRDCNT));
2550 }
2551 
2552 /**
2553   * @brief  Get the target address received during accepted IBI or Controller-role request.
2554   * @rmtoll RMR         RADD         LL_I3C_GetIBITargetAddr
2555   * @param  I3Cx I3C Instance.
2556   * @retval Value between Min_Data=0 to Max_Data=0x3F
2557   */
LL_I3C_GetIBITargetAddr(const I3C_TypeDef * I3Cx)2558 __STATIC_INLINE uint32_t LL_I3C_GetIBITargetAddr(const I3C_TypeDef *I3Cx)
2559 {
2560   return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RADD) >> I3C_RMR_RADD_Pos);
2561 }
2562 
2563 /**
2564   * @brief  Set TX FIFO Preload (target mode).
2565   * @note   Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO.
2566   * @rmtoll TGTTDR       PRELOAD       LL_I3C_ConfigTxPreload
2567   * @rmtoll TGTTDR       TDCNT        LL_I3C_ConfigTxPreload
2568   * @param  I3Cx I3C Instance.
2569   * @param  TxDataCount This parameter must be a value between Min_Data=0 and Max_Data=0xFFFF
2570   * @retval None
2571   */
LL_I3C_ConfigTxPreload(I3C_TypeDef * I3Cx,uint16_t TxDataCount)2572 __STATIC_INLINE void LL_I3C_ConfigTxPreload(I3C_TypeDef *I3Cx, uint16_t TxDataCount)
2573 {
2574   MODIFY_REG(I3Cx->TGTTDR, (I3C_TGTTDR_PRELOAD | I3C_TGTTDR_TGTTDCNT), (I3C_TGTTDR_PRELOAD | TxDataCount));
2575 }
2576 
2577 /**
2578   * @brief  Indicates the status of TX FIFO preload (target mode).
2579   *         RESET: No preload of TX FIFO.
2580   *         SET: Preload of TX FIFO ongoing.
2581   * @note   Set high by Software, cleared by hardware when all the bytes to transmit have been loaded to TX FIFO.
2582   * @rmtoll TGTTDR       PRELOAD       LL_I3C_IsActiveTxPreload
2583   * @param  I3Cx I3C Instance.
2584   * @retval State of bit (1 or 0).
2585   */
LL_I3C_IsActiveTxPreload(const I3C_TypeDef * I3Cx)2586 __STATIC_INLINE uint32_t LL_I3C_IsActiveTxPreload(const I3C_TypeDef *I3Cx)
2587 {
2588   return ((READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_PRELOAD) == (I3C_TGTTDR_PRELOAD)) ? 1UL : 0UL);
2589 }
2590 
2591 /**
2592   * @brief  Get the number of bytes to transmit (target mode).
2593   * @note   The return value correspond to the remaining number of bytes to load in TX FIFO.
2594   * @rmtoll TGTTDR       TDCNT        LL_I3C_GetTxPreloadDataCount
2595   * @param  I3Cx I3C Instance.
2596   * @retval Value between Min_Data=0 to Max_Data=0xFFFF
2597   */
LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef * I3Cx)2598 __STATIC_INLINE uint16_t LL_I3C_GetTxPreloadDataCount(const I3C_TypeDef *I3Cx)
2599 {
2600   return (uint16_t)(READ_BIT(I3Cx->TGTTDR, I3C_TGTTDR_TGTTDCNT));
2601 }
2602 
2603 /**
2604   * @brief  Get the number of data during a Transfer.
2605   * @note   The return value correspond to number of transmitted bytes reported
2606   *         during Address Assignment process in Target mode.
2607   * The return value  correspond to number of target detected
2608   * during Address Assignment process in Controller mode.
2609   * The return value  correspond to number of data bytes read from or sent to the I3C bus
2610   * during the message link to MID current value.
2611   * @rmtoll SR           XDCNT      LL_I3C_GetXferDataCount
2612   * @param  I3Cx I3C Instance.
2613   * @retval Value between Min_Data=0 to Max_Data=0xFFFF
2614   */
LL_I3C_GetXferDataCount(const I3C_TypeDef * I3Cx)2615 __STATIC_INLINE uint32_t LL_I3C_GetXferDataCount(const I3C_TypeDef *I3Cx)
2616 {
2617   return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_XDCNT));
2618 }
2619 
2620 /**
2621   * @brief  Indicates if a Target abort a private read command.
2622   * @rmtoll SR           ABT           LL_I3C_IsTargetAbortPrivateRead
2623   * @param  I3Cx I3C Instance.
2624   * @retval State of bit (1 or 0).
2625   */
LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef * I3Cx)2626 __STATIC_INLINE uint32_t LL_I3C_IsTargetAbortPrivateRead(const I3C_TypeDef *I3Cx)
2627 {
2628   return ((READ_BIT(I3Cx->SR, I3C_SR_ABT) == (I3C_SR_ABT)) ? 1UL : 0UL);
2629 }
2630 
2631 /**
2632   * @brief  Get Direction of the Message.
2633   * @rmtoll SR           DIR           LL_I3C_GetMessageDirection
2634   * @param  I3Cx I3C Instance.
2635   * @retval Returned value can be one of the following values:
2636   *         @arg @ref LL_I3C_MESSAGE_DIRECTION_WRITE
2637   *         @arg @ref LL_I3C_MESSAGE_DIRECTION_READ
2638   */
LL_I3C_GetMessageDirection(const I3C_TypeDef * I3Cx)2639 __STATIC_INLINE uint32_t LL_I3C_GetMessageDirection(const I3C_TypeDef *I3Cx)
2640 {
2641   return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_DIR));
2642 }
2643 
2644 /**
2645   * @brief  Get Message identifier.
2646   * @rmtoll SR           MID           LL_I3C_GetMessageIdentifier
2647   * @param  I3Cx I3C Instance.
2648   * @retval Value between Min_Data=0 to Max_Data=0xFF, representing the internal hardware counter value.
2649   */
LL_I3C_GetMessageIdentifier(const I3C_TypeDef * I3Cx)2650 __STATIC_INLINE uint32_t LL_I3C_GetMessageIdentifier(const I3C_TypeDef *I3Cx)
2651 {
2652   return (uint32_t)(READ_BIT(I3Cx->SR, I3C_SR_MID));
2653 }
2654 
2655 /**
2656   * @brief  Get Message error code.
2657   * @rmtoll SER          CODERR        LL_I3C_GetMessageErrorCode
2658   * @param  I3Cx I3C Instance.
2659   * @retval Returned value can be one of the following values:
2660   *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE0
2661   *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE1
2662   *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE2
2663   *         @arg @ref LL_I3C_CONTROLLER_ERROR_CE3
2664   *         @arg @ref LL_I3C_TARGET_ERROR_TE0
2665   *         @arg @ref LL_I3C_TARGET_ERROR_TE1
2666   *         @arg @ref LL_I3C_TARGET_ERROR_TE2
2667   *         @arg @ref LL_I3C_TARGET_ERROR_TE3
2668   *         @arg @ref LL_I3C_TARGET_ERROR_TE4
2669   *         @arg @ref LL_I3C_TARGET_ERROR_TE5
2670   *         @arg @ref LL_I3C_TARGET_ERROR_TE6
2671   */
LL_I3C_GetMessageErrorCode(const I3C_TypeDef * I3Cx)2672 __STATIC_INLINE uint32_t LL_I3C_GetMessageErrorCode(const I3C_TypeDef *I3Cx)
2673 {
2674   return (uint32_t)(READ_BIT(I3Cx->SER, I3C_SER_CODERR));
2675 }
2676 
2677 /**
2678   * @brief  Get CCC code of received command.
2679   * @rmtoll RMR         RCODE        LL_I3C_GetReceiveCommandCode
2680   * @param  I3Cx I3C Instance.
2681   * @retval Value between Min_Data=0 to Max_Data=0xFF.
2682   */
LL_I3C_GetReceiveCommandCode(const I3C_TypeDef * I3Cx)2683 __STATIC_INLINE uint32_t LL_I3C_GetReceiveCommandCode(const I3C_TypeDef *I3Cx)
2684 {
2685   return (uint32_t)(READ_BIT(I3Cx->RMR, I3C_RMR_RCODE) >> I3C_RMR_RCODE_Pos);
2686 }
2687 
2688 /**
2689   * @}
2690   */
2691 
2692 /** @defgroup I3C_LL_EF_Target Payload
2693   * @{
2694   */
2695 
2696 /**
2697   * @brief  Set Dynamic Address assigned to target x.
2698   * @rmtoll DEVRX        DA            LL_I3C_SetTargetDynamicAddress
2699   * @param  I3Cx I3C Instance.
2700   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2701   * @param  DynamicAddr Value between Min_Data=0 to Max_Data=0x7F
2702   * @retval None
2703   */
LL_I3C_SetTargetDynamicAddress(I3C_TypeDef * I3Cx,uint32_t TargetId,uint32_t DynamicAddr)2704 __STATIC_INLINE void LL_I3C_SetTargetDynamicAddress(I3C_TypeDef *I3Cx, uint32_t TargetId, uint32_t DynamicAddr)
2705 {
2706   MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA, (DynamicAddr << I3C_DEVRX_DA_Pos));
2707 }
2708 
2709 /**
2710   * @brief  Get Dynamic Address assigned to target x.
2711   * @rmtoll DEVRX        DA            LL_I3C_GetTargetDynamicAddress
2712   * @param  I3Cx I3C Instance.
2713   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2714   * @retval Value between Min_Data=0 to Max_Data=0x7F
2715   */
LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef * I3Cx,uint32_t TargetId)2716 __STATIC_INLINE uint32_t LL_I3C_GetTargetDynamicAddress(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2717 {
2718   return (uint32_t)((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DA)) >> I3C_DEVRX_DA_Pos);
2719 }
2720 
2721 /**
2722   * @brief  Enable IBI Acknowledgement from target x(controller mode).
2723   * @note   The bit DIS is automatically set when CRACK or IBIACK are set.
2724   *         This mean DEVRX register access is not allowed.
2725   *         Reset CRACK and IBIACK will reset DIS bit.
2726   * @rmtoll DEVRX        IBIACK        LL_I3C_EnableTargetIBIAck
2727   * @param  I3Cx I3C Instance.
2728   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2729   * @retval None
2730   */
LL_I3C_EnableTargetIBIAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2731 __STATIC_INLINE void LL_I3C_EnableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2732 {
2733   SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK);
2734 }
2735 
2736 /**
2737   * @brief  Disable IBI Acknowledgement from target x (controller mode).
2738   * @rmtoll DEVRX        IBIACK        LL_I3C_DisableTargetIBIAck
2739   * @param  I3Cx I3C Instance.
2740   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2741   * @retval None
2742   */
LL_I3C_DisableTargetIBIAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2743 __STATIC_INLINE void LL_I3C_DisableTargetIBIAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2744 {
2745   CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK);
2746 }
2747 
2748 /**
2749   * @brief  Indicates if IBI from target x will be Acknowledged or Not Acknowledged (controller mode).
2750   *         RESET: IBI Not Acknowledged.
2751   *         SET: IBI Acknowledged.
2752   * @rmtoll DEVRX        IBIACK        LL_I3C_IsEnabledTargetIBIAck
2753   * @param  I3Cx I3C Instance.
2754   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2755   * @retval State of bit (1 or 0).
2756   */
LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef * I3Cx,uint32_t TargetId)2757 __STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetIBIAck(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2758 {
2759   return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIACK) == I3C_DEVRX_IBIACK) ? 1UL : 0UL);
2760 }
2761 
2762 /**
2763   * @brief  Enable Controller-role Request Acknowledgement from target x(controller mode).
2764   * @note   The bit DIS is automatically set when CRACK or IBIACK are set.
2765   *         This mean DEVRX register access is not allowed.
2766   *         Reset CRACK and IBIACK will reset DIS bit.
2767   * @rmtoll DEVRX        CRACK         LL_I3C_EnableTargetCRAck
2768   * @param  I3Cx I3C Instance.
2769   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2770   * @retval None
2771   */
LL_I3C_EnableTargetCRAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2772 __STATIC_INLINE void LL_I3C_EnableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2773 {
2774   SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK);
2775 }
2776 
2777 /**
2778   * @brief  Disable Controller-role Request Acknowledgement from target x (controller mode).
2779   * @rmtoll DEVRX        CRACK         LL_I3C_DisableTargetCRAck
2780   * @param  I3Cx I3C Instance.
2781   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2782   * @retval None
2783   */
LL_I3C_DisableTargetCRAck(I3C_TypeDef * I3Cx,uint32_t TargetId)2784 __STATIC_INLINE void LL_I3C_DisableTargetCRAck(I3C_TypeDef *I3Cx, uint32_t TargetId)
2785 {
2786   CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK);
2787 }
2788 
2789 /**
2790   * @brief  Indicates if Controller-role Request from target x will be
2791   *         Acknowledged or Not Acknowledged (controller mode).
2792   *         RESET: Controller-role Request Not Acknowledged.
2793   *         SET: Controller-role Request Acknowledged.
2794   * @rmtoll DEVRX        CRACK         LL_I3C_IsEnabledTargetCRAck
2795   * @param  I3Cx I3C Instance.
2796   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2797   * @retval State of bit (1 or 0).
2798   */
LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef * I3Cx,uint32_t TargetId)2799 __STATIC_INLINE uint32_t LL_I3C_IsEnabledTargetCRAck(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2800 {
2801   return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_CRACK) == I3C_DEVRX_CRACK) ? 1UL : 0UL);
2802 }
2803 
2804 /**
2805   * @brief  Enable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
2806   * @rmtoll DEVRX        IBIDEN          LL_I3C_EnableIBIAddData
2807   * @param  I3Cx I3C Instance.
2808   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2809   * @retval None
2810   */
LL_I3C_EnableIBIAddData(I3C_TypeDef * I3Cx,uint32_t TargetId)2811 __STATIC_INLINE void LL_I3C_EnableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId)
2812 {
2813   SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN);
2814 }
2815 
2816 /**
2817   * @brief  Disable additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
2818   * @rmtoll DEVRX        IBIDEN          LL_I3C_DisableIBIAddData
2819   * @param  I3Cx I3C Instance.
2820   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2821   * @retval None
2822   */
LL_I3C_DisableIBIAddData(I3C_TypeDef * I3Cx,uint32_t TargetId)2823 __STATIC_INLINE void LL_I3C_DisableIBIAddData(I3C_TypeDef *I3Cx, uint32_t TargetId)
2824 {
2825   CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN);
2826 }
2827 
2828 /**
2829   * @brief  Indicates if additional Mandatory Data Byte (MDB) follows the accepted IBI from target x.
2830   *         RESET: No Mandatory Data Byte follows IBI.
2831   *         SET: Mandatory Data Byte follows IBI.
2832   * @rmtoll DEVRX        IBIDEN          LL_I3C_IsEnabledIBIAddData
2833   * @param  I3Cx I3C Instance.
2834   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2835   * @retval State of bit (1 or 0).
2836   */
LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef * I3Cx,uint32_t TargetId)2837 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIBIAddData(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2838 {
2839   return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_IBIDEN) == I3C_DEVRX_IBIDEN) ? 1UL : 0UL);
2840 }
2841 
2842 /**
2843   * @brief  Enable Suspension of Current transfer during IBI treatment.
2844   * @note   When set, this feature will allow controller to send
2845   *         a Stop condition and CR FIFO is flushed after IBI treatment.
2846   *         Software has to rewrite instructions in Control Register to start a new transfer.
2847   * @rmtoll DEVRX        SUSP          LL_I3C_EnableFrameSuspend
2848   * @param  I3Cx I3C Instance.
2849   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2850   * @retval None
2851   */
LL_I3C_EnableFrameSuspend(I3C_TypeDef * I3Cx,uint32_t TargetId)2852 __STATIC_INLINE void LL_I3C_EnableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId)
2853 {
2854   SET_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP);
2855 }
2856 
2857 /**
2858   * @brief  Disable Suspension of Current transfer during IBI treatment.
2859   * @note   When set, this feature will allow controller to continue CR FIFO treatment after IBI treatment.
2860   * @rmtoll DEVRX        SUSP          LL_I3C_DisableFrameSuspend
2861   * @param  I3Cx I3C Instance.
2862   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2863   * @retval None
2864   */
LL_I3C_DisableFrameSuspend(I3C_TypeDef * I3Cx,uint32_t TargetId)2865 __STATIC_INLINE void LL_I3C_DisableFrameSuspend(I3C_TypeDef *I3Cx, uint32_t TargetId)
2866 {
2867   CLEAR_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP);
2868 }
2869 
2870 /**
2871   * @brief  Indicates if I3C transfer must be Suspended or not Suspended during IBI treatment from target x.
2872   *         RESET: Transfer is not suspended. Instruction in CR FIFO are executed after IBI.
2873   *         SET: Transfer is suspended (a Stop condition is sent). CR FIFO is flushed.
2874   * @rmtoll DEVRX        SUSP          LL_I3C_IsFrameMustBeSuspended
2875   * @param  I3Cx I3C Instance.
2876   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2877   * @retval State of bit (1 or 0).
2878   */
LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef * I3Cx,uint32_t TargetId)2879 __STATIC_INLINE uint32_t LL_I3C_IsFrameMustBeSuspended(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2880 {
2881   return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_SUSP) == I3C_DEVRX_SUSP) ? 1UL : 0UL);
2882 }
2883 
2884 /**
2885   * @brief  Indicates if update of the Device Characteristics Register is Allowed or Not Allowed.
2886   *         RESET: Device Characteristics Register update is Not Allowed.
2887   *         SET: Device Characteristics Register update is Allowed.
2888   * @note   Used to prevent software writing during reception of an IBI or Controller-role Request from target x.
2889   * @rmtoll DEVRX        DIS           LL_I3C_IsAllowedPayloadUpdate
2890   * @param  I3Cx I3C Instance.
2891   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2892   * @retval State of bit (1 or 0).
2893   */
LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef * I3Cx,uint32_t TargetId)2894 __STATIC_INLINE uint32_t LL_I3C_IsAllowedPayloadUpdate(const I3C_TypeDef *I3Cx, uint32_t TargetId)
2895 {
2896   return ((READ_BIT(I3Cx->DEVRX[TargetId - 1U], I3C_DEVRX_DIS) != I3C_DEVRX_DIS) ? 1UL : 0UL);
2897 }
2898 
2899 /**
2900   * @brief  Set I3C bus devices configuration.
2901   * @note   This function is called only when the I3C instance is initialized as controller.
2902   *         This function can be called by the controller application to help the automatic treatment when target have
2903   *         capability of IBI and/or Control-Role.
2904   * @rmtoll DEVRX        DA            LL_I3C_ConfigDeviceCapabilities
2905   * @rmtoll DEVRX        IBIACK        LL_I3C_ConfigDeviceCapabilities
2906   * @rmtoll DEVRX        IBIDEN        LL_I3C_ConfigDeviceCapabilities
2907   * @rmtoll DEVRX        CRACK         LL_I3C_ConfigDeviceCapabilities
2908   * @param  I3Cx I3C Instance.
2909   * @param  TargetId This parameter must be a value between Min_Data=1 and Max_Data=4
2910   * @param  DynamicAddr Value between Min_Data=0 to Max_Data=0x7F
2911   * @param  IBIAck Value This parameter can be one of the following values:
2912   *         @arg @ref LL_I3C_IBI_CAPABILITY
2913   *         @arg @ref LL_I3C_IBI_NO_CAPABILITY
2914   * @param  IBIAddData This parameter can be one of the following values:
2915   *         @arg @ref LL_I3C_IBI_DATA_ENABLE
2916   *         @arg @ref LL_I3C_IBI_DATA_DISABLE
2917   * @param  CRAck This parameter can be one of the following values:
2918   *         @arg @ref LL_I3C_CR_CAPABILITY
2919   *         @arg @ref LL_I3C_CR_NO_CAPABILITY
2920   * @retval None
2921   */
LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef * I3Cx,uint32_t TargetId,uint32_t DynamicAddr,uint32_t IBIAck,uint32_t IBIAddData,uint32_t CRAck)2922 __STATIC_INLINE void LL_I3C_ConfigDeviceCapabilities(I3C_TypeDef *I3Cx,
2923                                                      uint32_t TargetId,
2924                                                      uint32_t DynamicAddr,
2925                                                      uint32_t IBIAck,
2926                                                      uint32_t IBIAddData,
2927                                                      uint32_t CRAck)
2928 {
2929   MODIFY_REG(I3Cx->DEVRX[TargetId - 1U], \
2930              (I3C_DEVRX_DA | I3C_DEVRX_IBIACK | I3C_DEVRX_CRACK | I3C_DEVRX_IBIDEN), \
2931              ((DynamicAddr << I3C_DEVRX_DA_Pos) | IBIAck | IBIAddData | CRAck));
2932 }
2933 /**
2934   * @}
2935   */
2936 
2937 /** @defgroup I3C_LL_EF_FLAG_management FLAG_management
2938   * @{
2939   */
2940 
2941 /**
2942   * @brief  Indicates the status of Control FIFO Empty flag.
2943   *         RESET: One or more data are available in Control FIFO.
2944   *         SET: No more data available in Control FIFO.
2945   * @rmtoll EVR          CFEF          LL_I3C_IsActiveFlag_CFE
2946   * @param  I3Cx I3C Instance.
2947   * @retval State of bit (1 or 0).
2948   */
LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef * I3Cx)2949 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFE(const I3C_TypeDef *I3Cx)
2950 {
2951   return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFEF) == (I3C_EVR_CFEF)) ? 1UL : 0UL);
2952 }
2953 
2954 /**
2955   * @brief  Indicates the status of Transmit FIFO Empty flag.
2956   *         RESET: One or more data are available in Transmit FIFO.
2957   *         SET: No more data available in Transmit FIFO.
2958   * @rmtoll EVR          TXFEF         LL_I3C_IsActiveFlag_TXFE
2959   * @param  I3Cx I3C Instance.
2960   * @retval State of bit (1 or 0).
2961   */
LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef * I3Cx)2962 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFE(const I3C_TypeDef *I3Cx)
2963 {
2964   return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFEF) == (I3C_EVR_TXFEF)) ? 1UL : 0UL);
2965 }
2966 
2967 /**
2968   * @brief  Indicates the status of Control FIFO Not Full flag.
2969   *         RESET: One or more free space available in Control FIFO.
2970   *         SET: No more free space available in Control FIFO.
2971   * @note   When a transfer is ongoing, the Control FIFO shall not be written unless this flag is set.
2972   * @rmtoll EVR          CFNFF         LL_I3C_IsActiveFlag_CFNF
2973   * @param  I3Cx I3C Instance.
2974   * @retval State of bit (1 or 0).
2975   */
LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef * I3Cx)2976 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CFNF(const I3C_TypeDef *I3Cx)
2977 {
2978   return ((READ_BIT(I3Cx->EVR, I3C_EVR_CFNFF) == (I3C_EVR_CFNFF)) ? 1UL : 0UL);
2979 }
2980 
2981 /**
2982   * @brief  Indicates the status of Status FIFO Not Empty flag.
2983   *         RESET: One or more free space available in Status FIFO.
2984   *         SET: No more free space available in Status FIFO.
2985   * @note   This flag is updated only when the FIFO is used, mean SMODE = 1.
2986   * @rmtoll EVR          SFNEF         LL_I3C_IsActiveFlag_SFNE
2987   * @param  I3Cx I3C Instance.
2988   * @retval State of bit (1 or 0).
2989   */
LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef * I3Cx)2990 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_SFNE(const I3C_TypeDef *I3Cx)
2991 {
2992   return ((READ_BIT(I3Cx->EVR, I3C_EVR_SFNEF) == (I3C_EVR_SFNEF)) ? 1UL : 0UL);
2993 }
2994 
2995 /**
2996   * @brief  Indicates the status of Transmit FIFO Not Full flag.
2997   *         RESET: One or more free space available in Transmit FIFO.
2998   *         SET: No more free space available in Transmit FIFO.
2999   * @note   When a transfer is ongoing, the Transmit FIFO shall not be written unless this flag is set.
3000   * @rmtoll EVR          TXFNFF        LL_I3C_IsActiveFlag_TXFNF
3001   * @param  I3Cx I3C Instance.
3002   * @retval State of bit (1 or 0).
3003   */
LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef * I3Cx)3004 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXFNF(const I3C_TypeDef *I3Cx)
3005 {
3006   return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXFNFF) == (I3C_EVR_TXFNFF)) ? 1UL : 0UL);
3007 }
3008 
3009 /**
3010   * @brief  Indicates the status of Receive FIFO Not Full flag.
3011   *         RESET: One or more data are available in Receive FIFO.
3012   *         SET: No more data available in Receive FIFO.
3013   * @rmtoll EVR          RXFNEF        LL_I3C_IsActiveFlag_RXFNE
3014   * @param  I3Cx I3C Instance.
3015   * @retval State of bit (1 or 0).
3016   */
LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef * I3Cx)3017 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXFNE(const I3C_TypeDef *I3Cx)
3018 {
3019   return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXFNEF) == (I3C_EVR_RXFNEF)) ? 1UL : 0UL);
3020 }
3021 
3022 /**
3023   * @brief  Indicates that the last Receive byte is available.
3024   *         RESET: Clear default value.
3025   *         SET: Last Receive byte ready to read from Receive FIFO.
3026   * @rmtoll EVR          RXLASTF       LL_I3C_IsActiveFlag_RXLAST
3027   * @param  I3Cx I3C Instance.
3028   * @retval State of bit (1 or 0).
3029   */
LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef * I3Cx)3030 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXLAST(const I3C_TypeDef *I3Cx)
3031 {
3032   return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXLASTF) == (I3C_EVR_RXLASTF)) ? 1UL : 0UL);
3033 }
3034 
3035 /**
3036   * @brief  Indicates that the last Transmit byte is written in FIFO.
3037   *         RESET: Transmission is not finalized.
3038   *         SET: Last Transmit byte is written in transmit FIFO.
3039   * @rmtoll EVR          TXLASTF       LL_I3C_IsActiveFlag_TXLAST
3040   * @param  I3Cx I3C Instance.
3041   * @retval State of bit (1 or 0).
3042   */
LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef * I3Cx)3043 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_TXLAST(const I3C_TypeDef *I3Cx)
3044 {
3045   return ((READ_BIT(I3Cx->EVR, I3C_EVR_TXLASTF) == (I3C_EVR_TXLASTF)) ? 1UL : 0UL);
3046 }
3047 
3048 /**
3049   * @brief  Indicates the status of Frame Complete flag (controller and target mode).
3050   *         RESET: Current Frame transfer is not finalized.
3051   *         SET: Current Frame transfer is completed.
3052   * @rmtoll EVR          FCF           LL_I3C_IsActiveFlag_FC
3053   * @param  I3Cx I3C Instance.
3054   * @retval State of bit (1 or 0).
3055   */
LL_I3C_IsActiveFlag_FC(const I3C_TypeDef * I3Cx)3056 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_FC(const I3C_TypeDef *I3Cx)
3057 {
3058   return ((READ_BIT(I3Cx->EVR, I3C_EVR_FCF) == (I3C_EVR_FCF)) ? 1UL : 0UL);
3059 }
3060 
3061 /**
3062   * @brief  Indicates the status of Reception Target End flag (controller mode).
3063   *         RESET: Clear default value.
3064   *         SET: Target prematurely ended a Read Command.
3065   * @note   This flag is set only when status FIFO is not used, mean SMODE = 0.
3066   * @rmtoll EVR          RXTGTENDF     LL_I3C_IsActiveFlag_RXTGTEND
3067   * @param  I3Cx I3C Instance.
3068   * @retval State of bit (1 or 0).
3069   */
LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef * I3Cx)3070 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RXTGTEND(const I3C_TypeDef *I3Cx)
3071 {
3072   return ((READ_BIT(I3Cx->EVR, I3C_EVR_RXTGTENDF) == (I3C_EVR_RXTGTENDF)) ? 1UL : 0UL);
3073 }
3074 
3075 /**
3076   * @brief  Indicates the status of Error flag (controller and target mode).
3077   *         RESET: Clear default value.
3078   *         SET: One or more Errors are detected.
3079   * @rmtoll EVR          ERRF          LL_I3C_IsActiveFlag_ERR
3080   * @param  I3Cx I3C Instance.
3081   * @retval State of bit (1 or 0).
3082   */
LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef * I3Cx)3083 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ERR(const I3C_TypeDef *I3Cx)
3084 {
3085   return ((READ_BIT(I3Cx->EVR, I3C_EVR_ERRF) == (I3C_EVR_ERRF)) ? 1UL : 0UL);
3086 }
3087 
3088 /**
3089   * @brief  Indicates the status of IBI flag (controller mode).
3090   *         RESET: Clear default value.
3091   *         SET: An IBI have been received.
3092   * @rmtoll EVR          IBIF          LL_I3C_IsActiveFlag_IBI
3093   * @param  I3Cx I3C Instance.
3094   * @retval State of bit (1 or 0).
3095   */
LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef * I3Cx)3096 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBI(const I3C_TypeDef *I3Cx)
3097 {
3098   return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIF) == (I3C_EVR_IBIF)) ? 1UL : 0UL);
3099 }
3100 
3101 /**
3102   * @brief  Indicates the status of IBI End flag (target mode).
3103   *         RESET: Clear default value.
3104   *         SET: IBI procedure is finished.
3105   * @rmtoll EVR          IBIENDF       LL_I3C_IsActiveFlag_IBIEND
3106   * @param  I3Cx I3C Instance.
3107   * @retval State of bit (1 or 0).
3108   */
LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef * I3Cx)3109 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_IBIEND(const I3C_TypeDef *I3Cx)
3110 {
3111   return ((READ_BIT(I3Cx->EVR, I3C_EVR_IBIENDF) == (I3C_EVR_IBIENDF)) ? 1UL : 0UL);
3112 }
3113 
3114 /**
3115   * @brief  Indicates the status of Controller-role Request flag (controller mode).
3116   *         RESET: Clear default value.
3117   *         SET: A Controller-role request procedure have been received.
3118   * @rmtoll EVR          CRF           LL_I3C_IsActiveFlag_CR
3119   * @param  I3Cx I3C Instance.
3120   * @retval State of bit (1 or 0).
3121   */
LL_I3C_IsActiveFlag_CR(const I3C_TypeDef * I3Cx)3122 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CR(const I3C_TypeDef *I3Cx)
3123 {
3124   return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRF) == (I3C_EVR_CRF)) ? 1UL : 0UL);
3125 }
3126 
3127 /**
3128   * @brief  Indicates the status of Controller-role Request Update flag (target mode).
3129   *         RESET: Clear default value.
3130   *         SET: I3C device have gained Controller-role of the I3C Bus.
3131   * @rmtoll EVR          BCUPDF        LL_I3C_IsActiveFlag_CRUPD
3132   * @param  I3Cx I3C Instance.
3133   * @retval State of bit (1 or 0).
3134   */
LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef * I3Cx)3135 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_CRUPD(const I3C_TypeDef *I3Cx)
3136 {
3137   return ((READ_BIT(I3Cx->EVR, I3C_EVR_CRUPDF) == (I3C_EVR_CRUPDF)) ? 1UL : 0UL);
3138 }
3139 
3140 /**
3141   * @brief  Indicates the status of Hot Join flag (controller mode).
3142   *         RESET: Clear default value.
3143   *         SET: A Hot Join request have been received.
3144   * @rmtoll EVR          HJF           LL_I3C_IsActiveFlag_HJ
3145   * @param  I3Cx I3C Instance.
3146   * @retval State of bit (1 or 0).
3147   */
LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef * I3Cx)3148 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_HJ(const I3C_TypeDef *I3Cx)
3149 {
3150   return ((READ_BIT(I3Cx->EVR, I3C_EVR_HJF) == (I3C_EVR_HJF)) ? 1UL : 0UL);
3151 }
3152 
3153 /**
3154   * @brief  Indicates the status of Wake Up flag (target mode).
3155   *         RESET: Clear default value.
3156   *         SET: I3C Internal clock not available on time to treat the falling edge on SCL.
3157   * @rmtoll EVR          WKPF          LL_I3C_IsActiveFlag_WKP
3158   * @param  I3Cx I3C Instance.
3159   * @retval State of bit (1 or 0).
3160   */
LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef * I3Cx)3161 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_WKP(const I3C_TypeDef *I3Cx)
3162 {
3163   return ((READ_BIT(I3Cx->EVR, I3C_EVR_WKPF) == (I3C_EVR_WKPF)) ? 1UL : 0UL);
3164 }
3165 
3166 /**
3167   * @brief  Indicates the status of Get flag (target mode).
3168   *         RESET: Clear default value.
3169   *         SET: A "get" type CCC have been received.
3170   * @rmtoll EVR          GETF          LL_I3C_IsActiveFlag_GET
3171   * @param  I3Cx I3C Instance.
3172   * @retval State of bit (1 or 0).
3173   */
LL_I3C_IsActiveFlag_GET(const I3C_TypeDef * I3Cx)3174 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GET(const I3C_TypeDef *I3Cx)
3175 {
3176   return ((READ_BIT(I3Cx->EVR, I3C_EVR_GETF) == (I3C_EVR_GETF)) ? 1UL : 0UL);
3177 }
3178 
3179 /**
3180   * @brief  Indicates the status of Get Status flag (target mode).
3181   *         RESET: Clear default value.
3182   *         SET: A GETSTATUS Command have been received.
3183   * @rmtoll EVR          STAF          LL_I3C_IsActiveFlag_STA
3184   * @param  I3Cx I3C Instance.
3185   * @retval State of bit (1 or 0).
3186   */
LL_I3C_IsActiveFlag_STA(const I3C_TypeDef * I3Cx)3187 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STA(const I3C_TypeDef *I3Cx)
3188 {
3189   return ((READ_BIT(I3Cx->EVR, I3C_EVR_STAF) == (I3C_EVR_STAF)) ? 1UL : 0UL);
3190 }
3191 
3192 /**
3193   * @brief  Indicates the status of Dynamic Address Update flag (target mode).
3194   *         RESET: Clear default value.
3195   *         SET: Own Dynamic Address have been updated.
3196   * @rmtoll EVR          DAUPDF        LL_I3C_IsActiveFlag_DAUPD
3197   * @param  I3Cx I3C Instance.
3198   * @retval State of bit (1 or 0).
3199   */
LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef * I3Cx)3200 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DAUPD(const I3C_TypeDef *I3Cx)
3201 {
3202   return ((READ_BIT(I3Cx->EVR, I3C_EVR_DAUPDF) == (I3C_EVR_DAUPDF)) ? 1UL : 0UL);
3203 }
3204 
3205 /**
3206   * @brief  Indicates the status of Max Write Length flag (target mode).
3207   *         RESET: Clear default value.
3208   *         SET: Max Write Length have been updated.
3209   * @rmtoll EVR          MWLUPDF       LL_I3C_IsActiveFlag_MWLUPD
3210   * @param  I3Cx I3C Instance.
3211   * @retval State of bit (1 or 0).
3212   */
LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef * I3Cx)3213 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MWLUPD(const I3C_TypeDef *I3Cx)
3214 {
3215   return ((READ_BIT(I3Cx->EVR, I3C_EVR_MWLUPDF) == (I3C_EVR_MWLUPDF)) ? 1UL : 0UL);
3216 }
3217 
3218 /**
3219   * @brief  Indicates the status of Max Read Length flag (target mode).
3220   *         RESET: Clear default value.
3221   *         SET: Max Read Length have been updated.
3222   * @rmtoll EVR          MRLUPDF       LL_I3C_IsActiveFlag_MRLUPD
3223   * @param  I3Cx I3C Instance.
3224   * @retval State of bit (1 or 0).
3225   */
LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef * I3Cx)3226 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_MRLUPD(const I3C_TypeDef *I3Cx)
3227 {
3228   return ((READ_BIT(I3Cx->EVR, I3C_EVR_MRLUPDF) == (I3C_EVR_MRLUPDF)) ? 1UL : 0UL);
3229 }
3230 
3231 /**
3232   * @brief  Indicates the status of Reset flag (target mode).
3233   *         RESET: Clear default value.
3234   *         SET: A Reset Pattern have been received.
3235   * @rmtoll EVR          RSTF          LL_I3C_IsActiveFlag_RST
3236   * @param  I3Cx I3C Instance.
3237   * @retval State of bit (1 or 0).
3238   */
LL_I3C_IsActiveFlag_RST(const I3C_TypeDef * I3Cx)3239 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_RST(const I3C_TypeDef *I3Cx)
3240 {
3241   return ((READ_BIT(I3Cx->EVR, I3C_EVR_RSTF) == (I3C_EVR_RSTF)) ? 1UL : 0UL);
3242 }
3243 
3244 /**
3245   * @brief  Indicates the status of Active State flag (target mode).
3246   *         RESET: Clear default value.
3247   *         SET: The Activity State have been updated.
3248   * @rmtoll EVR          ASUPDF        LL_I3C_IsActiveFlag_ASUPD
3249   * @param  I3Cx I3C Instance.
3250   * @retval State of bit (1 or 0).
3251   */
LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef * I3Cx)3252 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ASUPD(const I3C_TypeDef *I3Cx)
3253 {
3254   return ((READ_BIT(I3Cx->EVR, I3C_EVR_ASUPDF) == (I3C_EVR_ASUPDF)) ? 1UL : 0UL);
3255 }
3256 
3257 /**
3258   * @brief  Indicates the status of Interrupt Update flag (target mode).
3259   *         RESET: Clear default value.
3260   *         SET: One or more Interrupt autorized have been updated.
3261   * @rmtoll EVR          INTUPDF       LL_I3C_IsActiveFlag_INTUPD
3262   * @param  I3Cx I3C Instance.
3263   * @retval State of bit (1 or 0).
3264   */
LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef * I3Cx)3265 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_INTUPD(const I3C_TypeDef *I3Cx)
3266 {
3267   return ((READ_BIT(I3Cx->EVR, I3C_EVR_INTUPDF) == (I3C_EVR_INTUPDF)) ? 1UL : 0UL);
3268 }
3269 
3270 /**
3271   * @brief  Indicates the status of Define List Targets flag (target mode).
3272   *         RESET: Clear default value.
3273   *         SET: A Define List Targets Command have been received.
3274   * @rmtoll EVR          DEFF          LL_I3C_IsActiveFlag_DEF
3275   * @param  I3Cx I3C Instance.
3276   * @retval State of bit (1 or 0).
3277   */
LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef * I3Cx)3278 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DEF(const I3C_TypeDef *I3Cx)
3279 {
3280   return ((READ_BIT(I3Cx->EVR, I3C_EVR_DEFF) == (I3C_EVR_DEFF)) ? 1UL : 0UL);
3281 }
3282 
3283 /**
3284   * @brief  Indicates the status of Define List Group Addresses flag.
3285   *         RESET: Clear default value.
3286   *         SET: A Define List Group Addresses have been received.
3287   * @rmtoll EVR          GRPF          LL_I3C_IsActiveFlag_GRP
3288   * @param  I3Cx I3C Instance.
3289   * @retval State of bit (1 or 0).
3290   */
LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef * I3Cx)3291 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_GRP(const I3C_TypeDef *I3Cx)
3292 {
3293   return ((READ_BIT(I3Cx->EVR, I3C_EVR_GRPF) == (I3C_EVR_GRPF)) ? 1UL : 0UL);
3294 }
3295 
3296 /**
3297   * @brief  Indicates the status of Protocol Error flag.
3298   *         RESET: Clear default value.
3299   *         SET: Protocol error detected.
3300   * @rmtoll SER          PERR          LL_I3C_IsActiveFlag_PERR
3301   * @param  I3Cx I3C Instance.
3302   * @retval State of bit (1 or 0).
3303   */
LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef * I3Cx)3304 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_PERR(const I3C_TypeDef *I3Cx)
3305 {
3306   return ((READ_BIT(I3Cx->SER, I3C_SER_PERR) == (I3C_SER_PERR)) ? 1UL : 0UL);
3307 }
3308 
3309 /**
3310   * @brief  Indicates the status of SCL Stall Error flag (target mode).
3311   *         RESET: Clear default value.
3312   *         SET: Target detected that SCL was stable for more than 125us during I3C SDR read.
3313   * @rmtoll SER          STALL         LL_I3C_IsActiveFlag_STALL
3314   * @param  I3Cx I3C Instance.
3315   * @retval State of bit (1 or 0).
3316   */
LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef * I3Cx)3317 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_STALL(const I3C_TypeDef *I3Cx)
3318 {
3319   return ((READ_BIT(I3Cx->SER, I3C_SER_STALL) == (I3C_SER_STALL)) ? 1UL : 0UL);
3320 }
3321 
3322 /**
3323   * @brief  Indicates the status of RX or TX FIFO Overrun flag.
3324   *         RESET: Clear default value.
3325   *         SET: RX FIFO Full or TX FIFO Empty depending of direction of message.
3326   * @rmtoll SER          DOVR          LL_I3C_IsActiveFlag_DOVR
3327   * @param  I3Cx I3C Instance.
3328   * @retval State of bit (1 or 0).
3329   */
LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef * I3Cx)3330 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DOVR(const I3C_TypeDef *I3Cx)
3331 {
3332   return ((READ_BIT(I3Cx->SER, I3C_SER_DOVR) == (I3C_SER_DOVR)) ? 1UL : 0UL);
3333 }
3334 
3335 /**
3336   * @brief  Indicates the status of Control or Status FIFO Overrun flag (controller mode).
3337   *         RESET: Clear default value.
3338   *         SET: Status FIFO Full or Control FIFO Empty after Restart.
3339   * @rmtoll SER          COVR          LL_I3C_IsActiveFlag_COVR
3340   * @param  I3Cx I3C Instance.
3341   * @retval State of bit (1 or 0).
3342   */
LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef * I3Cx)3343 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_COVR(const I3C_TypeDef *I3Cx)
3344 {
3345   return ((READ_BIT(I3Cx->SER, I3C_SER_COVR) == (I3C_SER_COVR)) ? 1UL : 0UL);
3346 }
3347 
3348 /**
3349   * @brief  Indicates the status of Address not acknowledged flag (controller mode).
3350   *         RESET: Clear default value.
3351   *         SET: Controller detected that Target nacked static or dynamic address.
3352   * @rmtoll SER          ANACK         LL_I3C_IsActiveFlag_ANACK
3353   * @param  I3Cx I3C Instance.
3354   * @retval State of bit (1 or 0).
3355   */
LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef * I3Cx)3356 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_ANACK(const I3C_TypeDef *I3Cx)
3357 {
3358   return ((READ_BIT(I3Cx->SER, I3C_SER_ANACK) == (I3C_SER_ANACK)) ? 1UL : 0UL);
3359 }
3360 
3361 /**
3362   * @brief  Indicates the status of Data not acknowledged flag (controller mode).
3363   *         RESET: Clear default value.
3364   *         SET: Controller detected that Target nacked Data byte.
3365   * @rmtoll SER          DNACK         LL_I3C_IsActiveFlag_DNACK
3366   * @param  I3Cx I3C Instance.
3367   * @retval State of bit (1 or 0).
3368   */
LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef * I3Cx)3369 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DNACK(const I3C_TypeDef *I3Cx)
3370 {
3371   return ((READ_BIT(I3Cx->SER, I3C_SER_DNACK) == (I3C_SER_DNACK)) ? 1UL : 0UL);
3372 }
3373 
3374 /**
3375   * @brief  Indicates the status of Data error flag (controller mode).
3376   *         RESET: Clear default value.
3377   *         SET: Controller detected data error during Controller-role handoff process.
3378   * @rmtoll SER          DERR          LL_I3C_IsActiveFlag_DERR
3379   * @param  I3Cx I3C Instance.
3380   * @retval State of bit (1 or 0).
3381   */
LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef * I3Cx)3382 __STATIC_INLINE uint32_t LL_I3C_IsActiveFlag_DERR(const I3C_TypeDef *I3Cx)
3383 {
3384   return ((READ_BIT(I3Cx->SER, I3C_SER_DERR) == (I3C_SER_DERR)) ? 1UL : 0UL);
3385 }
3386 
3387 /**
3388   * @}
3389   */
3390 
3391 /** @defgroup I3C_LL_EF_IT_Management IT_Management
3392   * @{
3393   */
3394 
3395 /**
3396   * @brief  Enable Control FIFO Not Full interrupt.
3397   * @rmtoll IER          CFNFIE        LL_I3C_EnableIT_CFNF
3398   * @param  I3Cx I3C Instance.
3399   * @retval None
3400   */
LL_I3C_EnableIT_CFNF(I3C_TypeDef * I3Cx)3401 __STATIC_INLINE void LL_I3C_EnableIT_CFNF(I3C_TypeDef *I3Cx)
3402 {
3403   SET_BIT(I3Cx->IER, I3C_IER_CFNFIE);
3404 }
3405 
3406 /**
3407   * @brief  Disable Control FIFO Not Full interrupt.
3408   * @rmtoll IER          CFNFIE        LL_I3C_DisableIT_CFNF
3409   * @param  I3Cx I3C Instance.
3410   * @retval None
3411   */
LL_I3C_DisableIT_CFNF(I3C_TypeDef * I3Cx)3412 __STATIC_INLINE void LL_I3C_DisableIT_CFNF(I3C_TypeDef *I3Cx)
3413 {
3414   CLEAR_BIT(I3Cx->IER, I3C_IER_CFNFIE);
3415 }
3416 
3417 /**
3418   * @brief  Check if Control FIFO Not Full interrupt is enabled or disabled.
3419   * @rmtoll IER          CFNFIE        LL_I3C_IsEnabledIT_CFNF
3420   * @param  I3Cx I3C Instance.
3421   * @retval State of bit (1 or 0).
3422   */
LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef * I3Cx)3423 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CFNF(const I3C_TypeDef *I3Cx)
3424 {
3425   return ((READ_BIT(I3Cx->IER, I3C_IER_CFNFIE) == (I3C_IER_CFNFIE)) ? 1UL : 0UL);
3426 }
3427 
3428 /**
3429   * @brief  Enable Status FIFO Not Empty interrupt.
3430   * @rmtoll IER          SFNEIE        LL_I3C_EnableIT_SFNE
3431   * @param  I3Cx I3C Instance.
3432   * @retval None
3433   */
LL_I3C_EnableIT_SFNE(I3C_TypeDef * I3Cx)3434 __STATIC_INLINE void LL_I3C_EnableIT_SFNE(I3C_TypeDef *I3Cx)
3435 {
3436   SET_BIT(I3Cx->IER, I3C_IER_SFNEIE);
3437 }
3438 
3439 /**
3440   * @brief  Disable Status FIFO Not Empty interrupt.
3441   * @rmtoll IER          SFNEIE        LL_I3C_DisableIT_SFNE
3442   * @param  I3Cx I3C Instance.
3443   * @retval None
3444   */
LL_I3C_DisableIT_SFNE(I3C_TypeDef * I3Cx)3445 __STATIC_INLINE void LL_I3C_DisableIT_SFNE(I3C_TypeDef *I3Cx)
3446 {
3447   CLEAR_BIT(I3Cx->IER, I3C_IER_SFNEIE);
3448 }
3449 
3450 /**
3451   * @brief  Check if Status FIFO Not Empty interrupt is enabled or disabled.
3452   * @rmtoll IER          SFNEIE        LL_I3C_IsEnabledIT_SFNE
3453   * @param  I3Cx I3C Instance.
3454   * @retval State of bit (1 or 0).
3455   */
LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef * I3Cx)3456 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_SFNE(const I3C_TypeDef *I3Cx)
3457 {
3458   return ((READ_BIT(I3Cx->IER, I3C_IER_SFNEIE) == (I3C_IER_SFNEIE)) ? 1UL : 0UL);
3459 }
3460 
3461 /**
3462   * @brief  Enable Transmit FIFO Not Full interrupt.
3463   * @rmtoll IER          TXFNFIE       LL_I3C_EnableIT_TXFNF
3464   * @param  I3Cx I3C Instance.
3465   * @retval None
3466   */
LL_I3C_EnableIT_TXFNF(I3C_TypeDef * I3Cx)3467 __STATIC_INLINE void LL_I3C_EnableIT_TXFNF(I3C_TypeDef *I3Cx)
3468 {
3469   SET_BIT(I3Cx->IER, I3C_IER_TXFNFIE);
3470 }
3471 
3472 /**
3473   * @brief  Disable Transmit FIFO Not Full interrupt.
3474   * @rmtoll IER          TXFNFIE       LL_I3C_DisableIT_TXFNF
3475   * @param  I3Cx I3C Instance.
3476   * @retval None
3477   */
LL_I3C_DisableIT_TXFNF(I3C_TypeDef * I3Cx)3478 __STATIC_INLINE void LL_I3C_DisableIT_TXFNF(I3C_TypeDef *I3Cx)
3479 {
3480   CLEAR_BIT(I3Cx->IER, I3C_IER_TXFNFIE);
3481 }
3482 
3483 /**
3484   * @brief  Check if Transmit FIFO Not Full interrupt is enabled or disabled.
3485   * @rmtoll IER          TXFNFIE       LL_I3C_IsEnabledIT_TXFNF
3486   * @param  I3Cx I3C Instance.
3487   * @retval State of bit (1 or 0).
3488   */
LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef * I3Cx)3489 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_TXFNF(const I3C_TypeDef *I3Cx)
3490 {
3491   return ((READ_BIT(I3Cx->IER, I3C_IER_TXFNFIE) == (I3C_IER_TXFNFIE)) ? 1UL : 0UL);
3492 }
3493 
3494 /**
3495   * @brief  Enable Receive FIFO Not Empty interrupt.
3496   * @rmtoll IER          RXFNEIE       LL_I3C_EnableIT_RXFNE
3497   * @param  I3Cx I3C Instance.
3498   * @retval None
3499   */
LL_I3C_EnableIT_RXFNE(I3C_TypeDef * I3Cx)3500 __STATIC_INLINE void LL_I3C_EnableIT_RXFNE(I3C_TypeDef *I3Cx)
3501 {
3502   SET_BIT(I3Cx->IER, I3C_IER_RXFNEIE);
3503 }
3504 
3505 /**
3506   * @brief  Disable Receive FIFO Not Empty interrupt.
3507   * @rmtoll IER          RXFNEIE       LL_I3C_DisableIT_RXFNE
3508   * @param  I3Cx I3C Instance.
3509   * @retval None
3510   */
LL_I3C_DisableIT_RXFNE(I3C_TypeDef * I3Cx)3511 __STATIC_INLINE void LL_I3C_DisableIT_RXFNE(I3C_TypeDef *I3Cx)
3512 {
3513   CLEAR_BIT(I3Cx->IER, I3C_IER_RXFNEIE);
3514 }
3515 
3516 /**
3517   * @brief  Check if Receive FIFO Not Empty interrupt is enabled or disabled.
3518   * @rmtoll IER          RXFNEIE       LL_I3C_IsEnabledIT_RXFNE
3519   * @param  I3Cx I3C Instance.
3520   * @retval State of bit (1 or 0).
3521   */
LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef * I3Cx)3522 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXFNE(const I3C_TypeDef *I3Cx)
3523 {
3524   return ((READ_BIT(I3Cx->IER, I3C_IER_RXFNEIE) == (I3C_IER_RXFNEIE)) ? 1UL : 0UL);
3525 }
3526 
3527 /**
3528   * @brief  Enable Frame Complete interrupt.
3529   * @rmtoll IER          FCIE          LL_I3C_EnableIT_FC
3530   * @param  I3Cx I3C Instance.
3531   * @retval None
3532   */
LL_I3C_EnableIT_FC(I3C_TypeDef * I3Cx)3533 __STATIC_INLINE void LL_I3C_EnableIT_FC(I3C_TypeDef *I3Cx)
3534 {
3535   SET_BIT(I3Cx->IER, I3C_IER_FCIE);
3536 }
3537 
3538 /**
3539   * @brief  Disable Frame Complete interrupt.
3540   * @rmtoll IER          FCIE          LL_I3C_DisableIT_FC
3541   * @param  I3Cx I3C Instance.
3542   * @retval None
3543   */
LL_I3C_DisableIT_FC(I3C_TypeDef * I3Cx)3544 __STATIC_INLINE void LL_I3C_DisableIT_FC(I3C_TypeDef *I3Cx)
3545 {
3546   CLEAR_BIT(I3Cx->IER, I3C_IER_FCIE);
3547 }
3548 
3549 /**
3550   * @brief  Check if Frame Complete interrupt is enabled or disabled.
3551   * @rmtoll IER          FCIE          LL_I3C_IsEnabledIT_FC
3552   * @param  I3Cx I3C Instance.
3553   * @retval State of bit (1 or 0).
3554   */
LL_I3C_IsEnabledIT_FC(const I3C_TypeDef * I3Cx)3555 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_FC(const I3C_TypeDef *I3Cx)
3556 {
3557   return ((READ_BIT(I3Cx->IER, I3C_IER_FCIE) == (I3C_IER_FCIE)) ? 1UL : 0UL);
3558 }
3559 
3560 /**
3561   * @brief  Enable Reception Target End interrupt.
3562   * @rmtoll IER          RXTGTENDIE    LL_I3C_EnableIT_RXTGTEND
3563   * @param  I3Cx I3C Instance.
3564   * @retval None
3565   */
LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef * I3Cx)3566 __STATIC_INLINE void LL_I3C_EnableIT_RXTGTEND(I3C_TypeDef *I3Cx)
3567 {
3568   SET_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE);
3569 }
3570 
3571 /**
3572   * @brief  Disable Reception Target End interrupt.
3573   * @rmtoll IER          RXTGTENDIE    LL_I3C_DisableIT_RXTGTEND
3574   * @param  I3Cx I3C Instance.
3575   * @retval None
3576   */
LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef * I3Cx)3577 __STATIC_INLINE void LL_I3C_DisableIT_RXTGTEND(I3C_TypeDef *I3Cx)
3578 {
3579   CLEAR_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE);
3580 }
3581 
3582 /**
3583   * @brief  Check if Reception Target End interrupt is enabled or disabled.
3584   * @rmtoll IER          RXTGTENDIE    LL_I3C_IsEnabledIT_RXTGTEND
3585   * @param  I3Cx I3C Instance.
3586   * @retval State of bit (1 or 0).
3587   */
LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef * I3Cx)3588 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RXTGTEND(const I3C_TypeDef *I3Cx)
3589 {
3590   return ((READ_BIT(I3Cx->IER, I3C_IER_RXTGTENDIE) == (I3C_IER_RXTGTENDIE)) ? 1UL : 0UL);
3591 }
3592 
3593 /**
3594   * @brief  Enable Error interrupt.
3595   * @rmtoll IER          ERRIE         LL_I3C_EnableIT_ERR
3596   * @param  I3Cx I3C Instance.
3597   * @retval None
3598   */
LL_I3C_EnableIT_ERR(I3C_TypeDef * I3Cx)3599 __STATIC_INLINE void LL_I3C_EnableIT_ERR(I3C_TypeDef *I3Cx)
3600 {
3601   SET_BIT(I3Cx->IER, I3C_IER_ERRIE);
3602 }
3603 
3604 /**
3605   * @brief  Disable Error interrupt.
3606   * @rmtoll IER          ERRIE         LL_I3C_DisableIT_ERR
3607   * @param  I3Cx I3C Instance.
3608   * @retval None
3609   */
LL_I3C_DisableIT_ERR(I3C_TypeDef * I3Cx)3610 __STATIC_INLINE void LL_I3C_DisableIT_ERR(I3C_TypeDef *I3Cx)
3611 {
3612   CLEAR_BIT(I3Cx->IER, I3C_IER_ERRIE);
3613 }
3614 
3615 /**
3616   * @brief  Check if Error interrupt is enabled or disabled.
3617   * @rmtoll IER          ERRIE         LL_I3C_IsEnabledIT_ERR
3618   * @param  I3Cx I3C Instance.
3619   * @retval State of bit (1 or 0).
3620   */
LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef * I3Cx)3621 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ERR(const I3C_TypeDef *I3Cx)
3622 {
3623   return ((READ_BIT(I3Cx->IER, I3C_IER_ERRIE) == (I3C_IER_ERRIE)) ? 1UL : 0UL);
3624 }
3625 
3626 /**
3627   * @brief  Enable IBI interrupt.
3628   * @rmtoll IER          IBIIE         LL_I3C_EnableIT_IBI
3629   * @param  I3Cx I3C Instance.
3630   * @retval None
3631   */
LL_I3C_EnableIT_IBI(I3C_TypeDef * I3Cx)3632 __STATIC_INLINE void LL_I3C_EnableIT_IBI(I3C_TypeDef *I3Cx)
3633 {
3634   SET_BIT(I3Cx->IER, I3C_IER_IBIIE);
3635 }
3636 
3637 /**
3638   * @brief  Disable IBI interrupt.
3639   * @rmtoll IER          IBIIE         LL_I3C_DisableIT_IBI
3640   * @param  I3Cx I3C Instance.
3641   * @retval None
3642   */
LL_I3C_DisableIT_IBI(I3C_TypeDef * I3Cx)3643 __STATIC_INLINE void LL_I3C_DisableIT_IBI(I3C_TypeDef *I3Cx)
3644 {
3645   CLEAR_BIT(I3Cx->IER, I3C_IER_IBIIE);
3646 }
3647 
3648 /**
3649   * @brief  Check if IBI interrupt is enabled or disabled.
3650   * @rmtoll IER          IBIIE         LL_I3C_IsEnabledIT_IBI
3651   * @param  I3Cx I3C Instance.
3652   * @retval State of bit (1 or 0).
3653   */
LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef * I3Cx)3654 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBI(const I3C_TypeDef *I3Cx)
3655 {
3656   return ((READ_BIT(I3Cx->IER, I3C_IER_IBIIE) == (I3C_IER_IBIIE)) ? 1UL : 0UL);
3657 }
3658 
3659 /**
3660   * @brief  Enable IBI End interrupt.
3661   * @rmtoll IER          IBIENDIE      LL_I3C_EnableIT_IBIEND
3662   * @param  I3Cx I3C Instance.
3663   * @retval None
3664   */
LL_I3C_EnableIT_IBIEND(I3C_TypeDef * I3Cx)3665 __STATIC_INLINE void LL_I3C_EnableIT_IBIEND(I3C_TypeDef *I3Cx)
3666 {
3667   SET_BIT(I3Cx->IER, I3C_IER_IBIENDIE);
3668 }
3669 
3670 /**
3671   * @brief  Disable IBI End interrupt.
3672   * @rmtoll IER          IBIENDIE      LL_I3C_DisableIT_IBIEND
3673   * @param  I3Cx I3C Instance.
3674   * @retval None
3675   */
LL_I3C_DisableIT_IBIEND(I3C_TypeDef * I3Cx)3676 __STATIC_INLINE void LL_I3C_DisableIT_IBIEND(I3C_TypeDef *I3Cx)
3677 {
3678   CLEAR_BIT(I3Cx->IER, I3C_IER_IBIENDIE);
3679 }
3680 
3681 /**
3682   * @brief  Check if IBI End interrupt is enabled or disabled.
3683   * @rmtoll IER          IBIENDIE      LL_I3C_IsEnabledIT_IBIEND
3684   * @param  I3Cx I3C Instance.
3685   * @retval State of bit (1 or 0).
3686   */
LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef * I3Cx)3687 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_IBIEND(const I3C_TypeDef *I3Cx)
3688 {
3689   return ((READ_BIT(I3Cx->IER, I3C_IER_IBIENDIE) == (I3C_IER_IBIENDIE)) ? 1UL : 0UL);
3690 }
3691 
3692 /**
3693   * @brief  Enable Controller-role interrupt.
3694   * @rmtoll IER          CRIE          LL_I3C_EnableIT_CR
3695   * @param  I3Cx I3C Instance.
3696   * @retval None
3697   */
LL_I3C_EnableIT_CR(I3C_TypeDef * I3Cx)3698 __STATIC_INLINE void LL_I3C_EnableIT_CR(I3C_TypeDef *I3Cx)
3699 {
3700   SET_BIT(I3Cx->IER, I3C_IER_CRIE);
3701 }
3702 
3703 /**
3704   * @brief  Disable Controller-role interrupt.
3705   * @rmtoll IER          CRIE          LL_I3C_DisableIT_CR
3706   * @param  I3Cx I3C Instance.
3707   * @retval None
3708   */
LL_I3C_DisableIT_CR(I3C_TypeDef * I3Cx)3709 __STATIC_INLINE void LL_I3C_DisableIT_CR(I3C_TypeDef *I3Cx)
3710 {
3711   CLEAR_BIT(I3Cx->IER, I3C_IER_CRIE);
3712 }
3713 
3714 /**
3715   * @brief  Check if Controller-role interrupt is enabled or disabled.
3716   * @rmtoll IER          CRIE          LL_I3C_IsEnabledIT_CR
3717   * @param  I3Cx I3C Instance.
3718   * @retval State of bit (1 or 0).
3719   */
LL_I3C_IsEnabledIT_CR(const I3C_TypeDef * I3Cx)3720 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CR(const I3C_TypeDef *I3Cx)
3721 {
3722   return ((READ_BIT(I3Cx->IER, I3C_IER_CRIE) == (I3C_IER_CRIE)) ? 1UL : 0UL);
3723 }
3724 
3725 /**
3726   * @brief  Enable Controller-role Update interrupt.
3727   * @rmtoll IER          CRUPDIE       LL_I3C_EnableIT_CRUPD
3728   * @param  I3Cx I3C Instance.
3729   * @retval None
3730   */
LL_I3C_EnableIT_CRUPD(I3C_TypeDef * I3Cx)3731 __STATIC_INLINE void LL_I3C_EnableIT_CRUPD(I3C_TypeDef *I3Cx)
3732 {
3733   SET_BIT(I3Cx->IER, I3C_IER_CRUPDIE);
3734 }
3735 
3736 /**
3737   * @brief  Disable Controller-role Update interrupt.
3738   * @rmtoll IER          CRUPDIE       LL_I3C_DisableIT_CRUPD
3739   * @param  I3Cx I3C Instance.
3740   * @retval None
3741   */
LL_I3C_DisableIT_CRUPD(I3C_TypeDef * I3Cx)3742 __STATIC_INLINE void LL_I3C_DisableIT_CRUPD(I3C_TypeDef *I3Cx)
3743 {
3744   CLEAR_BIT(I3Cx->IER, I3C_IER_CRUPDIE);
3745 }
3746 
3747 /**
3748   * @brief  Check if Controller-role Update interrupt is enabled or disabled.
3749   * @rmtoll IER          CRUPDIE       LL_I3C_IsEnabledIT_CRUPD
3750   * @param  I3Cx I3C Instance.
3751   * @retval State of bit (1 or 0).
3752   */
LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef * I3Cx)3753 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_CRUPD(const I3C_TypeDef *I3Cx)
3754 {
3755   return ((READ_BIT(I3Cx->IER, I3C_IER_CRUPDIE) == (I3C_IER_CRUPDIE)) ? 1UL : 0UL);
3756 }
3757 
3758 /**
3759   * @brief  Enable Hot Join interrupt.
3760   * @rmtoll IER          HJIE          LL_I3C_EnableIT_HJ
3761   * @param  I3Cx I3C Instance.
3762   * @retval None
3763   */
LL_I3C_EnableIT_HJ(I3C_TypeDef * I3Cx)3764 __STATIC_INLINE void LL_I3C_EnableIT_HJ(I3C_TypeDef *I3Cx)
3765 {
3766   SET_BIT(I3Cx->IER, I3C_IER_HJIE);
3767 }
3768 
3769 /**
3770   * @brief  Disable Hot Join interrupt.
3771   * @rmtoll IER          HJIE          LL_I3C_DisableIT_HJ
3772   * @param  I3Cx I3C Instance.
3773   * @retval None
3774   */
LL_I3C_DisableIT_HJ(I3C_TypeDef * I3Cx)3775 __STATIC_INLINE void LL_I3C_DisableIT_HJ(I3C_TypeDef *I3Cx)
3776 {
3777   CLEAR_BIT(I3Cx->IER, I3C_IER_HJIE);
3778 }
3779 
3780 /**
3781   * @brief  Check if Hot Join interrupt is enabled or disabled.
3782   * @rmtoll IER          HJIE          LL_I3C_IsEnabledIT_HJ
3783   * @param  I3Cx I3C Instance.
3784   * @retval State of bit (1 or 0).
3785   */
LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef * I3Cx)3786 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_HJ(const I3C_TypeDef *I3Cx)
3787 {
3788   return ((READ_BIT(I3Cx->IER, I3C_IER_HJIE) == (I3C_IER_HJIE)) ? 1UL : 0UL);
3789 }
3790 
3791 /**
3792   * @brief  Enable Wake Up interrupt.
3793   * @rmtoll IER          WKPIE         LL_I3C_EnableIT_WKP
3794   * @param  I3Cx I3C Instance.
3795   * @retval None
3796   */
LL_I3C_EnableIT_WKP(I3C_TypeDef * I3Cx)3797 __STATIC_INLINE void LL_I3C_EnableIT_WKP(I3C_TypeDef *I3Cx)
3798 {
3799   SET_BIT(I3Cx->IER, I3C_IER_WKPIE);
3800 }
3801 
3802 /**
3803   * @brief  Disable Wake Up interrupt.
3804   * @rmtoll IER          WKPIE         LL_I3C_DisableIT_WKP
3805   * @param  I3Cx I3C Instance.
3806   * @retval None
3807   */
LL_I3C_DisableIT_WKP(I3C_TypeDef * I3Cx)3808 __STATIC_INLINE void LL_I3C_DisableIT_WKP(I3C_TypeDef *I3Cx)
3809 {
3810   CLEAR_BIT(I3Cx->IER, I3C_IER_WKPIE);
3811 }
3812 
3813 /**
3814   * @brief  Check if Wake Up is enabled or disabled.
3815   * @rmtoll IER          WKPIE         LL_I3C_IsEnabledIT_WKP
3816   * @param  I3Cx I3C Instance.
3817   * @retval State of bit (1 or 0).
3818   */
LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef * I3Cx)3819 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_WKP(const I3C_TypeDef *I3Cx)
3820 {
3821   return ((READ_BIT(I3Cx->IER, I3C_IER_WKPIE) == (I3C_IER_WKPIE)) ? 1UL : 0UL);
3822 }
3823 
3824 /**
3825   * @brief  Enable Get Command interrupt.
3826   * @rmtoll IER          GETIE         LL_I3C_EnableIT_GET
3827   * @param  I3Cx I3C Instance.
3828   * @retval None
3829   */
LL_I3C_EnableIT_GET(I3C_TypeDef * I3Cx)3830 __STATIC_INLINE void LL_I3C_EnableIT_GET(I3C_TypeDef *I3Cx)
3831 {
3832   SET_BIT(I3Cx->IER, I3C_IER_GETIE);
3833 }
3834 
3835 /**
3836   * @brief  Disable Get Command interrupt.
3837   * @rmtoll IER          GETIE         LL_I3C_DisableIT_GET
3838   * @param  I3Cx I3C Instance.
3839   * @retval None
3840   */
LL_I3C_DisableIT_GET(I3C_TypeDef * I3Cx)3841 __STATIC_INLINE void LL_I3C_DisableIT_GET(I3C_TypeDef *I3Cx)
3842 {
3843   CLEAR_BIT(I3Cx->IER, I3C_IER_GETIE);
3844 }
3845 
3846 /**
3847   * @brief  Check if Get Command is enabled or disabled.
3848   * @rmtoll IER          GETIE         LL_I3C_IsEnabledIT_GET
3849   * @param  I3Cx I3C Instance.
3850   * @retval State of bit (1 or 0).
3851   */
LL_I3C_IsEnabledIT_GET(const I3C_TypeDef * I3Cx)3852 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GET(const I3C_TypeDef *I3Cx)
3853 {
3854   return ((READ_BIT(I3Cx->IER, I3C_IER_GETIE) == (I3C_IER_GETIE)) ? 1UL : 0UL);
3855 }
3856 
3857 /**
3858   * @brief  Enable Get Status interrupt.
3859   * @rmtoll IER          STAIE         LL_I3C_EnableIT_STA
3860   * @param  I3Cx I3C Instance.
3861   * @retval None
3862   */
LL_I3C_EnableIT_STA(I3C_TypeDef * I3Cx)3863 __STATIC_INLINE void LL_I3C_EnableIT_STA(I3C_TypeDef *I3Cx)
3864 {
3865   SET_BIT(I3Cx->IER, I3C_IER_STAIE);
3866 }
3867 
3868 /**
3869   * @brief  Disable Get Status interrupt.
3870   * @rmtoll IER          STAIE         LL_I3C_DisableIT_STA
3871   * @param  I3Cx I3C Instance.
3872   * @retval None
3873   */
LL_I3C_DisableIT_STA(I3C_TypeDef * I3Cx)3874 __STATIC_INLINE void LL_I3C_DisableIT_STA(I3C_TypeDef *I3Cx)
3875 {
3876   CLEAR_BIT(I3Cx->IER, I3C_IER_STAIE);
3877 }
3878 
3879 /**
3880   * @brief  Check if Get Status interrupt is enabled or disabled.
3881   * @rmtoll IER          STAIE         LL_I3C_IsEnabledIT_STA
3882   * @param  I3Cx I3C Instance.
3883   * @retval State of bit (1 or 0).
3884   */
LL_I3C_IsEnabledIT_STA(const I3C_TypeDef * I3Cx)3885 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_STA(const I3C_TypeDef *I3Cx)
3886 {
3887   return ((READ_BIT(I3Cx->IER, I3C_IER_STAIE) == (I3C_IER_STAIE)) ? 1UL : 0UL);
3888 }
3889 
3890 /**
3891   * @brief  Enable Dynamic Address Update interrupt.
3892   * @rmtoll IER          DAUPDIE       LL_I3C_EnableIT_DAUPD
3893   * @param  I3Cx I3C Instance.
3894   * @retval None
3895   */
LL_I3C_EnableIT_DAUPD(I3C_TypeDef * I3Cx)3896 __STATIC_INLINE void LL_I3C_EnableIT_DAUPD(I3C_TypeDef *I3Cx)
3897 {
3898   SET_BIT(I3Cx->IER, I3C_IER_DAUPDIE);
3899 }
3900 
3901 /**
3902   * @brief  Disable Dynamic Address Update interrupt.
3903   * @rmtoll IER          DAUPDIE       LL_I3C_DisableIT_DAUPD
3904   * @param  I3Cx I3C Instance.
3905   * @retval None
3906   */
LL_I3C_DisableIT_DAUPD(I3C_TypeDef * I3Cx)3907 __STATIC_INLINE void LL_I3C_DisableIT_DAUPD(I3C_TypeDef *I3Cx)
3908 {
3909   CLEAR_BIT(I3Cx->IER, I3C_IER_DAUPDIE);
3910 }
3911 
3912 /**
3913   * @brief  Check if Dynamic Address Update interrupt is enabled or disabled.
3914   * @rmtoll IER          DAUPDIE       LL_I3C_IsEnabledIT_DAUPD
3915   * @param  I3Cx I3C Instance.
3916   * @retval State of bit (1 or 0).
3917   */
LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef * I3Cx)3918 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DAUPD(const I3C_TypeDef *I3Cx)
3919 {
3920   return ((READ_BIT(I3Cx->IER, I3C_IER_DAUPDIE) == (I3C_IER_DAUPDIE)) ? 1UL : 0UL);
3921 }
3922 
3923 /**
3924   * @brief  Enable Max Write Length Update interrupt.
3925   * @rmtoll IER          MWLUPDIE      LL_I3C_EnableIT_MWLUPD
3926   * @param  I3Cx I3C Instance.
3927   * @retval None
3928   */
LL_I3C_EnableIT_MWLUPD(I3C_TypeDef * I3Cx)3929 __STATIC_INLINE void LL_I3C_EnableIT_MWLUPD(I3C_TypeDef *I3Cx)
3930 {
3931   SET_BIT(I3Cx->IER, I3C_IER_MWLUPDIE);
3932 }
3933 
3934 /**
3935   * @brief  Disable Max Write Length Update interrupt.
3936   * @rmtoll IER          MWLUPDIE      LL_I3C_DisableIT_MWLUPD
3937   * @param  I3Cx I3C Instance.
3938   * @retval None
3939   */
LL_I3C_DisableIT_MWLUPD(I3C_TypeDef * I3Cx)3940 __STATIC_INLINE void LL_I3C_DisableIT_MWLUPD(I3C_TypeDef *I3Cx)
3941 {
3942   CLEAR_BIT(I3Cx->IER, I3C_IER_MWLUPDIE);
3943 }
3944 
3945 /**
3946   * @brief  Check if Max Write Length Update interrupt is enabled or disabled.
3947   * @rmtoll IER          MWLUPDIE      LL_I3C_IsEnabledIT_MWLUPD
3948   * @param  I3Cx I3C Instance.
3949   * @retval State of bit (1 or 0).
3950   */
LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef * I3Cx)3951 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MWLUPD(const I3C_TypeDef *I3Cx)
3952 {
3953   return ((READ_BIT(I3Cx->IER, I3C_IER_MWLUPDIE) == (I3C_IER_MWLUPDIE)) ? 1UL : 0UL);
3954 }
3955 
3956 /**
3957   * @brief  Enable Max Read Length Update interrupt.
3958   * @rmtoll IER          MRLUPDIE      LL_I3C_EnableIT_MRLUPD
3959   * @param  I3Cx I3C Instance.
3960   * @retval None
3961   */
LL_I3C_EnableIT_MRLUPD(I3C_TypeDef * I3Cx)3962 __STATIC_INLINE void LL_I3C_EnableIT_MRLUPD(I3C_TypeDef *I3Cx)
3963 {
3964   SET_BIT(I3Cx->IER, I3C_IER_MRLUPDIE);
3965 }
3966 
3967 /**
3968   * @brief  Disable Max Read Length Update interrupt.
3969   * @rmtoll IER          MRLUPDIE      LL_I3C_DisableIT_MRLUPD
3970   * @param  I3Cx I3C Instance.
3971   * @retval None
3972   */
LL_I3C_DisableIT_MRLUPD(I3C_TypeDef * I3Cx)3973 __STATIC_INLINE void LL_I3C_DisableIT_MRLUPD(I3C_TypeDef *I3Cx)
3974 {
3975   CLEAR_BIT(I3Cx->IER, I3C_IER_MRLUPDIE);
3976 }
3977 
3978 /**
3979   * @brief  Check if Max Read Length Update interrupt is enabled or disabled.
3980   * @rmtoll IER          MRLUPDIE      LL_I3C_IsEnabledIT_MRLUPD
3981   * @param  I3Cx I3C Instance.
3982   * @retval State of bit (1 or 0).
3983   */
LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef * I3Cx)3984 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_MRLUPD(const I3C_TypeDef *I3Cx)
3985 {
3986   return ((READ_BIT(I3Cx->IER, I3C_IER_MRLUPDIE) == (I3C_IER_MRLUPDIE)) ? 1UL : 0UL);
3987 }
3988 
3989 /**
3990   * @brief  Enable Reset interrupt.
3991   * @rmtoll IER          RSTIE         LL_I3C_EnableIT_RST
3992   * @param  I3Cx I3C Instance.
3993   * @retval None
3994   */
LL_I3C_EnableIT_RST(I3C_TypeDef * I3Cx)3995 __STATIC_INLINE void LL_I3C_EnableIT_RST(I3C_TypeDef *I3Cx)
3996 {
3997   SET_BIT(I3Cx->IER, I3C_IER_RSTIE);
3998 }
3999 
4000 /**
4001   * @brief  Disable Reset interrupt.
4002   * @rmtoll IER          RSTIE         LL_I3C_DisableIT_RST
4003   * @param  I3Cx I3C Instance.
4004   * @retval None
4005   */
LL_I3C_DisableIT_RST(I3C_TypeDef * I3Cx)4006 __STATIC_INLINE void LL_I3C_DisableIT_RST(I3C_TypeDef *I3Cx)
4007 {
4008   CLEAR_BIT(I3Cx->IER, I3C_IER_RSTIE);
4009 }
4010 
4011 /**
4012   * @brief  Check if Reset interrupt is enabled or disabled.
4013   * @rmtoll IER          RSTIE         LL_I3C_IsEnabledIT_RST
4014   * @param  I3Cx I3C Instance.
4015   * @retval State of bit (1 or 0).
4016   */
LL_I3C_IsEnabledIT_RST(const I3C_TypeDef * I3Cx)4017 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_RST(const I3C_TypeDef *I3Cx)
4018 {
4019   return ((READ_BIT(I3Cx->IER, I3C_IER_RSTIE) == (I3C_IER_RSTIE)) ? 1UL : 0UL);
4020 }
4021 
4022 /**
4023   * @brief  Enable Activity State Update interrupt.
4024   * @rmtoll IER          ASUPDIE       LL_I3C_EnableIT_ASUPD
4025   * @param  I3Cx I3C Instance.
4026   * @retval None
4027   */
LL_I3C_EnableIT_ASUPD(I3C_TypeDef * I3Cx)4028 __STATIC_INLINE void LL_I3C_EnableIT_ASUPD(I3C_TypeDef *I3Cx)
4029 {
4030   SET_BIT(I3Cx->IER, I3C_IER_ASUPDIE);
4031 }
4032 
4033 /**
4034   * @brief  Disable Activity State Update interrupt.
4035   * @rmtoll IER          ASUPDIE       LL_I3C_DisableIT_ASUPD
4036   * @param  I3Cx I3C Instance.
4037   * @retval None
4038   */
LL_I3C_DisableIT_ASUPD(I3C_TypeDef * I3Cx)4039 __STATIC_INLINE void LL_I3C_DisableIT_ASUPD(I3C_TypeDef *I3Cx)
4040 {
4041   CLEAR_BIT(I3Cx->IER, I3C_IER_ASUPDIE);
4042 }
4043 
4044 /**
4045   * @brief  Check if Activity State Update interrupt is enabled or disabled.
4046   * @rmtoll IER          ASUPDIE       LL_I3C_IsEnabledIT_ASUPD
4047   * @param  I3Cx I3C Instance.
4048   * @retval State of bit (1 or 0).
4049   */
LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef * I3Cx)4050 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_ASUPD(const I3C_TypeDef *I3Cx)
4051 {
4052   return ((READ_BIT(I3Cx->IER, I3C_IER_ASUPDIE) == (I3C_IER_ASUPDIE)) ? 1UL : 0UL);
4053 }
4054 
4055 /**
4056   * @brief  Enable Interrupt Update interrupt.
4057   * @rmtoll IER          INTUPDIE      LL_I3C_EnableIT_INTUPD
4058   * @param  I3Cx I3C Instance.
4059   * @retval None
4060   */
LL_I3C_EnableIT_INTUPD(I3C_TypeDef * I3Cx)4061 __STATIC_INLINE void LL_I3C_EnableIT_INTUPD(I3C_TypeDef *I3Cx)
4062 {
4063   SET_BIT(I3Cx->IER, I3C_IER_INTUPDIE);
4064 }
4065 
4066 /**
4067   * @brief  Disable Interrupt Update interrupt.
4068   * @rmtoll IER          INTUPDIE      LL_I3C_DisableIT_INTUPD
4069   * @param  I3Cx I3C Instance.
4070   * @retval None
4071   */
LL_I3C_DisableIT_INTUPD(I3C_TypeDef * I3Cx)4072 __STATIC_INLINE void LL_I3C_DisableIT_INTUPD(I3C_TypeDef *I3Cx)
4073 {
4074   CLEAR_BIT(I3Cx->IER, I3C_IER_INTUPDIE);
4075 }
4076 
4077 /**
4078   * @brief  Check if Interrupt Update interrupt is enabled or disabled.
4079   * @rmtoll IER          INTUPDIE      LL_I3C_IsEnabledIT_INTUPD
4080   * @param  I3Cx I3C Instance.
4081   * @retval State of bit (1 or 0).
4082   */
LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef * I3Cx)4083 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_INTUPD(const I3C_TypeDef *I3Cx)
4084 {
4085   return ((READ_BIT(I3Cx->IER, I3C_IER_INTUPDIE) == (I3C_IER_INTUPDIE)) ? 1UL : 0UL);
4086 }
4087 
4088 /**
4089   * @brief  Enable Define List Target interrupt.
4090   * @rmtoll IER          DEFIE         LL_I3C_EnableIT_DEF
4091   * @param  I3Cx I3C Instance.
4092   * @retval None
4093   */
LL_I3C_EnableIT_DEF(I3C_TypeDef * I3Cx)4094 __STATIC_INLINE void LL_I3C_EnableIT_DEF(I3C_TypeDef *I3Cx)
4095 {
4096   SET_BIT(I3Cx->IER, I3C_IER_DEFIE);
4097 }
4098 
4099 /**
4100   * @brief  Disable Define List Target interrupt.
4101   * @rmtoll IER          DEFIE         LL_I3C_DisableIT_DEF
4102   * @param  I3Cx I3C Instance.
4103   * @retval None
4104   */
LL_I3C_DisableIT_DEF(I3C_TypeDef * I3Cx)4105 __STATIC_INLINE void LL_I3C_DisableIT_DEF(I3C_TypeDef *I3Cx)
4106 {
4107   CLEAR_BIT(I3Cx->IER, I3C_IER_DEFIE);
4108 }
4109 
4110 /**
4111   * @brief  Check if Define List Target interrupt is enabled or disabled.
4112   * @rmtoll IER          DEFIE         LL_I3C_IsEnabledIT_DEF
4113   * @param  I3Cx I3C Instance.
4114   * @retval State of bit (1 or 0).
4115   */
LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef * I3Cx)4116 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_DEF(const I3C_TypeDef *I3Cx)
4117 {
4118   return ((READ_BIT(I3Cx->IER, I3C_IER_DEFIE) == (I3C_IER_DEFIE)) ? 1UL : 0UL);
4119 }
4120 
4121 /**
4122   * @brief  Enable Define List Group Addresses interrupt.
4123   * @rmtoll IER          GRPIE         LL_I3C_EnableIT_GRP
4124   * @param  I3Cx I3C Instance.
4125   * @retval None
4126   */
LL_I3C_EnableIT_GRP(I3C_TypeDef * I3Cx)4127 __STATIC_INLINE void LL_I3C_EnableIT_GRP(I3C_TypeDef *I3Cx)
4128 {
4129   SET_BIT(I3Cx->IER, I3C_IER_GRPIE);
4130 }
4131 
4132 /**
4133   * @brief  Disable Define List Group Addresses interrupt.
4134   * @rmtoll IER          GRPIE         LL_I3C_DisableIT_GRP
4135   * @param  I3Cx I3C Instance.
4136   * @retval None
4137   */
LL_I3C_DisableIT_GRP(I3C_TypeDef * I3Cx)4138 __STATIC_INLINE void LL_I3C_DisableIT_GRP(I3C_TypeDef *I3Cx)
4139 {
4140   CLEAR_BIT(I3Cx->IER, I3C_IER_GRPIE);
4141 }
4142 
4143 /**
4144   * @brief  Check if Define List Group Addresses interrupt is enabled or disabled.
4145   * @rmtoll IER          GRPIE         LL_I3C_IsEnabledIT_GRP
4146   * @param  I3Cx I3C Instance.
4147   * @retval State of bit (1 or 0).
4148   */
LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef * I3Cx)4149 __STATIC_INLINE uint32_t LL_I3C_IsEnabledIT_GRP(const I3C_TypeDef *I3Cx)
4150 {
4151   return ((READ_BIT(I3Cx->IER, I3C_IER_GRPIE) == (I3C_IER_GRPIE)) ? 1UL : 0UL);
4152 }
4153 
4154 /**
4155   * @}
4156   */
4157 
4158 /** @addtogroup I3C_LL_EF_FLAG_management FLAG_management
4159   * @{
4160   */
4161 
4162 /**
4163   * @brief  Clear Frame Complete flag (controller and target mode).
4164   * @rmtoll CEVR         CFCF          LL_I3C_ClearFlag_FC
4165   * @param  I3Cx I3C Instance.
4166   * @retval None
4167   */
LL_I3C_ClearFlag_FC(I3C_TypeDef * I3Cx)4168 __STATIC_INLINE void LL_I3C_ClearFlag_FC(I3C_TypeDef *I3Cx)
4169 {
4170   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CFCF);
4171 }
4172 
4173 /**
4174   * @brief  Clear Reception Target End flag (controller mode).
4175   * @rmtoll CEVR         CRXTGTENDF    LL_I3C_ClearFlag_RXTGTEND
4176   * @param  I3Cx I3C Instance.
4177   * @retval None
4178   */
LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef * I3Cx)4179 __STATIC_INLINE void LL_I3C_ClearFlag_RXTGTEND(I3C_TypeDef *I3Cx)
4180 {
4181   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRXTGTENDF);
4182 }
4183 
4184 /**
4185   * @brief  Clear Error flag (controller and target mode).
4186   * @rmtoll CEVR         CERRF         LL_I3C_ClearFlag_ERR
4187   * @param  I3Cx I3C Instance.
4188   * @retval None
4189   */
LL_I3C_ClearFlag_ERR(I3C_TypeDef * I3Cx)4190 __STATIC_INLINE void LL_I3C_ClearFlag_ERR(I3C_TypeDef *I3Cx)
4191 {
4192   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CERRF);
4193 }
4194 
4195 /**
4196   * @brief  Clear IBI flag (controller mode).
4197   * @rmtoll CEVR         CIBIF         LL_I3C_ClearFlag_IBI
4198   * @param  I3Cx I3C Instance.
4199   * @retval None
4200   */
LL_I3C_ClearFlag_IBI(I3C_TypeDef * I3Cx)4201 __STATIC_INLINE void LL_I3C_ClearFlag_IBI(I3C_TypeDef *I3Cx)
4202 {
4203   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIF);
4204 }
4205 
4206 /**
4207   * @brief  Clear IBI End flag (target mode).
4208   * @rmtoll CEVR         CIBIENDF      LL_I3C_ClearFlag_IBIEND
4209   * @param  I3Cx I3C Instance.
4210   * @retval None
4211   */
LL_I3C_ClearFlag_IBIEND(I3C_TypeDef * I3Cx)4212 __STATIC_INLINE void LL_I3C_ClearFlag_IBIEND(I3C_TypeDef *I3Cx)
4213 {
4214   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CIBIENDF);
4215 }
4216 
4217 /**
4218   * @brief  Clear Controller-role Request flag (controller mode).
4219   * @rmtoll CEVR         CCRF          LL_I3C_ClearFlag_CR
4220   * @param  I3Cx I3C Instance.
4221   * @retval None
4222   */
LL_I3C_ClearFlag_CR(I3C_TypeDef * I3Cx)4223 __STATIC_INLINE void LL_I3C_ClearFlag_CR(I3C_TypeDef *I3Cx)
4224 {
4225   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRF);
4226 }
4227 
4228 /**
4229   * @brief  Clear Controller-role Request Update flag (target mode).
4230   * @rmtoll CEVR         CCRUPDF       LL_I3C_ClearFlag_CRUPD
4231   * @param  I3Cx I3C Instance.
4232   * @retval None
4233   */
LL_I3C_ClearFlag_CRUPD(I3C_TypeDef * I3Cx)4234 __STATIC_INLINE void LL_I3C_ClearFlag_CRUPD(I3C_TypeDef *I3Cx)
4235 {
4236   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CCRUPDF);
4237 }
4238 
4239 /**
4240   * @brief  Clear Hot Join flag (controller mode).
4241   * @rmtoll CEVR         CHJF          LL_I3C_ClearFlag_HJ
4242   * @param  I3Cx I3C Instance.
4243   * @retval None
4244   */
LL_I3C_ClearFlag_HJ(I3C_TypeDef * I3Cx)4245 __STATIC_INLINE void LL_I3C_ClearFlag_HJ(I3C_TypeDef *I3Cx)
4246 {
4247   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CHJF);
4248 }
4249 
4250 /**
4251   * @brief  Clear Wake Up flag (target mode).
4252   * @rmtoll CEVR         CWKPF         LL_I3C_ClearFlag_WKP
4253   * @param  I3Cx I3C Instance.
4254   * @retval None
4255   */
LL_I3C_ClearFlag_WKP(I3C_TypeDef * I3Cx)4256 __STATIC_INLINE void LL_I3C_ClearFlag_WKP(I3C_TypeDef *I3Cx)
4257 {
4258   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CWKPF);
4259 }
4260 
4261 /**
4262   * @brief  Clear Get flag (target mode).
4263   * @rmtoll CEVR         CGETF         LL_I3C_ClearFlag_GET
4264   * @param  I3Cx I3C Instance.
4265   * @retval None
4266   */
LL_I3C_ClearFlag_GET(I3C_TypeDef * I3Cx)4267 __STATIC_INLINE void LL_I3C_ClearFlag_GET(I3C_TypeDef *I3Cx)
4268 {
4269   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGETF);
4270 }
4271 
4272 /**
4273   * @brief  Clear Get Status flag (target mode).
4274   * @rmtoll CEVR         CSTAF         LL_I3C_ClearFlag_STA
4275   * @param  I3Cx I3C Instance.
4276   * @retval None
4277   */
LL_I3C_ClearFlag_STA(I3C_TypeDef * I3Cx)4278 __STATIC_INLINE void LL_I3C_ClearFlag_STA(I3C_TypeDef *I3Cx)
4279 {
4280   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CSTAF);
4281 }
4282 
4283 /**
4284   * @brief  Clear Dynamic Address Update flag (target mode).
4285   * @rmtoll CEVR         CDAUPDF       LL_I3C_ClearFlag_DAUPD
4286   * @param  I3Cx I3C Instance.
4287   * @retval None
4288   */
LL_I3C_ClearFlag_DAUPD(I3C_TypeDef * I3Cx)4289 __STATIC_INLINE void LL_I3C_ClearFlag_DAUPD(I3C_TypeDef *I3Cx)
4290 {
4291   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDAUPDF);
4292 }
4293 
4294 /**
4295   * @brief  Clear Max Write Length flag (target mode).
4296   * @rmtoll CEVR         CMWLUPDF      LL_I3C_ClearFlag_MWLUPD
4297   * @param  I3Cx I3C Instance.
4298   * @retval None
4299   */
LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef * I3Cx)4300 __STATIC_INLINE void LL_I3C_ClearFlag_MWLUPD(I3C_TypeDef *I3Cx)
4301 {
4302   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMWLUPDF);
4303 }
4304 
4305 /**
4306   * @brief  Clear Max Read Length flag (target mode).
4307   * @rmtoll CEVR         CMRLUPDF      LL_I3C_ClearFlag_MRLUPD
4308   * @param  I3Cx I3C Instance.
4309   * @retval None
4310   */
LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef * I3Cx)4311 __STATIC_INLINE void LL_I3C_ClearFlag_MRLUPD(I3C_TypeDef *I3Cx)
4312 {
4313   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CMRLUPDF);
4314 }
4315 
4316 /**
4317   * @brief  Clear Reset flag (target mode).
4318   * @rmtoll CEVR         CRSTF         LL_I3C_ClearFlag_RST
4319   * @param  I3Cx I3C Instance.
4320   * @retval None
4321   */
LL_I3C_ClearFlag_RST(I3C_TypeDef * I3Cx)4322 __STATIC_INLINE void LL_I3C_ClearFlag_RST(I3C_TypeDef *I3Cx)
4323 {
4324   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CRSTF);
4325 }
4326 
4327 /**
4328   * @brief  Clear Active State flag (target mode).
4329   * @rmtoll CEVR         CASUPDF       LL_I3C_ClearFlag_ASUPD
4330   * @param  I3Cx I3C Instance.
4331   * @retval None
4332   */
LL_I3C_ClearFlag_ASUPD(I3C_TypeDef * I3Cx)4333 __STATIC_INLINE void LL_I3C_ClearFlag_ASUPD(I3C_TypeDef *I3Cx)
4334 {
4335   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CASUPDF);
4336 }
4337 
4338 /**
4339   * @brief  Clear Interrupt Update flag (target mode).
4340   * @rmtoll CEVR         CINTUPDF      LL_I3C_ClearFlag_INTUPD
4341   * @param  I3Cx I3C Instance.
4342   * @retval None
4343   */
LL_I3C_ClearFlag_INTUPD(I3C_TypeDef * I3Cx)4344 __STATIC_INLINE void LL_I3C_ClearFlag_INTUPD(I3C_TypeDef *I3Cx)
4345 {
4346   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CINTUPDF);
4347 }
4348 
4349 /**
4350   * @brief  Clear Define List Targets flag (target mode).
4351   * @rmtoll CEVR         CDEFF         LL_I3C_ClearFlag_DEF
4352   * @param  I3Cx I3C Instance.
4353   * @retval None
4354   */
LL_I3C_ClearFlag_DEF(I3C_TypeDef * I3Cx)4355 __STATIC_INLINE void LL_I3C_ClearFlag_DEF(I3C_TypeDef *I3Cx)
4356 {
4357   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CDEFF);
4358 }
4359 
4360 /**
4361   * @brief  Clear Define List Group Addresses flag.
4362   * @rmtoll CEVR         CGRPF         LL_I3C_ClearFlag_GRP
4363   * @param  I3Cx I3C Instance.
4364   * @retval None
4365   */
LL_I3C_ClearFlag_GRP(I3C_TypeDef * I3Cx)4366 __STATIC_INLINE void LL_I3C_ClearFlag_GRP(I3C_TypeDef *I3Cx)
4367 {
4368   WRITE_REG(I3Cx->CEVR, I3C_CEVR_CGRPF);
4369 }
4370 
4371 /**
4372   * @}
4373   */
4374 
4375 #if defined(USE_FULL_LL_DRIVER)
4376 /** @defgroup I3C_LL_EF_Init Initialization and de-initialization functions
4377   * @{
4378   */
4379 
4380 ErrorStatus LL_I3C_Init(I3C_TypeDef *I3Cx, LL_I3C_InitTypeDef *I3C_InitStruct, uint32_t Mode);
4381 ErrorStatus LL_I3C_DeInit(const I3C_TypeDef *I3Cx);
4382 void LL_I3C_StructInit(LL_I3C_InitTypeDef *I3C_InitStruct);
4383 
4384 /**
4385   * @}
4386   */
4387 #endif /* USE_FULL_LL_DRIVER */
4388 
4389 /**
4390   * @}
4391   */
4392 
4393 /**
4394   * @}
4395   */
4396 
4397 #endif /* I3C1 */
4398 
4399 /**
4400   * @}
4401   */
4402 
4403 #ifdef __cplusplus
4404 }
4405 #endif
4406 
4407 #endif /* __STM32H7RSxx_LL_I3C_H */
4408