1 /**
2   ******************************************************************************
3   * @file    stm32h7rsxx_hal_adc_ex.h
4   * @author  MCD Application Team
5   * @brief   Header file of ADC HAL extended module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2022 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_HAL_ADC_EX_H
21 #define STM32H7RSxx_HAL_ADC_EX_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx_hal_def.h"
29 
30 /** @addtogroup STM32H7RSxx_HAL_Driver
31   * @{
32   */
33 
34 /** @addtogroup ADCEx
35   * @{
36   */
37 
38 /* Exported types ------------------------------------------------------------*/
39 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
40   * @{
41   */
42 
43 /**
44   * @brief  ADC Injected Conversion Oversampling structure definition
45   */
46 typedef struct
47 {
48   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
49                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
50 
51   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
52                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
53 } ADC_InjOversamplingTypeDef;
54 
55 /**
56   * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
57   * @note   Parameters of this structure are shared within 2 scopes:
58   *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
59   *            InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
60   *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
61   *            InjectedDiscontinuousConvMode,
62   *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
63   *            InjecOversamplingMode, InjecOversampling.
64   * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
65   *         ADC state can be either:
66   *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
67   *            'InjectedSingleDiff')
68   *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled
69   *            without conversion on going on injected group.
70   *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign',
71   *            'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and
72   *            injected groups.
73   *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
74   *            'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
75   *            on ADC groups regular and injected.
76   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
77   *         without error reporting (as it can be the expected behavior in case of intended action to update another
78   *         parameter (which fulfills the ADC state condition) on the fly).
79   */
80 typedef struct
81 {
82   uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
83                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
84                                                Note: Depending on devices and ADC instances, some channels may not be
85                                                      available on device package pins. Refer to device datasheet for
86                                                      channels availability. */
87 
88   uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
89                                                This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
90                                                Note: to disable a channel or change order of conversion sequencer,
91                                                      rank containing a previous channel setting can be overwritten by
92                                                      the new channel setting (or parameter number of conversions
93                                                      adjusted) */
94 
95   uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
96                                                Unit: ADC clock cycles.
97                                                Conversion time is the addition of sampling time and processing time
98                                                (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
99                                                8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
100                                                This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
101                                                Caution: This parameter applies to a channel that can be used in a
102                                                         regular and/or injected group. It overwrites the last setting.
103                                                Note: In case of usage of internal measurement channels (VrefInt, ...),
104                                                      sampling time constraints must be respected (sampling time can be
105                                                      adjusted in function of ADC clock frequency and sampling time
106                                                      setting). Refer to device datasheet for timings values. */
107 
108   uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
109                                                In differential mode: Differential measurement is between the selected
110                                                channel 'i' (positive input) and channel 'i+1' (negative input).
111                                                Only channel 'i' has to be configured, channel 'i+1' is configured
112                                                automatically.
113                                                This parameter must be a value of
114                                                @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
115                                                Caution: This parameter applies to a channel that can be used in a
116                                                regular and/or injected group. It overwrites the last setting.
117                                                Note: Refer to Reference Manual to ensure the selected channel is
118                                                      available in differential mode.
119                                                Note: When configuring a channel 'i' in differential mode, the channel
120                                                      'i+1' is not usable separately.
121                                                Note: This parameter must be modified when ADC is disabled (before ADC
122                                                      start conversion or after ADC stop conversion).
123                                                If ADC is enabled, this parameter setting is bypassed without error
124                                                reporting (as it can be the expected behavior in case of another
125                                                parameter update on the fly) */
126 
127   uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
128                                                This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
129                                                Caution: Only one offset is allowed per channel. This parameter
130                                                         overwrites the last setting. */
131 
132   uint32_t InjectedOffset;                /*!< Defines the offset to be applied on the raw converted data.
133                                                Offset value must be a positive number.
134                                                Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
135                                                parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
136                                                0x3FF, 0xFF or 0x3F respectively.
137                                                Note: This parameter must be modified when no conversion is on going
138                                                      on both regular and injected groups (ADC disabled, or ADC enabled
139                                                      without continuous mode or external trigger that could launch a
140                                                      conversion). */
141 
142   uint32_t InjectedOffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added
143                                                   (positive sign) from or to the raw converted data.
144                                                   This parameter can be a value of @ref ADCEx_OffsetSign.
145                                                   Note: This parameter must be modified when no conversion is on going
146                                                         on both regular and injected groups (ADC disabled, or ADC
147                                                         enabled without continuous mode or external trigger that could
148                                                         launch a conversion). */
149   FunctionalState InjectedOffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
150                                                This parameter value can be ENABLE or DISABLE.
151                                                Note: This parameter must be modified when no conversion is on going
152                                                      on both regular and injected groups (ADC disabled, or ADC enabled
153                                                      without continuous mode or external trigger that could launch a
154                                                      conversion). */
155 
156   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group
157                                                injected sequencer.
158                                                To use the injected group sequencer and convert several ranks, parameter
159                                                'ScanConvMode' must be enabled.
160                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
161                                                Caution: this setting impacts the entire injected group. Therefore,
162                                                call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on
163                                                injected group can impact the configuration of other channels previously
164                                                set. */
165 
166   FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
167                                                is performed in Complete-sequence/Discontinuous-sequence
168                                                (main sequence subdivided in successive parts).
169                                                Discontinuous mode is used only if sequencer is enabled (parameter
170                                                'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
171                                                Discontinuous mode can be enabled only if continuous mode is disabled.
172                                                This parameter can be set to ENABLE or DISABLE.
173                                                Note: This parameter must be modified when ADC is disabled (before ADC
174                                                start conversion or after ADC stop conversion).
175                                                Note: For injected group, discontinuous mode converts the sequence
176                                                channel by channel (discontinuous length fixed to 1 rank).
177                                                Caution: this setting impacts the entire injected group. Therefore,
178                                                         call of HAL_ADCEx_InjectedConfigChannel() to
179                                                         configure a channel on injected group can impact the
180                                                         configuration of other channels previously set. */
181 
182   FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion
183                                                after regular one
184                                                This parameter can be set to ENABLE or DISABLE.
185                                                Note: To use Automatic injected conversion, discontinuous mode must
186                                                      be disabled ('DiscontinuousConvMode' and
187                                                      'InjectedDiscontinuousConvMode' set to DISABLE)
188                                                Note: To use Automatic injected conversion, injected group external
189                                                      triggers must be disabled ('ExternalTrigInjecConv' set to
190                                                      ADC_INJECTED_SOFTWARE_START)
191                                                Note: In case of DMA used with regular group: if DMA configured in
192                                                      normal mode (single shot) JAUTO will be stopped upon DMA transfer
193                                                      complete.
194                                                      To maintain JAUTO always enabled, DMA must be configured in
195                                                      circular mode.
196                                                Caution: this setting impacts the entire injected group. Therefore,
197                                                         call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
198                                                         on injected group can impact the configuration of other channels
199                                                         previously set. */
200 
201   FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.
202                                                This parameter can be set to ENABLE or DISABLE.
203                                                If context queue is enabled, injected sequencer&channels configurations
204                                                are queued on up to 2 contexts. If a
205                                                new injected context is set when queue is full, error is triggered by
206                                                interruption and through function
207                                                'HAL_ADCEx_InjectedQueueOverflowCallback'.
208                                                Caution: This feature request that the sequence is fully configured
209                                                         before injected conversion start.
210                                                         Therefore, configure channels with as many calls to
211                                                         HAL_ADCEx_InjectedConfigChannel() as the
212                                                         'InjectedNbrOfConversion' parameter.
213                                                Caution: this setting impacts the entire injected group. Therefore,
214                                                         call of HAL_ADCEx_InjectedConfigChannel() to
215                                                         configure a channel on injected group can impact the
216                                                         configuration of other channels previously set.
217                                                Note: This parameter must be modified when ADC is disabled (before ADC
218                                                      start conversion or after ADC stop conversion). */
219 
220   uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of
221                                                injected group.
222                                                If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
223                                                and software trigger is used instead.
224                                                This parameter can be a value of
225                                                @ref ADC_injected_external_trigger_source.
226                                                Caution: this setting impacts the entire injected group. Therefore,
227                                                         call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
228                                                         on injected group can impact the configuration of other channels
229                                                         previously set. */
230 
231   uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
232                                                This parameter can be a value of @ref ADC_injected_external_trigger_edge.
233                                                If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
234                                                is discarded.
235                                                Caution: this setting impacts the entire injected group. Therefore,
236                                                         call of HAL_ADCEx_InjectedConfigChannel() to
237                                                         configure a channel on injected group can impact the
238                                                         configuration of other channels previously set. */
239 
240   FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.
241                                                       This parameter can be set to ENABLE or DISABLE.
242                                                       Note: This parameter can be modified only if there is no
243                                                       conversion is ongoing (both ADSTART and JADSTART cleared). */
244 
245   ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
246                                                       Caution: this setting overwrites the previous oversampling
247                                                                configuration if oversampling already enabled.
248                                                       Note: This parameter can be modified only if there is no
249                                                             conversion is ongoing (both ADSTART and JADSTART cleared).*/
250 } ADC_InjectionConfTypeDef;
251 
252 #if defined(ADC_MULTIMODE_SUPPORT)
253 /**
254   * @brief  Structure definition of ADC multimode
255   * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state
256   *         (both Master and Slave ADCs).
257   *         Both Master and Slave ADCs must be disabled.
258   */
259 typedef struct
260 {
261   uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
262                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
263 
264   uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
265                                    selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel
266                                    (one DMA channel for both ADC, DMA of ADC master).
267                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
268 
269   uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
270                                    This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
271                                    Delay range depends on selected resolution:
272                                     from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
273                                     from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
274 } ADC_MultiModeTypeDef;
275 #endif /* ADC_MULTIMODE_SUPPORT */
276 
277 /**
278   * @}
279   */
280 
281 /* Exported constants --------------------------------------------------------*/
282 
283 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
284   * @{
285   */
286 
287 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
288   * @{
289   */
290 /* ADC group regular trigger sources for all ADC instances */
291 #define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< ADC group injected conversion
292                                            trigger software start */
293 #define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion
294                                            trigger from external peripheral: TIM1 TRGO event. */
295 #define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion
296                                            trigger from external peripheral: TIM1 channel 4 event (capture compare). */
297 #define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion
298                                            trigger from external peripheral: TIM2 TRGO event. */
299 #define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion
300                                            trigger from external peripheral: TIM2 channel 1 event (capture compare). */
301 #define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)        /*!< ADC group injected conversion
302                                            trigger from external peripheral: TIM3 channel 4 event (capture compare). */
303 #define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)       /*!< ADC group injected conversion
304                                            trigger from external peripheral: TIM4 TRGO event. */
305 #define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion
306                                            trigger from external peripheral: external interrupt line 15. */
307 #define ADC_EXTERNALTRIGINJEC_T9_CC1       (LL_ADC_INJ_TRIG_EXT_TIM9_CH1)        /*!< ADC group injected conversion
308                                            trigger from external peripheral: TIM9 channel 1 event (capture compare). */
309 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion
310                                            trigger from external peripheral: TIM1 TRGO2 event. */
311 #define ADC_EXTERNALTRIGINJEC_T12_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM12_TRGO)      /*!< ADC group injected conversion
312                                            trigger from external peripheral: TIM12 TRGO event. */
313 #define ADC_EXTERNALTRIGINJEC_T9_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM9_TRGO)       /*!< ADC group injected conversion
314                                            trigger from external peripheral: TIM9 TRGO event. */
315 #define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)        /*!< ADC group injected conversion
316                                            trigger from external peripheral: TIM3 channel 3 event (capture compare). */
317 #define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)       /*!< ADC group injected conversion
318                                            trigger from external peripheral: TIM3 TRGO event. */
319 #define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion
320                                            trigger from external peripheral: TIM3 channel 1 event (capture compare). */
321 #define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion
322                                            trigger from external peripheral: TIM6 TRGO event. */
323 #define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion
324                                            trigger from external peripheral: TIM15 TRGO event. */
325 #define ADC_EXTERNALTRIGINJEC_LPTIM1_CH2   (LL_ADC_INJ_TRIG_EXT_LPTIM1_CH2)      /*!< ADC group injected conversion
326                                            trigger from external peripheral: LPTIM1 channel 2 event (capture compare).*/
327 #define ADC_EXTERNALTRIGINJEC_LPTIM2_CH2   (LL_ADC_INJ_TRIG_EXT_LPTIM2_CH2)      /*!< ADC group injected conversion
328                                            trigger from external peripheral: LPTIM2 channel 2 event (capture compare).*/
329 #define ADC_EXTERNALTRIGINJEC_LPTIM3_CH1   (LL_ADC_INJ_TRIG_EXT_LPTIM3_CH1)      /*!< ADC group injected conversion
330                                            trigger from external peripheral: LPTIM3 channel 1 event (capture compare).*/
331 /**
332   * @}
333   */
334 
335 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
336   * @{
337   */
338 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions trigger
339                                                       disabled (SW start)*/
340 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions trigger
341                                                       polarity set to rising edge */
342 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions trigger
343                                                       polarity set to falling edge */
344 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions trigger
345                                                       polarity set to both rising and falling edges */
346 /**
347   * @}
348   */
349 
350 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
351   * @{
352   */
353 #define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended */
354 #define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential */
355 /**
356   * @}
357   */
358 
359 /** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
360   * @{
361   */
362 #define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
363                                      ADC channel */
364 #define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
365                                      the offset programmed will be applied (independently of channel mapped
366                                      on ADC group regular or group injected) */
367 #define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
368                                      the offset programmed will be applied (independently of channel mapped
369                                      on ADC group regular or group injected) */
370 #define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
371                                      the offset programmed will be applied (independently of channel mapped
372                                      on ADC group regular or group injected) */
373 #define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
374                                      the offset programmed will be applied (independently of channel mapped
375                                      on ADC group regular or group injected) */
376 /**
377   * @}
378   */
379 
380 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
381   * @{
382   */
383 #define ADC_OFFSET_SIGN_NEGATIVE      (0x00000000UL)         /*!< Offset sign negative, offset is subtracted */
384 #define ADC_OFFSET_SIGN_POSITIVE      (ADC_OFR1_OFFSETPOS)   /*!< Offset sign positive, offset is added  */
385 /**
386   * @}
387   */
388 
389 /** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
390   * @{
391   */
392 #define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
393 #define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
394 #define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
395 #define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
396 /**
397   * @}
398   */
399 
400 #if defined(ADC_MULTIMODE_SUPPORT)
401 /** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode
402   * @{
403   */
404 #define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)          /*!< ADC dual mode disabled
405                                            (ADC independent mode) */
406 #define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT)      /*!< ADC dual mode enabled: group regular
407                                            simultaneous */
408 #define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL)      /*!< ADC dual mode enabled: Combined
409                                            group regular interleaved */
410 #define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT)      /*!< ADC dual mode enabled: group
411                                            injected simultaneous */
412 #define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN)      /*!< ADC dual mode enabled: group
413                                            injected alternate trigger. Works only with external triggers (not internal
414                                            SW start) */
415 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
416                                            group regular simultaneous + group injected simultaneous */
417 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
418                                            group regular simultaneous + group injected alternate trigger */
419 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
420                                            group regular interleaved + group injected simultaneous */
421 
422 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION  Multimode - DMA transfer mode depending on ADC resolution
423   * @{
424   */
425 #define ADC_DMAACCESSMODE_DISABLED         (0x00000000UL)     /*!< DMA multimode disabled: each ADC uses its own
426                                            DMA channel */
427 #define ADC_DMAACCESSMODE_12_10_BITS       (ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC,
428                                            DMA of ADC master) for 12 and 10 bits resolution */
429 #define ADC_DMAACCESSMODE_8_6_BITS         (ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC,
430                                            DMA of ADC master) for 8 and 6 bits resolution */
431 /**
432   * @}
433   */
434 
435 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
436   * @{
437   */
438 #define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)    /*!< ADC multimode delay between two
439                                            sampling phases: 1 ADC clock cycle */
440 #define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)   /*!< ADC multimode delay between two
441                                            sampling phases: 2 ADC clock cycles */
442 #define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)   /*!< ADC multimode delay between two
443                                            sampling phases: 3 ADC clock cycles */
444 #define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)   /*!< ADC multimode delay between two
445                                            sampling phases: 4 ADC clock cycles */
446 #define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)   /*!< ADC multimode delay between two
447                                            sampling phases: 5 ADC clock cycles */
448 #define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)   /*!< ADC multimode delay between two
449                                            sampling phases: 6 ADC clock cycles */
450 #define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)   /*!< ADC multimode delay between two
451                                            sampling phases: 7 ADC clock cycles */
452 #define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)   /*!< ADC multimode delay between two
453                                            sampling phases: 8 ADC clock cycles */
454 #define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)   /*!< ADC multimode delay between two
455                                            sampling phases: 9 ADC clock cycles */
456 #define ADC_TWOSAMPLINGDELAY_10CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)  /*!< ADC multimode delay between two
457                                            sampling phases: 10 ADC clock cycles */
458 #define ADC_TWOSAMPLINGDELAY_11CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)  /*!< ADC multimode delay between two
459                                            sampling phases: 11 ADC clock cycles */
460 #define ADC_TWOSAMPLINGDELAY_12CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)  /*!< ADC multimode delay between two
461                                            sampling phases: 12 ADC clock cycles */
462 /**
463   * @}
464   */
465 
466 /**
467   * @}
468   */
469 #endif /* ADC_MULTIMODE_SUPPORT */
470 
471 /** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
472   * @{
473   */
474 #define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)          /*!< ADC group regular (available on
475                                                                                 all STM32 devices) */
476 #define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)         /*!< ADC group injected (not available on
477                                                                                 all STM32 devices) */
478 #define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
479 /**
480   * @}
481   */
482 
483 /** @defgroup ADC_CFGR_fields ADCx CFGR fields
484   * @{
485   */
486 #define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
487                             ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
488                             ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
489                             ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
490                             ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
491                             ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
492 /**
493   * @}
494   */
495 
496 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
497   * @{
498   */
499 #define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
500                              ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
501                              ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
502                              ADC_SMPR1_SMP0)
503 /**
504   * @}
505   */
506 
507 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
508   * @{
509   */
510 /* ADC_CFGR fields of parameters that can be updated when no conversion
511    (neither regular nor injected) is on-going  */
512 #define ADC_CFGR_FIELDS_2  ((ADC_CFGR_DMACFG | ADC_CFGR_ADFCFG | ADC_CFGR_AUTDLY))
513 /**
514   * @}
515   */
516 
517 /**
518   * @}
519   */
520 
521 /* Exported macros -----------------------------------------------------------*/
522 
523 #if defined(ADC_MULTIMODE_SUPPORT)
524 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
525   * @{
526   */
527 
528 /** @brief  Force ADC instance in multimode mode independent (multimode disable).
529   * @note   This macro must be used only in case of transition from multimode
530   *         to mode independent and in case of unknown previous state,
531   *         to ensure ADC configuration is in mode independent.
532   * @note   Standard way of multimode configuration change is done from
533   *         HAL ADC handle of ADC master using function
534   *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
535   *         Usage of this macro is not the Standard way of multimode
536   *         configuration and can lead to have HAL ADC handles status
537   *         misaligned. Usage of this macro must be limited to cases
538   *         mentioned above.
539   * @param __HANDLE__ ADC handle.
540   * @retval None
541   */
542 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
543   LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
544 
545 /**
546   * @}
547   */
548 #endif /* ADC_MULTIMODE_SUPPORT */
549 
550 /* Private macros ------------------------------------------------------------*/
551 
552 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
553   * @{
554   */
555 /* Macro reserved for internal HAL driver usage, not intended to be used in   */
556 /* code of final user.                                                        */
557 
558 /**
559   * @brief Test if conversion trigger of injected group is software start
560   *        or external trigger.
561   * @param __HANDLE__ ADC handle.
562   * @retval SET (software start) or RESET (external trigger).
563   */
564 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
565   (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
566 
567 /**
568   * @brief Check whether or not ADC is independent.
569   * @param __HANDLE__ ADC handle.
570   * @note  When multimode feature is not available, the macro always returns SET.
571   * @retval SET (ADC is independent) or RESET (ADC is not).
572   */
573 #define ADC_IS_INDEPENDENT(__HANDLE__)   (RESET)
574 
575 /**
576   * @brief Set the selected injected Channel rank.
577   * @param __CHANNELNB__ Channel number.
578   * @param __RANKNB__ Rank number.
579   * @retval None
580   */
581 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
582   ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
583    << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
584 
585 /**
586   * @brief Configure ADC injected context queue
587   * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
588   * @retval None
589   */
590 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
591   ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
592 
593 /**
594   * @brief Configure ADC discontinuous conversion mode for injected group
595   * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
596   * @retval None
597   */
598 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
599   ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)
600 
601 /**
602   * @brief Configure ADC discontinuous conversion mode for regular group
603   * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
604   * @retval None
605   */
606 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
607   ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
608 
609 /**
610   * @brief Configure the number of discontinuous conversions for regular group.
611   * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
612   * @retval None
613   */
614 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
615   (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
616 
617 /**
618   * @brief Configure the ADC auto delay mode.
619   * @param __AUTOWAIT__ Auto delay bit enable or disable.
620   * @retval None
621   */
622 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
623 
624 /**
625   * @brief Configure ADC continuous conversion mode.
626   * @param __CONTINUOUS_MODE__ Continuous mode.
627   * @retval None
628   */
629 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
630 
631 
632 #if defined(ADC_MULTIMODE_SUPPORT)
633 /**
634   * @brief Configure the ADC DMA continuous request for ADC multimode.
635   * @param __DMACONTREQ_MODE__ DMA continuous request mode.
636   * @retval None
637   */
638 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
639 #endif /* ADC_MULTIMODE_SUPPORT */
640 
641 /**
642   * @brief Shift the offset with respect to the selected ADC resolution.
643   * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
644   *         If resolution 12 bits, no shift.
645   *         If resolution 10 bits, shift of 2 ranks on the left.
646   *         If resolution 8 bits, shift of 4 ranks on the left.
647   *         If resolution 6 bits, shift of 6 ranks on the left.
648   *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
649   * @param __HANDLE__ ADC handle
650   * @param __OFFSET__ Value to be shifted
651   * @retval None
652   */
653 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
654   ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
655 
656 /**
657   * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
658   * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
659   *        If resolution 12 bits, no shift.
660   *        If resolution 10 bits, shift of 2 ranks on the left.
661   *        If resolution 8 bits, shift of 4 ranks on the left.
662   *        If resolution 6 bits, shift of 6 ranks on the left.
663   *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
664   * @param __HANDLE__ ADC handle
665   * @param __THRESHOLD__ Value to be shifted
666   * @retval None
667   */
668 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
669   ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
670 
671 /**
672   * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
673   * @note  Thresholds have to be left-aligned on bit 7.
674   *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
675   *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
676   *        If resolution 8 bits, no shift.
677   *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
678   * @param __HANDLE__ ADC handle
679   * @param __THRESHOLD__ Value to be shifted
680   * @retval None
681   */
682 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                       \
683   ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
684    ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
685    ((__THRESHOLD__) << 2UL)                                                                                 \
686   )
687 
688 /**
689   * @brief Clear Common Control Register.
690   * @param __HANDLE__ ADC handle.
691   * @retval None
692   */
693 #if defined(ADC_MULTIMODE_SUPPORT)
694 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
695                                                                 ADC_CCR_CKMODE | \
696                                                                 ADC_CCR_PRESC  | \
697                                                                 ADC_CCR_VBATEN | \
698                                                                 ADC_CCR_TSEN   | \
699                                                                 ADC_CCR_VREFEN | \
700                                                                 ADC_CCR_MDMA   | \
701                                                                 ADC_CCR_DMACFG | \
702                                                                 ADC_CCR_DELAY  | \
703                                                                 ADC_CCR_DUAL)
704 #else
705 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
706                                                                 ADC_CCR_CKMODE | \
707                                                                 ADC_CCR_PRESC  | \
708                                                                 ADC_CCR_VBATEN | \
709                                                                 ADC_CCR_TSEN   | \
710                                                                 ADC_CCR_VREFEN)
711 
712 #endif /* ADC_MULTIMODE_SUPPORT */
713 
714 /**
715   * @brief Set handle instance of the ADC slave associated to the ADC master.
716   * @param __HANDLE_MASTER__ ADC master handle.
717   * @param __HANDLE_SLAVE__ ADC slave handle.
718   * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is
719   *       set to NULL.
720   * @retval None
721   */
722 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
723   ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? \
724     ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
725 
726 
727 /**
728   * @brief Verify the ADC instance connected to the temperature sensor.
729   * @param __HANDLE__ ADC handle.
730   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
731   */
732 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
733 
734 /**
735   * @brief Verify the ADC instance connected to the battery voltage VBAT.
736   * @param __HANDLE__ ADC handle.
737   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
738   */
739 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
740 
741 /**
742   * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
743   * @param __HANDLE__ ADC handle.
744   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
745   */
746 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
747 
748 /**
749   * @brief Verify the ADC instance connected to the internal voltage reference VDDCORE.
750   * @param __HANDLE__ ADC handle.
751   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
752   */
753 /* The internal voltage reference VDDCORE measurement path (channel 0) is available on ADC2 */
754 #define ADC_VDDCORE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
755 
756 /**
757   * @brief Verify the length of scheduled injected conversions group.
758   * @param __LENGTH__ number of programmed conversions.
759   * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions)
760   *         or RESET (__LENGTH__ is null or too large)
761   */
762 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
763 
764 /**
765   * @brief Calibration factor size verification (7 bits maximum).
766   * @param __CALIBRATION_FACTOR__ Calibration factor value.
767   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
768   */
769 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
770 
771 
772 /**
773   * @brief Verify the ADC channel setting.
774   * @param __HANDLE__ ADC handle.
775   * @param __CHANNEL__ programmed ADC channel.
776   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
777   */
778 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0)           || \
779                                                  ((__CHANNEL__) == ADC_CHANNEL_1)           || \
780                                                  ((__CHANNEL__) == ADC_CHANNEL_2)           || \
781                                                  ((__CHANNEL__) == ADC_CHANNEL_3)           || \
782                                                  ((__CHANNEL__) == ADC_CHANNEL_4)           || \
783                                                  ((__CHANNEL__) == ADC_CHANNEL_5)           || \
784                                                  ((__CHANNEL__) == ADC_CHANNEL_6)           || \
785                                                  ((__CHANNEL__) == ADC_CHANNEL_7)           || \
786                                                  ((__CHANNEL__) == ADC_CHANNEL_8)           || \
787                                                  ((__CHANNEL__) == ADC_CHANNEL_9)           || \
788                                                  ((__CHANNEL__) == ADC_CHANNEL_10)          || \
789                                                  ((__CHANNEL__) == ADC_CHANNEL_11)          || \
790                                                  ((__CHANNEL__) == ADC_CHANNEL_12)          || \
791                                                  ((__CHANNEL__) == ADC_CHANNEL_13)          || \
792                                                  ((__CHANNEL__) == ADC_CHANNEL_14)          || \
793                                                  ((__CHANNEL__) == ADC_CHANNEL_15)          || \
794                                                  ((__CHANNEL__) == ADC_CHANNEL_16)          || \
795                                                  ((__CHANNEL__) == ADC_CHANNEL_17)          || \
796                                                  ((__CHANNEL__) == ADC_CHANNEL_18)          || \
797                                                  ((__CHANNEL__) == ADC_CHANNEL_VREFINT)     || \
798                                                  ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \
799                                                  ((__CHANNEL__) == ADC_CHANNEL_VBAT)        || \
800                                                  ((__CHANNEL__) == ADC_CHANNEL_VDDCORE)       )
801 
802 /**
803   * @brief Verify the ADC channel setting in differential mode.
804   * @param __HANDLE__ ADC handle.
805   * @param __CHANNEL__ programmed ADC channel.
806   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
807   */
808 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \
809                                                       ((__CHANNEL__) == ADC_CHANNEL_2)      || \
810                                                       ((__CHANNEL__) == ADC_CHANNEL_3)      || \
811                                                       ((__CHANNEL__) == ADC_CHANNEL_4)      || \
812                                                       ((__CHANNEL__) == ADC_CHANNEL_8)      || \
813                                                       ((__CHANNEL__) == ADC_CHANNEL_10)     || \
814                                                       ((__CHANNEL__) == ADC_CHANNEL_11)     || \
815                                                       ((__CHANNEL__) == ADC_CHANNEL_12)      )
816 
817 /**
818   * @brief Verify the ADC single-ended input or differential mode setting.
819   * @param __SING_DIFF__ programmed channel setting.
820   * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
821   */
822 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
823                                                    ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
824 
825 /**
826   * @brief Verify the ADC offset management setting.
827   * @param __OFFSET_NUMBER__ ADC offset management.
828   * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
829   */
830 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
831                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
832                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
833                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
834                                                  ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
835 
836 /**
837   * @brief Verify the ADC offset sign setting.
838   * @param __OFFSET_SIGN__ ADC offset sign.
839   * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
840   */
841 #define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__)     (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
842                                                  ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE)    )
843 
844 /**
845   * @brief Verify the ADC injected channel setting.
846   * @param __CHANNEL__ programmed ADC injected channel.
847   * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
848   */
849 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
850                                            ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
851                                            ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
852                                            ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
853 
854 /**
855   * @brief Verify the ADC injected conversions external trigger.
856   * @param __INJTRIG__ programmed ADC injected conversions external trigger.
857   * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
858   */
859 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
860                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
861                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
862                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
863                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
864                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
865                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
866                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T9_CC1)      || \
867                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
868                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T12_TRGO)    || \
869                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T9_TRGO)     || \
870                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
871                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
872                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
873                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
874                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
875                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_CH2)  || \
876                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_CH2)  || \
877                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_CH1)  || \
878                                           ((__INJTRIG__) == ADC_SOFTWARE_START)                   )
879 
880 /**
881   * @brief Verify the ADC edge trigger setting for injected group.
882   * @param __EDGE__ programmed ADC edge trigger setting.
883   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
884   */
885 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
886                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
887                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
888                                             ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
889 
890 #if defined(ADC_MULTIMODE_SUPPORT)
891 /**
892   * @brief Verify the ADC multimode setting.
893   * @param __MODE__ programmed ADC multimode setting.
894   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
895   */
896 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
897                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
898                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
899                                     ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
900                                     ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
901                                     ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
902                                     ((__MODE__) == ADC_DUALMODE_INTERL)                || \
903                                     ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
904 
905 /**
906   * @brief Verify the ADC multimode DMA access setting.
907   * @param __MODE__ programmed ADC multimode DMA access setting.
908   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
909   */
910 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
911                                                ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
912                                                ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )
913 
914 /**
915   * @brief Verify the ADC multimode delay setting.
916   * @param __DELAY__ programmed ADC multimode delay setting.
917   * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
918   */
919 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
920                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
921                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
922                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
923                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
924                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
925                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
926                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
927                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
928                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
929                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
930                                           ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )
931 #endif /* ADC_MULTIMODE_SUPPORT */
932 
933 /**
934   * @brief Verify the ADC analog watchdog setting.
935   * @param __WATCHDOG__ programmed ADC analog watchdog setting.
936   * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
937   */
938 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
939                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
940                                                      ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
941 
942 /**
943   * @brief Verify the ADC analog watchdog mode setting.
944   * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
945   * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
946   */
947 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)            || \
948                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)      || \
949                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)    || \
950                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
951                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)         || \
952                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)       || \
953                                                         ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      )
954 
955 /**
956   * @brief Verify the ADC analog watchdog filtering setting.
957   * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
958   * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
959   */
960 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
961   (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE)            || \
962    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES)        || \
963    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES)        || \
964    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES)        || \
965    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES)        || \
966    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES)        || \
967    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES)        || \
968    ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES)           )
969 
970 
971 /**
972   * @brief Verify the ADC conversion (regular or injected or both).
973   * @param __CONVERSION__ ADC conversion group.
974   * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
975   */
976 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
977                                                  ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
978                                                  ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
979 
980 /**
981   * @brief Verify the ADC event type.
982   * @param __EVENT__ ADC event.
983   * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
984   */
985 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
986                                       ((__EVENT__) == ADC_AWD_EVENT)    || \
987                                       ((__EVENT__) == ADC_AWD2_EVENT)   || \
988                                       ((__EVENT__) == ADC_AWD3_EVENT)   || \
989                                       ((__EVENT__) == ADC_OVR_EVENT)    || \
990                                       ((__EVENT__) == ADC_JQOVF_EVENT)  )
991 
992 /**
993   * @brief Verify the ADC oversampling ratio.
994   * @param __RATIO__ programmed ADC oversampling ratio.
995   * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
996   */
997 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
998                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
999                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
1000                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
1001                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
1002                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
1003                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
1004                                                    ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
1005 
1006 /**
1007   * @brief Verify the ADC oversampling shift.
1008   * @param __SHIFT__ programmed ADC oversampling shift.
1009   * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
1010   */
1011 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
1012                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
1013                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
1014                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
1015                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
1016                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
1017                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
1018                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
1019                                                   ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
1020 
1021 /**
1022   * @brief Verify the ADC oversampling triggered mode.
1023   * @param __MODE__ programmed ADC oversampling triggered mode.
1024   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
1025   */
1026 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
1027                                                       ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
1028 
1029 /**
1030   * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
1031   * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
1032   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
1033   */
1034 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
1035                                                ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
1036 
1037 /**
1038   * @brief Verify the DFSDM mode configuration.
1039   * @param __HANDLE__ ADC handle.
1040   * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
1041   *      this reason, the input parameter is the ADC handle and not the configuration parameter
1042   *      directly.
1043   * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
1044   */
1045 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
1046 
1047 /**
1048   * @brief Return the DFSDM configuration mode.
1049   * @param __HANDLE__ ADC handle.
1050   * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
1051   *       For this reason, the input parameter is the ADC handle and not the configuration parameter
1052   *       directly.
1053   * @retval DFSDM configuration mode
1054   */
1055 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
1056 
1057 /**
1058   * @}
1059   */
1060 
1061 
1062 /* Exported functions --------------------------------------------------------*/
1063 /** @addtogroup ADCEx_Exported_Functions
1064   * @{
1065   */
1066 
1067 /** @addtogroup ADCEx_Exported_Functions_Group1
1068   * @{
1069   */
1070 /* IO operation functions *****************************************************/
1071 
1072 /* ADC calibration */
1073 HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
1074 uint32_t                HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
1075 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
1076                                                        uint32_t CalibrationFactor);
1077 
1078 /* Blocking mode: Polling */
1079 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
1080 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
1081 HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
1082 
1083 /* Non-blocking mode: Interruption */
1084 HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
1085 HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
1086 
1087 #if defined(ADC_MULTIMODE_SUPPORT)
1088 /* ADC multimode */
1089 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
1090 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
1091 uint32_t                HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
1092 #endif /* ADC_MULTIMODE_SUPPORT */
1093 
1094 /* ADC retrieve conversion value intended to be used with polling or interruption */
1095 uint32_t                HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
1096 
1097 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
1098 void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
1099 void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
1100 void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
1101 void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
1102 void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
1103 
1104 /* ADC group regular conversions stop */
1105 HAL_StatusTypeDef       HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
1106 HAL_StatusTypeDef       HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
1107 HAL_StatusTypeDef       HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
1108 #if defined(ADC_MULTIMODE_SUPPORT)
1109 HAL_StatusTypeDef       HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
1110 #endif /* ADC_MULTIMODE_SUPPORT */
1111 
1112 /**
1113   * @}
1114   */
1115 
1116 /** @addtogroup ADCEx_Exported_Functions_Group2
1117   * @{
1118   */
1119 /* Peripheral Control functions ***********************************************/
1120 HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
1121                                                         const ADC_InjectionConfTypeDef *pConfigInjected);
1122 #if defined(ADC_MULTIMODE_SUPPORT)
1123 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
1124                                                          const ADC_MultiModeTypeDef *pMultimode);
1125 #endif /* ADC_MULTIMODE_SUPPORT */
1126 
1127 HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
1128 HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
1129 HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
1130 HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
1131 
1132 /**
1133   * @}
1134   */
1135 
1136 /**
1137   * @}
1138   */
1139 
1140 /**
1141   * @}
1142   */
1143 
1144 /**
1145   * @}
1146   */
1147 
1148 #ifdef __cplusplus
1149 }
1150 #endif
1151 
1152 #endif /* STM32H7RSxx_HAL_ADC_EX_H */
1153