1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SBS registers
16 (+) Access to VREFBUF registers
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2023 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32H5xx_LL_SYSTEM_H
33 #define STM32H5xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32h5xx.h"
41
42 /** @addtogroup STM32H5xx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59 #define LL_SBS_HDPL_INCREMENT_VALUE 0x6AU /*!< Define used for the HDPL increment */
60 #define LL_SBS_DBG_UNLOCK (0xB4U << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< Define used to unlock debug */
61 #define LL_SBS_ACCESS_PORT_UNLOCK 0xB4U /*!< Define used to unlock access port */
62 #define LL_SBS_DBG_CONFIG_LOCK 0xC3U /*!< Define used to lock debug configuration */
63 #define LL_SBS_DBG_CONFIG_UNLOCK 0xB4U /*!< Define used to unlock debug configuration */
64 #define LL_SBS_DEBUG_SEC_NSEC 0xB4U /*!< Define used to open debug for secure and non-secure */
65 #define LL_SBS_DEBUG_NSEC 0x3CU /*!< Define used to open debug for non-secure only */
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
75 * @{
76 */
77
78 /** @defgroup SYSTEM_LL_SBS_EC_FASTMODEPLUS SBS FASTMODEPLUS
79 * @{
80 */
81 #define LL_SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
82 #define LL_SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
83 #define LL_SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
84 #if defined(SBS_PMCR_PB9_FMP)
85 #define LL_SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
86 #endif /* SBS_PMCR_PB9_FMP */
87 /**
88 * @}
89 */
90
91 /** @defgroup SYSTEM_LL_SBS_EC_CS1 SBS Vdd compensation cell Code selection
92 * @{
93 */
94 #define LL_SBS_VDD_CELL_CODE 0x0UL /*!< VDD I/Os code from the cell (available in the SBS_CCVALR) */
95 #define LL_SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< VDD I/Os code from the SBS compensation cell code register (SBS_CCSWCR) */
96 /**
97 * @}
98 */
99
100 /** @defgroup SYSTEM_LL_SBS_EC_CS2 SBS VddIO compensation cell Code selection
101 * @{
102 */
103 #define LL_SBS_VDDIO_CELL_CODE 0x0UL /*!< VDDIO I/Os code from the cell (available in the SBS_CCVALR)*/
104 #define LL_SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< VDDIO I/Os code from the SBS compensation cell code register (SBS_CCSWCR)*/
105 /**
106 * @}
107 */
108
109 #if defined(SBS_PMCR_ETH_SEL_PHY)
110 /** @defgroup SYSTEM_LL_SBS_ETHERNET_CONFIG ETHENET CONFIG
111 * @{
112 */
113 #define LL_SBS_ETH_MII 0x0UL /*!< Select the Media Independent Interface (MII) or GMII */
114 #define LL_SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */
115
116 /**
117 * @}
118 */
119 #endif /* SBS_PMCR_ETH_SEL_PHY */
120
121 /** @defgroup SYSTEM_Memories_Erase_Flag_Status Memories Erase Flags Status
122 * @{
123 */
124 #define LL_SBS_MEMORIES_ERASE_MCLR_ON_GOING 0x0UL /*!< Erase after Power-on Reset of SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs on going or cleared by SW */
125 #define LL_SBS_MEMORIES_ERASE_MCLR_ENDED SBS_MESR_MCLR /*!< Erase after Power-on Reset of SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs done */
126 #define LL_SBS_MEMORIES_ERASE_IPMEE_ON_GOING 0x0UL /*!< Erase after Power-on Reset or Tamper detection for ICACHE and PKA RAMs on going or cleared by SW */
127 #define LL_SBS_MEMORIES_ERASE_IPMEE_ENDED SBS_MESR_IPMEE /*!< Erase after Power-on Reset or Tamper detection for ICACHE and PKA RAMs done */
128 /**
129 * @}
130 */
131
132 /** @defgroup SYSTEM_LL_SBS_EC_TIMBREAK SBS TIMER BREAK
133 * @{
134 */
135 #define LL_SBS_TIMBREAK_ECC SBS_CFGR2_ECCL /*!< Enables and locks the Flash ECC double error signal
136 with Break Input of TIM1/8/15/16/17 */
137 #define LL_SBS_TIMBREAK_PVD SBS_CFGR2_PVDL /*!< Enables and locks the PVD connection
138 with TIM1/8/15/16/17 Break Input and also the PVDE
139 and PLS bits of the Power Control Interface */
140 #define LL_SBS_TIMBREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enables and locks the SRAM ECC double error signal
141 with Break Input of TIM1/8/15/16/17 */
142 #define LL_SBS_TIMBREAK_LOCKUP SBS_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of
143 Cortex-M33 with Break Input of TIM1/15/16/17 */
144 /**
145 * @}
146 */
147
148
149 /** @defgroup SYSTEM_LL_SBS_EPOCH_Selection EPOCH Selection
150 * @{
151 */
152 #define LL_SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */
153 #define LL_SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */
154 #define LL_SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */
155
156 /**
157 * @}
158 */
159
160 /** @defgroup SYSTEM_LL_SBS_NextHDPL_Selection Next HDPL Selection
161 * @{
162 */
163 #define LL_SBS_OBKHDPL_INCR_0 0x00000000U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
164 #define LL_SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
165 #define LL_SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
166 #define LL_SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
167 /**
168 * @}
169 */
170
171 /** @defgroup SYSTEM_LL_SBS_HDPL_Value HDPL Value
172 * @{
173 */
174 #define LL_SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
175 #define LL_SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */
176 #define LL_SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */
177 #define LL_SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */
178 /**
179 * @}
180 */
181
182 /** @defgroup SYSTEM_LL_SBS_NS_Lock_items Lock items
183 * @brief SBS non secure items to set lock on
184 * @{
185 */
186 #define LL_SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */
187 #define LL_SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
188 #define LL_SBS_LOCK_ALL_NSEC (LL_SBS_MPU_NSEC | LL_SBS_VTOR_NSEC) /*!< lock all Non-secure (privileged secure or non-secure only) */
189 /**
190 * @}
191 */
192
193 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
194 /** @defgroup SYSTEM_LL_SBS_S_Lock_items SBS Lock items
195 * @brief SBS secure items to set lock on
196 * @{
197 */
198 #define LL_SBS_SAU SBS_CSLCKR_LOCKSAU /*!< SAU lock (privileged secure code only) */
199 #define LL_SBS_MPU_SEC SBS_CSLCKR_LOCKSMPU /*!< Secure MPU lock (privileged secure code only) */
200 #define LL_SBS_VTOR_AIRCR_SEC SBS_CSLCKR_LOCKSVTAIRCR /*!< VTOR_S and AIRCR lock (privileged secure code only) */
201 #define LL_SBS_LOCK_ALL_SEC (LL_SBS_SAU | LL_SBS_MPU_SEC | LL_SBS_VTOR_AIRCR_SEC) /*!< lock all secure (privileged secure only) */
202 /**
203 * @}
204 */
205
206 /** @defgroup SYSTEM_LL_SBS_EC_SECURE_ATTRIBUTES Secure attributes
207 * @note Only available when system implements security (TZEN=1)
208 * @{
209 */
210 #define LL_SBS_CLOCK_SEC SBS_SECCFGR_SBSSEC /*!< SBS clock configuration secure-only access */
211 #define LL_SBS_CLOCK_NSEC 0U /*!< SBS clock configuration secure/non-secure access */
212 #define LL_SBS_CLASSB_SEC SBS_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
213 #define LL_SBS_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
214 #define LL_SBS_FPU_SEC SBS_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
215 #define LL_SBS_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
216 /**
217 * @}
218 */
219 #endif /* __ARM_FEATURE_CMSE */
220
221 /** @defgroup SYSTEM_LL_DBGMCU_EC_TRACE DBGMCU TRACE Pin Assignment
222 * @{
223 */
224 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
225 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
226 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
227 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
228 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
229 /**
230 * @}
231 */
232
233 /** @defgroup SYSTEM_LL_DBGMCU_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
234 * @{
235 */
236 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
237 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
238 #if defined(TIM4)
239 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
240 #endif /* TIM4 */
241 #if defined(TIM5)
242 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
243 #endif /* TIM5 */
244 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
245 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
246 #if defined(TIM12)
247 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1FZR1_DBG_TIM12_STOP /*!< The counter clock of TIM12 is stopped when the core is halted*/
248 #endif /* TIM12 */
249 #if defined(TIM13)
250 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1FZR1_DBG_TIM13_STOP /*!< The counter clock of TIM13 is stopped when the core is halted*/
251 #endif /* TIM13 */
252 #if defined(TIM14)
253 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1FZR1_DBG_TIM14_STOP /*!< The counter clock of TIM14 is stopped when the core is halted*/
254 #endif /* TIM14 */
255 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
256 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
257 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
258 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
259 #define LL_DBGMCU_APB1_GRP1_I3C1_STOP DBGMCU_APB1FZR1_DBG_I3C1_STOP /*!< The I3C1 SMBus timeout is frozen*/
260 /**
261 * @}
262 */
263
264 /** @defgroup SYSTEM_LL_DBGMCU_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
265 * @{
266 */
267 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
268 /**
269 * @}
270 */
271
272 /** @defgroup SYSTEM_LL_DBGMCU_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
273 * @{
274 */
275 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
276 #if defined(TIM8)
277 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
278 #endif /* TIM8 */
279 #if defined(TIM15)
280 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
281 #endif /* TIM15 */
282 #if defined(TIM16)
283 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
284 #endif /* TIM16 */
285 #if defined(TIM17)
286 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
287 #endif /* TIM17 */
288 /**
289 * @}
290 */
291
292 /** @defgroup SYSTEM_LL_DBGMCU_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
293 * @{
294 */
295 #if defined(I2C3)
296 #define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/
297 #endif /* I2C3 */
298 #if defined(I2C4)
299 #define LL_DBGMCU_APB3_GRP1_I2C4_STOP DBGMCU_APB3FZR_DBG_I2C4_STOP /*!< The counter clock of I2C4 is stopped when the core is halted*/
300 #endif /* I2C4 */
301 #if defined(I3C2)
302 #define LL_DBGMCU_APB3_GRP1_I3C2_STOP DBGMCU_APB3FZR_DBG_I3C2_STOP /*!< The counter clock of I3C2 is stopped when the core is halted*/
303 #endif /* I3C2 */
304 #define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
305 #if defined(LPTIM3)
306 #define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/
307 #endif /* LPTIM3 */
308 #if defined(LPTIM4)
309 #define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
310 #endif /* LPTIM4 */
311 #if defined(LPTIM5)
312 #define LL_DBGMCU_APB3_GRP1_LPTIM5_STOP DBGMCU_APB3FZR_DBG_LPTIM5_STOP /*!< The counter clock of LPTIM5 is stopped when the core is halted*/
313 #endif /* LPTIM5 */
314 #if defined(LPTIM6)
315 #define LL_DBGMCU_APB3_GRP1_LPTIM6_STOP DBGMCU_APB3FZR_DBG_LPTIM6_STOP /*!< The counter clock of LPTIM6 is stopped when the core is halted*/
316 #endif /* LPTIM6 */
317 #define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/
318 /**
319 * @}
320 */
321
322
323 #if defined(VREFBUF)
324 /** @defgroup SYSTEM_LL_VREFBUF_EC_VOLTAGE VREFBUF VOLTAGE
325 * @{
326 */
327 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
328 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
329 #define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */
330 #define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */
331 /**
332 * @}
333 */
334 #endif /* VREFBUF */
335
336 /** @defgroup SYSTEM_LL_FLASH_EC_LATENCY FLASH LATENCY
337 * @{
338 */
339 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */
340 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */
341 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */
342 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */
343 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */
344 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */
345 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
346 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
347 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
348 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
349 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
350 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
351 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
352 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
353 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
354 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
355 /**
356 * @}
357 */
358
359 /**
360 * @}
361 */
362
363 /* Exported macro ------------------------------------------------------------*/
364
365 /* Exported functions --------------------------------------------------------*/
366 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
367 * @{
368 */
369
370 /** @defgroup SYSTEM_LL_EF_SBS SBS
371 * @{
372 */
373
374 #if defined(SBS_PMCR_ETH_SEL_PHY)
375 /**
376 * @brief Select Ethernet PHY interface
377 * @rmtoll PMCR EPIS_SEL LL_SBS_SetPHYInterface
378 * @param Interface This parameter can be one of the following values:
379 * @arg @ref LL_SBS_ETH_MII
380 * @arg @ref LL_SBS_ETH_RMII
381 * @retval None
382 */
LL_SBS_SetPHYInterface(uint32_t Interface)383 __STATIC_INLINE void LL_SBS_SetPHYInterface(uint32_t Interface)
384 {
385 MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, Interface);
386 }
387
388 /**
389 * @brief Get Ethernet PHY interface
390 * @rmtoll PMCR EPIS_SEL LL_SBS_GetPHYInterface
391 * @retval Returned value can be one of the following values:
392 * @arg @ref LL_SBS_ETH_MII
393 * @arg @ref LL_SBS_ETH_RMII
394 */
LL_SBS_GetPHYInterface(void)395 __STATIC_INLINE uint32_t LL_SBS_GetPHYInterface(void)
396 {
397 return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY));
398 }
399 #endif /* SBS_PMCR_ETH_SEL_PHY */
400
401 /**
402 * @brief Enable the fast mode plus driving capability.
403 * @rmtoll PMCR PBx_FMP LL_SBS_EnableFastModePlus\n
404 * PMCR PBx_FMP LL_SBS_EnableFastModePlus
405 * @param ConfigFastModePlus This parameter can be a combination of the following values:
406 * @arg @ref LL_SBS_FASTMODEPLUS_PB6
407 * @arg @ref LL_SBS_FASTMODEPLUS_PB7
408 * @arg @ref LL_SBS_FASTMODEPLUS_PB8
409 * @arg @ref LL_SBS_FASTMODEPLUS_PB9
410 * @retval None
411 */
LL_SBS_EnableFastModePlus(uint32_t ConfigFastModePlus)412 __STATIC_INLINE void LL_SBS_EnableFastModePlus(uint32_t ConfigFastModePlus)
413 {
414 SET_BIT(SBS->PMCR, ConfigFastModePlus);
415 }
416
417 /**
418 * @brief Disable the fast mode plus driving capability.
419 * @rmtoll PMCR PBx_FMP LL_SBS_DisableFastModePlus\n
420 * PMCR PBx_FMP LL_SBS_DisableFastModePlus
421 * @param ConfigFastModePlus This parameter can be a combination of the following values:
422 * @arg @ref LL_SBS_FASTMODEPLUS_PB6
423 * @arg @ref LL_SBS_FASTMODEPLUS_PB7
424 * @arg @ref LL_SBS_FASTMODEPLUS_PB8
425 * @arg @ref LL_SBS_FASTMODEPLUS_PB9
426 * @retval None
427 */
LL_SBS_DisableFastModePlus(uint32_t ConfigFastModePlus)428 __STATIC_INLINE void LL_SBS_DisableFastModePlus(uint32_t ConfigFastModePlus)
429 {
430 CLEAR_BIT(SBS->PMCR, ConfigFastModePlus);
431 }
432
433 /**
434 * @brief Enable Floating Point Unit Invalid operation Interrupt
435 * @rmtoll FPUIMR FPU_IE_0 LL_SBS_EnableIT_FPU_IOC
436 * @retval None
437 */
LL_SBS_EnableIT_FPU_IOC(void)438 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IOC(void)
439 {
440 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0);
441 }
442
443 /**
444 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
445 * @rmtoll FPUIMR FPU_IE_1 LL_SBS_EnableIT_FPU_DZC
446 * @retval None
447 */
LL_SBS_EnableIT_FPU_DZC(void)448 __STATIC_INLINE void LL_SBS_EnableIT_FPU_DZC(void)
449 {
450 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1);
451 }
452
453 /**
454 * @brief Enable Floating Point Unit Underflow Interrupt
455 * @rmtoll FPUIMR FPU_IE_2 LL_SBS_EnableIT_FPU_UFC
456 * @retval None
457 */
LL_SBS_EnableIT_FPU_UFC(void)458 __STATIC_INLINE void LL_SBS_EnableIT_FPU_UFC(void)
459 {
460 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2);
461 }
462
463 /**
464 * @brief Enable Floating Point Unit Overflow Interrupt
465 * @rmtoll FPUIMR FPU_IE_3 LL_SBS_EnableIT_FPU_OFC
466 * @retval None
467 */
LL_SBS_EnableIT_FPU_OFC(void)468 __STATIC_INLINE void LL_SBS_EnableIT_FPU_OFC(void)
469 {
470 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3);
471 }
472
473 /**
474 * @brief Enable Floating Point Unit Input denormal Interrupt
475 * @rmtoll FPUIMR FPU_IE_4 LL_SBS_EnableIT_FPU_IDC
476 * @retval None
477 */
LL_SBS_EnableIT_FPU_IDC(void)478 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IDC(void)
479 {
480 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4);
481 }
482
483 /**
484 * @brief Enable Floating Point Unit Inexact Interrupt
485 * @rmtoll FPUIMR FPU_IE_5 LL_SBS_EnableIT_FPU_IXC
486 * @retval None
487 */
LL_SBS_EnableIT_FPU_IXC(void)488 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IXC(void)
489 {
490 SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5);
491 }
492
493 /**
494 * @brief Disable Floating Point Unit Invalid operation Interrupt
495 * @rmtoll FPUIMR FPU_IE_0 LL_SBS_DisableIT_FPU_IOC
496 * @retval None
497 */
LL_SBS_DisableIT_FPU_IOC(void)498 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IOC(void)
499 {
500 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0);
501 }
502
503 /**
504 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
505 * @rmtoll FPUIMR FPU_IE_1 LL_SBS_DisableIT_FPU_DZC
506 * @retval None
507 */
LL_SBS_DisableIT_FPU_DZC(void)508 __STATIC_INLINE void LL_SBS_DisableIT_FPU_DZC(void)
509 {
510 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1);
511 }
512
513 /**
514 * @brief Disable Floating Point Unit Underflow Interrupt
515 * @rmtoll FPUIMR FPU_IE_2 LL_SBS_DisableIT_FPU_UFC
516 * @retval None
517 */
LL_SBS_DisableIT_FPU_UFC(void)518 __STATIC_INLINE void LL_SBS_DisableIT_FPU_UFC(void)
519 {
520 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2);
521 }
522
523 /**
524 * @brief Disable Floating Point Unit Overflow Interrupt
525 * @rmtoll FPUIMR FPU_IE_3 LL_SBS_DisableIT_FPU_OFC
526 * @retval None
527 */
LL_SBS_DisableIT_FPU_OFC(void)528 __STATIC_INLINE void LL_SBS_DisableIT_FPU_OFC(void)
529 {
530 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3);
531 }
532
533 /**
534 * @brief Disable Floating Point Unit Input denormal Interrupt
535 * @rmtoll FPUIMR FPU_IE_4 LL_SBS_DisableIT_FPU_IDC
536 * @retval None
537 */
LL_SBS_DisableIT_FPU_IDC(void)538 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IDC(void)
539 {
540 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4);
541 }
542
543 /**
544 * @brief Disable Floating Point Unit Inexact Interrupt
545 * @rmtoll FPUIMR FPU_IE_5 LL_SBS_DisableIT_FPU_IXC
546 * @retval None
547 */
LL_SBS_DisableIT_FPU_IXC(void)548 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IXC(void)
549 {
550 CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5);
551 }
552
553 /**
554 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
555 * @rmtoll FPUIMR FPU_IE_0 LL_SBS_IsEnabledIT_FPU_IOC
556 * @retval State of bit (1 or 0).
557 */
LL_SBS_IsEnabledIT_FPU_IOC(void)558 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IOC(void)
559 {
560 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0) == SBS_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
565 * @rmtoll FPUIMR FPU_IE_1 LL_SBS_IsEnabledIT_FPU_DZC
566 * @retval State of bit (1 or 0).
567 */
LL_SBS_IsEnabledIT_FPU_DZC(void)568 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_DZC(void)
569 {
570 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1) == SBS_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
571 }
572
573 /**
574 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
575 * @rmtoll FPUIMR FPU_IE_2 LL_SBS_IsEnabledIT_FPU_UFC
576 * @retval State of bit (1 or 0).
577 */
LL_SBS_IsEnabledIT_FPU_UFC(void)578 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_UFC(void)
579 {
580 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2) == SBS_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
585 * @rmtoll FPUIMR FPU_IE_3 LL_SBS_IsEnabledIT_FPU_OFC
586 * @retval State of bit (1 or 0).
587 */
LL_SBS_IsEnabledIT_FPU_OFC(void)588 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_OFC(void)
589 {
590 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3) == SBS_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
591 }
592
593 /**
594 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
595 * @rmtoll FPUIMR FPU_IE_4 LL_SBS_IsEnabledIT_FPU_IDC
596 * @retval State of bit (1 or 0).
597 */
LL_SBS_IsEnabledIT_FPU_IDC(void)598 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IDC(void)
599 {
600 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4) == SBS_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
601 }
602
603 /**
604 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
605 * @rmtoll FPUIMR FPU_IE_5 LL_SBS_IsEnabledIT_FPU_IXC
606 * @retval State of bit (1 or 0).
607 */
LL_SBS_IsEnabledIT_FPU_IXC(void)608 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IXC(void)
609 {
610 return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5) == SBS_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
611 }
612
613 /**
614 * @brief Set connections to TIM1/8/15/16/17 Break inputs
615 * @rmtoll CFGR2 CLL LL_SBS_SetTIMBreakInputs\n
616 * CFGR2 SEL LL_SBS_SetTIMBreakInputs\n
617 * CFGR2 PVDL LL_SBS_SetTIMBreakInputs\n
618 * CFGR2 ECCL LL_SBS_SetTIMBreakInputs
619 * @param Break This parameter can be a combination of the following values:
620 * where non selected TIMBREAK input is disconnected.
621 * @arg @ref LL_SBS_TIMBREAK_ECC
622 * @arg @ref LL_SBS_TIMBREAK_PVD
623 * @arg @ref LL_SBS_TIMBREAK_SRAM_ECC
624 * @arg @ref LL_SBS_TIMBREAK_LOCKUP
625 * @retval None
626 */
LL_SBS_SetTIMBreakInputs(uint32_t Break)627 __STATIC_INLINE void LL_SBS_SetTIMBreakInputs(uint32_t Break)
628 {
629 MODIFY_REG(SBS->CFGR2, SBS_CFGR2_CLL | SBS_CFGR2_SEL | SBS_CFGR2_PVDL | SBS_CFGR2_ECCL, Break);
630 }
631
632 /**
633 * @brief Get connections to TIM1/8/15/16/17 Break inputs
634 * @rmtoll CFGR2 CLL LL_SBS_GetTIMBreakInputs\n
635 * CFGR2 SEL LL_SBS_GetTIMBreakInputs\n
636 * CFGR2 PVDL LL_SBS_GetTIMBreakInputs\n
637 * CFGR2 ECCL LL_SBS_GetTIMBreakInputs
638 * @retval Returned value can be a combination of the following values:
639 * @arg @ref LL_SBS_TIMBREAK_ECC
640 * @arg @ref LL_SBS_TIMBREAK_PVD
641 * @arg @ref LL_SBS_TIMBREAK_SRAM_ECC
642 * @arg @ref LL_SBS_TIMBREAK_LOCKUP
643 */
LL_SBS_GetTIMBreakInputs(void)644 __STATIC_INLINE uint32_t LL_SBS_GetTIMBreakInputs(void)
645 {
646 return (uint32_t)(READ_BIT(SBS->CFGR2, SBS_CFGR2_CLL | SBS_CFGR2_SEL | SBS_CFGR2_PVDL | SBS_CFGR2_ECCL));
647 }
648
649 #if defined(SBS_EPOCHSELCR_EPOCH_SEL)
650 /**
651 * @brief Select EPOCH security sent to SAES IP to encrypt/decrypt keys
652 * @rmtoll EPOCHSELCR EPOCH_SEL LL_SBS_EPOCHSelection
653 * @param Epoch_Selection: Select EPOCH security
654 * This parameter can be one of the following values:
655 * @arg LL_SBS_EPOCH_SEL_SECURE : EPOCH secure selected.
656 * @arg LL_SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected.
657 * @arg LL_SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check.
658 * @retval None
659 */
LL_SBS_EPOCHSelection(uint32_t Epoch_Selection)660 __STATIC_INLINE void LL_SBS_EPOCHSelection(uint32_t Epoch_Selection)
661 {
662 MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection));
663 }
664
665 /**
666 * @brief Get EPOCH security selection
667 * @rmtoll EPOCHSELCR EPOCH_SEL LL_SBS_GetEPOCHSelection
668 * @retval Returned value can be one of the following values:
669 * @arg LL_SBS_EPOCH_SEL_SECURE : EPOCH secure selected.
670 * @arg LL_SBS_EPOCH_SEL_NONSECURE : EPOCH non secure selected.
671 * @arg LL_SBS_EPOCH_SEL_PUFCHECK : EPOCH all zeros for PUF integrity check.
672 */
LL_SBS_GetEPOCHSelection(void)673 __STATIC_INLINE uint32_t LL_SBS_GetEPOCHSelection(void)
674 {
675 return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL));
676 }
677 #endif /* SBS_EPOCHSELCR_EPOCH_SEL */
678
679 /**
680 * @brief Disable the NMI in case of double ECC error in FLASH Interface.
681 * @rmtoll ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_DisableECCNMI
682 * @retval None
683 */
LL_SBS_FLASH_DisableECCNMI(void)684 __STATIC_INLINE void LL_SBS_FLASH_DisableECCNMI(void)
685 {
686 SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN);
687 }
688
689 /**
690 * @brief Enable the NMI in case of double ECC error in FLASH Interface.
691 * @rmtoll ECCNMIR SBS_ECCNMIR_ECCNMI_MASK_EN LL_SBS_FLASH_EnableECCNMI
692 * @retval None
693 */
LL_SBS_FLASH_EnableECCNMI(void)694 __STATIC_INLINE void LL_SBS_FLASH_EnableECCNMI(void)
695 {
696 CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN);
697 }
698
699 /** @defgroup SYSTEM_LL_SBS_EF_HDPL_Management HDPL Management
700 * @{
701 */
702
703 /**
704 * @brief Increment by 1 the HDPL value
705 * @rmtoll HDPLCR HDPL_INCR LL_SBS_IncrementHDPLValue
706 * @retval None
707 */
LL_SBS_IncrementHDPLValue(void)708 __STATIC_INLINE void LL_SBS_IncrementHDPLValue(void)
709 {
710 MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE);
711 }
712
713 /**
714 * @brief Get the HDPL Value.
715 * @rmtoll HDPLSR HDPL LL_SBS_GetHDPLValue
716 * @retval Returns the HDPL value
717 * This return value can be one of the following values:
718 * @arg LL_SBS_HDPL_VALUE_0: HDPL0
719 * @arg LL_SBS_HDPL_VALUE_1: HDPL1
720 * @arg LL_SBS_HDPL_VALUE_2: HDPL2
721 * @arg LL_SBS_HDPL_VALUE_3: HDPL3
722 */
LL_SBS_GetHDPLValue(void)723 __STATIC_INLINE uint32_t LL_SBS_GetHDPLValue(void)
724 {
725 return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL));
726 }
727
728 #if defined(SBS_NEXTHDPLCR_NEXTHDPL)
729 /**
730 * @brief Set the OBK-HDPL Value.
731 * @rmtoll NEXTHDPLCR NEXTHDPL LL_SBS_SetOBKHDPL
732 * @param OBKHDPL_Value Value of increment to add to HDPL value to generate the OBK-HDPL.
733 * This parameter can be one of the following values:
734 * @arg LL_SBS_OBKHDPL_INCR_0 : HDPL
735 * @arg LL_SBS_OBKHDPL_INCR_1 : HDPL + 1
736 * @arg LL_SBS_OBKHDPL_INCR_2 : HDPL + 2
737 * @arg LL_SBS_OBKHDPL_INCR_3 : HDPL + 3
738 * @retval None
739 */
LL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value)740 __STATIC_INLINE void LL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value)
741 {
742 MODIFY_REG(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL, (uint32_t)(OBKHDPL_Value));
743 }
744
745 /**
746 * @brief Get the OBK-HDPL Value.
747 * @rmtoll NEXTHDPLCR NEXTHDPL LL_SBS_GetOBKHDPL
748 * @retval Returns the incremement to add to HDPL value to generate OBK-HDPL
749 * This return value can be one of the following values:
750 * @arg LL_SBS_OBKHDPL_INCR_0: HDPL
751 * @arg LL_SBS_OBKHDPL_INCR_1: HDPL + 1
752 * @arg LL_SBS_OBKHDPL_INCR_2: HDPL + 2
753 * @arg LL_SBS_OBKHDPL_INCR_3: HDPL + 3
754 */
LL_SBS_GetOBKHDPL(void)755 __STATIC_INLINE uint32_t LL_SBS_GetOBKHDPL(void)
756 {
757 return (uint32_t)(READ_BIT(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL));
758 }
759 #endif /* SBS_NEXTHDPLCR_NEXTHDPL */
760
761 /**
762 * @}
763 */
764
765 /** @defgroup SYSTEM_LL_SBS_EF_Debug_Control Debug Control
766 * @{
767 */
768
769 /**
770 * @brief Set the authenticated debug hide protection level
771 * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_SetAuthDbgHDPL
772 * @param Level This parameter can be one of the following values:
773 * @arg @ref LL_SBS_HDPL_VALUE_1
774 * @arg @ref LL_SBS_HDPL_VALUE_2
775 * @arg @ref LL_SBS_HDPL_VALUE_3
776 * @retval None
777 */
LL_SBS_SetAuthDbgHDPL(uint32_t Level)778 __STATIC_INLINE void LL_SBS_SetAuthDbgHDPL(uint32_t Level)
779 {
780 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos));
781 }
782
783 /**
784 * @brief Get current hide protection level
785 * @rmtoll SBS_DBGCR DBG_AUTH_HDPL LL_SBS_GetAuthDbgHDPL
786 * @retval Returned value is the hide protection level where the authenticated debug is opened:
787 * @arg @ref LL_SBS_HDPL_VALUE_1
788 * @arg @ref LL_SBS_HDPL_VALUE_2
789 * @arg @ref LL_SBS_HDPL_VALUE_3
790 */
LL_SBS_GetAuthDbgHDPL(void)791 __STATIC_INLINE uint32_t LL_SBS_GetAuthDbgHDPL(void)
792 {
793 return (uint32_t)(READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos);
794 }
795
796 #if defined(SBS_DBGCR_DBG_AUTH_SEC)
797 /**
798 * @brief Configure the authenticated debug security access.
799 * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_SetAuthDbgSec
800 * @param Control debug opening secure/non-secure or non-secure only
801 * This parameter can be one of the following values:
802 * @arg LL_SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure.
803 * @arg LL_SBS_DEBUG_NSEC: debug opening for non-secure only.
804 * @retval None
805 */
LL_SBS_SetAuthDbgSec(uint32_t Security)806 __STATIC_INLINE void LL_SBS_SetAuthDbgSec(uint32_t Security)
807 {
808 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos));
809 }
810
811 /**
812 * @brief Get the current value of the hide protection level.
813 * @rmtoll SBS_DBGCR DBG_AUTH_SEC LL_SBS_GetAuthDbgSec
814 * @note This function can be only used when device state is Closed.
815 * @retval Returned value can be one of the following values:
816 * @arg SBS_DEBUG_SEC_NSEC: debug opening for secure and non-secure.
817 * @arg any other value: debug opening for non-secure only.
818 */
LL_SBS_GetAuthDbgSec(void)819 __STATIC_INLINE uint32_t LL_SBS_GetAuthDbgSec(void)
820 {
821 return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos);
822 }
823 #endif /* SBS_DBGCR_DBG_AUTH_SEC */
824
825 /**
826 * @brief Unlock the debug
827 * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_UnlockDebug
828 * @retval None
829 */
LL_SBS_UnlockDebug(void)830 __STATIC_INLINE void LL_SBS_UnlockDebug(void)
831 {
832 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, LL_SBS_DBG_UNLOCK);
833 }
834
835 /**
836 * @brief Check if the debug is unlocked
837 * @rmtoll SBS_DBGCR DBG_UNLOCK LL_SBS_IsUnlockedDebug
838 * @retval State of bit (1 or 0).
839 */
LL_SBS_IsUnlockedDebug(void)840 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebug(void)
841 {
842 return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK) == LL_SBS_DBG_UNLOCK) ? 1UL : 0UL);
843 }
844
845 /**
846 * @brief Unlock the access port
847 * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_UnlockAccessPort
848 * @retval None
849 */
LL_SBS_UnlockAccessPort(void)850 __STATIC_INLINE void LL_SBS_UnlockAccessPort(void)
851 {
852 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, LL_SBS_ACCESS_PORT_UNLOCK);
853 }
854
855 /**
856 * @brief Check if the access port is unlocked
857 * @rmtoll SBS_DBGCR AP_UNLOCK LL_SBS_IsUnlockedAccessPort
858 * @retval State of bit (1 or 0).
859 */
LL_SBS_IsUnlockedAccessPort(void)860 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedAccessPort(void)
861 {
862 return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK) == LL_SBS_ACCESS_PORT_UNLOCK) ? 1UL : 0UL);
863 }
864
865 /**
866 * @brief Lock the debug configuration
867 * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_LockDebugConfig
868 * @retval None
869 */
LL_SBS_LockDebugConfig(void)870 __STATIC_INLINE void LL_SBS_LockDebugConfig(void)
871 {
872 MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_LOCK);
873 }
874
875 /**
876 * @brief Check if the debug configuration is locked
877 * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK LL_SBS_IsLockedDebugConfig
878 * @retval State of bit (1 or 0).
879 */
LL_SBS_IsLockedDebugConfig(void)880 __STATIC_INLINE uint32_t LL_SBS_IsLockedDebugConfig(void)
881 {
882 return ((READ_BIT(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK) != LL_SBS_DBG_CONFIG_UNLOCK) ? 1UL : 0UL);
883 }
884
885 /**
886 * @}
887 */
888
889 /** @defgroup SYSTEM_LL_SBS_EF_lock_Management lock Management
890 * @{
891 */
892
893 /**
894 * @brief Non-secure Lock of SBS item(s).
895 * @note Setting lock(s) depends on privilege mode in secure/non-secure code
896 * Lock(s) cleared only at system reset
897 * @rmtoll CNSLCKR LOCKNSVTOR LL_SBS_NonSecureLock\n
898 * CNSLCKR LOCKNSMPU LL_SBS_NonSecureLock
899 * @param Item Item(s) to set lock on.
900 * This parameter can be one of the following values :
901 * @arg LL_SBS_VTOR_NSEC : VTOR_NS register lock
902 * @arg LL_SBS_MPU_NSEC : Non-secure MPU registers lock
903 * @arg LL_SBS_LOCK_ALL_NSEC : Non-secure MPU and VTOR_NS lock
904 * @retval None
905 */
LL_SBS_NonSecureLock(uint32_t Item)906 __STATIC_INLINE void LL_SBS_NonSecureLock(uint32_t Item)
907 {
908 /* Privilege secure/non-secure locks */
909 SBS->CNSLCKR = Item;
910 }
911
912 /**
913 * @brief Get the non secure lock state of SBS items.
914 * @note Getting lock(s) depends on privilege mode in secure/non-secure code
915 * @rmtoll CNSLCKR LOCKNSVTOR LL_SBS_NonSecureLock\n
916 * CNSLCKR LOCKNSMPU LL_SBS_NonSecureLock
917 * @retval the return value can be one of the following values :
918 * @arg LL_SBS_VTOR_NSEC : VTOR_NS register lock
919 * @arg LL_SBS_MPU_NSEC : Non-secure MPU registers lock
920 * @arg LL_SBS_LOCK_ALL_NSEC : VTOR_NS and Non-secure MPU registers lock
921 */
LL_SBS_GetNonSecureLock(void)922 __STATIC_INLINE uint32_t LL_SBS_GetNonSecureLock(void)
923 {
924 return (uint32_t)(READ_BIT(SBS->CNSLCKR, LL_SBS_LOCK_ALL_NSEC));
925 }
926
927 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
928 /**
929 * @brief Secure Lock of System item(s).
930 * @note Setting lock(s) depends on privilege mode in secure code
931 * Lock(s) cleared only at system reset
932 * @rmtoll CSLCKR LOCKSVTAIRCR LL_SBS_SecureLock\n
933 * CSLCKR LOCKSMPU LL_SBS_SecureLock\n
934 * CSLCKR LOCKSAU LL_SBS_SecureLock
935 * @param Item Item(s) to set lock on.
936 * This parameter can be a combination of the following values :
937 * @arg LL_SBS_VTOR_AIRCR_SEC : VTOR_S and AIRCR registers lock
938 * @arg LL_SBS_MPU_SEC : Secure MPU registers lock
939 * @arg LL_SBS_SAU : SAU registers lock
940 * @arg LL_SBS_LOCK_ALL_SEC : VTOR_S, AIRCR, Secure MPU and SAU registers lock
941 * @retval None
942 */
LL_SBS_SecureLock(uint32_t Item)943 __STATIC_INLINE void LL_SBS_SecureLock(uint32_t Item)
944 {
945 /* Privilege secure only locks */
946 SBS->CSLCKR = Item;
947 }
948
949 /**
950 * @brief Get the secure lock state of System items.
951 * @note Getting lock(s) depends on privilege mode in secure code
952 * @rmtoll CSLCKR LOCKSVTAIRCR LL_SBS_GetSecureLock\n
953 * CSLCKR LOCKSMPU LL_SBS_GetSecureLock\n
954 * CSLCKR LOCKSAU LL_SBS_GetSecureLock
955 * @retval the return value is a combination of the following values :
956 * @arg LL_SBS_VTOR_AIRCR_SEC : VTOR_S and AIRCR registers lock
957 * @arg LL_SBS_MPU_SEC : Secure MPU registers lock
958 * @arg LL_SBS_SAU : SAU registers lock
959 * @arg LL_SBS_LOCK_ALL_SEC : VTOR_S, AIRCR, Secure MPU and SAU registers lock
960 */
LL_SBS_GetSecureLock(void)961 __STATIC_INLINE uint32_t LL_SBS_GetSecureLock(void)
962 {
963 return (uint32_t)(READ_BIT(SBS->CSLCKR, LL_SBS_LOCK_ALL_SEC));
964 }
965 #endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */
966
967 /**
968 * @}
969 */
970
971 /** @defgroup SYSTEM_LL_SBS_EF_Secure_Management Secure Management
972 * @{
973 */
974
975 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
976 /**
977 * @brief Configure Secure mode
978 * @note Only available from secure state when system implements security (TZEN=1)
979 * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n
980 * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n
981 * SECCFGR FPUSEC LL_SBS_ConfigSecure
982 * @param Configuration This parameter shall be the full combination
983 * of the following values:
984 * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC
985 * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC
986 * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC
987 * @retval None
988 */
LL_SBS_ConfigSecure(uint32_t Configuration)989 __STATIC_INLINE void LL_SBS_ConfigSecure(uint32_t Configuration)
990 {
991 WRITE_REG(SBS->SECCFGR, Configuration);
992 }
993
994 /**
995 * @brief Get Secure mode configuration
996 * @note Only available when system implements security (TZEN=1)
997 * @rmtoll SECCFGR SBSSEC LL_SBS_ConfigSecure\n
998 * SECCFGR CLASSBSEC LL_SBS_ConfigSecure\n
999 * SECCFGR FPUSEC LL_SBS_ConfigSecure
1000 * @retval Returned value is the combination of the following values:
1001 * @arg @ref LL_SBS_CLOCK_SEC or LL_SBS_CLOCK_NSEC
1002 * @arg @ref LL_SBS_CLASSB_SEC or LL_SBS_CLASSB_NSEC
1003 * @arg @ref LL_SBS_FPU_SEC or LL_SBS_FPU_NSEC
1004 */
LL_SBS_GetConfigSecure(void)1005 __STATIC_INLINE uint32_t LL_SBS_GetConfigSecure(void)
1006 {
1007 return (uint32_t)(READ_BIT(SBS->SECCFGR, LL_SBS_CLOCK_SEC | LL_SBS_CLASSB_SEC | LL_SBS_FPU_SEC));
1008 }
1009 #endif /* __ARM_FEATURE_CMSE && __ARM_FEATURE_CMSE == 3U */
1010
1011 /**
1012 * @}
1013 */
1014
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup SYSTEM_LL_SBS_EF_COMPENSATION Compensation Cell Control
1020 * @{
1021 */
1022
1023 /**
1024 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD
1025 * @rmtoll CCVALR APSRC1 LL_SBS_GetPMOSVddCompensationValue
1026 * @retval Returned value is the PMOS compensation cell
1027 */
LL_SBS_GetPMOSVddCompensationValue(void)1028 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationValue(void)
1029 {
1030 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1));
1031 }
1032
1033 /**
1034 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD
1035 * @rmtoll CCVALR ANSRC1 LL_SBS_GetNMOSVddCompensationValue
1036 * @retval Returned value is the NMOS compensation cell
1037 */
LL_SBS_GetNMOSVddCompensationValue(void)1038 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationValue(void)
1039 {
1040 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1));
1041 }
1042
1043 /**
1044 * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2
1045 * @rmtoll CCVALR APSRC2 LL_SBS_GetPMOSVddIO2CompensationValue
1046 * @retval Returned value is the PMOS compensation cell
1047 */
LL_SBS_GetPMOSVddIO2CompensationValue(void)1048 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIO2CompensationValue(void)
1049 {
1050 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC2));
1051 }
1052
1053 /**
1054 * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2
1055 * @rmtoll CCVALR ANSRC2 LL_SBS_GetNMOSVddIO2CompensationValue
1056 * @retval Returned value is the NMOS compensation cell
1057 */
LL_SBS_GetNMOSVddIO2CompensationValue(void)1058 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIO2CompensationValue(void)
1059 {
1060 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC2));
1061 }
1062
1063 /**
1064 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD
1065 * @rmtoll CCSWCR SW_APSRC1 LL_SBS_SetPMOSVddCompensationCode
1066 * @param PMOSCode PMOS compensation code
1067 * This code is applied to the PMOS compensation cell when the CS1 bit of the
1068 * SBS_CCCSR is set
1069 * @retval None
1070 */
LL_SBS_SetPMOSVddCompensationCode(uint32_t PMOSCode)1071 __STATIC_INLINE void LL_SBS_SetPMOSVddCompensationCode(uint32_t PMOSCode)
1072 {
1073 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1, PMOSCode << SBS_CCSWCR_SW_APSRC1_Pos);
1074 }
1075
1076 /**
1077 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD
1078 * @rmtoll CCSWCR SW_APSRC1 LL_SBS_GetPMOSVddCompensationCode
1079 * @retval Returned value is the PMOS compensation cell
1080 */
LL_SBS_GetPMOSVddCompensationCode(void)1081 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddCompensationCode(void)
1082 {
1083 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC1));
1084 }
1085
1086 /**
1087 * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO
1088 * @rmtoll CCSWCR SW_APSRC2 LL_SBS_SetPMOSVddIOCompensationCode
1089 * @param PMOSCode PMOS compensation code
1090 * This code is applied to the PMOS compensation cell when the CS2 bit of the
1091 * SBS_CCCSR is set
1092 * @retval None
1093 */
LL_SBS_SetPMOSVddIOCompensationCode(uint32_t PMOSCode)1094 __STATIC_INLINE void LL_SBS_SetPMOSVddIOCompensationCode(uint32_t PMOSCode)
1095 {
1096 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2, PMOSCode << SBS_CCSWCR_SW_APSRC2_Pos);
1097 }
1098
1099 /**
1100 * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO
1101 * @rmtoll CCSWCR SW_APSRC2 LL_SBS_GetPMOSVddIOCompensationCode
1102 * @retval Returned value is the PMOS compensation
1103 */
LL_SBS_GetPMOSVddIOCompensationCode(void)1104 __STATIC_INLINE uint32_t LL_SBS_GetPMOSVddIOCompensationCode(void)
1105 {
1106 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_APSRC2));
1107 }
1108
1109 /**
1110 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD
1111 * @rmtoll CCSWCR PCC2 LL_SBS_SetNMOSVddCompensationCode
1112 * @param NMOSCode NMOS compensation code
1113 * This code is applied to the NMOS compensation cell when the CS2 bit of the
1114 * SBS_CCCSR is set
1115 * @retval None
1116 */
LL_SBS_SetNMOSVddCompensationCode(uint32_t NMOSCode)1117 __STATIC_INLINE void LL_SBS_SetNMOSVddCompensationCode(uint32_t NMOSCode)
1118 {
1119 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1, NMOSCode << SBS_CCSWCR_SW_ANSRC1_Pos);
1120 }
1121
1122 /**
1123 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD
1124 * @rmtoll CCSWCR NCC1 LL_SBS_GetNMOSVddCompensationCode
1125 * @retval Returned value is the Vdd compensation cell code for NMOS transistors
1126 */
LL_SBS_GetNMOSVddCompensationCode(void)1127 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddCompensationCode(void)
1128 {
1129 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1));
1130 }
1131
1132 /**
1133 * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO
1134 * @rmtoll CCSWCR NCC2 LL_SBS_SetNMOSVddIOCompensationCode
1135 * @param NMOSCode NMOS compensation cell code
1136 * This code is applied to the NMOS compensation cell when the CS2 bit of the
1137 * SBS_CCCSR is set
1138 * @retval None
1139 */
LL_SBS_SetNMOSVddIOCompensationCode(uint32_t NMOSCode)1140 __STATIC_INLINE void LL_SBS_SetNMOSVddIOCompensationCode(uint32_t NMOSCode)
1141 {
1142 MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2, NMOSCode << SBS_CCSWCR_SW_ANSRC2_Pos);
1143 }
1144
1145
1146 /**
1147 * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO
1148 * @rmtoll CCSWCR NCC2 LL_SBS_GetNMOSVddIOCompensationCode
1149 * @retval Returned value is the NMOS compensation cell code
1150 */
LL_SBS_GetNMOSVddIOCompensationCode(void)1151 __STATIC_INLINE uint32_t LL_SBS_GetNMOSVddIOCompensationCode(void)
1152 {
1153 return (uint32_t)(READ_BIT(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2));
1154 }
1155
1156 /**
1157 * @brief Enable the Compensation Cell of GPIO supplied by VDD
1158 * @rmtoll CCCSR EN1 LL_SBS_EnableVddCompensationCell
1159 * @note The vdd compensation cell can be used only when the device supply
1160 * voltage ranges from 1.71 to 3.6 V
1161 * @retval None
1162 */
LL_SBS_EnableVddCompensationCell(void)1163 __STATIC_INLINE void LL_SBS_EnableVddCompensationCell(void)
1164 {
1165 SET_BIT(SBS->CCCSR, SBS_CCCSR_EN1);
1166 }
1167
1168 /**
1169 * @brief Enable the Compensation Cell of GPIO supplied by VDDIO
1170 * @rmtoll CCCSR EN2 LL_SBS_EnableVddIOCompensationCell
1171 * @note The Vdd I/O compensation cell can be used only when the device supply
1172 * voltage ranges from 1.08 to 3.6 V
1173 * @retval None
1174 */
LL_SBS_EnableVddIOCompensationCell(void)1175 __STATIC_INLINE void LL_SBS_EnableVddIOCompensationCell(void)
1176 {
1177 SET_BIT(SBS->CCCSR, SBS_CCCSR_EN2);
1178 }
1179
1180 /**
1181 * @brief Disable the Compensation Cell of GPIO supplied by VDD
1182 * @rmtoll CCCSR EN1 LL_SBS_DisableVddCompensationCell
1183 * @note The Vdd compensation cell can be used only when the device supply
1184 * voltage ranges from 1.71 to 3.6 V
1185 * @retval None
1186 */
LL_SBS_DisableVddCompensationCell(void)1187 __STATIC_INLINE void LL_SBS_DisableVddCompensationCell(void)
1188 {
1189 CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN1);
1190 }
1191
1192 /**
1193 * @brief Disable the Compensation Cell of GPIO supplied by VDDIO
1194 * @rmtoll CCCSR EN2 LL_SBS_DisableVddIOCompensationCell
1195 * @note The Vdd I/O compensation cell can be used only when the device supply
1196 * voltage ranges from 1.08 to 3.6 V
1197 * @retval None
1198 */
LL_SBS_DisableVddIOCompensationCell(void)1199 __STATIC_INLINE void LL_SBS_DisableVddIOCompensationCell(void)
1200 {
1201 CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN2);
1202 }
1203
1204 /**
1205 * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable
1206 * @rmtoll CCCSR EN1 LL_SBS_IsEnabled_VddCompensationCell
1207 * @retval State of bit (1 or 0).
1208 */
LL_SBS_IsEnabled_VddCompensationCell(void)1209 __STATIC_INLINE uint32_t LL_SBS_IsEnabled_VddCompensationCell(void)
1210 {
1211 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_EN1) == SBS_CCCSR_EN1) ? 1UL : 0UL);
1212 }
1213
1214 /**
1215 * @brief Check if the Compensation Cell of GPIO supplied by VDDIO is enable
1216 * @rmtoll CCCSR EN2 LL_SBS_IsEnabled_VddIOCompensationCell
1217 * @retval State of bit (1 or 0).
1218 */
LL_SBS_IsEnabled_VddIOCompensationCell(void)1219 __STATIC_INLINE uint32_t LL_SBS_IsEnabled_VddIOCompensationCell(void)
1220 {
1221 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_EN2) == SBS_CCCSR_EN2) ? 1UL : 0UL);
1222 }
1223
1224 /**
1225 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD
1226 * @rmtoll CCCSR RDY1 LL_SBS_IsActiveFlag_VddCMPCR
1227 * @retval State of bit (1 or 0).
1228 */
LL_SBS_IsActiveFlag_VddCMPCR(void)1229 __STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddCMPCR(void)
1230 {
1231 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY1) == (SBS_CCCSR_RDY1)) ? 1UL : 0UL);
1232 }
1233
1234 /**
1235 * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO
1236 * @rmtoll CCCSR RDY2 LL_SBS_IsActiveFlag_VddIOCMPCR
1237 * @retval State of bit (1 or 0).
1238 */
LL_SBS_IsActiveFlag_VddIOCMPCR(void)1239 __STATIC_INLINE uint32_t LL_SBS_IsActiveFlag_VddIOCMPCR(void)
1240 {
1241 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY2) == (SBS_CCCSR_RDY2)) ? 1UL : 0UL);
1242 }
1243
1244
1245 /**
1246 * @brief Set the compensation cell code selection of GPIO supplied by VDD
1247 * @rmtoll CCCSR CS1 LL_SBS_SetVddCellCompensationCode
1248 * @param CompCode: Selects the code to be applied for the Vdd compensation cell
1249 * This parameter can be one of the following values:
1250 * @arg LL_SBS_VDD_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR)
1251 * @arg LL_SBS_VDD_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR)
1252 * @retval None
1253 */
LL_SBS_SetVddCellCompensationCode(uint32_t CompCode)1254 __STATIC_INLINE void LL_SBS_SetVddCellCompensationCode(uint32_t CompCode)
1255 {
1256 SET_BIT(SBS->CCCSR, CompCode);
1257 }
1258
1259 /**
1260 * @brief Set the compensation cell code selection of GPIO supplied by VDDIO
1261 * @rmtoll CCCSR CS2 LL_SBS_SetVddIOCellCompensationCode
1262 * @param CompCode: Selects the code to be applied for the VddIO compensation cell
1263 * This parameter can be one of the following values:
1264 * @arg LL_SBS_VDDIO_CELL_CODE : Select Code from the cell (available in the SBS_CCVALR)
1265 * @arg LL_SBS_VDDIO_REGISTER_CODE: Select Code from the SBS compensation cell code register (SBS_CCSWCR)
1266 * @retval None
1267 */
LL_SBS_SetVddIOCellCompensationCode(uint32_t CompCode)1268 __STATIC_INLINE void LL_SBS_SetVddIOCellCompensationCode(uint32_t CompCode)
1269 {
1270 SET_BIT(SBS->CCCSR, CompCode);
1271 }
1272
1273 /**
1274 * @brief Get the compensation cell code selection of GPIO supplied by VDD
1275 * @rmtoll CCCSR CS1 LL_SBS_GetVddCellCompensationCode
1276 * @retval Returned value can be one of the following values:
1277 * @arg LL_SBS_VDD_CELL_CODE : Selected Code is from the cell (available in the SBS_CCVALR)
1278 * @arg LL_SBS_VDD_REGISTER_CODE: Selected Code is from the SBS compensation cell code register (SBS_CCSWCR)
1279 */
LL_SBS_GetVddCellCompensationCode(void)1280 __STATIC_INLINE uint32_t LL_SBS_GetVddCellCompensationCode(void)
1281 {
1282 return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_CS1));
1283 }
1284
1285 /**
1286 * @brief Get the compensation cell code selection of GPIO supplied by VDDIO
1287 * @rmtoll CCCSR CS2 LL_SBS_GetVddIOCellCompensationCode
1288 * @retval Returned value can be one of the following values:
1289 * @arg LL_SBS_VDDIO_CELL_CODE : Selected Code is from the cell (available in the SBS_CCVALR)
1290 * @arg LL_SBS_VDDIO_REGISTER_CODE: Selected Code is from the SBS compensation cell code register (SBS_CCSWCR)
1291 */
LL_SBS_GetVddIOCellCompensationCode(void)1292 __STATIC_INLINE uint32_t LL_SBS_GetVddIOCellCompensationCode(void)
1293 {
1294 return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_CS2));
1295 }
1296
1297 /**
1298 * @}
1299 */
1300
1301 /** @defgroup SYSTEM_LL_DBGMCU_EF DBGMCU
1302 * @{
1303 */
1304
1305 /**
1306 * @brief Return the device identifier
1307 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1308 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1309 */
LL_DBGMCU_GetDeviceID(void)1310 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1311 {
1312 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1313 }
1314
1315 /**
1316 * @brief Return the device revision identifier
1317 * @note This field indicates the revision of the device.
1318 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1319 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1320 */
LL_DBGMCU_GetRevisionID(void)1321 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1322 {
1323 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1324 }
1325
1326 /**
1327 * @brief Enable the Debug Module during STOP mode
1328 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1329 * @retval None
1330 */
LL_DBGMCU_EnableDBGStopMode(void)1331 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1332 {
1333 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1334 }
1335
1336 /**
1337 * @brief Disable the Debug Module during STOP mode
1338 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1339 * @retval None
1340 */
LL_DBGMCU_DisableDBGStopMode(void)1341 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1342 {
1343 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1344 }
1345
1346 /**
1347 * @brief Enable the Debug Module during STANDBY mode
1348 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1349 * @retval None
1350 */
LL_DBGMCU_EnableDBGStandbyMode(void)1351 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1352 {
1353 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1354 }
1355
1356 /**
1357 * @brief Disable the Debug Module during STANDBY mode
1358 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1359 * @retval None
1360 */
LL_DBGMCU_DisableDBGStandbyMode(void)1361 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1362 {
1363 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1364 }
1365
1366
1367 /**
1368 * @brief Enable the Debug Clock Trace
1369 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock
1370 * @retval None
1371 */
LL_DBGMCU_EnableTraceClock(void)1372 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1373 {
1374 SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1375 }
1376
1377 /**
1378 * @brief Disable the Debug Clock Trace
1379 * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock
1380 * @retval None
1381 */
LL_DBGMCU_DisableTraceClock(void)1382 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1383 {
1384 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1385 }
1386
1387
1388 /**
1389 * @brief Check if clock trace is enabled or disabled.
1390 * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock
1391 * @retval State of bit (1 or 0).
1392 */
LL_DBGMCU_IsEnabledTraceClock(void)1393 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1394 {
1395 return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL);
1396 }
1397
1398 /**
1399 * @brief Set Trace pin assignment control
1400 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1401 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1402 * @param PinAssignment This parameter can be one of the following values:
1403 * @arg @ref LL_DBGMCU_TRACE_NONE
1404 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1405 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1406 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1407 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1408 * @retval None
1409 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1410 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1411 {
1412 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1413 }
1414
1415 /**
1416 * @brief Get Trace pin assignment control
1417 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1418 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1419 * @retval Returned value can be one of the following values:
1420 * @arg @ref LL_DBGMCU_TRACE_NONE
1421 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1422 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1423 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1424 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1425 */
LL_DBGMCU_GetTracePinAssignment(void)1426 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1427 {
1428 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1429 }
1430
1431 /**
1432 * @brief Freeze APB1 peripherals (group1 peripherals)
1433 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1434 * @param Periphs This parameter can be a combination of the following values:
1435 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1436 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1437 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1438 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1439 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1440 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1441 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1442 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1443 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1444 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1445 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1446 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1447 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1448 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
1449 * @retval None
1450 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1451 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1452 {
1453 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1454 }
1455
1456 /**
1457 * @brief Freeze APB1 peripherals (group2 peripherals)
1458 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1459 * @param Periphs This parameter can be a combination of the following values:
1460 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1461 * @retval None
1462 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1463 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1464 {
1465 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1466 }
1467
1468 /**
1469 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1470 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1471 * @param Periphs This parameter can be a combination of the following values:
1472 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1473 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1474 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1475 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1476 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1477 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1478 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1479 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1480 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1481 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1482 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1483 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1484 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1485 * @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
1486 * @retval None
1487 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1488 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1489 {
1490 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1491 }
1492
1493 /**
1494 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1495 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1496 * @param Periphs This parameter can be a combination of the following values:
1497 * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1498 * @retval None
1499 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1500 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1501 {
1502 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1503 }
1504
1505 /**
1506 * @brief Freeze APB2 peripherals
1507 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1508 * @param Periphs This parameter can be a combination of the following values:
1509 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1510 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1511 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1512 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1513 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1514 * @retval None
1515 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1516 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1517 {
1518 SET_BIT(DBGMCU->APB2FZR, Periphs);
1519 }
1520
1521 /**
1522 * @brief Unfreeze APB2 peripherals
1523 * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1524 * @param Periphs This parameter can be a combination of the following values:
1525 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1526 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1527 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1528 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1529 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1530 * @retval None
1531 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1532 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1533 {
1534 CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1535 }
1536
1537 /**
1538 * @brief Freeze APB3 peripherals
1539 * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph
1540 * @param Periphs This parameter can be a combination of the following values:
1541 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1542 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP
1543 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1544 * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1545 * @retval None
1546 */
LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)1547 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
1548 {
1549 SET_BIT(DBGMCU->APB3FZR, Periphs);
1550 }
1551
1552 /**
1553 * @brief Unfreeze APB3 peripherals
1554 * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph
1555 * @param Periphs This parameter can be a combination of the following values:
1556 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1557 * @arg @ref LL_DBGMCU_APB3_GRP1_I2C4_STOP
1558 * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1559 * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1560 * @retval None
1561 */
LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)1562 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
1563 {
1564 CLEAR_BIT(DBGMCU->APB3FZR, Periphs);
1565 }
1566
1567 /**
1568 * @}
1569 */
1570
1571 #if defined(VREFBUF)
1572 /** @defgroup SYSTEM_LL_VREFBUF_EF VREFBUF
1573 * @{
1574 */
1575
1576 /**
1577 * @brief Enable Internal voltage reference
1578 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1579 * @retval None
1580 */
LL_VREFBUF_Enable(void)1581 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1582 {
1583 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1584 }
1585
1586 /**
1587 * @brief Disable Internal voltage reference
1588 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1589 * @retval None
1590 */
LL_VREFBUF_Disable(void)1591 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1592 {
1593 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1594 }
1595
1596 /**
1597 * @brief Enable high impedance (VREF+pin is high impedance)
1598 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1599 * @retval None
1600 */
LL_VREFBUF_EnableHIZ(void)1601 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1602 {
1603 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1604 }
1605
1606 /**
1607 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1608 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1609 * @retval None
1610 */
LL_VREFBUF_DisableHIZ(void)1611 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1612 {
1613 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1614 }
1615
1616 /**
1617 * @brief Set the Voltage reference scale
1618 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1619 * @param Scale This parameter can be one of the following values:
1620 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1621 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1622 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1623 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1624 * @retval None
1625 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1626 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1627 {
1628 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1629 }
1630
1631 /**
1632 * @brief Get the Voltage reference scale
1633 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1634 * @retval Returned value can be one of the following values:
1635 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1636 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1637 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1638 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1639 */
LL_VREFBUF_GetVoltageScaling(void)1640 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1641 {
1642 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1643 }
1644
1645 /**
1646 * @brief Check if Voltage reference buffer is ready
1647 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1648 * @retval State of bit (1 or 0).
1649 */
LL_VREFBUF_IsVREFReady(void)1650 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1651 {
1652 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Get the trimming code for VREFBUF calibration
1657 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1658 * @retval Between 0 and 0x3F
1659 */
LL_VREFBUF_GetTrimming(void)1660 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1661 {
1662 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1663 }
1664
1665 /**
1666 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1667 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1668 * @param Value Between 0 and 0x3F
1669 * @retval None
1670 */
LL_VREFBUF_SetTrimming(uint32_t Value)1671 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1672 {
1673 WRITE_REG(VREFBUF->CCR, Value);
1674 }
1675
1676 /**
1677 * @}
1678 */
1679 #endif /* VREFBUF */
1680
1681 /** @defgroup SYSTEM_LL_FLASH_EF FLASH
1682 * @{
1683 */
1684 /**
1685 * @brief Set FLASH Latency
1686 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1687 * @param Latency This parameter can be one of the following values:
1688 * @arg @ref LL_FLASH_LATENCY_0
1689 * @arg @ref LL_FLASH_LATENCY_1
1690 * @arg @ref LL_FLASH_LATENCY_2
1691 * @arg @ref LL_FLASH_LATENCY_3
1692 * @arg @ref LL_FLASH_LATENCY_4
1693 * @arg @ref LL_FLASH_LATENCY_5
1694 * @arg @ref LL_FLASH_LATENCY_6
1695 * @arg @ref LL_FLASH_LATENCY_7
1696 * @arg @ref LL_FLASH_LATENCY_8
1697 * @arg @ref LL_FLASH_LATENCY_9
1698 * @arg @ref LL_FLASH_LATENCY_10
1699 * @arg @ref LL_FLASH_LATENCY_11
1700 * @arg @ref LL_FLASH_LATENCY_12
1701 * @arg @ref LL_FLASH_LATENCY_13
1702 * @arg @ref LL_FLASH_LATENCY_14
1703 * @arg @ref LL_FLASH_LATENCY_15
1704 * @retval None
1705 */
LL_FLASH_SetLatency(uint32_t Latency)1706 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1707 {
1708 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1709 }
1710
1711 /**
1712 * @brief Get FLASH Latency
1713 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1714 * @retval Returned value can be one of the following values:
1715 * @arg @ref LL_FLASH_LATENCY_0
1716 * @arg @ref LL_FLASH_LATENCY_1
1717 * @arg @ref LL_FLASH_LATENCY_2
1718 * @arg @ref LL_FLASH_LATENCY_3
1719 * @arg @ref LL_FLASH_LATENCY_4
1720 * @arg @ref LL_FLASH_LATENCY_5
1721 * @arg @ref LL_FLASH_LATENCY_6
1722 * @arg @ref LL_FLASH_LATENCY_7
1723 * @arg @ref LL_FLASH_LATENCY_8
1724 * @arg @ref LL_FLASH_LATENCY_9
1725 * @arg @ref LL_FLASH_LATENCY_10
1726 * @arg @ref LL_FLASH_LATENCY_11
1727 * @arg @ref LL_FLASH_LATENCY_12
1728 * @arg @ref LL_FLASH_LATENCY_13
1729 * @arg @ref LL_FLASH_LATENCY_14
1730 * @arg @ref LL_FLASH_LATENCY_15
1731 */
LL_FLASH_GetLatency(void)1732 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1733 {
1734 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1735 }
1736
1737 /**
1738 * @}
1739 */
1740
1741
1742 /** @defgroup SYSTEM_LL_SBS_EF_ERASE_MEMORY_STATUS_CLEAR Erase Memory Status
1743 * @{
1744 */
1745
1746 /**
1747 * @brief Clear Status of End of Erase for ICACHE and PKA RAMs
1748 * @rmtoll MESR IPMEE LL_SBS_ClearEraseEndStatus
1749 * @retval None
1750 */
LL_SBS_ClearEraseEndStatus(void)1751 __STATIC_INLINE void LL_SBS_ClearEraseEndStatus(void)
1752 {
1753 WRITE_REG(SBS->MESR, SBS_MESR_IPMEE);
1754 }
1755
1756 /**
1757 * @brief Get Status of End of Erase for ICACHE and PKA RAMs
1758 * @rmtoll MESR IPMEE LL_SBS_GetEraseEndStatus
1759 * @retval Returned value can be one of the following values:
1760 * @arg LL_SBS_MEMORIES_ERASE_IPMEE_ON_GOING : Erase of ICACHE and PKA RAMs on going or flag cleared by SW
1761 * @arg LL_SBS_MEMORIES_ERASE_IPMEE_ENDED: Erase of ICACHE and PKA RAMs ended
1762 */
LL_SBS_GetEraseEndStatus(void)1763 __STATIC_INLINE uint32_t LL_SBS_GetEraseEndStatus(void)
1764 {
1765 return (uint32_t)(READ_BIT(SBS->MESR, SBS_MESR_IPMEE));
1766 }
1767
1768 /**
1769 * @brief Clear Status of End of Erase after Power-on Reset for SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs
1770 * @rmtoll MESR MCLR LL_SBS_ClearEraseAfterResetStatus
1771 * @retval None
1772 */
LL_SBS_ClearEraseAfterResetStatus(void)1773 __STATIC_INLINE void LL_SBS_ClearEraseAfterResetStatus(void)
1774 {
1775 WRITE_REG(SBS->MESR, SBS_MESR_MCLR);
1776 }
1777
1778 /**
1779 * @brief Get Status of End of Erase after Power-on Reset for SRAM2, BKPRAM, ICACHE, DCACHE and PKA RAMs
1780 * @rmtoll MESR MCLR LL_SBS_GetEraseAfterResetStatus
1781 * @retval Returned value can be one of the following values:
1782 * @arg LL_SBS_MEMORIES_ERASE_MCLR_ON_GOING : Erase of memories on going or flag cleared by SW
1783 * @arg LL_SBS_MEMORIES_ERASE_MCLR_ENDED: Erase of memories ended
1784 */
LL_SBS_GetEraseAfterResetStatus(void)1785 __STATIC_INLINE uint32_t LL_SBS_GetEraseAfterResetStatus(void)
1786 {
1787 return (uint32_t)(READ_BIT(SBS->MESR, SBS_MESR_MCLR));
1788 }
1789 /**
1790 * @}
1791 */
1792
1793
1794 /**
1795 * @}
1796 */
1797
1798
1799 /**
1800 * @}
1801 */
1802
1803 #endif /* defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) */
1804
1805 /**
1806 * @}
1807 */
1808
1809 #ifdef __cplusplus
1810 }
1811 #endif
1812
1813 #endif /* STM32H5xx_LL_SYSTEM_H */
1814
