1 /** 2 ****************************************************************************** 3 * @file stm32h5xx_hal_spi.h 4 * @author MCD Application Team 5 * @brief Header file of SPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H5xx_HAL_SPI_H 21 #define STM32H5xx_HAL_SPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h5xx_hal_def.h" 29 30 /** @addtogroup STM32H5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SPI 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SPI_Exported_Types SPI Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SPI Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Mode; /*!< Specifies the SPI operating mode. 49 This parameter can be a value of @ref SPI_Mode */ 50 51 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 52 This parameter can be a value of @ref SPI_Direction */ 53 54 uint32_t DataSize; /*!< Specifies the SPI data size. 55 This parameter can be a value of @ref SPI_Data_Size */ 56 57 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 58 This parameter can be a value of @ref SPI_Clock_Polarity */ 59 60 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 61 This parameter can be a value of @ref SPI_Clock_Phase */ 62 63 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 64 hardware (NSS pin) or by software using the SSI bit. 65 This parameter can be a value of 66 @ref SPI_Slave_Select_Management */ 67 68 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 69 used to configure the transmit and receive SCK clock. 70 This parameter can be a value of @ref SPI_BaudRate_Prescaler 71 @note The communication clock is derived from the master 72 clock. The slave clock does not need to be set. */ 73 74 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 75 This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ 76 77 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 78 This parameter can be a value of @ref SPI_TI_Mode */ 79 80 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 81 This parameter can be a value of @ref SPI_CRC_Calculation */ 82 83 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 84 This parameter must be an odd number between 85 Min_Data = 0 and Max_Data = 65535 */ 86 87 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 88 This parameter can be a value of @ref SPI_CRC_length */ 89 90 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 91 This parameter can be a value of @ref SPI_NSSP_Mode 92 This mode is activated by the SSOM bit in the SPIx_CR2 register 93 and it takes effect only if the SPI interface is configured 94 as Motorola SPI master (FRF=0). */ 95 96 uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal 97 (present on SS pin) is considered as active one. 98 This parameter can be a value of @ref SPI_NSS_Polarity */ 99 100 uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. 101 This parameter can be a value of @ref SPI_Fifo_Threshold */ 102 103 uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for 104 the CRC calculation. This parameter can be a value of 105 @ref SPI_CRC_Calculation_Initialization_Pattern */ 106 107 uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for 108 the CRC calculation. This parameter can be a value of 109 @ref SPI_CRC_Calculation_Initialization_Pattern */ 110 111 uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle 112 periods, inserted additionally between active edge of SS 113 and first data transaction start in master mode. 114 This parameter can be a value of @ref SPI_Master_SS_Idleness */ 115 116 uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) 117 inserted between two consecutive data frames in master mode. 118 This parameter can be a value of 119 @ref SPI_Master_InterData_Idleness */ 120 121 uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode 122 and automatic management in order to avoid overrun condition. 123 This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ 124 125 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state 126 This parameter can be a value of @ref SPI_Master_Keep_IO_State */ 127 128 uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions 129 This parameter can be a value of @ref SPI_IO_Swap */ 130 131 uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not. 132 This parameter can be a value of @ref SPI_RDY_Master_Management */ 133 134 uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin) 135 is considered as active one. 136 This parameter can be a value of @ref SPI_RDY_Polarity */ 137 } SPI_InitTypeDef; 138 139 /** 140 * @brief HAL SPI State structure definition 141 */ 142 typedef enum 143 { 144 HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ 145 HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ 146 HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ 147 HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ 148 HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ 149 HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ 150 HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ 151 HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ 152 } HAL_SPI_StateTypeDef; 153 154 155 /** 156 * @brief SPI handle Structure definition 157 */ 158 typedef struct __SPI_HandleTypeDef 159 { 160 SPI_TypeDef *Instance; /*!< SPI registers base address */ 161 162 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 163 164 const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 165 166 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 167 168 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 169 170 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 171 172 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 173 174 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 175 176 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 177 178 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 179 180 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 181 182 #if defined(HAL_DMA_MODULE_ENABLED) 183 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 184 185 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 186 #endif /* HAL_DMA_MODULE_ENABLED */ 187 188 HAL_LockTypeDef Lock; /*!< Locking object */ 189 190 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 191 192 __IO uint32_t ErrorCode; /*!< SPI Error code */ 193 194 195 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 196 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 197 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 198 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 199 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 200 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 201 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 202 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 203 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 204 void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ 205 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 206 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 207 208 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 209 } SPI_HandleTypeDef; 210 211 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 212 /** 213 * @brief HAL SPI Callback ID enumeration definition 214 */ 215 typedef enum 216 { 217 HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ 218 HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ 219 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ 220 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ 221 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ 222 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ 223 HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ 224 HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ 225 HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ 226 HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ 227 HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ 228 229 } HAL_SPI_CallbackIDTypeDef; 230 231 /** 232 * @brief HAL SPI Callback pointer definition 233 */ 234 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 235 236 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 237 /** 238 * @} 239 */ 240 241 /* Exported constants --------------------------------------------------------*/ 242 243 /** @defgroup SPI_Exported_Constants SPI Exported Constants 244 * @{ 245 */ 246 247 /** @defgroup SPI_FIFO_Type SPI FIFO Type 248 * @{ 249 */ 250 #define SPI_LOWEND_FIFO_SIZE 8UL 251 #define SPI_HIGHEND_FIFO_SIZE 16UL 252 /** 253 * @} 254 */ 255 256 /** @defgroup SPI_Error_Code SPI Error Codes 257 * @{ 258 */ 259 #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ 260 #define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ 261 #define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ 262 #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ 263 #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ 264 #if defined(HAL_DMA_MODULE_ENABLED) 265 #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ 266 #endif /* HAL_DMA_MODULE_ENABLED */ 267 #define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ 268 #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ 269 #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ 270 #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ 271 #define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ 272 #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ 273 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 274 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ 275 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup SPI_Mode SPI Mode 281 * @{ 282 */ 283 #define SPI_MODE_SLAVE (0x00000000UL) 284 #define SPI_MODE_MASTER SPI_CFG2_MASTER 285 /** 286 * @} 287 */ 288 289 /** @defgroup SPI_Direction SPI Direction Mode 290 * @{ 291 */ 292 #define SPI_DIRECTION_2LINES (0x00000000UL) 293 #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 294 #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 295 #define SPI_DIRECTION_1LINE SPI_CFG2_COMM 296 /** 297 * @} 298 */ 299 300 /** @defgroup SPI_Data_Size SPI Data Size 301 * @{ 302 */ 303 #define SPI_DATASIZE_4BIT (0x00000003UL) 304 #define SPI_DATASIZE_5BIT (0x00000004UL) 305 #define SPI_DATASIZE_6BIT (0x00000005UL) 306 #define SPI_DATASIZE_7BIT (0x00000006UL) 307 #define SPI_DATASIZE_8BIT (0x00000007UL) 308 #define SPI_DATASIZE_9BIT (0x00000008UL) 309 #define SPI_DATASIZE_10BIT (0x00000009UL) 310 #define SPI_DATASIZE_11BIT (0x0000000AUL) 311 #define SPI_DATASIZE_12BIT (0x0000000BUL) 312 #define SPI_DATASIZE_13BIT (0x0000000CUL) 313 #define SPI_DATASIZE_14BIT (0x0000000DUL) 314 #define SPI_DATASIZE_15BIT (0x0000000EUL) 315 #define SPI_DATASIZE_16BIT (0x0000000FUL) 316 #define SPI_DATASIZE_17BIT (0x00000010UL) 317 #define SPI_DATASIZE_18BIT (0x00000011UL) 318 #define SPI_DATASIZE_19BIT (0x00000012UL) 319 #define SPI_DATASIZE_20BIT (0x00000013UL) 320 #define SPI_DATASIZE_21BIT (0x00000014UL) 321 #define SPI_DATASIZE_22BIT (0x00000015UL) 322 #define SPI_DATASIZE_23BIT (0x00000016UL) 323 #define SPI_DATASIZE_24BIT (0x00000017UL) 324 #define SPI_DATASIZE_25BIT (0x00000018UL) 325 #define SPI_DATASIZE_26BIT (0x00000019UL) 326 #define SPI_DATASIZE_27BIT (0x0000001AUL) 327 #define SPI_DATASIZE_28BIT (0x0000001BUL) 328 #define SPI_DATASIZE_29BIT (0x0000001CUL) 329 #define SPI_DATASIZE_30BIT (0x0000001DUL) 330 #define SPI_DATASIZE_31BIT (0x0000001EUL) 331 #define SPI_DATASIZE_32BIT (0x0000001FUL) 332 /** 333 * @} 334 */ 335 336 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 337 * @{ 338 */ 339 #define SPI_POLARITY_LOW (0x00000000UL) 340 #define SPI_POLARITY_HIGH SPI_CFG2_CPOL 341 /** 342 * @} 343 */ 344 345 /** @defgroup SPI_Clock_Phase SPI Clock Phase 346 * @{ 347 */ 348 #define SPI_PHASE_1EDGE (0x00000000UL) 349 #define SPI_PHASE_2EDGE SPI_CFG2_CPHA 350 /** 351 * @} 352 */ 353 354 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management 355 * @{ 356 */ 357 #define SPI_NSS_SOFT SPI_CFG2_SSM 358 #define SPI_NSS_HARD_INPUT (0x00000000UL) 359 #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE 360 /** 361 * @} 362 */ 363 364 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 365 * @{ 366 */ 367 #define SPI_NSS_PULSE_DISABLE (0x00000000UL) 368 #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM 369 /** 370 * @} 371 */ 372 373 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 374 * @{ 375 */ 376 #define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL) 377 #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) 378 #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) 379 #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) 380 #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) 381 #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) 382 #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) 383 #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) 384 #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) 385 /** 386 * @} 387 */ 388 389 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission 390 * @{ 391 */ 392 #define SPI_FIRSTBIT_MSB (0x00000000UL) 393 #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST 394 /** 395 * @} 396 */ 397 398 /** @defgroup SPI_TI_Mode SPI TI Mode 399 * @{ 400 */ 401 #define SPI_TIMODE_DISABLE (0x00000000UL) 402 #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 403 /** 404 * @} 405 */ 406 407 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 408 * @{ 409 */ 410 #define SPI_CRCCALCULATION_DISABLE (0x00000000UL) 411 #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN 412 /** 413 * @} 414 */ 415 416 /** @defgroup SPI_CRC_length SPI CRC Length 417 * @{ 418 */ 419 #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) 420 #define SPI_CRC_LENGTH_4BIT (0x00030000UL) 421 #define SPI_CRC_LENGTH_5BIT (0x00040000UL) 422 #define SPI_CRC_LENGTH_6BIT (0x00050000UL) 423 #define SPI_CRC_LENGTH_7BIT (0x00060000UL) 424 #define SPI_CRC_LENGTH_8BIT (0x00070000UL) 425 #define SPI_CRC_LENGTH_9BIT (0x00080000UL) 426 #define SPI_CRC_LENGTH_10BIT (0x00090000UL) 427 #define SPI_CRC_LENGTH_11BIT (0x000A0000UL) 428 #define SPI_CRC_LENGTH_12BIT (0x000B0000UL) 429 #define SPI_CRC_LENGTH_13BIT (0x000C0000UL) 430 #define SPI_CRC_LENGTH_14BIT (0x000D0000UL) 431 #define SPI_CRC_LENGTH_15BIT (0x000E0000UL) 432 #define SPI_CRC_LENGTH_16BIT (0x000F0000UL) 433 #define SPI_CRC_LENGTH_17BIT (0x00100000UL) 434 #define SPI_CRC_LENGTH_18BIT (0x00110000UL) 435 #define SPI_CRC_LENGTH_19BIT (0x00120000UL) 436 #define SPI_CRC_LENGTH_20BIT (0x00130000UL) 437 #define SPI_CRC_LENGTH_21BIT (0x00140000UL) 438 #define SPI_CRC_LENGTH_22BIT (0x00150000UL) 439 #define SPI_CRC_LENGTH_23BIT (0x00160000UL) 440 #define SPI_CRC_LENGTH_24BIT (0x00170000UL) 441 #define SPI_CRC_LENGTH_25BIT (0x00180000UL) 442 #define SPI_CRC_LENGTH_26BIT (0x00190000UL) 443 #define SPI_CRC_LENGTH_27BIT (0x001A0000UL) 444 #define SPI_CRC_LENGTH_28BIT (0x001B0000UL) 445 #define SPI_CRC_LENGTH_29BIT (0x001C0000UL) 446 #define SPI_CRC_LENGTH_30BIT (0x001D0000UL) 447 #define SPI_CRC_LENGTH_31BIT (0x001E0000UL) 448 #define SPI_CRC_LENGTH_32BIT (0x001F0000UL) 449 /** 450 * @} 451 */ 452 453 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold 454 * @{ 455 */ 456 #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) 457 #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) 458 #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) 459 #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) 460 #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) 461 #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) 462 #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) 463 #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) 464 #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) 465 #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) 466 #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) 467 #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) 468 #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) 469 #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) 470 #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) 471 #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) 472 /** 473 * @} 474 */ 475 476 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern 477 * @{ 478 */ 479 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) 480 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) 481 /** 482 * @} 483 */ 484 485 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity 486 * @{ 487 */ 488 #define SPI_NSS_POLARITY_LOW (0x00000000UL) 489 #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP 490 /** 491 * @} 492 */ 493 494 /** @defgroup SPI_Master_Keep_IO_State Keep IO State 495 * @{ 496 */ 497 #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) 498 #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR 499 /** 500 * @} 501 */ 502 503 /** @defgroup SPI_IO_Swap Control SPI IO Swap 504 * @{ 505 */ 506 #define SPI_IO_SWAP_DISABLE (0x00000000UL) 507 #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP 508 /** 509 * @} 510 */ 511 512 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness 513 * @{ 514 */ 515 #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) 516 #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) 517 #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) 518 #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) 519 #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) 520 #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) 521 #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) 522 #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) 523 #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) 524 #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) 525 #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) 526 #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) 527 #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) 528 #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) 529 #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) 530 #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) 531 /** 532 * @} 533 */ 534 535 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness 536 * @{ 537 */ 538 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) 539 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) 540 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) 541 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) 542 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) 543 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) 544 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) 545 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) 546 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) 547 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) 548 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) 549 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) 550 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) 551 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) 552 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) 553 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) 554 /** 555 * @} 556 */ 557 558 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend 559 * @{ 560 */ 561 #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) 562 #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX 563 /** 564 * @} 565 */ 566 567 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior 568 * @{ 569 */ 570 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) 571 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG 572 /** 573 * @} 574 */ 575 576 /** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management 577 * @{ 578 */ 579 #define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) 580 #define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIOM 581 /** 582 * @} 583 */ 584 585 /** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity 586 * @{ 587 */ 588 #define SPI_RDY_POLARITY_HIGH (0x00000000UL) 589 #define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP 590 /** 591 * @} 592 */ 593 594 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 595 * @{ 596 */ 597 #define SPI_IT_RXP SPI_IER_RXPIE 598 #define SPI_IT_TXP SPI_IER_TXPIE 599 #define SPI_IT_DXP SPI_IER_DXPIE 600 #define SPI_IT_EOT SPI_IER_EOTIE 601 #define SPI_IT_TXTF SPI_IER_TXTFIE 602 #define SPI_IT_UDR SPI_IER_UDRIE 603 #define SPI_IT_OVR SPI_IER_OVRIE 604 #define SPI_IT_CRCERR SPI_IER_CRCEIE 605 #define SPI_IT_FRE SPI_IER_TIFREIE 606 #define SPI_IT_MODF SPI_IER_MODFIE 607 #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) 608 /** 609 * @} 610 */ 611 612 /** @defgroup SPI_Flags_definition SPI Flags Definition 613 * @{ 614 */ 615 #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ 616 #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ 617 #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ 618 #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ 619 #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ 620 #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ 621 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ 622 #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ 623 #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ 624 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ 625 #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ 626 #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ 627 #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ 628 #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 634 * @{ 635 */ 636 #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ 637 #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) 638 #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) 639 #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) 640 /** 641 * @} 642 */ 643 644 /** 645 * @} 646 */ 647 648 /* Exported macros -----------------------------------------------------------*/ 649 /** @defgroup SPI_Exported_Macros SPI Exported Macros 650 * @{ 651 */ 652 653 /** @brief Reset SPI handle state. 654 * @param __HANDLE__: specifies the SPI Handle. 655 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 656 * @retval None 657 */ 658 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 659 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 660 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 661 (__HANDLE__)->MspInitCallback = NULL; \ 662 (__HANDLE__)->MspDeInitCallback = NULL; \ 663 } while(0) 664 #else 665 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 666 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 667 668 /** @brief Enable the specified SPI interrupts. 669 * @param __HANDLE__: specifies the SPI Handle. 670 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 671 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 672 * This parameter can be one of the following values: 673 * @arg SPI_IT_RXP : Rx-Packet available interrupt 674 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 675 * @arg SPI_IT_DXP : Duplex Packet interrupt 676 * @arg SPI_IT_EOT : End of transfer interrupt 677 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 678 * @arg SPI_IT_UDR : Underrun interrupt 679 * @arg SPI_IT_OVR : Overrun interrupt 680 * @arg SPI_IT_CRCERR : CRC error interrupt 681 * @arg SPI_IT_FRE : TI mode frame format error interrupt 682 * @arg SPI_IT_MODF : Mode fault interrupt 683 * @arg SPI_IT_ERR : Error interrupt 684 * @retval None 685 */ 686 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 687 688 /** @brief Disable the specified SPI interrupts. 689 * @param __HANDLE__: specifies the SPI Handle. 690 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 691 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 692 * This parameter can be one of the following values: 693 * @arg SPI_IT_RXP : Rx-Packet available interrupt 694 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 695 * @arg SPI_IT_DXP : Duplex Packet interrupt 696 * @arg SPI_IT_EOT : End of transfer interrupt 697 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 698 * @arg SPI_IT_UDR : Underrun interrupt 699 * @arg SPI_IT_OVR : Overrun interrupt 700 * @arg SPI_IT_CRCERR : CRC error interrupt 701 * @arg SPI_IT_FRE : TI mode frame format error interrupt 702 * @arg SPI_IT_MODF : Mode fault interrupt 703 * @arg SPI_IT_ERR : Error interrupt 704 * @retval None 705 */ 706 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 707 708 /** @brief Check whether the specified SPI interrupt source is enabled or not. 709 * @param __HANDLE__: specifies the SPI Handle. 710 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 711 * @param __INTERRUPT__: specifies the SPI interrupt source to check. 712 * This parameter can be one of the following values: 713 * @arg SPI_IT_RXP : Rx-Packet available interrupt 714 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 715 * @arg SPI_IT_DXP : Duplex Packet interrupt 716 * @arg SPI_IT_EOT : End of transfer interrupt 717 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 718 * @arg SPI_IT_UDR : Underrun interrupt 719 * @arg SPI_IT_OVR : Overrun interrupt 720 * @arg SPI_IT_CRCERR : CRC error interrupt 721 * @arg SPI_IT_FRE : TI mode frame format error interrupt 722 * @arg SPI_IT_MODF : Mode fault interrupt 723 * @arg SPI_IT_ERR : Error interrupt 724 * @retval The new state of __IT__ (TRUE or FALSE). 725 */ 726 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ 727 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 728 729 /** @brief Check whether the specified SPI flag is set or not. 730 * @param __HANDLE__: specifies the SPI Handle. 731 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 732 * @param __FLAG__: specifies the flag to check. 733 * This parameter can be one of the following values: 734 * @arg SPI_FLAG_RXP : Rx-Packet available flag 735 * @arg SPI_FLAG_TXP : Tx-Packet space available flag 736 * @arg SPI_FLAG_DXP : Duplex Packet flag 737 * @arg SPI_FLAG_EOT : End of transfer flag 738 * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag 739 * @arg SPI_FLAG_UDR : Underrun flag 740 * @arg SPI_FLAG_OVR : Overrun flag 741 * @arg SPI_FLAG_CRCERR : CRC error flag 742 * @arg SPI_FLAG_FRE : TI mode frame format error flag 743 * @arg SPI_FLAG_MODF : Mode fault flag 744 * @arg SPI_FLAG_SUSP : Transfer suspend complete flag 745 * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag 746 * @arg SPI_FLAG_FRLVL : Fifo reception level flag 747 * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag 748 * @retval The new state of __FLAG__ (TRUE or FALSE). 749 */ 750 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 751 752 /** @brief Clear the SPI CRCERR pending flag. 753 * @param __HANDLE__: specifies the SPI Handle. 754 * @retval None 755 */ 756 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) 757 758 /** @brief Clear the SPI MODF pending flag. 759 * @param __HANDLE__: specifies the SPI Handle. 760 * @retval None 761 */ 762 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); 763 764 /** @brief Clear the SPI OVR pending flag. 765 * @param __HANDLE__: specifies the SPI Handle. 766 * @retval None 767 */ 768 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) 769 770 /** @brief Clear the SPI FRE pending flag. 771 * @param __HANDLE__: specifies the SPI Handle. 772 * @retval None 773 */ 774 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) 775 776 /** @brief Clear the SPI UDR pending flag. 777 * @param __HANDLE__: specifies the SPI Handle. 778 * @retval None 779 */ 780 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) 781 782 /** @brief Clear the SPI EOT pending flag. 783 * @param __HANDLE__: specifies the SPI Handle. 784 * @retval None 785 */ 786 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) 787 788 /** @brief Clear the SPI UDR pending flag. 789 * @param __HANDLE__: specifies the SPI Handle. 790 * @retval None 791 */ 792 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) 793 794 /** @brief Clear the SPI SUSP pending flag. 795 * @param __HANDLE__: specifies the SPI Handle. 796 * @retval None 797 */ 798 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) 799 800 /** @brief Enable the SPI peripheral. 801 * @param __HANDLE__: specifies the SPI Handle. 802 * @retval None 803 */ 804 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 805 806 /** @brief Disable the SPI peripheral. 807 * @param __HANDLE__: specifies the SPI Handle. 808 * @retval None 809 */ 810 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 811 /** 812 * @} 813 */ 814 815 816 /* Include SPI HAL Extension module */ 817 #include "stm32h5xx_hal_spi_ex.h" 818 819 820 /* Exported functions --------------------------------------------------------*/ 821 /** @addtogroup SPI_Exported_Functions 822 * @{ 823 */ 824 825 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions 826 * @{ 827 */ 828 /* Initialization/de-initialization functions ********************************/ 829 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 830 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 831 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 832 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 833 834 /* Callbacks Register/UnRegister functions ***********************************/ 835 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 836 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, 837 pSPI_CallbackTypeDef pCallback); 838 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 839 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 840 /** 841 * @} 842 */ 843 844 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions 845 * @{ 846 */ 847 /* I/O operation functions ***************************************************/ 848 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); 849 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 850 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 851 uint16_t Size, uint32_t Timeout); 852 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 853 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 854 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 855 uint16_t Size); 856 857 #if defined(HAL_DMA_MODULE_ENABLED) 858 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 859 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 860 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 861 uint16_t Size); 862 #endif /* HAL_DMA_MODULE_ENABLED */ 863 864 865 #if defined(HAL_DMA_MODULE_ENABLED) 866 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 867 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 868 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 869 #endif /* HAL_DMA_MODULE_ENABLED */ 870 871 /* Transfer Abort functions */ 872 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 873 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 874 875 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 876 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 877 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 878 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 879 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 880 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 881 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 882 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 883 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 884 void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); 885 /** 886 * @} 887 */ 888 889 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions 890 * @{ 891 */ 892 893 /* Peripheral State and Error functions ***************************************/ 894 HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); 895 uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); 896 /** 897 * @} 898 */ 899 900 /** 901 * @} 902 */ 903 904 /* Private macros ------------------------------------------------------------*/ 905 /** @defgroup SPI_Private_Macros SPI Private Macros 906 * @{ 907 */ 908 909 /** @brief Set the SPI transmit-only mode in 1Line configuration. 910 * @param __HANDLE__: specifies the SPI Handle. 911 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 912 * @retval None 913 */ 914 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) 915 916 /** @brief Set the SPI receive-only mode in 1Line configuration. 917 * @param __HANDLE__: specifies the SPI Handle. 918 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 919 * @retval None 920 */ 921 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) 922 923 /** @brief Set the SPI transmit-only mode in 2Lines configuration. 924 * @param __HANDLE__: specifies the SPI Handle. 925 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 926 * @retval None 927 */ 928 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) 929 930 /** @brief Set the SPI receive-only mode in 2Lines configuration. 931 * @param __HANDLE__: specifies the SPI Handle. 932 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 933 * @retval None 934 */ 935 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) 936 937 /** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. 938 * @param __HANDLE__: specifies the SPI Handle. 939 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 940 * @retval None 941 */ 942 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) 943 944 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ 945 ((MODE) == SPI_MODE_MASTER)) 946 947 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ 948 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ 949 ((MODE) == SPI_DIRECTION_1LINE) || \ 950 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 951 952 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) 953 954 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 955 ((MODE) == SPI_DIRECTION_1LINE) || \ 956 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 957 958 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 959 ((MODE) == SPI_DIRECTION_1LINE) || \ 960 ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) 961 962 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ 963 ((DATASIZE) == SPI_DATASIZE_31BIT) || \ 964 ((DATASIZE) == SPI_DATASIZE_30BIT) || \ 965 ((DATASIZE) == SPI_DATASIZE_29BIT) || \ 966 ((DATASIZE) == SPI_DATASIZE_28BIT) || \ 967 ((DATASIZE) == SPI_DATASIZE_27BIT) || \ 968 ((DATASIZE) == SPI_DATASIZE_26BIT) || \ 969 ((DATASIZE) == SPI_DATASIZE_25BIT) || \ 970 ((DATASIZE) == SPI_DATASIZE_24BIT) || \ 971 ((DATASIZE) == SPI_DATASIZE_23BIT) || \ 972 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 973 ((DATASIZE) == SPI_DATASIZE_21BIT) || \ 974 ((DATASIZE) == SPI_DATASIZE_20BIT) || \ 975 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 976 ((DATASIZE) == SPI_DATASIZE_19BIT) || \ 977 ((DATASIZE) == SPI_DATASIZE_18BIT) || \ 978 ((DATASIZE) == SPI_DATASIZE_17BIT) || \ 979 ((DATASIZE) == SPI_DATASIZE_16BIT) || \ 980 ((DATASIZE) == SPI_DATASIZE_15BIT) || \ 981 ((DATASIZE) == SPI_DATASIZE_14BIT) || \ 982 ((DATASIZE) == SPI_DATASIZE_13BIT) || \ 983 ((DATASIZE) == SPI_DATASIZE_12BIT) || \ 984 ((DATASIZE) == SPI_DATASIZE_11BIT) || \ 985 ((DATASIZE) == SPI_DATASIZE_10BIT) || \ 986 ((DATASIZE) == SPI_DATASIZE_9BIT) || \ 987 ((DATASIZE) == SPI_DATASIZE_8BIT) || \ 988 ((DATASIZE) == SPI_DATASIZE_7BIT) || \ 989 ((DATASIZE) == SPI_DATASIZE_6BIT) || \ 990 ((DATASIZE) == SPI_DATASIZE_5BIT) || \ 991 ((DATASIZE) == SPI_DATASIZE_4BIT)) 992 993 /** 994 * @brief DataSize for limited instance 995 */ 996 #define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ 997 ((DATASIZE) == SPI_DATASIZE_8BIT)) 998 999 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ 1000 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ 1001 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ 1002 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ 1003 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ 1004 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ 1005 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ 1006 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ 1007 ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ 1008 ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ 1009 ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ 1010 ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ 1011 ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ 1012 ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ 1013 ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ 1014 ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) 1015 1016 /** 1017 * @brief FifoThreshold for limited instance 1018 */ 1019 #define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ 1020 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ 1021 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ 1022 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ 1023 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ 1024 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ 1025 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ 1026 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA)) 1027 1028 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ 1029 ((CPOL) == SPI_POLARITY_HIGH)) 1030 1031 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ 1032 ((CPHA) == SPI_PHASE_2EDGE)) 1033 1034 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ 1035 ((NSS) == SPI_NSS_HARD_INPUT) || \ 1036 ((NSS) == SPI_NSS_HARD_OUTPUT)) 1037 1038 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ 1039 ((NSSP) == SPI_NSS_PULSE_DISABLE)) 1040 1041 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ 1042 ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ 1043 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ 1044 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ 1045 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ 1046 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ 1047 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ 1048 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ 1049 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) 1050 1051 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ 1052 ((BIT) == SPI_FIRSTBIT_LSB)) 1053 1054 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ 1055 ((MODE) == SPI_TIMODE_ENABLE)) 1056 1057 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ 1058 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) 1059 1060 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ 1061 ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) 1062 1063 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ 1064 ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ 1065 ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ 1066 ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ 1067 ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ 1068 ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ 1069 ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ 1070 ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ 1071 ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ 1072 ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ 1073 ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ 1074 ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ 1075 ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ 1076 ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ 1077 ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ 1078 ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ 1079 ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ 1080 ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ 1081 ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ 1082 ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ 1083 ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ 1084 ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ 1085 ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ 1086 ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ 1087 ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ 1088 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ 1089 ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ 1090 ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ 1091 ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ 1092 ((LENGTH) == SPI_CRC_LENGTH_4BIT)) 1093 1094 1095 #define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) 1096 1097 /** 1098 * @brief CRC Length for limited instance 1099 */ 1100 #define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ 1101 ((LENGTH) == SPI_CRC_LENGTH_16BIT)) 1102 1103 1104 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) 1105 1106 #define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) 1107 1108 1109 1110 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ 1111 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) 1112 1113 #define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \ 1114 ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY)) 1115 1116 #define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ 1117 ((POLARITY) == SPI_RDY_POLARITY_LOW)) 1118 1119 #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ 1120 ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) 1121 1122 #define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) 1123 /** 1124 * @} 1125 */ 1126 1127 /** 1128 * @} 1129 */ 1130 1131 /** 1132 * @} 1133 */ 1134 1135 #ifdef __cplusplus 1136 } 1137 #endif 1138 1139 #endif /* STM32H5xx_HAL_SPI_H */ 1140 1141 /** 1142 * @} 1143 */ 1144
