1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_i2s.c
4 * @author MCD Application Team
5 * @brief I2S HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ===============================================================================
24 ##### How to use this driver #####
25 ===============================================================================
26 [..]
27 The I2S HAL driver can be used as follow:
28
29 (#) Declare a I2S_HandleTypeDef handle structure.
30 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
31 (##) Enable the SPIx interface clock.
32 (##) I2S pins configuration:
33 (+++) Enable the clock for the I2S GPIOs.
34 (+++) Configure these I2S pins as alternate function pull-up.
35 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
36 and HAL_I2S_Receive_IT() APIs).
37 (+++) Configure the I2Sx interrupt priority.
38 (+++) Enable the NVIC I2S IRQ handle.
39 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
40 and HAL_I2S_Receive_DMA() APIs:
41 (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
42 (+++) Enable the DMAx interface clock.
43 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
44 (+++) Configure the DMA Tx/Rx Stream/Channel.
45 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
46 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
47 DMA Tx/Rx Stream/Channel.
48
49 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
50 using HAL_I2S_Init() function.
51
52 -@- The specific I2S interrupts (Transmission complete interrupt,
53 RXNE interrupt and Error Interrupts) will be managed using the macros
54 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
55 -@- Make sure that either:
56 (+@) SYSCLK is configured or
57 (+@) PLLADCCLK output is configured or
58 (+@) HSI is enabled or
59 (+@) External clock source is configured after setting correctly
60 the define constant EXTERNAL_CLOCK_VALUE in the stm32g4xx_hal_conf.h file.
61
62 (#) Three mode of operations are available within this driver :
63
64 *** Polling mode IO operation ***
65 =================================
66 [..]
67 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
68 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
69
70 *** Interrupt mode IO operation ***
71 ===================================
72 [..]
73 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
74 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
75 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
76 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
77 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
78 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
79 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
80 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
81 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
82 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
83 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
84 add his own code by customization of function pointer HAL_I2S_ErrorCallback
85
86 *** DMA mode IO operation ***
87 ==============================
88 [..]
89 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
90 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
91 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
92 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
93 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
94 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
95 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
96 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
97 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
98 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
99 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
100 add his own code by customization of function pointer HAL_I2S_ErrorCallback
101 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
102 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
103 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
104 In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
105 HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
106 In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
107 inside DR register and avoid using DeInit/Init process for the next transfer.
108
109 *** I2S HAL driver macros list ***
110 ===================================
111 [..]
112 Below the list of most used macros in I2S HAL driver.
113
114 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
115 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
116 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
117 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
118 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
119 (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
120
121 [..]
122 (@) You can refer to the I2S HAL driver header file for more useful macros
123
124 *** I2S HAL driver macros list ***
125 ===================================
126 [..]
127 Callback registration:
128
129 (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
130 allows the user to configure dynamically the driver callbacks.
131 Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
132
133 Function HAL_I2S_RegisterCallback() allows to register following callbacks:
134 (++) TxCpltCallback : I2S Tx Completed callback
135 (++) RxCpltCallback : I2S Rx Completed callback
136 (++) TxHalfCpltCallback : I2S Tx Half Completed callback
137 (++) RxHalfCpltCallback : I2S Rx Half Completed callback
138 (++) ErrorCallback : I2S Error callback
139 (++) MspInitCallback : I2S Msp Init callback
140 (++) MspDeInitCallback : I2S Msp DeInit callback
141 This function takes as parameters the HAL peripheral handle, the Callback ID
142 and a pointer to the user callback function.
143
144
145 (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
146 weak function.
147 HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
148 and the Callback ID.
149 This function allows to reset following callbacks:
150 (++) TxCpltCallback : I2S Tx Completed callback
151 (++) RxCpltCallback : I2S Rx Completed callback
152 (++) TxHalfCpltCallback : I2S Tx Half Completed callback
153 (++) RxHalfCpltCallback : I2S Rx Half Completed callback
154 (++) ErrorCallback : I2S Error callback
155 (++) MspInitCallback : I2S Msp Init callback
156 (++) MspDeInitCallback : I2S Msp DeInit callback
157
158 [..]
159 By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
160 all callbacks are set to the corresponding weak functions:
161 examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
162 Exception done for MspInit and MspDeInit functions that are
163 reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
164 these callbacks are null (not registered beforehand).
165 If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
166 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
167
168 [..]
169 Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
170 Exception done MspInit/MspDeInit functions that can be registered/unregistered
171 in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
172 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
173 Then, the user first registers the MspInit/MspDeInit user callbacks
174 using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
175 or HAL_I2S_Init() function.
176
177 [..]
178 When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
179 not defined, the callback registering feature is not available
180 and weak (surcharged) callbacks are used.
181
182 @endverbatim
183
184 */
185
186 /* Includes ------------------------------------------------------------------*/
187 #include "stm32g4xx_hal.h"
188
189 #ifdef HAL_I2S_MODULE_ENABLED
190
191 #if defined(SPI_I2S_SUPPORT)
192 /** @addtogroup STM32G4xx_HAL_Driver
193 * @{
194 */
195
196 /** @defgroup I2S I2S
197 * @brief I2S HAL module driver
198 * @{
199 */
200
201 /* Private typedef -----------------------------------------------------------*/
202 /* Private define ------------------------------------------------------------*/
203 #define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */
204 /* Private macro -------------------------------------------------------------*/
205 /* Private variables ---------------------------------------------------------*/
206 /* Private function prototypes -----------------------------------------------*/
207 /** @defgroup I2S_Private_Functions I2S Private Functions
208 * @{
209 */
210 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
211 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
212 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
213 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
214 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
215 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
216 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
217 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
218 uint32_t Timeout);
219 /**
220 * @}
221 */
222
223 /* Exported functions ---------------------------------------------------------*/
224
225 /** @defgroup I2S_Exported_Functions I2S Exported Functions
226 * @{
227 */
228
229 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
230 * @brief Initialization and Configuration functions
231 *
232 @verbatim
233 ===============================================================================
234 ##### Initialization and de-initialization functions #####
235 ===============================================================================
236 [..] This subsection provides a set of functions allowing to initialize and
237 de-initialize the I2Sx peripheral in simplex mode:
238
239 (+) User must Implement HAL_I2S_MspInit() function in which he configures
240 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
241
242 (+) Call the function HAL_I2S_Init() to configure the selected device with
243 the selected configuration:
244 (++) Mode
245 (++) Standard
246 (++) Data Format
247 (++) MCLK Output
248 (++) Audio frequency
249 (++) Polarity
250
251 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
252 of the selected I2Sx peripheral.
253 @endverbatim
254 * @{
255 */
256
257 /**
258 * @brief Initializes the I2S according to the specified parameters
259 * in the I2S_InitTypeDef and create the associated handle.
260 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
261 * the configuration information for I2S module
262 * @retval HAL status
263 */
HAL_I2S_Init(I2S_HandleTypeDef * hi2s)264 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
265 {
266 uint32_t i2sdiv;
267 uint32_t i2sodd;
268 uint32_t packetlength;
269 uint32_t tmp;
270 uint32_t i2sclk;
271
272 /* Check the I2S handle allocation */
273 if (hi2s == NULL)
274 {
275 return HAL_ERROR;
276 }
277
278 /* Check the I2S parameters */
279 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
280 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
281 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
282 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
283 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
284 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
285 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
286
287 if (hi2s->State == HAL_I2S_STATE_RESET)
288 {
289 /* Allocate lock resource and initialize it */
290 hi2s->Lock = HAL_UNLOCKED;
291
292 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
293 /* Init the I2S Callback settings */
294 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
295 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
296 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
297 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
298 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
299
300 if (hi2s->MspInitCallback == NULL)
301 {
302 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
303 }
304
305 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
306 hi2s->MspInitCallback(hi2s);
307 #else
308 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
309 HAL_I2S_MspInit(hi2s);
310 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
311 }
312
313 hi2s->State = HAL_I2S_STATE_BUSY;
314
315 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
316 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
317 CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
318 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
319 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
320 hi2s->Instance->I2SPR = 0x0002U;
321
322 /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
323 /* If the requested audio frequency is not the default, compute the prescaler */
324 if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
325 {
326 /* Check the frame length (For the Prescaler computing) ********************/
327 if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
328 {
329 /* Packet length is 16 bits */
330 packetlength = 16U;
331 }
332 else
333 {
334 /* Packet length is 32 bits */
335 packetlength = 32U;
336 }
337
338 /* I2S standard */
339 if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
340 {
341 /* In I2S standard packet length is multiplied by 2 */
342 packetlength = packetlength * 2U;
343 }
344
345 /* Get the source clock value: based on System Clock value */
346 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
347
348 /* Compute the Real divider depending on the MCLK output state, with a floating point */
349 if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
350 {
351 /* MCLK output is enabled */
352 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
353 {
354 tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
355 }
356 else
357 {
358 tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
359 }
360 }
361 else
362 {
363 /* MCLK output is disabled */
364 tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
365 }
366
367 /* Remove the flatting point */
368 tmp = tmp / 10U;
369
370 /* Check the parity of the divider */
371 i2sodd = (uint32_t)(tmp & (uint32_t)1U);
372
373 /* Compute the i2sdiv prescaler */
374 i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
375
376 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
377 i2sodd = (uint32_t)(i2sodd << 8U);
378 }
379 else
380 {
381 /* Set the default values */
382 i2sdiv = 2U;
383 i2sodd = 0U;
384 }
385
386 /* Test if the divider is 1 or 0 or greater than 0xFF */
387 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
388 {
389 /* Set the error code and execute error callback*/
390 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
391 return HAL_ERROR;
392 }
393
394 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
395
396 /* Write to SPIx I2SPR register the computed value */
397 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
398
399 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
400 /* And configure the I2S with the I2S_InitStruct values */
401 MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
402 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
403 SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
404 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
405 (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
406 hi2s->Init.Standard | hi2s->Init.DataFormat | \
407 hi2s->Init.CPOL));
408
409 #if defined(SPI_I2SCFGR_ASTRTEN)
410 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
411 {
412 /* Write to SPIx I2SCFGR */
413 SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
414 }
415 #endif /* SPI_I2SCFGR_ASTRTEN */
416
417 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
418 hi2s->State = HAL_I2S_STATE_READY;
419
420 return HAL_OK;
421 }
422
423 /**
424 * @brief DeInitializes the I2S peripheral
425 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
426 * the configuration information for I2S module
427 * @retval HAL status
428 */
HAL_I2S_DeInit(I2S_HandleTypeDef * hi2s)429 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
430 {
431 /* Check the I2S handle allocation */
432 if (hi2s == NULL)
433 {
434 return HAL_ERROR;
435 }
436
437 /* Check the parameters */
438 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
439
440 hi2s->State = HAL_I2S_STATE_BUSY;
441
442 /* Disable the I2S Peripheral Clock */
443 __HAL_I2S_DISABLE(hi2s);
444
445 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
446 if (hi2s->MspDeInitCallback == NULL)
447 {
448 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
449 }
450
451 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
452 hi2s->MspDeInitCallback(hi2s);
453 #else
454 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
455 HAL_I2S_MspDeInit(hi2s);
456 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
457
458 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
459 hi2s->State = HAL_I2S_STATE_RESET;
460
461 /* Release Lock */
462 __HAL_UNLOCK(hi2s);
463
464 return HAL_OK;
465 }
466
467 /**
468 * @brief I2S MSP Init
469 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
470 * the configuration information for I2S module
471 * @retval None
472 */
HAL_I2S_MspInit(I2S_HandleTypeDef * hi2s)473 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
474 {
475 /* Prevent unused argument(s) compilation warning */
476 UNUSED(hi2s);
477
478 /* NOTE : This function Should not be modified, when the callback is needed,
479 the HAL_I2S_MspInit could be implemented in the user file
480 */
481 }
482
483 /**
484 * @brief I2S MSP DeInit
485 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
486 * the configuration information for I2S module
487 * @retval None
488 */
HAL_I2S_MspDeInit(I2S_HandleTypeDef * hi2s)489 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
490 {
491 /* Prevent unused argument(s) compilation warning */
492 UNUSED(hi2s);
493
494 /* NOTE : This function Should not be modified, when the callback is needed,
495 the HAL_I2S_MspDeInit could be implemented in the user file
496 */
497 }
498
499 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
500 /**
501 * @brief Register a User I2S Callback
502 * To be used instead of the weak predefined callback
503 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
504 * the configuration information for the specified I2S.
505 * @param CallbackID ID of the callback to be registered
506 * @param pCallback pointer to the Callback function
507 * @retval HAL status
508 */
HAL_I2S_RegisterCallback(I2S_HandleTypeDef * hi2s,HAL_I2S_CallbackIDTypeDef CallbackID,pI2S_CallbackTypeDef pCallback)509 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
510 pI2S_CallbackTypeDef pCallback)
511 {
512 HAL_StatusTypeDef status = HAL_OK;
513
514 if (pCallback == NULL)
515 {
516 /* Update the error code */
517 hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
518
519 return HAL_ERROR;
520 }
521 /* Process locked */
522 __HAL_LOCK(hi2s);
523
524 if (HAL_I2S_STATE_READY == hi2s->State)
525 {
526 switch (CallbackID)
527 {
528 case HAL_I2S_TX_COMPLETE_CB_ID :
529 hi2s->TxCpltCallback = pCallback;
530 break;
531
532 case HAL_I2S_RX_COMPLETE_CB_ID :
533 hi2s->RxCpltCallback = pCallback;
534 break;
535
536 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
537 hi2s->TxHalfCpltCallback = pCallback;
538 break;
539
540 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
541 hi2s->RxHalfCpltCallback = pCallback;
542 break;
543
544 case HAL_I2S_ERROR_CB_ID :
545 hi2s->ErrorCallback = pCallback;
546 break;
547
548 case HAL_I2S_MSPINIT_CB_ID :
549 hi2s->MspInitCallback = pCallback;
550 break;
551
552 case HAL_I2S_MSPDEINIT_CB_ID :
553 hi2s->MspDeInitCallback = pCallback;
554 break;
555
556 default :
557 /* Update the error code */
558 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
559
560 /* Return error status */
561 status = HAL_ERROR;
562 break;
563 }
564 }
565 else if (HAL_I2S_STATE_RESET == hi2s->State)
566 {
567 switch (CallbackID)
568 {
569 case HAL_I2S_MSPINIT_CB_ID :
570 hi2s->MspInitCallback = pCallback;
571 break;
572
573 case HAL_I2S_MSPDEINIT_CB_ID :
574 hi2s->MspDeInitCallback = pCallback;
575 break;
576
577 default :
578 /* Update the error code */
579 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
580
581 /* Return error status */
582 status = HAL_ERROR;
583 break;
584 }
585 }
586 else
587 {
588 /* Update the error code */
589 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
590
591 /* Return error status */
592 status = HAL_ERROR;
593 }
594
595 /* Release Lock */
596 __HAL_UNLOCK(hi2s);
597 return status;
598 }
599
600 /**
601 * @brief Unregister an I2S Callback
602 * I2S callback is redirected to the weak predefined callback
603 * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
604 * the configuration information for the specified I2S.
605 * @param CallbackID ID of the callback to be unregistered
606 * @retval HAL status
607 */
HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef * hi2s,HAL_I2S_CallbackIDTypeDef CallbackID)608 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
609 {
610 HAL_StatusTypeDef status = HAL_OK;
611
612 /* Process locked */
613 __HAL_LOCK(hi2s);
614
615 if (HAL_I2S_STATE_READY == hi2s->State)
616 {
617 switch (CallbackID)
618 {
619 case HAL_I2S_TX_COMPLETE_CB_ID :
620 hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
621 break;
622
623 case HAL_I2S_RX_COMPLETE_CB_ID :
624 hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
625 break;
626
627 case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
628 hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
629 break;
630
631 case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
632 hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
633 break;
634
635 case HAL_I2S_ERROR_CB_ID :
636 hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
637 break;
638
639 case HAL_I2S_MSPINIT_CB_ID :
640 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
641 break;
642
643 case HAL_I2S_MSPDEINIT_CB_ID :
644 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
645 break;
646
647 default :
648 /* Update the error code */
649 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
650
651 /* Return error status */
652 status = HAL_ERROR;
653 break;
654 }
655 }
656 else if (HAL_I2S_STATE_RESET == hi2s->State)
657 {
658 switch (CallbackID)
659 {
660 case HAL_I2S_MSPINIT_CB_ID :
661 hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
662 break;
663
664 case HAL_I2S_MSPDEINIT_CB_ID :
665 hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
666 break;
667
668 default :
669 /* Update the error code */
670 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
671
672 /* Return error status */
673 status = HAL_ERROR;
674 break;
675 }
676 }
677 else
678 {
679 /* Update the error code */
680 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
681
682 /* Return error status */
683 status = HAL_ERROR;
684 }
685
686 /* Release Lock */
687 __HAL_UNLOCK(hi2s);
688 return status;
689 }
690 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
691 /**
692 * @}
693 */
694
695 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
696 * @brief Data transfers functions
697 *
698 @verbatim
699 ===============================================================================
700 ##### IO operation functions #####
701 ===============================================================================
702 [..]
703 This subsection provides a set of functions allowing to manage the I2S data
704 transfers.
705
706 (#) There are two modes of transfer:
707 (++) Blocking mode : The communication is performed in the polling mode.
708 The status of all data processing is returned by the same function
709 after finishing transfer.
710 (++) No-Blocking mode : The communication is performed using Interrupts
711 or DMA. These functions return the status of the transfer startup.
712 The end of the data processing will be indicated through the
713 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
714 using DMA mode.
715
716 (#) Blocking mode functions are :
717 (++) HAL_I2S_Transmit()
718 (++) HAL_I2S_Receive()
719
720 (#) No-Blocking mode functions with Interrupt are :
721 (++) HAL_I2S_Transmit_IT()
722 (++) HAL_I2S_Receive_IT()
723
724 (#) No-Blocking mode functions with DMA are :
725 (++) HAL_I2S_Transmit_DMA()
726 (++) HAL_I2S_Receive_DMA()
727
728 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
729 (++) HAL_I2S_TxCpltCallback()
730 (++) HAL_I2S_RxCpltCallback()
731 (++) HAL_I2S_ErrorCallback()
732
733 @endverbatim
734 * @{
735 */
736
737 /**
738 * @brief Transmit an amount of data in blocking mode
739 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
740 * the configuration information for I2S module
741 * @param pData a 16-bit pointer to data buffer.
742 * @param Size number of data sample to be sent:
743 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
744 * configuration phase, the Size parameter means the number of 16-bit data length
745 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
746 * the Size parameter means the number of 24-bit or 32-bit data length.
747 * @param Timeout Timeout duration
748 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
749 * between Master and Slave(example: audio streaming).
750 * @retval HAL status
751 */
HAL_I2S_Transmit(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size,uint32_t Timeout)752 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
753 {
754 uint32_t tmpreg_cfgr;
755
756 if ((pData == NULL) || (Size == 0U))
757 {
758 return HAL_ERROR;
759 }
760
761 if (hi2s->State != HAL_I2S_STATE_READY)
762 {
763 return HAL_BUSY;
764 }
765
766 /* Process Locked */
767 __HAL_LOCK(hi2s);
768
769 /* Set state and reset error code */
770 hi2s->State = HAL_I2S_STATE_BUSY_TX;
771 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
772 hi2s->pTxBuffPtr = pData;
773
774 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
775
776 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
777 {
778 hi2s->TxXferSize = (Size << 1U);
779 hi2s->TxXferCount = (Size << 1U);
780 }
781 else
782 {
783 hi2s->TxXferSize = Size;
784 hi2s->TxXferCount = Size;
785 }
786
787 tmpreg_cfgr = hi2s->Instance->I2SCFGR;
788
789 /* Check if the I2S is already enabled */
790 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
791 {
792 /* Enable I2S peripheral */
793 __HAL_I2S_ENABLE(hi2s);
794 }
795
796 /* Wait until TXE flag is set */
797 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
798 {
799 /* Set the error code */
800 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
801 hi2s->State = HAL_I2S_STATE_READY;
802 __HAL_UNLOCK(hi2s);
803 return HAL_ERROR;
804 }
805
806 while (hi2s->TxXferCount > 0U)
807 {
808 hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
809 hi2s->pTxBuffPtr++;
810 hi2s->TxXferCount--;
811
812 /* Wait until TXE flag is set */
813 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
814 {
815 /* Set the error code */
816 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
817 hi2s->State = HAL_I2S_STATE_READY;
818 __HAL_UNLOCK(hi2s);
819 return HAL_ERROR;
820 }
821
822 /* Check if an underrun occurs */
823 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
824 {
825 /* Clear underrun flag */
826 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
827
828 /* Set the error code */
829 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
830 }
831 }
832
833 /* Check if Slave mode is selected */
834 if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
835 || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
836 {
837 /* Wait until Busy flag is reset */
838 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
839 {
840 /* Set the error code */
841 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
842 hi2s->State = HAL_I2S_STATE_READY;
843 __HAL_UNLOCK(hi2s);
844 return HAL_ERROR;
845 }
846 }
847
848 hi2s->State = HAL_I2S_STATE_READY;
849 __HAL_UNLOCK(hi2s);
850 return HAL_OK;
851 }
852
853 /**
854 * @brief Receive an amount of data in blocking mode
855 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
856 * the configuration information for I2S module
857 * @param pData a 16-bit pointer to data buffer.
858 * @param Size number of data sample to be sent:
859 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
860 * configuration phase, the Size parameter means the number of 16-bit data length
861 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
862 * the Size parameter means the number of 24-bit or 32-bit data length.
863 * @param Timeout Timeout duration
864 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
865 * between Master and Slave(example: audio streaming).
866 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
867 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
868 * @retval HAL status
869 */
HAL_I2S_Receive(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size,uint32_t Timeout)870 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
871 {
872 uint32_t tmpreg_cfgr;
873
874 if ((pData == NULL) || (Size == 0U))
875 {
876 return HAL_ERROR;
877 }
878
879 if (hi2s->State != HAL_I2S_STATE_READY)
880 {
881 return HAL_BUSY;
882 }
883
884 /* Process Locked */
885 __HAL_LOCK(hi2s);
886
887 /* Set state and reset error code */
888 hi2s->State = HAL_I2S_STATE_BUSY_RX;
889 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
890 hi2s->pRxBuffPtr = pData;
891
892 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
893
894 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
895 {
896 hi2s->RxXferSize = (Size << 1U);
897 hi2s->RxXferCount = (Size << 1U);
898 }
899 else
900 {
901 hi2s->RxXferSize = Size;
902 hi2s->RxXferCount = Size;
903 }
904
905 /* Check if the I2S is already enabled */
906 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
907 {
908 /* Enable I2S peripheral */
909 __HAL_I2S_ENABLE(hi2s);
910 }
911
912 /* Check if Master Receiver mode is selected */
913 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
914 {
915 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
916 access to the SPI_SR register. */
917 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
918 }
919
920 /* Receive data */
921 while (hi2s->RxXferCount > 0U)
922 {
923 /* Wait until RXNE flag is set */
924 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
925 {
926 /* Set the error code */
927 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
928 hi2s->State = HAL_I2S_STATE_READY;
929 __HAL_UNLOCK(hi2s);
930 return HAL_ERROR;
931 }
932
933 (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
934 hi2s->pRxBuffPtr++;
935 hi2s->RxXferCount--;
936
937 /* Check if an overrun occurs */
938 if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
939 {
940 /* Clear overrun flag */
941 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
942
943 /* Set the error code */
944 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
945 }
946 }
947
948 hi2s->State = HAL_I2S_STATE_READY;
949 __HAL_UNLOCK(hi2s);
950 return HAL_OK;
951 }
952
953 /**
954 * @brief Transmit an amount of data in non-blocking mode with Interrupt
955 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
956 * the configuration information for I2S module
957 * @param pData a 16-bit pointer to data buffer.
958 * @param Size number of data sample to be sent:
959 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
960 * configuration phase, the Size parameter means the number of 16-bit data length
961 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
962 * the Size parameter means the number of 24-bit or 32-bit data length.
963 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
964 * between Master and Slave(example: audio streaming).
965 * @retval HAL status
966 */
HAL_I2S_Transmit_IT(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)967 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
968 {
969 uint32_t tmpreg_cfgr;
970
971 if ((pData == NULL) || (Size == 0U))
972 {
973 return HAL_ERROR;
974 }
975
976 if (hi2s->State != HAL_I2S_STATE_READY)
977 {
978 return HAL_BUSY;
979 }
980
981 /* Process Locked */
982 __HAL_LOCK(hi2s);
983
984 /* Set state and reset error code */
985 hi2s->State = HAL_I2S_STATE_BUSY_TX;
986 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
987 hi2s->pTxBuffPtr = pData;
988
989 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
990
991 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
992 {
993 hi2s->TxXferSize = (Size << 1U);
994 hi2s->TxXferCount = (Size << 1U);
995 }
996 else
997 {
998 hi2s->TxXferSize = Size;
999 hi2s->TxXferCount = Size;
1000 }
1001
1002 __HAL_UNLOCK(hi2s);
1003
1004 /* Enable TXE and ERR interrupt */
1005 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1006
1007 /* Check if the I2S is already enabled */
1008 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
1009 {
1010 /* Enable I2S peripheral */
1011 __HAL_I2S_ENABLE(hi2s);
1012 }
1013
1014 return HAL_OK;
1015 }
1016
1017 /**
1018 * @brief Receive an amount of data in non-blocking mode with Interrupt
1019 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1020 * the configuration information for I2S module
1021 * @param pData a 16-bit pointer to the Receive data buffer.
1022 * @param Size number of data sample to be sent:
1023 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1024 * configuration phase, the Size parameter means the number of 16-bit data length
1025 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1026 * the Size parameter means the number of 24-bit or 32-bit data length.
1027 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1028 * between Master and Slave(example: audio streaming).
1029 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
1030 * between Master and Slave otherwise the I2S interrupt should be optimized.
1031 * @retval HAL status
1032 */
HAL_I2S_Receive_IT(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1033 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1034 {
1035 uint32_t tmpreg_cfgr;
1036
1037 if ((pData == NULL) || (Size == 0U))
1038 {
1039 return HAL_ERROR;
1040 }
1041
1042 if (hi2s->State != HAL_I2S_STATE_READY)
1043 {
1044 return HAL_BUSY;
1045 }
1046
1047 /* Process Locked */
1048 __HAL_LOCK(hi2s);
1049
1050 /* Set state and reset error code */
1051 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1052 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1053 hi2s->pRxBuffPtr = pData;
1054
1055 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
1056
1057 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
1058 {
1059 hi2s->RxXferSize = (Size << 1U);
1060 hi2s->RxXferCount = (Size << 1U);
1061 }
1062 else
1063 {
1064 hi2s->RxXferSize = Size;
1065 hi2s->RxXferCount = Size;
1066 }
1067
1068 __HAL_UNLOCK(hi2s);
1069
1070 /* Enable RXNE and ERR interrupt */
1071 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1072
1073 /* Check if the I2S is already enabled */
1074 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
1075 {
1076 /* Enable I2S peripheral */
1077 __HAL_I2S_ENABLE(hi2s);
1078 }
1079
1080 return HAL_OK;
1081 }
1082
1083 /**
1084 * @brief Transmit an amount of data in non-blocking mode with DMA
1085 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1086 * the configuration information for I2S module
1087 * @param pData a 16-bit pointer to the Transmit data buffer.
1088 * @param Size number of data sample to be sent:
1089 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1090 * configuration phase, the Size parameter means the number of 16-bit data length
1091 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1092 * the Size parameter means the number of 24-bit or 32-bit data length.
1093 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1094 * between Master and Slave(example: audio streaming).
1095 * @retval HAL status
1096 */
HAL_I2S_Transmit_DMA(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1097 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1098 {
1099 uint32_t tmpreg_cfgr;
1100
1101 if ((pData == NULL) || (Size == 0U))
1102 {
1103 return HAL_ERROR;
1104 }
1105
1106 if (hi2s->State != HAL_I2S_STATE_READY)
1107 {
1108 return HAL_BUSY;
1109 }
1110
1111 /* Process Locked */
1112 __HAL_LOCK(hi2s);
1113
1114 /* Set state and reset error code */
1115 hi2s->State = HAL_I2S_STATE_BUSY_TX;
1116 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1117 hi2s->pTxBuffPtr = pData;
1118
1119 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
1120
1121 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
1122 {
1123 hi2s->TxXferSize = (Size << 1U);
1124 hi2s->TxXferCount = (Size << 1U);
1125 }
1126 else
1127 {
1128 hi2s->TxXferSize = Size;
1129 hi2s->TxXferCount = Size;
1130 }
1131
1132 /* Set the I2S Tx DMA Half transfer complete callback */
1133 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
1134
1135 /* Set the I2S Tx DMA transfer complete callback */
1136 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
1137
1138 /* Set the DMA error callback */
1139 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
1140
1141 /* Enable the Tx DMA Stream/Channel */
1142 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
1143 (uint32_t)hi2s->pTxBuffPtr,
1144 (uint32_t)&hi2s->Instance->DR,
1145 hi2s->TxXferSize))
1146 {
1147 /* Update SPI error code */
1148 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1149 hi2s->State = HAL_I2S_STATE_READY;
1150
1151 __HAL_UNLOCK(hi2s);
1152 return HAL_ERROR;
1153 }
1154
1155 __HAL_UNLOCK(hi2s);
1156
1157 /* Check if the I2S Tx request is already enabled */
1158 if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
1159 {
1160 /* Enable Tx DMA Request */
1161 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1162 }
1163
1164 /* Check if the I2S is already enabled */
1165 if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
1166 {
1167 /* Enable I2S peripheral */
1168 __HAL_I2S_ENABLE(hi2s);
1169 }
1170
1171 return HAL_OK;
1172 }
1173
1174 /**
1175 * @brief Receive an amount of data in non-blocking mode with DMA
1176 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1177 * the configuration information for I2S module
1178 * @param pData a 16-bit pointer to the Receive data buffer.
1179 * @param Size number of data sample to be sent:
1180 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
1181 * configuration phase, the Size parameter means the number of 16-bit data length
1182 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
1183 * the Size parameter means the number of 24-bit or 32-bit data length.
1184 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
1185 * between Master and Slave(example: audio streaming).
1186 * @retval HAL status
1187 */
HAL_I2S_Receive_DMA(I2S_HandleTypeDef * hi2s,uint16_t * pData,uint16_t Size)1188 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
1189 {
1190 uint32_t tmpreg_cfgr;
1191
1192 if ((pData == NULL) || (Size == 0U))
1193 {
1194 return HAL_ERROR;
1195 }
1196
1197 if (hi2s->State != HAL_I2S_STATE_READY)
1198 {
1199 return HAL_BUSY;
1200 }
1201
1202 /* Process Locked */
1203 __HAL_LOCK(hi2s);
1204
1205 /* Set state and reset error code */
1206 hi2s->State = HAL_I2S_STATE_BUSY_RX;
1207 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
1208 hi2s->pRxBuffPtr = pData;
1209
1210 tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
1211
1212 if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
1213 {
1214 hi2s->RxXferSize = (Size << 1U);
1215 hi2s->RxXferCount = (Size << 1U);
1216 }
1217 else
1218 {
1219 hi2s->RxXferSize = Size;
1220 hi2s->RxXferCount = Size;
1221 }
1222
1223 /* Set the I2S Rx DMA Half transfer complete callback */
1224 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
1225
1226 /* Set the I2S Rx DMA transfer complete callback */
1227 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
1228
1229 /* Set the DMA error callback */
1230 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
1231
1232 /* Check if Master Receiver mode is selected */
1233 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
1234 {
1235 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
1236 access to the SPI_SR register. */
1237 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1238 }
1239
1240 /* Enable the Rx DMA Stream/Channel */
1241 if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
1242 hi2s->RxXferSize))
1243 {
1244 /* Update SPI error code */
1245 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1246 hi2s->State = HAL_I2S_STATE_READY;
1247
1248 __HAL_UNLOCK(hi2s);
1249 return HAL_ERROR;
1250 }
1251
1252 __HAL_UNLOCK(hi2s);
1253
1254 /* Check if the I2S Rx request is already enabled */
1255 if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
1256 {
1257 /* Enable Rx DMA Request */
1258 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1259 }
1260
1261 /* Check if the I2S is already enabled */
1262 if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
1263 {
1264 /* Enable I2S peripheral */
1265 __HAL_I2S_ENABLE(hi2s);
1266 }
1267
1268 return HAL_OK;
1269 }
1270
1271 /**
1272 * @brief Pauses the audio DMA Stream/Channel playing from the Media.
1273 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1274 * the configuration information for I2S module
1275 * @retval HAL status
1276 */
HAL_I2S_DMAPause(I2S_HandleTypeDef * hi2s)1277 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
1278 {
1279 /* Process Locked */
1280 __HAL_LOCK(hi2s);
1281
1282 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
1283 {
1284 /* Disable the I2S DMA Tx request */
1285 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1286 }
1287 else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
1288 {
1289 /* Disable the I2S DMA Rx request */
1290 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1291 }
1292 else
1293 {
1294 /* nothing to do */
1295 }
1296
1297 /* Process Unlocked */
1298 __HAL_UNLOCK(hi2s);
1299
1300 return HAL_OK;
1301 }
1302
1303 /**
1304 * @brief Resumes the audio DMA Stream/Channel playing from the Media.
1305 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1306 * the configuration information for I2S module
1307 * @retval HAL status
1308 */
HAL_I2S_DMAResume(I2S_HandleTypeDef * hi2s)1309 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
1310 {
1311 /* Process Locked */
1312 __HAL_LOCK(hi2s);
1313
1314 if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
1315 {
1316 /* Enable the I2S DMA Tx request */
1317 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1318 }
1319 else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
1320 {
1321 /* Enable the I2S DMA Rx request */
1322 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1323 }
1324 else
1325 {
1326 /* nothing to do */
1327 }
1328
1329 /* If the I2S peripheral is still not enabled, enable it */
1330 if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
1331 {
1332 /* Enable I2S peripheral */
1333 __HAL_I2S_ENABLE(hi2s);
1334 }
1335
1336 /* Process Unlocked */
1337 __HAL_UNLOCK(hi2s);
1338
1339 return HAL_OK;
1340 }
1341
1342 /**
1343 * @brief Stops the audio DMA Stream/Channel playing from the Media.
1344 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1345 * the configuration information for I2S module
1346 * @retval HAL status
1347 */
HAL_I2S_DMAStop(I2S_HandleTypeDef * hi2s)1348 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
1349 {
1350 HAL_StatusTypeDef errorcode = HAL_OK;
1351 /* The Lock is not implemented on this API to allow the user application
1352 to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1353 when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
1354 and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
1355 */
1356
1357 if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
1358 {
1359 /* Abort the I2S DMA tx Stream/Channel */
1360 if (hi2s->hdmatx != NULL)
1361 {
1362 /* Disable the I2S DMA tx Stream/Channel */
1363 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
1364 {
1365 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1366 errorcode = HAL_ERROR;
1367 }
1368 }
1369
1370 /* Wait until TXE flag is set */
1371 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK)
1372 {
1373 /* Set the error code */
1374 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1375 hi2s->State = HAL_I2S_STATE_READY;
1376 errorcode = HAL_ERROR;
1377 }
1378
1379 /* Wait until BSY flag is Reset */
1380 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK)
1381 {
1382 /* Set the error code */
1383 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
1384 hi2s->State = HAL_I2S_STATE_READY;
1385 errorcode = HAL_ERROR;
1386 }
1387
1388 /* Disable I2S peripheral */
1389 __HAL_I2S_DISABLE(hi2s);
1390
1391 /* Clear UDR flag */
1392 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
1393
1394 /* Disable the I2S Tx DMA requests */
1395 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1396
1397 }
1398
1399 else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
1400 {
1401 /* Abort the I2S DMA rx Stream/Channel */
1402 if (hi2s->hdmarx != NULL)
1403 {
1404 /* Disable the I2S DMA rx Stream/Channel */
1405 if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
1406 {
1407 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1408 errorcode = HAL_ERROR;
1409 }
1410 }
1411
1412 /* Disable I2S peripheral */
1413 __HAL_I2S_DISABLE(hi2s);
1414
1415 /* Clear OVR flag */
1416 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
1417
1418 /* Disable the I2S Rx DMA request */
1419 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1420
1421 if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)
1422 {
1423 /* Set the error code */
1424 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX);
1425
1426 /* Set the I2S State ready */
1427 hi2s->State = HAL_I2S_STATE_READY;
1428 errorcode = HAL_ERROR;
1429 }
1430 else
1431 {
1432 /* Read DR to Flush RX Data */
1433 READ_REG((hi2s->Instance)->DR);
1434 }
1435 }
1436
1437 hi2s->State = HAL_I2S_STATE_READY;
1438
1439 return errorcode;
1440 }
1441
1442 /**
1443 * @brief This function handles I2S interrupt request.
1444 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1445 * the configuration information for I2S module
1446 * @retval None
1447 */
HAL_I2S_IRQHandler(I2S_HandleTypeDef * hi2s)1448 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1449 {
1450 uint32_t itsource = hi2s->Instance->CR2;
1451 uint32_t itflag = hi2s->Instance->SR;
1452
1453 /* I2S in mode Receiver ------------------------------------------------*/
1454 if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
1455 (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
1456 {
1457 I2S_Receive_IT(hi2s);
1458 return;
1459 }
1460
1461 /* I2S in mode Tramitter -----------------------------------------------*/
1462 if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
1463 {
1464 I2S_Transmit_IT(hi2s);
1465 return;
1466 }
1467
1468 /* I2S interrupt error -------------------------------------------------*/
1469 if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
1470 {
1471 /* I2S Overrun error interrupt occurred ---------------------------------*/
1472 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
1473 {
1474 /* Disable RXNE and ERR interrupt */
1475 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1476
1477 /* Set the error code and execute error callback*/
1478 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
1479 }
1480
1481 /* I2S Underrun error interrupt occurred --------------------------------*/
1482 if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
1483 {
1484 /* Disable TXE and ERR interrupt */
1485 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1486
1487 /* Set the error code and execute error callback*/
1488 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
1489 }
1490
1491 /* Set the I2S State ready */
1492 hi2s->State = HAL_I2S_STATE_READY;
1493
1494 /* Call user error callback */
1495 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1496 hi2s->ErrorCallback(hi2s);
1497 #else
1498 HAL_I2S_ErrorCallback(hi2s);
1499 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1500 }
1501 }
1502
1503 /**
1504 * @brief Tx Transfer Half completed callbacks
1505 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1506 * the configuration information for I2S module
1507 * @retval None
1508 */
HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef * hi2s)1509 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1510 {
1511 /* Prevent unused argument(s) compilation warning */
1512 UNUSED(hi2s);
1513
1514 /* NOTE : This function Should not be modified, when the callback is needed,
1515 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
1516 */
1517 }
1518
1519 /**
1520 * @brief Tx Transfer completed callbacks
1521 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1522 * the configuration information for I2S module
1523 * @retval None
1524 */
HAL_I2S_TxCpltCallback(I2S_HandleTypeDef * hi2s)1525 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1526 {
1527 /* Prevent unused argument(s) compilation warning */
1528 UNUSED(hi2s);
1529
1530 /* NOTE : This function Should not be modified, when the callback is needed,
1531 the HAL_I2S_TxCpltCallback could be implemented in the user file
1532 */
1533 }
1534
1535 /**
1536 * @brief Rx Transfer half completed callbacks
1537 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1538 * the configuration information for I2S module
1539 * @retval None
1540 */
HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef * hi2s)1541 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1542 {
1543 /* Prevent unused argument(s) compilation warning */
1544 UNUSED(hi2s);
1545
1546 /* NOTE : This function Should not be modified, when the callback is needed,
1547 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
1548 */
1549 }
1550
1551 /**
1552 * @brief Rx Transfer completed callbacks
1553 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1554 * the configuration information for I2S module
1555 * @retval None
1556 */
HAL_I2S_RxCpltCallback(I2S_HandleTypeDef * hi2s)1557 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
1558 {
1559 /* Prevent unused argument(s) compilation warning */
1560 UNUSED(hi2s);
1561
1562 /* NOTE : This function Should not be modified, when the callback is needed,
1563 the HAL_I2S_RxCpltCallback could be implemented in the user file
1564 */
1565 }
1566
1567 /**
1568 * @brief I2S error callbacks
1569 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1570 * the configuration information for I2S module
1571 * @retval None
1572 */
HAL_I2S_ErrorCallback(I2S_HandleTypeDef * hi2s)1573 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
1574 {
1575 /* Prevent unused argument(s) compilation warning */
1576 UNUSED(hi2s);
1577
1578 /* NOTE : This function Should not be modified, when the callback is needed,
1579 the HAL_I2S_ErrorCallback could be implemented in the user file
1580 */
1581 }
1582
1583 /**
1584 * @}
1585 */
1586
1587 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
1588 * @brief Peripheral State functions
1589 *
1590 @verbatim
1591 ===============================================================================
1592 ##### Peripheral State and Errors functions #####
1593 ===============================================================================
1594 [..]
1595 This subsection permits to get in run-time the status of the peripheral
1596 and the data flow.
1597
1598 @endverbatim
1599 * @{
1600 */
1601
1602 /**
1603 * @brief Return the I2S state
1604 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1605 * the configuration information for I2S module
1606 * @retval HAL state
1607 */
HAL_I2S_GetState(I2S_HandleTypeDef * hi2s)1608 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
1609 {
1610 return hi2s->State;
1611 }
1612
1613 /**
1614 * @brief Return the I2S error code
1615 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1616 * the configuration information for I2S module
1617 * @retval I2S Error Code
1618 */
HAL_I2S_GetError(I2S_HandleTypeDef * hi2s)1619 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
1620 {
1621 return hi2s->ErrorCode;
1622 }
1623 /**
1624 * @}
1625 */
1626
1627 /**
1628 * @}
1629 */
1630
1631 /** @addtogroup I2S_Private_Functions I2S Private Functions
1632 * @{
1633 */
1634 /**
1635 * @brief DMA I2S transmit process complete callback
1636 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1637 * the configuration information for the specified DMA module.
1638 * @retval None
1639 */
I2S_DMATxCplt(DMA_HandleTypeDef * hdma)1640 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
1641 {
1642 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1643
1644 /* if DMA is configured in DMA_NORMAL Mode */
1645 if (hdma->Init.Mode == DMA_NORMAL)
1646 {
1647 /* Disable Tx DMA Request */
1648 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
1649
1650 hi2s->TxXferCount = 0U;
1651 hi2s->State = HAL_I2S_STATE_READY;
1652 }
1653 /* Call user Tx complete callback */
1654 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1655 hi2s->TxCpltCallback(hi2s);
1656 #else
1657 HAL_I2S_TxCpltCallback(hi2s);
1658 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1659 }
1660
1661 /**
1662 * @brief DMA I2S transmit process half complete callback
1663 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1664 * the configuration information for the specified DMA module.
1665 * @retval None
1666 */
I2S_DMATxHalfCplt(DMA_HandleTypeDef * hdma)1667 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1668 {
1669 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1670
1671 /* Call user Tx half complete callback */
1672 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1673 hi2s->TxHalfCpltCallback(hi2s);
1674 #else
1675 HAL_I2S_TxHalfCpltCallback(hi2s);
1676 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1677 }
1678
1679 /**
1680 * @brief DMA I2S receive process complete callback
1681 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1682 * the configuration information for the specified DMA module.
1683 * @retval None
1684 */
I2S_DMARxCplt(DMA_HandleTypeDef * hdma)1685 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
1686 {
1687 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1688
1689 /* if DMA is configured in DMA_NORMAL Mode */
1690 if (hdma->Init.Mode == DMA_NORMAL)
1691 {
1692 /* Disable Rx DMA Request */
1693 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
1694 hi2s->RxXferCount = 0U;
1695 hi2s->State = HAL_I2S_STATE_READY;
1696 }
1697 /* Call user Rx complete callback */
1698 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1699 hi2s->RxCpltCallback(hi2s);
1700 #else
1701 HAL_I2S_RxCpltCallback(hi2s);
1702 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1703 }
1704
1705 /**
1706 * @brief DMA I2S receive process half complete callback
1707 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1708 * the configuration information for the specified DMA module.
1709 * @retval None
1710 */
I2S_DMARxHalfCplt(DMA_HandleTypeDef * hdma)1711 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1712 {
1713 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1714
1715 /* Call user Rx half complete callback */
1716 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1717 hi2s->RxHalfCpltCallback(hi2s);
1718 #else
1719 HAL_I2S_RxHalfCpltCallback(hi2s);
1720 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1721 }
1722
1723 /**
1724 * @brief DMA I2S communication error callback
1725 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1726 * the configuration information for the specified DMA module.
1727 * @retval None
1728 */
I2S_DMAError(DMA_HandleTypeDef * hdma)1729 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
1730 {
1731 I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
1732
1733 /* Disable Rx and Tx DMA Request */
1734 CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
1735 hi2s->TxXferCount = 0U;
1736 hi2s->RxXferCount = 0U;
1737
1738 hi2s->State = HAL_I2S_STATE_READY;
1739
1740 /* Set the error code and execute error callback*/
1741 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
1742 /* Call user error callback */
1743 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1744 hi2s->ErrorCallback(hi2s);
1745 #else
1746 HAL_I2S_ErrorCallback(hi2s);
1747 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1748 }
1749
1750 /**
1751 * @brief Transmit an amount of data in non-blocking mode with Interrupt
1752 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1753 * the configuration information for I2S module
1754 * @retval None
1755 */
I2S_Transmit_IT(I2S_HandleTypeDef * hi2s)1756 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
1757 {
1758 /* Transmit data */
1759 hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
1760 hi2s->pTxBuffPtr++;
1761 hi2s->TxXferCount--;
1762
1763 if (hi2s->TxXferCount == 0U)
1764 {
1765 /* Disable TXE and ERR interrupt */
1766 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1767
1768 hi2s->State = HAL_I2S_STATE_READY;
1769 /* Call user Tx complete callback */
1770 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1771 hi2s->TxCpltCallback(hi2s);
1772 #else
1773 HAL_I2S_TxCpltCallback(hi2s);
1774 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1775 }
1776 }
1777
1778 /**
1779 * @brief Receive an amount of data in non-blocking mode with Interrupt
1780 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1781 * the configuration information for I2S module
1782 * @retval None
1783 */
I2S_Receive_IT(I2S_HandleTypeDef * hi2s)1784 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
1785 {
1786 /* Receive data */
1787 (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
1788 hi2s->pRxBuffPtr++;
1789 hi2s->RxXferCount--;
1790
1791 if (hi2s->RxXferCount == 0U)
1792 {
1793 /* Disable RXNE and ERR interrupt */
1794 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1795
1796 hi2s->State = HAL_I2S_STATE_READY;
1797 /* Call user Rx complete callback */
1798 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
1799 hi2s->RxCpltCallback(hi2s);
1800 #else
1801 HAL_I2S_RxCpltCallback(hi2s);
1802 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
1803 }
1804 }
1805
1806 /**
1807 * @brief This function handles I2S Communication Timeout.
1808 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
1809 * the configuration information for I2S module
1810 * @param Flag Flag checked
1811 * @param State Value of the flag expected
1812 * @param Timeout Duration of the timeout
1813 * @retval HAL status
1814 */
I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef * hi2s,uint32_t Flag,FlagStatus State,uint32_t Timeout)1815 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
1816 uint32_t Timeout)
1817 {
1818 uint32_t tickstart;
1819
1820 /* Get tick */
1821 tickstart = HAL_GetTick();
1822
1823 /* Wait until flag is set to status*/
1824 while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
1825 {
1826 if (Timeout != HAL_MAX_DELAY)
1827 {
1828 if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
1829 {
1830 /* Set the I2S State ready */
1831 hi2s->State = HAL_I2S_STATE_READY;
1832
1833 /* Process Unlocked */
1834 __HAL_UNLOCK(hi2s);
1835
1836 return HAL_TIMEOUT;
1837 }
1838 }
1839 }
1840 return HAL_OK;
1841 }
1842
1843 /**
1844 * @}
1845 */
1846
1847 /**
1848 * @}
1849 */
1850
1851 /**
1852 * @}
1853 */
1854 #endif /* SPI_I2S_SUPPORT */
1855
1856 #endif /* HAL_I2S_MODULE_ENABLED */
1857
1858
