1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 (+) Access to VREFBUF registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32G4xx_LL_SYSTEM_H
35 #define __STM32G4xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32g4xx.h"
43
44 /** @addtogroup STM32G4xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /* Defines used for position in the register */
63 #define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
64
65 /**
66 * @brief Power-down in Run mode Flash key
67 */
68 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
69 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
70 to unlock the RUN_PD bit in FLASH_ACR */
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77
78 /* Exported types ------------------------------------------------------------*/
79 /* Exported constants --------------------------------------------------------*/
80 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
81 * @{
82 */
83
84 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
85 * @{
86 */
87 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
88 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
89 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
90 #if defined(FMC_Bank1_R)
91 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
92 #endif /* FMC_Bank1_R */
93 #define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
94 /**
95 * @}
96 */
97
98 #if defined(SYSCFG_MEMRMP_FB_MODE)
99 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
100 * @{
101 */
102 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
103 and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00080000) */
104 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
105 and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00080000) */
106 /**
107 * @}
108 */
109
110 #endif /* SYSCFG_MEMRMP_FB_MODE */
111 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
112 * @{
113 */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
116 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
117 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
118 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
119 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
120 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
121 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
123 #if defined(I2C2)
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
125 #endif /* I2C2 */
126 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
127 #if defined(I2C4)
128 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
129 #endif /* I2C4 */
130 /**
131 * @}
132 */
133
134 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
135 * @{
136 */
137 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
138 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
139 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
140 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
141 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
142 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
143 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
144 /**
145 * @}
146 */
147
148 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
149 * @{
150 */
151 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
152 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
153 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
154 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
155 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
156 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
157 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
158 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
159 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
160 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
161 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
162 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
163 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
164 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
165 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
166 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
167 /**
168 * @}
169 */
170
171 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
172 * @{
173 */
174 #define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
175 with Break Input of TIM1/8/15/16/17 */
176 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
177 with TIM1/8/15/16/17 Break Input
178 and also the PVDE and PLS bits of the Power Control Interface */
179 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal
180 with Break Input of TIM1/8/15/16/17 */
181 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
182 with Break Input of TIM1/15/16/17 */
183 /**
184 * @}
185 */
186
187 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
188 * @{
189 */
190 #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
191 #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
192 #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
193 #define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
194 #define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
195 #define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
196 #define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
197 #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
198 #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
199 #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
200 #if defined(SYSCFG_SWPR_PAGE10)
201 #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
202 #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
203 #define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
204 #define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
205 #define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
206 #define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
207 #define LL_SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
208 #define LL_SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
209 #define LL_SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
210 #define LL_SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
211 #endif /* SYSCFG_SWPR_PAGE10 */
212 #if defined(SYSCFG_SWPR_PAGE20)
213 #define LL_SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
214 #define LL_SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
215 #define LL_SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
216 #define LL_SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
217 #define LL_SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
218 #define LL_SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
219 #define LL_SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
220 #define LL_SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
221 #define LL_SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
222 #define LL_SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
223 #define LL_SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
224 #define LL_SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
225 #endif /* SYSCFG_SWPR_PAGE20 */
226 /**
227 * @}
228 */
229
230 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
231 * @{
232 */
233 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
234 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
235 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
236 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
237 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
238 /**
239 * @}
240 */
241
242 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
243 * @{
244 */
245 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
246 #if defined(TIM3)
247 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
248 #endif /* TIM3 */
249 #if defined(TIM4)
250 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
251 #endif /* TIM4 */
252 #if defined(TIM5)
253 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
254 #endif /* TIM5 */
255 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
256 #if defined(TIM7)
257 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
258 #endif /* TIM7 */
259 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
260 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
261 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
262 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
263 #if defined(I2C2)
264 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
265 #endif /* I2C2 */
266 #if defined(I2C3)
267 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
268 #endif /* I2C3 */
269 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
270 /**
271 * @}
272 */
273
274 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
275 * @{
276 */
277 #if defined(I2C4)
278 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
279 #endif /* I2C4 */
280 /**
281 * @}
282 */
283
284 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
285 * @{
286 */
287 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
288 #if defined(TIM8)
289 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
290 #endif /* TIM8 */
291 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
292 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
293 #if defined(TIM17)
294 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
295 #endif /* TIM17 */
296 #if defined(TIM20)
297 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP /*!< The counter clock of TIM20 is stopped when the core is halted*/
298 #endif /* TIM20 */
299 #if defined(HRTIM1)
300 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2FZ_DBG_HRTIM1_STOP /*!< The counter clock of HRTIM1 is stopped when the core is halted*/
301 #endif /* HRTIM1 */
302 /**
303 * @}
304 */
305
306 #if defined(VREFBUF)
307 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
308 * @{
309 */
310 #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
311 #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
312 #define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
313 /**
314 * @}
315 */
316 #endif /* VREFBUF */
317
318 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
319 * @{
320 */
321 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
322 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
323 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
324 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
325 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
326 #if defined(FLASH_ACR_LATENCY_5WS)
327 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
328 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
329 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
330 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
331 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
332 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
333 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
334 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
335 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
336 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
337 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
338 #endif /* FLASH_ACR_LATENCY_5WS */
339 /**
340 * @}
341 */
342
343 /**
344 * @}
345 */
346
347 /* Exported macro ------------------------------------------------------------*/
348
349 /* Exported functions --------------------------------------------------------*/
350 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
351 * @{
352 */
353
354 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
355 * @{
356 */
357
358 /**
359 * @brief Set memory mapping at address 0x00000000
360 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
361 * @param Memory This parameter can be one of the following values:
362 * @arg @ref LL_SYSCFG_REMAP_FLASH
363 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
364 * @arg @ref LL_SYSCFG_REMAP_SRAM
365 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
366 * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
367 *
368 * (*) value not defined in all devices
369 * @retval None
370 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)371 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
372 {
373 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
374 }
375
376 /**
377 * @brief Get memory mapping at address 0x00000000
378 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
379 * @retval Returned value can be one of the following values:
380 * @arg @ref LL_SYSCFG_REMAP_FLASH
381 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
382 * @arg @ref LL_SYSCFG_REMAP_SRAM
383 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
384 * @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
385 *
386 * (*) value not defined in all devices
387 */
LL_SYSCFG_GetRemapMemory(void)388 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
389 {
390 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
391 }
392
393 #if defined(SYSCFG_MEMRMP_FB_MODE)
394 /**
395 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
396 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
397 * @param Bank This parameter can be one of the following values:
398 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
399 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
400 * @retval None
401 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)402 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
403 {
404 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
405 }
406
407 /**
408 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
409 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
410 * @retval Returned value can be one of the following values:
411 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
412 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
413 */
LL_SYSCFG_GetFlashBankMode(void)414 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
415 {
416 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
417 }
418 #endif /* SYSCFG_MEMRMP_FB_MODE */
419
420 /**
421 * @brief Enable I/O analog switch voltage booster.
422 * @note When voltage booster is enabled, I/O analog switches are supplied
423 * by a dedicated voltage booster, from VDD power domain. This is
424 * the recommended configuration with low VDDA voltage operation.
425 * @note The I/O analog switch voltage booster is relevant for peripherals
426 * using I/O in analog input: ADC, COMP, OPAMP.
427 * However, COMP and OPAMP inputs have a high impedance and
428 * voltage booster do not impact performance significantly.
429 * Therefore, the voltage booster is mainly intended for
430 * usage with ADC.
431 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
432 * @retval None
433 */
LL_SYSCFG_EnableAnalogBooster(void)434 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
435 {
436 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
437 }
438
439 /**
440 * @brief Disable I/O analog switch voltage booster.
441 * @note When voltage booster is enabled, I/O analog switches are supplied
442 * by a dedicated voltage booster, from VDD power domain. This is
443 * the recommended configuration with low VDDA voltage operation.
444 * @note The I/O analog switch voltage booster is relevant for peripherals
445 * using I/O in analog input: ADC, COMP, OPAMP.
446 * However, COMP and OPAMP inputs have a high impedance and
447 * voltage booster do not impact performance significantly.
448 * Therefore, the voltage booster is mainly intended for
449 * usage with ADC.
450 * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
451 * @retval None
452 */
LL_SYSCFG_DisableAnalogBooster(void)453 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
454 {
455 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
456 }
457
458 /**
459 * @brief Enable the I2C fast mode plus driving capability.
460 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
461 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
462 * @param ConfigFastModePlus This parameter can be a combination of the following values:
463 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
464 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
465 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
466 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
467 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
468 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
469 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
470 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
471 *
472 * (*) value not defined in all devices
473 * @retval None
474 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)475 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
476 {
477 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
478 }
479
480 /**
481 * @brief Disable the I2C fast mode plus driving capability.
482 * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
483 * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
484 * @param ConfigFastModePlus This parameter can be a combination of the following values:
485 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
486 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
487 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
488 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
489 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
490 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
491 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
492 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
493 *
494 * (*) value not defined in all devices
495 * @retval None
496 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)497 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
498 {
499 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
500 }
501
502 /**
503 * @brief Enable Floating Point Unit Invalid operation Interrupt
504 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
505 * @retval None
506 */
LL_SYSCFG_EnableIT_FPU_IOC(void)507 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
508 {
509 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
510 }
511
512 /**
513 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
514 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
515 * @retval None
516 */
LL_SYSCFG_EnableIT_FPU_DZC(void)517 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
518 {
519 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
520 }
521
522 /**
523 * @brief Enable Floating Point Unit Underflow Interrupt
524 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
525 * @retval None
526 */
LL_SYSCFG_EnableIT_FPU_UFC(void)527 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
528 {
529 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
530 }
531
532 /**
533 * @brief Enable Floating Point Unit Overflow Interrupt
534 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
535 * @retval None
536 */
LL_SYSCFG_EnableIT_FPU_OFC(void)537 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
538 {
539 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
540 }
541
542 /**
543 * @brief Enable Floating Point Unit Input denormal Interrupt
544 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
545 * @retval None
546 */
LL_SYSCFG_EnableIT_FPU_IDC(void)547 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
548 {
549 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
550 }
551
552 /**
553 * @brief Enable Floating Point Unit Inexact Interrupt
554 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
555 * @retval None
556 */
LL_SYSCFG_EnableIT_FPU_IXC(void)557 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
558 {
559 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
560 }
561
562 /**
563 * @brief Disable Floating Point Unit Invalid operation Interrupt
564 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
565 * @retval None
566 */
LL_SYSCFG_DisableIT_FPU_IOC(void)567 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
568 {
569 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
570 }
571
572 /**
573 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
574 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
575 * @retval None
576 */
LL_SYSCFG_DisableIT_FPU_DZC(void)577 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
578 {
579 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
580 }
581
582 /**
583 * @brief Disable Floating Point Unit Underflow Interrupt
584 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
585 * @retval None
586 */
LL_SYSCFG_DisableIT_FPU_UFC(void)587 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
588 {
589 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
590 }
591
592 /**
593 * @brief Disable Floating Point Unit Overflow Interrupt
594 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
595 * @retval None
596 */
LL_SYSCFG_DisableIT_FPU_OFC(void)597 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
598 {
599 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
600 }
601
602 /**
603 * @brief Disable Floating Point Unit Input denormal Interrupt
604 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
605 * @retval None
606 */
LL_SYSCFG_DisableIT_FPU_IDC(void)607 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
608 {
609 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
610 }
611
612 /**
613 * @brief Disable Floating Point Unit Inexact Interrupt
614 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
615 * @retval None
616 */
LL_SYSCFG_DisableIT_FPU_IXC(void)617 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
618 {
619 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
620 }
621
622 /**
623 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
624 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
625 * @retval State of bit (1 or 0).
626 */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)627 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
628 {
629 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
630 }
631
632 /**
633 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
634 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
635 * @retval State of bit (1 or 0).
636 */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)637 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
638 {
639 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
640 }
641
642 /**
643 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
644 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
645 * @retval State of bit (1 or 0).
646 */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)647 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
648 {
649 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
650 }
651
652 /**
653 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
654 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
655 * @retval State of bit (1 or 0).
656 */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)657 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
658 {
659 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
660 }
661
662 /**
663 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
664 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
665 * @retval State of bit (1 or 0).
666 */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)667 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
668 {
669 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
670 }
671
672 /**
673 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
674 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
675 * @retval State of bit (1 or 0).
676 */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)677 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
678 {
679 return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
680 }
681
682 /**
683 * @brief Configure source input for the EXTI external interrupt.
684 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
685 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
686 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
687 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
688 * @param Port This parameter can be one of the following values:
689 * @arg @ref LL_SYSCFG_EXTI_PORTA
690 * @arg @ref LL_SYSCFG_EXTI_PORTB
691 * @arg @ref LL_SYSCFG_EXTI_PORTC
692 * @arg @ref LL_SYSCFG_EXTI_PORTD
693 * @arg @ref LL_SYSCFG_EXTI_PORTE
694 * @arg @ref LL_SYSCFG_EXTI_PORTF
695 * @arg @ref LL_SYSCFG_EXTI_PORTG
696 *
697 * (*) value not defined in all devices
698 * @param Line This parameter can be one of the following values:
699 * @arg @ref LL_SYSCFG_EXTI_LINE0
700 * @arg @ref LL_SYSCFG_EXTI_LINE1
701 * @arg @ref LL_SYSCFG_EXTI_LINE2
702 * @arg @ref LL_SYSCFG_EXTI_LINE3
703 * @arg @ref LL_SYSCFG_EXTI_LINE4
704 * @arg @ref LL_SYSCFG_EXTI_LINE5
705 * @arg @ref LL_SYSCFG_EXTI_LINE6
706 * @arg @ref LL_SYSCFG_EXTI_LINE7
707 * @arg @ref LL_SYSCFG_EXTI_LINE8
708 * @arg @ref LL_SYSCFG_EXTI_LINE9
709 * @arg @ref LL_SYSCFG_EXTI_LINE10
710 * @arg @ref LL_SYSCFG_EXTI_LINE11
711 * @arg @ref LL_SYSCFG_EXTI_LINE12
712 * @arg @ref LL_SYSCFG_EXTI_LINE13
713 * @arg @ref LL_SYSCFG_EXTI_LINE14
714 * @arg @ref LL_SYSCFG_EXTI_LINE15
715 * @retval None
716 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)717 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
718 {
719 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << (POSITION_VAL((Line >> 16U)) & 0x1FU) );
720 }
721
722 /**
723 * @brief Get the configured defined for specific EXTI Line
724 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
725 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
726 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
727 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
728 * @param Line This parameter can be one of the following values:
729 * @arg @ref LL_SYSCFG_EXTI_LINE0
730 * @arg @ref LL_SYSCFG_EXTI_LINE1
731 * @arg @ref LL_SYSCFG_EXTI_LINE2
732 * @arg @ref LL_SYSCFG_EXTI_LINE3
733 * @arg @ref LL_SYSCFG_EXTI_LINE4
734 * @arg @ref LL_SYSCFG_EXTI_LINE5
735 * @arg @ref LL_SYSCFG_EXTI_LINE6
736 * @arg @ref LL_SYSCFG_EXTI_LINE7
737 * @arg @ref LL_SYSCFG_EXTI_LINE8
738 * @arg @ref LL_SYSCFG_EXTI_LINE9
739 * @arg @ref LL_SYSCFG_EXTI_LINE10
740 * @arg @ref LL_SYSCFG_EXTI_LINE11
741 * @arg @ref LL_SYSCFG_EXTI_LINE12
742 * @arg @ref LL_SYSCFG_EXTI_LINE13
743 * @arg @ref LL_SYSCFG_EXTI_LINE14
744 * @arg @ref LL_SYSCFG_EXTI_LINE15
745 * @retval Returned value can be one of the following values:
746 * @arg @ref LL_SYSCFG_EXTI_PORTA
747 * @arg @ref LL_SYSCFG_EXTI_PORTB
748 * @arg @ref LL_SYSCFG_EXTI_PORTC
749 * @arg @ref LL_SYSCFG_EXTI_PORTD
750 * @arg @ref LL_SYSCFG_EXTI_PORTE
751 * @arg @ref LL_SYSCFG_EXTI_PORTF
752 * @arg @ref LL_SYSCFG_EXTI_PORTG
753 *
754 * (*) value not defined in all devices
755 */
LL_SYSCFG_GetEXTISource(uint32_t Line)756 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
757 {
758 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU));
759 }
760
761 /**
762 * @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is
763 * automatically cleared at the end of the CCMSRAM erase operation.)
764 * @note This bit is write-protected: setting this bit is possible only after the
765 * correct key sequence is written in the SYSCFG_SKR register as described in
766 * the Reference Manual.
767 * @rmtoll SYSCFG_SCSR CCMER LL_SYSCFG_EnableCCMSRAMErase
768 * @retval None
769 */
LL_SYSCFG_EnableCCMSRAMErase(void)770 __STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void)
771 {
772 /* Starts a hardware CCMSRAM erase operation*/
773 SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
774 }
775
776 /**
777 * @brief Check if CCMSRAM erase operation is on going
778 * @rmtoll SYSCFG_SCSR CCMBSY LL_SYSCFG_IsCCMSRAMEraseOngoing
779 * @retval State of bit (1 or 0).
780 */
LL_SYSCFG_IsCCMSRAMEraseOngoing(void)781 __STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void)
782 {
783 return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL);
784 }
785
786 /**
787 * @brief Set connections to TIM1/8/15/16/17 Break inputs
788 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
789 * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
790 * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
791 * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
792 * @param Break This parameter can be a combination of the following values:
793 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
794 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
795 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
796 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
797 * @retval None
798 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)799 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
800 {
801 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
802 }
803
804 /**
805 * @brief Get connections to TIM1/8/15/16/17 Break inputs
806 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
807 * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
808 * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
809 * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
810 * @retval Returned value can be can be a combination of the following values:
811 * @arg @ref LL_SYSCFG_TIMBREAK_ECC
812 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
813 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
814 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
815 */
LL_SYSCFG_GetTIMBreakInputs(void)816 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
817 {
818 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
819 }
820
821 /**
822 * @brief Check if SRAM parity error detected
823 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
824 * @retval State of bit (1 or 0).
825 */
LL_SYSCFG_IsActiveFlag_SP(void)826 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
827 {
828 return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
829 }
830
831 /**
832 * @brief Clear SRAM parity error flag
833 * @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
834 * @retval None
835 */
LL_SYSCFG_ClearFlag_SP(void)836 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
837 {
838 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
839 }
840
841 /**
842 * @brief Enable CCMSRAM page write protection
843 * @note Write protection is cleared only by a system reset
844 * @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableCCMSRAMPageWRP
845 * @param CCMSRAMWRP This parameter can be a combination of the following values:
846 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
847 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
848 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
849 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
850 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
851 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
852 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
853 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
854 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
855 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
856 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
857 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
858 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
859 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
860 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
861 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
862 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
863 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
864 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
865 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
866 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
867 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
868 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
869 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
870 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
871 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
872 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
873 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
874 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
875 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
876 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
877 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
878 *
879 * (*) value not defined in all devices
880 * @retval None
881 */
LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)882 __STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)
883 {
884 SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
885 }
886
887 /**
888 * @brief CCMSRAM page write protection lock prior to erase
889 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockCCMSRAMWRP
890 * @retval None
891 */
LL_SYSCFG_LockCCMSRAMWRP(void)892 __STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void)
893 {
894 /* Writing a wrong key reactivates the write protection */
895 WRITE_REG(SYSCFG->SKR, 0x00);
896 }
897
898 /**
899 * @brief CCMSRAM page write protection unlock prior to erase
900 * @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockCCMSRAMWRP
901 * @retval None
902 */
LL_SYSCFG_UnlockCCMSRAMWRP(void)903 __STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void)
904 {
905 /* unlock the write protection of the CCMER bit */
906 WRITE_REG(SYSCFG->SKR, 0xCA);
907 WRITE_REG(SYSCFG->SKR, 0x53);
908 }
909 /**
910 * @}
911 */
912
913
914 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
915 * @{
916 */
917
918 /**
919 * @brief Return the device identifier
920 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
921 * @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is 0x6415)
922 */
LL_DBGMCU_GetDeviceID(void)923 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
924 {
925 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
926 }
927
928 /**
929 * @brief Return the device revision identifier
930 * @note This field indicates the revision of the device.
931 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
932 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
933 */
LL_DBGMCU_GetRevisionID(void)934 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
935 {
936 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> (DBGMCU_REVID_POSITION & 0x1FU));
937 }
938
939 /**
940 * @brief Enable the Debug Module during SLEEP mode
941 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
942 * @retval None
943 */
LL_DBGMCU_EnableDBGSleepMode(void)944 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
945 {
946 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
947 }
948
949 /**
950 * @brief Disable the Debug Module during SLEEP mode
951 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
952 * @retval None
953 */
LL_DBGMCU_DisableDBGSleepMode(void)954 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
955 {
956 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
957 }
958
959 /**
960 * @brief Enable the Debug Module during STOP mode
961 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
962 * @retval None
963 */
LL_DBGMCU_EnableDBGStopMode(void)964 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
965 {
966 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
967 }
968
969 /**
970 * @brief Disable the Debug Module during STOP mode
971 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
972 * @retval None
973 */
LL_DBGMCU_DisableDBGStopMode(void)974 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
975 {
976 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
977 }
978
979 /**
980 * @brief Enable the Debug Module during STANDBY mode
981 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
982 * @retval None
983 */
LL_DBGMCU_EnableDBGStandbyMode(void)984 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
985 {
986 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
987 }
988
989 /**
990 * @brief Disable the Debug Module during STANDBY mode
991 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
992 * @retval None
993 */
LL_DBGMCU_DisableDBGStandbyMode(void)994 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
995 {
996 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
997 }
998
999 /**
1000 * @brief Set Trace pin assignment control
1001 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1002 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1003 * @param PinAssignment This parameter can be one of the following values:
1004 * @arg @ref LL_DBGMCU_TRACE_NONE
1005 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1006 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1007 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1008 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1009 * @retval None
1010 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1011 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1012 {
1013 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1014 }
1015
1016 /**
1017 * @brief Get Trace pin assignment control
1018 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1019 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1020 * @retval Returned value can be one of the following values:
1021 * @arg @ref LL_DBGMCU_TRACE_NONE
1022 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1023 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1024 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1025 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1026 */
LL_DBGMCU_GetTracePinAssignment(void)1027 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1028 {
1029 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1030 }
1031
1032 /**
1033 * @brief Freeze APB1 peripherals (group1 peripherals)
1034 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1035 * @param Periphs This parameter can be a combination of the following values:
1036 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1037 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1038 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1039 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1040 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1041 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1042 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1043 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1044 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1045 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1046 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1047 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1048 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1049 *
1050 * (*) value not defined in all devices.
1051 * @retval None
1052 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1053 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1054 {
1055 SET_BIT(DBGMCU->APB1FZR1, Periphs);
1056 }
1057
1058 /**
1059 * @brief Freeze APB1 peripherals (group2 peripherals)
1060 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
1061 * @param Periphs This parameter can be a combination of the following values:
1062 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1063 *
1064 * (*) value not defined in all devices.
1065 * @retval None
1066 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1067 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1068 {
1069 SET_BIT(DBGMCU->APB1FZR2, Periphs);
1070 }
1071
1072 /**
1073 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1074 * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1075 * @param Periphs This parameter can be a combination of the following values:
1076 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1077 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1078 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1079 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1080 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1081 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1082 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1083 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1084 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1085 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1086 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1087 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1088 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1089 *
1090 * (*) value not defined in all devices.
1091 * @retval None
1092 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1093 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1094 {
1095 CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1096 }
1097
1098 /**
1099 * @brief Unfreeze APB1 peripherals (group2 peripherals)
1100 * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1101 * @param Periphs This parameter can be a combination of the following values:
1102 * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1103 *
1104 * (*) value not defined in all devices.
1105 * @retval None
1106 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1107 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1108 {
1109 CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1110 }
1111
1112 /**
1113 * @brief Freeze APB2 peripherals
1114 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1115 * @param Periphs This parameter can be a combination of the following values:
1116 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1117 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1118 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1119 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1120 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1121 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1122 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1123 *
1124 * (*) value not defined in all devices.
1125 * @retval None
1126 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1127 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1128 {
1129 SET_BIT(DBGMCU->APB2FZ, Periphs);
1130 }
1131
1132 /**
1133 * @brief Unfreeze APB2 peripherals
1134 * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1135 * @param Periphs This parameter can be a combination of the following values:
1136 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1137 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1138 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1139 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1140 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1141 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1142 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1143 *
1144 * (*) value not defined in all devices.
1145 * @retval None
1146 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1147 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1148 {
1149 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1150 }
1151
1152 /**
1153 * @}
1154 */
1155
1156 #if defined(VREFBUF)
1157 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1158 * @{
1159 */
1160
1161 /**
1162 * @brief Enable Internal voltage reference
1163 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
1164 * @retval None
1165 */
LL_VREFBUF_Enable(void)1166 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1167 {
1168 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1169 }
1170
1171 /**
1172 * @brief Disable Internal voltage reference
1173 * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
1174 * @retval None
1175 */
LL_VREFBUF_Disable(void)1176 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1177 {
1178 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1179 }
1180
1181 /**
1182 * @brief Enable high impedance (VREF+pin is high impedance)
1183 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
1184 * @retval None
1185 */
LL_VREFBUF_EnableHIZ(void)1186 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1187 {
1188 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1189 }
1190
1191 /**
1192 * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1193 * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
1194 * @retval None
1195 */
LL_VREFBUF_DisableHIZ(void)1196 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1197 {
1198 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1199 }
1200
1201 /**
1202 * @brief Set the Voltage reference scale
1203 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
1204 * @param Scale This parameter can be one of the following values:
1205 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1206 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1207 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1208 * @retval None
1209 */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1210 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1211 {
1212 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1213 }
1214
1215 /**
1216 * @brief Get the Voltage reference scale
1217 * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
1218 * @retval Returned value can be one of the following values:
1219 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1220 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1221 * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1222 */
LL_VREFBUF_GetVoltageScaling(void)1223 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1224 {
1225 return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1226 }
1227
1228 /**
1229 * @brief Check if Voltage reference buffer is ready
1230 * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
1231 * @retval State of bit (1 or 0).
1232 */
LL_VREFBUF_IsVREFReady(void)1233 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1234 {
1235 return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
1236 }
1237
1238 /**
1239 * @brief Get the trimming code for VREFBUF calibration
1240 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
1241 * @retval Between 0 and 0x3F
1242 */
LL_VREFBUF_GetTrimming(void)1243 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1244 {
1245 return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1246 }
1247
1248 /**
1249 * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1250 * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
1251 * @param Value Between 0 and 0x3F
1252 * @retval None
1253 */
LL_VREFBUF_SetTrimming(uint32_t Value)1254 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1255 {
1256 WRITE_REG(VREFBUF->CCR, Value);
1257 }
1258
1259 /**
1260 * @}
1261 */
1262 #endif /* VREFBUF */
1263
1264 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1265 * @{
1266 */
1267
1268 /**
1269 * @brief Set FLASH Latency
1270 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1271 * @param Latency This parameter can be one of the following values:
1272 * @arg @ref LL_FLASH_LATENCY_0
1273 * @arg @ref LL_FLASH_LATENCY_1
1274 * @arg @ref LL_FLASH_LATENCY_2
1275 * @arg @ref LL_FLASH_LATENCY_3
1276 * @arg @ref LL_FLASH_LATENCY_4
1277 * @arg @ref LL_FLASH_LATENCY_5 (*)
1278 * @arg @ref LL_FLASH_LATENCY_6 (*)
1279 * @arg @ref LL_FLASH_LATENCY_7 (*)
1280 * @arg @ref LL_FLASH_LATENCY_8 (*)
1281 * @arg @ref LL_FLASH_LATENCY_9 (*)
1282 * @arg @ref LL_FLASH_LATENCY_10 (*)
1283 * @arg @ref LL_FLASH_LATENCY_11 (*)
1284 * @arg @ref LL_FLASH_LATENCY_12 (*)
1285 * @arg @ref LL_FLASH_LATENCY_13 (*)
1286 * @arg @ref LL_FLASH_LATENCY_14 (*)
1287 * @arg @ref LL_FLASH_LATENCY_15 (*)
1288 *
1289 * (*) value not defined in all devices.
1290 * @retval None
1291 */
LL_FLASH_SetLatency(uint32_t Latency)1292 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1293 {
1294 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1295 }
1296
1297 /**
1298 * @brief Get FLASH Latency
1299 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1300 * @retval Returned value can be one of the following values:
1301 * @arg @ref LL_FLASH_LATENCY_0
1302 * @arg @ref LL_FLASH_LATENCY_1
1303 * @arg @ref LL_FLASH_LATENCY_2
1304 * @arg @ref LL_FLASH_LATENCY_3
1305 * @arg @ref LL_FLASH_LATENCY_4
1306 * @arg @ref LL_FLASH_LATENCY_5 (*)
1307 * @arg @ref LL_FLASH_LATENCY_6 (*)
1308 * @arg @ref LL_FLASH_LATENCY_7 (*)
1309 * @arg @ref LL_FLASH_LATENCY_8 (*)
1310 * @arg @ref LL_FLASH_LATENCY_9 (*)
1311 * @arg @ref LL_FLASH_LATENCY_10 (*)
1312 * @arg @ref LL_FLASH_LATENCY_11 (*)
1313 * @arg @ref LL_FLASH_LATENCY_12 (*)
1314 * @arg @ref LL_FLASH_LATENCY_13 (*)
1315 * @arg @ref LL_FLASH_LATENCY_14 (*)
1316 * @arg @ref LL_FLASH_LATENCY_15 (*)
1317 *
1318 * (*) value not defined in all devices.
1319 */
LL_FLASH_GetLatency(void)1320 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1321 {
1322 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1323 }
1324
1325 /**
1326 * @brief Enable Prefetch
1327 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1328 * @retval None
1329 */
LL_FLASH_EnablePrefetch(void)1330 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1331 {
1332 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1333 }
1334
1335 /**
1336 * @brief Disable Prefetch
1337 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1338 * @retval None
1339 */
LL_FLASH_DisablePrefetch(void)1340 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1341 {
1342 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1343 }
1344
1345 /**
1346 * @brief Check if Prefetch buffer is enabled
1347 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1348 * @retval State of bit (1 or 0).
1349 */
LL_FLASH_IsPrefetchEnabled(void)1350 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1351 {
1352 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1353 }
1354
1355 /**
1356 * @brief Enable Instruction cache
1357 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1358 * @retval None
1359 */
LL_FLASH_EnableInstCache(void)1360 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1361 {
1362 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1363 }
1364
1365 /**
1366 * @brief Disable Instruction cache
1367 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1368 * @retval None
1369 */
LL_FLASH_DisableInstCache(void)1370 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1371 {
1372 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1373 }
1374
1375 /**
1376 * @brief Enable Data cache
1377 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1378 * @retval None
1379 */
LL_FLASH_EnableDataCache(void)1380 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1381 {
1382 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1383 }
1384
1385 /**
1386 * @brief Disable Data cache
1387 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1388 * @retval None
1389 */
LL_FLASH_DisableDataCache(void)1390 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1391 {
1392 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1393 }
1394
1395 /**
1396 * @brief Enable Instruction cache reset
1397 * @note bit can be written only when the instruction cache is disabled
1398 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1399 * @retval None
1400 */
LL_FLASH_EnableInstCacheReset(void)1401 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1402 {
1403 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1404 }
1405
1406 /**
1407 * @brief Disable Instruction cache reset
1408 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1409 * @retval None
1410 */
LL_FLASH_DisableInstCacheReset(void)1411 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1412 {
1413 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1414 }
1415
1416 /**
1417 * @brief Enable Data cache reset
1418 * @note bit can be written only when the data cache is disabled
1419 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1420 * @retval None
1421 */
LL_FLASH_EnableDataCacheReset(void)1422 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1423 {
1424 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1425 }
1426
1427 /**
1428 * @brief Disable Data cache reset
1429 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1430 * @retval None
1431 */
LL_FLASH_DisableDataCacheReset(void)1432 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1433 {
1434 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1435 }
1436
1437 /**
1438 * @brief Enable Flash Power-down mode during run mode or Low-power run mode
1439 * @note Flash memory can be put in power-down mode only when the code is executed
1440 * from RAM
1441 * @note Flash must not be accessed when power down is enabled
1442 * @note Flash must not be put in power-down while a program or an erase operation
1443 * is on-going
1444 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
1445 * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
1446 * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
1447 * @retval None
1448 */
LL_FLASH_EnableRunPowerDown(void)1449 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1450 {
1451 /* Following values must be written consecutively to unlock the RUN_PD bit in
1452 FLASH_ACR */
1453 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1454 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1455 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1456 }
1457
1458 /**
1459 * @brief Disable Flash Power-down mode during run mode or Low-power run mode
1460 * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
1461 * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
1462 * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
1463 * @retval None
1464 */
LL_FLASH_DisableRunPowerDown(void)1465 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1466 {
1467 /* Following values must be written consecutively to unlock the RUN_PD bit in
1468 FLASH_ACR */
1469 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1470 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1471 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1472 }
1473
1474 /**
1475 * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
1476 * @note Flash must not be put in power-down while a program or an erase operation
1477 * is on-going
1478 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
1479 * @retval None
1480 */
LL_FLASH_EnableSleepPowerDown(void)1481 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1482 {
1483 SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1484 }
1485
1486 /**
1487 * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
1488 * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
1489 * @retval None
1490 */
LL_FLASH_DisableSleepPowerDown(void)1491 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1492 {
1493 CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1494 }
1495
1496 /**
1497 * @}
1498 */
1499
1500 /**
1501 * @}
1502 */
1503
1504 /**
1505 * @}
1506 */
1507
1508 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1509
1510 /**
1511 * @}
1512 */
1513
1514 #ifdef __cplusplus
1515 }
1516 #endif
1517
1518 #endif /* __STM32G4xx_LL_SYSTEM_H */
1519
1520
