1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_spi.h 4 * @author MCD Application Team 5 * @brief Header file of SPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_SPI_H 21 #define STM32G4xx_HAL_SPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SPI 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SPI_Exported_Types SPI Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SPI Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Mode; /*!< Specifies the SPI operating mode. 49 This parameter can be a value of @ref SPI_Mode */ 50 51 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 52 This parameter can be a value of @ref SPI_Direction */ 53 54 uint32_t DataSize; /*!< Specifies the SPI data size. 55 This parameter can be a value of @ref SPI_Data_Size */ 56 57 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 58 This parameter can be a value of @ref SPI_Clock_Polarity */ 59 60 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 61 This parameter can be a value of @ref SPI_Clock_Phase */ 62 63 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 64 hardware (NSS pin) or by software using the SSI bit. 65 This parameter can be a value of @ref SPI_Slave_Select_management */ 66 67 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 68 used to configure the transmit and receive SCK clock. 69 This parameter can be a value of @ref SPI_BaudRate_Prescaler 70 @note The communication clock is derived from the master 71 clock. The slave clock does not need to be set. */ 72 73 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 74 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 75 76 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 77 This parameter can be a value of @ref SPI_TI_mode */ 78 79 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 80 This parameter can be a value of @ref SPI_CRC_Calculation */ 81 82 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 83 This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ 84 85 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 86 CRC Length is only used with Data8 and Data16, not other data size 87 This parameter can be a value of @ref SPI_CRC_length */ 88 89 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 90 This parameter can be a value of @ref SPI_NSSP_Mode 91 This mode is activated by the NSSP bit in the SPIx_CR2 register and 92 it takes effect only if the SPI interface is configured as Motorola SPI 93 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, 94 CPOL setting is ignored).. */ 95 } SPI_InitTypeDef; 96 97 /** 98 * @brief HAL SPI State structure definition 99 */ 100 typedef enum 101 { 102 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ 103 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 104 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 105 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 106 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 107 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ 108 HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ 109 HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ 110 } HAL_SPI_StateTypeDef; 111 112 /** 113 * @brief SPI handle Structure definition 114 */ 115 typedef struct __SPI_HandleTypeDef 116 { 117 SPI_TypeDef *Instance; /*!< SPI registers base address */ 118 119 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 120 121 const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 122 123 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 124 125 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 126 127 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 128 129 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 130 131 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 132 133 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 134 135 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 136 137 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 138 139 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 140 141 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 142 143 HAL_LockTypeDef Lock; /*!< Locking object */ 144 145 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 146 147 __IO uint32_t ErrorCode; /*!< SPI Error code */ 148 149 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 150 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 151 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 152 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 153 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 154 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 155 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 156 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 157 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 158 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 159 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 160 161 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 162 } SPI_HandleTypeDef; 163 164 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 165 /** 166 * @brief HAL SPI Callback ID enumeration definition 167 */ 168 typedef enum 169 { 170 HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ 171 HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ 172 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ 173 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ 174 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ 175 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ 176 HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ 177 HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ 178 HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ 179 HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ 180 181 } HAL_SPI_CallbackIDTypeDef; 182 183 /** 184 * @brief HAL SPI Callback pointer definition 185 */ 186 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 187 188 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 189 /** 190 * @} 191 */ 192 193 /* Exported constants --------------------------------------------------------*/ 194 /** @defgroup SPI_Exported_Constants SPI Exported Constants 195 * @{ 196 */ 197 198 /** @defgroup SPI_Error_Code SPI Error Code 199 * @{ 200 */ 201 #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ 202 #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ 203 #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ 204 #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ 205 #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ 206 #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ 207 #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ 208 #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ 209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 210 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ 211 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 212 /** 213 * @} 214 */ 215 216 /** @defgroup SPI_Mode SPI Mode 217 * @{ 218 */ 219 #define SPI_MODE_SLAVE (0x00000000U) 220 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) 221 /** 222 * @} 223 */ 224 225 /** @defgroup SPI_Direction SPI Direction Mode 226 * @{ 227 */ 228 #define SPI_DIRECTION_2LINES (0x00000000U) 229 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY 230 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE 231 /** 232 * @} 233 */ 234 235 /** @defgroup SPI_Data_Size SPI Data Size 236 * @{ 237 */ 238 #define SPI_DATASIZE_4BIT (0x00000300U) 239 #define SPI_DATASIZE_5BIT (0x00000400U) 240 #define SPI_DATASIZE_6BIT (0x00000500U) 241 #define SPI_DATASIZE_7BIT (0x00000600U) 242 #define SPI_DATASIZE_8BIT (0x00000700U) 243 #define SPI_DATASIZE_9BIT (0x00000800U) 244 #define SPI_DATASIZE_10BIT (0x00000900U) 245 #define SPI_DATASIZE_11BIT (0x00000A00U) 246 #define SPI_DATASIZE_12BIT (0x00000B00U) 247 #define SPI_DATASIZE_13BIT (0x00000C00U) 248 #define SPI_DATASIZE_14BIT (0x00000D00U) 249 #define SPI_DATASIZE_15BIT (0x00000E00U) 250 #define SPI_DATASIZE_16BIT (0x00000F00U) 251 /** 252 * @} 253 */ 254 255 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 256 * @{ 257 */ 258 #define SPI_POLARITY_LOW (0x00000000U) 259 #define SPI_POLARITY_HIGH SPI_CR1_CPOL 260 /** 261 * @} 262 */ 263 264 /** @defgroup SPI_Clock_Phase SPI Clock Phase 265 * @{ 266 */ 267 #define SPI_PHASE_1EDGE (0x00000000U) 268 #define SPI_PHASE_2EDGE SPI_CR1_CPHA 269 /** 270 * @} 271 */ 272 273 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management 274 * @{ 275 */ 276 #define SPI_NSS_SOFT SPI_CR1_SSM 277 #define SPI_NSS_HARD_INPUT (0x00000000U) 278 #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) 279 /** 280 * @} 281 */ 282 283 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 284 * @{ 285 */ 286 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP 287 #define SPI_NSS_PULSE_DISABLE (0x00000000U) 288 /** 289 * @} 290 */ 291 292 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 293 * @{ 294 */ 295 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) 296 #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) 297 #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) 298 #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) 299 #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) 300 #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) 301 #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) 302 #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) 303 /** 304 * @} 305 */ 306 307 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission 308 * @{ 309 */ 310 #define SPI_FIRSTBIT_MSB (0x00000000U) 311 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST 312 /** 313 * @} 314 */ 315 316 /** @defgroup SPI_TI_mode SPI TI Mode 317 * @{ 318 */ 319 #define SPI_TIMODE_DISABLE (0x00000000U) 320 #define SPI_TIMODE_ENABLE SPI_CR2_FRF 321 /** 322 * @} 323 */ 324 325 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 326 * @{ 327 */ 328 #define SPI_CRCCALCULATION_DISABLE (0x00000000U) 329 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN 330 /** 331 * @} 332 */ 333 334 /** @defgroup SPI_CRC_length SPI CRC Length 335 * @{ 336 * This parameter can be one of the following values: 337 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size 338 * SPI_CRC_LENGTH_8BIT : CRC 8bit 339 * SPI_CRC_LENGTH_16BIT : CRC 16bit 340 */ 341 #define SPI_CRC_LENGTH_DATASIZE (0x00000000U) 342 #define SPI_CRC_LENGTH_8BIT (0x00000001U) 343 #define SPI_CRC_LENGTH_16BIT (0x00000002U) 344 /** 345 * @} 346 */ 347 348 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold 349 * @{ 350 * This parameter can be one of the following values: 351 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : 352 * RXNE event is generated if the FIFO 353 * level is greater or equal to 1/4(8-bits). 354 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO 355 * level is greater or equal to 1/2(16 bits). */ 356 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH 357 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH 358 #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) 359 /** 360 * @} 361 */ 362 363 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 364 * @{ 365 */ 366 #define SPI_IT_TXE SPI_CR2_TXEIE 367 #define SPI_IT_RXNE SPI_CR2_RXNEIE 368 #define SPI_IT_ERR SPI_CR2_ERRIE 369 /** 370 * @} 371 */ 372 373 /** @defgroup SPI_Flags_definition SPI Flags Definition 374 * @{ 375 */ 376 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ 377 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ 378 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ 379 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ 380 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ 381 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ 382 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ 383 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ 384 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ 385 #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ 386 | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) 387 /** 388 * @} 389 */ 390 391 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level 392 * @{ 393 */ 394 #define SPI_FTLVL_EMPTY (0x00000000U) 395 #define SPI_FTLVL_QUARTER_FULL (0x00000800U) 396 #define SPI_FTLVL_HALF_FULL (0x00001000U) 397 #define SPI_FTLVL_FULL (0x00001800U) 398 399 /** 400 * @} 401 */ 402 403 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 404 * @{ 405 */ 406 #define SPI_FRLVL_EMPTY (0x00000000U) 407 #define SPI_FRLVL_QUARTER_FULL (0x00000200U) 408 #define SPI_FRLVL_HALF_FULL (0x00000400U) 409 #define SPI_FRLVL_FULL (0x00000600U) 410 /** 411 * @} 412 */ 413 414 /** 415 * @} 416 */ 417 418 /* Exported macros -----------------------------------------------------------*/ 419 /** @defgroup SPI_Exported_Macros SPI Exported Macros 420 * @{ 421 */ 422 423 /** @brief Reset SPI handle state. 424 * @param __HANDLE__ specifies the SPI Handle. 425 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 426 * @retval None 427 */ 428 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 429 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ 430 do{ \ 431 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 432 (__HANDLE__)->MspInitCallback = NULL; \ 433 (__HANDLE__)->MspDeInitCallback = NULL; \ 434 } while(0) 435 #else 436 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 437 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 438 439 /** @brief Enable the specified SPI interrupts. 440 * @param __HANDLE__ specifies the SPI Handle. 441 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 442 * @param __INTERRUPT__ specifies the interrupt source to enable. 443 * This parameter can be one of the following values: 444 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 445 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 446 * @arg SPI_IT_ERR: Error interrupt enable 447 * @retval None 448 */ 449 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) 450 451 /** @brief Disable the specified SPI interrupts. 452 * @param __HANDLE__ specifies the SPI handle. 453 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. 454 * @param __INTERRUPT__ specifies the interrupt source to disable. 455 * This parameter can be one of the following values: 456 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 457 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 458 * @arg SPI_IT_ERR: Error interrupt enable 459 * @retval None 460 */ 461 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) 462 463 /** @brief Check whether the specified SPI interrupt source is enabled or not. 464 * @param __HANDLE__ specifies the SPI Handle. 465 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 466 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 467 * This parameter can be one of the following values: 468 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 469 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 470 * @arg SPI_IT_ERR: Error interrupt enable 471 * @retval The new state of __IT__ (TRUE or FALSE). 472 */ 473 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ 474 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 475 476 /** @brief Check whether the specified SPI flag is set or not. 477 * @param __HANDLE__ specifies the SPI Handle. 478 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 479 * @param __FLAG__ specifies the flag to check. 480 * This parameter can be one of the following values: 481 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag 482 * @arg SPI_FLAG_TXE: Transmit buffer empty flag 483 * @arg SPI_FLAG_CRCERR: CRC error flag 484 * @arg SPI_FLAG_MODF: Mode fault flag 485 * @arg SPI_FLAG_OVR: Overrun flag 486 * @arg SPI_FLAG_BSY: Busy flag 487 * @arg SPI_FLAG_FRE: Frame format error flag 488 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level 489 * @arg SPI_FLAG_FRLVL: SPI fifo reception level 490 * @retval The new state of __FLAG__ (TRUE or FALSE). 491 */ 492 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 493 494 /** @brief Clear the SPI CRCERR pending flag. 495 * @param __HANDLE__ specifies the SPI Handle. 496 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 497 * @retval None 498 */ 499 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) 500 501 /** @brief Clear the SPI MODF pending flag. 502 * @param __HANDLE__ specifies the SPI Handle. 503 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 504 * @retval None 505 */ 506 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ 507 do{ \ 508 __IO uint32_t tmpreg_modf = 0x00U; \ 509 tmpreg_modf = (__HANDLE__)->Instance->SR; \ 510 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ 511 UNUSED(tmpreg_modf); \ 512 } while(0U) 513 514 /** @brief Clear the SPI OVR pending flag. 515 * @param __HANDLE__ specifies the SPI Handle. 516 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 517 * @retval None 518 */ 519 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ 520 do{ \ 521 __IO uint32_t tmpreg_ovr = 0x00U; \ 522 tmpreg_ovr = (__HANDLE__)->Instance->DR; \ 523 tmpreg_ovr = (__HANDLE__)->Instance->SR; \ 524 UNUSED(tmpreg_ovr); \ 525 } while(0U) 526 527 /** @brief Clear the SPI FRE pending flag. 528 * @param __HANDLE__ specifies the SPI Handle. 529 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 530 * @retval None 531 */ 532 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ 533 do{ \ 534 __IO uint32_t tmpreg_fre = 0x00U; \ 535 tmpreg_fre = (__HANDLE__)->Instance->SR; \ 536 UNUSED(tmpreg_fre); \ 537 } while(0U) 538 539 /** @brief Enable the SPI peripheral. 540 * @param __HANDLE__ specifies the SPI Handle. 541 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 542 * @retval None 543 */ 544 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) 545 546 /** @brief Disable the SPI peripheral. 547 * @param __HANDLE__ specifies the SPI Handle. 548 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 549 * @retval None 550 */ 551 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) 552 553 /** 554 * @} 555 */ 556 557 /* Private macros ------------------------------------------------------------*/ 558 /** @defgroup SPI_Private_Macros SPI Private Macros 559 * @{ 560 */ 561 562 /** @brief Set the SPI transmit-only mode. 563 * @param __HANDLE__ specifies the SPI Handle. 564 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 565 * @retval None 566 */ 567 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 568 569 /** @brief Set the SPI receive-only mode. 570 * @param __HANDLE__ specifies the SPI Handle. 571 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 572 * @retval None 573 */ 574 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 575 576 /** @brief Reset the CRC calculation of the SPI. 577 * @param __HANDLE__ specifies the SPI Handle. 578 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 579 * @retval None 580 */ 581 #define SPI_RESET_CRC(__HANDLE__) \ 582 do{ \ 583 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ 584 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ 585 } while(0U) 586 587 /** @brief Check whether the specified SPI flag is set or not. 588 * @param __SR__ copy of SPI SR register. 589 * @param __FLAG__ specifies the flag to check. 590 * This parameter can be one of the following values: 591 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag 592 * @arg SPI_FLAG_TXE: Transmit buffer empty flag 593 * @arg SPI_FLAG_CRCERR: CRC error flag 594 * @arg SPI_FLAG_MODF: Mode fault flag 595 * @arg SPI_FLAG_OVR: Overrun flag 596 * @arg SPI_FLAG_BSY: Busy flag 597 * @arg SPI_FLAG_FRE: Frame format error flag 598 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level 599 * @arg SPI_FLAG_FRLVL: SPI fifo reception level 600 * @retval SET or RESET. 601 */ 602 #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ 603 ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) 604 605 /** @brief Check whether the specified SPI Interrupt is set or not. 606 * @param __CR2__ copy of SPI CR2 register. 607 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 608 * This parameter can be one of the following values: 609 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 610 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 611 * @arg SPI_IT_ERR: Error interrupt enable 612 * @retval SET or RESET. 613 */ 614 #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ 615 (__INTERRUPT__)) ? SET : RESET) 616 617 /** @brief Checks if SPI Mode parameter is in allowed range. 618 * @param __MODE__ specifies the SPI Mode. 619 * This parameter can be a value of @ref SPI_Mode 620 * @retval None 621 */ 622 #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ 623 ((__MODE__) == SPI_MODE_MASTER)) 624 625 /** @brief Checks if SPI Direction Mode parameter is in allowed range. 626 * @param __MODE__ specifies the SPI Direction Mode. 627 * This parameter can be a value of @ref SPI_Direction 628 * @retval None 629 */ 630 #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ 631 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ 632 ((__MODE__) == SPI_DIRECTION_1LINE)) 633 634 /** @brief Checks if SPI Direction Mode parameter is 2 lines. 635 * @param __MODE__ specifies the SPI Direction Mode. 636 * @retval None 637 */ 638 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) 639 640 /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. 641 * @param __MODE__ specifies the SPI Direction Mode. 642 * @retval None 643 */ 644 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ 645 ((__MODE__) == SPI_DIRECTION_1LINE)) 646 647 /** @brief Checks if SPI Data Size parameter is in allowed range. 648 * @param __DATASIZE__ specifies the SPI Data Size. 649 * This parameter can be a value of @ref SPI_Data_Size 650 * @retval None 651 */ 652 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ 653 ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ 654 ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ 655 ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ 656 ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ 657 ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ 658 ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ 659 ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ 660 ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ 661 ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ 662 ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ 663 ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ 664 ((__DATASIZE__) == SPI_DATASIZE_4BIT)) 665 666 /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. 667 * @param __CPOL__ specifies the SPI serial clock steady state. 668 * This parameter can be a value of @ref SPI_Clock_Polarity 669 * @retval None 670 */ 671 #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ 672 ((__CPOL__) == SPI_POLARITY_HIGH)) 673 674 /** @brief Checks if SPI Clock Phase parameter is in allowed range. 675 * @param __CPHA__ specifies the SPI Clock Phase. 676 * This parameter can be a value of @ref SPI_Clock_Phase 677 * @retval None 678 */ 679 #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ 680 ((__CPHA__) == SPI_PHASE_2EDGE)) 681 682 /** @brief Checks if SPI Slave Select parameter is in allowed range. 683 * @param __NSS__ specifies the SPI Slave Select management parameter. 684 * This parameter can be a value of @ref SPI_Slave_Select_management 685 * @retval None 686 */ 687 #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ 688 ((__NSS__) == SPI_NSS_HARD_INPUT) || \ 689 ((__NSS__) == SPI_NSS_HARD_OUTPUT)) 690 691 /** @brief Checks if SPI NSS Pulse parameter is in allowed range. 692 * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. 693 * This parameter can be a value of @ref SPI_NSSP_Mode 694 * @retval None 695 */ 696 #define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ 697 ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) 698 699 /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. 700 * @param __PRESCALER__ specifies the SPI Baudrate prescaler. 701 * This parameter can be a value of @ref SPI_BaudRate_Prescaler 702 * @retval None 703 */ 704 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ 705 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ 706 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ 707 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ 708 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ 709 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ 710 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ 711 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) 712 713 /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. 714 * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). 715 * This parameter can be a value of @ref SPI_MSB_LSB_transmission 716 * @retval None 717 */ 718 #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ 719 ((__BIT__) == SPI_FIRSTBIT_LSB)) 720 721 /** @brief Checks if SPI TI mode parameter is in allowed range. 722 * @param __MODE__ specifies the SPI TI mode. 723 * This parameter can be a value of @ref SPI_TI_mode 724 * @retval None 725 */ 726 #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ 727 ((__MODE__) == SPI_TIMODE_ENABLE)) 728 729 /** @brief Checks if SPI CRC calculation enabled state is in allowed range. 730 * @param __CALCULATION__ specifies the SPI CRC calculation enable state. 731 * This parameter can be a value of @ref SPI_CRC_Calculation 732 * @retval None 733 */ 734 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ 735 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) 736 737 /** @brief Checks if SPI CRC length is in allowed range. 738 * @param __LENGTH__ specifies the SPI CRC length. 739 * This parameter can be a value of @ref SPI_CRC_length 740 * @retval None 741 */ 742 #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ 743 ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ 744 ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) 745 746 /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. 747 * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. 748 * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 749 * @retval None 750 */ 751 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ 752 ((__POLYNOMIAL__) <= 0xFFFFU) && \ 753 (((__POLYNOMIAL__)&0x1U) != 0U)) 754 755 /** @brief Checks if DMA handle is valid. 756 * @param __HANDLE__ specifies a DMA Handle. 757 * @retval None 758 */ 759 #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) 760 761 /** 762 * @} 763 */ 764 765 /* Include SPI HAL Extended module */ 766 #include "stm32g4xx_hal_spi_ex.h" 767 768 /* Exported functions --------------------------------------------------------*/ 769 /** @addtogroup SPI_Exported_Functions 770 * @{ 771 */ 772 773 /** @addtogroup SPI_Exported_Functions_Group1 774 * @{ 775 */ 776 /* Initialization/de-initialization functions ********************************/ 777 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 778 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 779 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 780 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 781 782 /* Callbacks Register/UnRegister functions ***********************************/ 783 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 784 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, 785 pSPI_CallbackTypeDef pCallback); 786 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 787 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 788 /** 789 * @} 790 */ 791 792 /** @addtogroup SPI_Exported_Functions_Group2 793 * @{ 794 */ 795 /* I/O operation functions ***************************************************/ 796 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); 797 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 798 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 799 uint16_t Size, uint32_t Timeout); 800 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 801 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 802 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 803 uint16_t Size); 804 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 805 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 806 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 807 uint16_t Size); 808 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 809 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 810 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 811 /* Transfer Abort functions */ 812 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 813 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 814 815 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 816 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 817 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 818 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 819 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 820 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 821 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 822 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 823 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 824 /** 825 * @} 826 */ 827 828 /** @addtogroup SPI_Exported_Functions_Group3 829 * @{ 830 */ 831 /* Peripheral State and Error functions ***************************************/ 832 HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); 833 uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); 834 /** 835 * @} 836 */ 837 838 /** 839 * @} 840 */ 841 842 /** 843 * @} 844 */ 845 846 /** 847 * @} 848 */ 849 850 #ifdef __cplusplus 851 } 852 #endif 853 854 #endif /* STM32G4xx_HAL_SPI_H */ 855 856
