1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32G4xx_HAL_DMA_H 21 #define __STM32G4xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup DMA_Exported_Types DMA Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief DMA Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Request; /*!< Specifies the request selected for the specified channel. 49 This parameter can be a value of @ref DMA_request */ 50 51 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 52 from memory to memory or from peripheral to memory. 53 This parameter can be a value of @ref DMA_Data_transfer_direction */ 54 55 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 57 58 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 59 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 60 61 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 62 This parameter can be a value of @ref DMA_Peripheral_data_size */ 63 64 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 65 This parameter can be a value of @ref DMA_Memory_data_size */ 66 67 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 68 This parameter can be a value of @ref DMA_mode 69 @note The circular buffer mode cannot be used if the memory-to-memory 70 data transfer is configured on the selected Channel */ 71 72 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 73 This parameter can be a value of @ref DMA_Priority_level */ 74 } DMA_InitTypeDef; 75 76 /** 77 * @brief HAL DMA State structures definition 78 */ 79 typedef enum 80 { 81 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 82 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 83 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 84 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 85 } HAL_DMA_StateTypeDef; 86 87 /** 88 * @brief HAL DMA Error Code structure definition 89 */ 90 typedef enum 91 { 92 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 93 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 94 } HAL_DMA_LevelCompleteTypeDef; 95 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 107 108 } HAL_DMA_CallbackIDTypeDef; 109 110 /** 111 * @brief DMA handle Structure definition 112 */ 113 typedef struct __DMA_HandleTypeDef 114 { 115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 116 117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 118 119 HAL_LockTypeDef Lock; /*!< DMA locking object */ 120 121 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 122 123 void *Parent; /*!< Parent object state */ 124 125 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 126 127 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 128 129 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 130 131 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 132 133 __IO uint32_t ErrorCode; /*!< DMA Error code */ 134 135 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 136 137 uint32_t ChannelIndex; /*!< DMA Channel Index */ 138 139 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 140 141 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 142 143 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 144 145 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 146 147 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 148 149 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 150 151 } DMA_HandleTypeDef; 152 /** 153 * @} 154 */ 155 156 /* Exported constants --------------------------------------------------------*/ 157 158 /** @defgroup DMA_Exported_Constants DMA Exported Constants 159 * @{ 160 */ 161 162 /** @defgroup DMA_Error_Code DMA Error Code 163 * @{ 164 */ 165 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 166 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 167 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 168 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 169 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 170 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 171 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 172 /** 173 * @} 174 */ 175 176 /** @defgroup DMA_request DMA request 177 * @{ 178 */ 179 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 180 181 #define DMA_REQUEST_GENERATOR0 1U 182 #define DMA_REQUEST_GENERATOR1 2U 183 #define DMA_REQUEST_GENERATOR2 3U 184 #define DMA_REQUEST_GENERATOR3 4U 185 186 #define DMA_REQUEST_ADC1 5U 187 188 #define DMA_REQUEST_DAC1_CHANNEL1 6U 189 #define DMA_REQUEST_DAC1_CHANNEL2 7U 190 191 #define DMA_REQUEST_TIM6_UP 8U 192 #define DMA_REQUEST_TIM7_UP 9U 193 194 #define DMA_REQUEST_SPI1_RX 10U 195 #define DMA_REQUEST_SPI1_TX 11U 196 #define DMA_REQUEST_SPI2_RX 12U 197 #define DMA_REQUEST_SPI2_TX 13U 198 #define DMA_REQUEST_SPI3_RX 14U 199 #define DMA_REQUEST_SPI3_TX 15U 200 201 #define DMA_REQUEST_I2C1_RX 16U 202 #define DMA_REQUEST_I2C1_TX 17U 203 #define DMA_REQUEST_I2C2_RX 18U 204 #define DMA_REQUEST_I2C2_TX 19U 205 #define DMA_REQUEST_I2C3_RX 20U 206 #define DMA_REQUEST_I2C3_TX 21U 207 #if defined (I2C4) 208 #define DMA_REQUEST_I2C4_RX 22U 209 #define DMA_REQUEST_I2C4_TX 23U 210 #endif /* I2C4 */ 211 212 #define DMA_REQUEST_USART1_RX 24U 213 #define DMA_REQUEST_USART1_TX 25U 214 #define DMA_REQUEST_USART2_RX 26U 215 #define DMA_REQUEST_USART2_TX 27U 216 #define DMA_REQUEST_USART3_RX 28U 217 #define DMA_REQUEST_USART3_TX 29U 218 219 #define DMA_REQUEST_UART4_RX 30U 220 #define DMA_REQUEST_UART4_TX 31U 221 #if defined (UART5) 222 #define DMA_REQUEST_UART5_RX 32U 223 #define DMA_REQUEST_UART5_TX 33U 224 #endif /* UART5 */ 225 226 #define DMA_REQUEST_LPUART1_RX 34U 227 #define DMA_REQUEST_LPUART1_TX 35U 228 229 #define DMA_REQUEST_ADC2 36U 230 #if defined (ADC3) 231 #define DMA_REQUEST_ADC3 37U 232 #endif /* ADC3 */ 233 #if defined (ADC4) 234 #define DMA_REQUEST_ADC4 38U 235 #endif /* ADC4 */ 236 #if defined (ADC5) 237 #define DMA_REQUEST_ADC5 39U 238 #endif /* ADC5 */ 239 240 #if defined (QUADSPI) 241 #define DMA_REQUEST_QUADSPI 40U 242 #endif /* QUADSPI */ 243 244 #if defined (DAC2) 245 #define DMA_REQUEST_DAC2_CHANNEL1 41U 246 #endif /* DAC2 */ 247 248 #define DMA_REQUEST_TIM1_CH1 42U 249 #define DMA_REQUEST_TIM1_CH2 43U 250 #define DMA_REQUEST_TIM1_CH3 44U 251 #define DMA_REQUEST_TIM1_CH4 45U 252 #define DMA_REQUEST_TIM1_UP 46U 253 #define DMA_REQUEST_TIM1_TRIG 47U 254 #define DMA_REQUEST_TIM1_COM 48U 255 256 #define DMA_REQUEST_TIM8_CH1 49U 257 #define DMA_REQUEST_TIM8_CH2 50U 258 #define DMA_REQUEST_TIM8_CH3 51U 259 #define DMA_REQUEST_TIM8_CH4 52U 260 #define DMA_REQUEST_TIM8_UP 53U 261 #define DMA_REQUEST_TIM8_TRIG 54U 262 #define DMA_REQUEST_TIM8_COM 55U 263 264 #define DMA_REQUEST_TIM2_CH1 56U 265 #define DMA_REQUEST_TIM2_CH2 57U 266 #define DMA_REQUEST_TIM2_CH3 58U 267 #define DMA_REQUEST_TIM2_CH4 59U 268 #define DMA_REQUEST_TIM2_UP 60U 269 270 #define DMA_REQUEST_TIM3_CH1 61U 271 #define DMA_REQUEST_TIM3_CH2 62U 272 #define DMA_REQUEST_TIM3_CH3 63U 273 #define DMA_REQUEST_TIM3_CH4 64U 274 #define DMA_REQUEST_TIM3_UP 65U 275 #define DMA_REQUEST_TIM3_TRIG 66U 276 277 #define DMA_REQUEST_TIM4_CH1 67U 278 #define DMA_REQUEST_TIM4_CH2 68U 279 #define DMA_REQUEST_TIM4_CH3 69U 280 #define DMA_REQUEST_TIM4_CH4 70U 281 #define DMA_REQUEST_TIM4_UP 71U 282 283 #if defined (TIM5) 284 #define DMA_REQUEST_TIM5_CH1 72U 285 #define DMA_REQUEST_TIM5_CH2 73U 286 #define DMA_REQUEST_TIM5_CH3 74U 287 #define DMA_REQUEST_TIM5_CH4 75U 288 #define DMA_REQUEST_TIM5_UP 76U 289 #define DMA_REQUEST_TIM5_TRIG 77U 290 #endif /* TIM5 */ 291 292 #define DMA_REQUEST_TIM15_CH1 78U 293 #define DMA_REQUEST_TIM15_UP 79U 294 #define DMA_REQUEST_TIM15_TRIG 80U 295 #define DMA_REQUEST_TIM15_COM 81U 296 297 #define DMA_REQUEST_TIM16_CH1 82U 298 #define DMA_REQUEST_TIM16_UP 83U 299 #define DMA_REQUEST_TIM17_CH1 84U 300 #define DMA_REQUEST_TIM17_UP 85U 301 302 #if defined (TIM20) 303 #define DMA_REQUEST_TIM20_CH1 86U 304 #define DMA_REQUEST_TIM20_CH2 87U 305 #define DMA_REQUEST_TIM20_CH3 88U 306 #define DMA_REQUEST_TIM20_CH4 89U 307 #define DMA_REQUEST_TIM20_UP 90U 308 #endif /* TIM20 */ 309 310 #define DMA_REQUEST_AES_IN 91U 311 #define DMA_REQUEST_AES_OUT 92U 312 313 #if defined (TIM20) 314 #define DMA_REQUEST_TIM20_TRIG 93U 315 #define DMA_REQUEST_TIM20_COM 94U 316 #endif /* TIM20 */ 317 318 #if defined (HRTIM1) 319 #define DMA_REQUEST_HRTIM1_M 95U 320 #define DMA_REQUEST_HRTIM1_A 96U 321 #define DMA_REQUEST_HRTIM1_B 97U 322 #define DMA_REQUEST_HRTIM1_C 98U 323 #define DMA_REQUEST_HRTIM1_D 99U 324 #define DMA_REQUEST_HRTIM1_E 100U 325 #define DMA_REQUEST_HRTIM1_F 101U 326 #endif /* HRTIM1 */ 327 328 #define DMA_REQUEST_DAC3_CHANNEL1 102U 329 #define DMA_REQUEST_DAC3_CHANNEL2 103U 330 #if defined (DAC4) 331 #define DMA_REQUEST_DAC4_CHANNEL1 104U 332 #define DMA_REQUEST_DAC4_CHANNEL2 105U 333 #endif /* DAC4 */ 334 335 #if defined (SPI4) 336 #define DMA_REQUEST_SPI4_RX 106U 337 #define DMA_REQUEST_SPI4_TX 107U 338 #endif /* SPI4 */ 339 340 #define DMA_REQUEST_SAI1_A 108U 341 #define DMA_REQUEST_SAI1_B 109U 342 343 #define DMA_REQUEST_FMAC_READ 110U 344 #define DMA_REQUEST_FMAC_WRITE 111U 345 346 #define DMA_REQUEST_CORDIC_READ 112U 347 #define DMA_REQUEST_CORDIC_WRITE 113U 348 349 #define DMA_REQUEST_UCPD1_RX 114U 350 #define DMA_REQUEST_UCPD1_TX 115U 351 352 /** 353 * @} 354 */ 355 356 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 357 * @{ 358 */ 359 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 360 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 361 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 362 /** 363 * @} 364 */ 365 366 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 367 * @{ 368 */ 369 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 370 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 371 /** 372 * @} 373 */ 374 375 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 376 * @{ 377 */ 378 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 379 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 385 * @{ 386 */ 387 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 388 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 389 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup DMA_Memory_data_size DMA Memory data size 395 * @{ 396 */ 397 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 398 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 399 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 400 /** 401 * @} 402 */ 403 404 /** @defgroup DMA_mode DMA mode 405 * @{ 406 */ 407 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 408 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 409 /** 410 * @} 411 */ 412 413 /** @defgroup DMA_Priority_level DMA Priority level 414 * @{ 415 */ 416 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 417 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 418 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 419 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 420 /** 421 * @} 422 */ 423 424 425 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 426 * @{ 427 */ 428 #define DMA_IT_TC DMA_CCR_TCIE 429 #define DMA_IT_HT DMA_CCR_HTIE 430 #define DMA_IT_TE DMA_CCR_TEIE 431 /** 432 * @} 433 */ 434 435 /** @defgroup DMA_flag_definitions DMA flag definitions 436 * @{ 437 */ 438 #define DMA_FLAG_GL1 0x00000001U 439 #define DMA_FLAG_TC1 0x00000002U 440 #define DMA_FLAG_HT1 0x00000004U 441 #define DMA_FLAG_TE1 0x00000008U 442 #define DMA_FLAG_GL2 0x00000010U 443 #define DMA_FLAG_TC2 0x00000020U 444 #define DMA_FLAG_HT2 0x00000040U 445 #define DMA_FLAG_TE2 0x00000080U 446 #define DMA_FLAG_GL3 0x00000100U 447 #define DMA_FLAG_TC3 0x00000200U 448 #define DMA_FLAG_HT3 0x00000400U 449 #define DMA_FLAG_TE3 0x00000800U 450 #define DMA_FLAG_GL4 0x00001000U 451 #define DMA_FLAG_TC4 0x00002000U 452 #define DMA_FLAG_HT4 0x00004000U 453 #define DMA_FLAG_TE4 0x00008000U 454 #define DMA_FLAG_GL5 0x00010000U 455 #define DMA_FLAG_TC5 0x00020000U 456 #define DMA_FLAG_HT5 0x00040000U 457 #define DMA_FLAG_TE5 0x00080000U 458 #define DMA_FLAG_GL6 0x00100000U 459 #define DMA_FLAG_TC6 0x00200000U 460 #define DMA_FLAG_HT6 0x00400000U 461 #define DMA_FLAG_TE6 0x00800000U 462 #if defined (DMA1_Channel7) 463 #define DMA_FLAG_GL7 0x01000000U 464 #define DMA_FLAG_TC7 0x02000000U 465 #define DMA_FLAG_HT7 0x04000000U 466 #define DMA_FLAG_TE7 0x08000000U 467 #endif /* DMA1_Channel7 */ 468 #if defined (DMA1_Channel8) 469 #define DMA_FLAG_GL8 0x10000000U 470 #define DMA_FLAG_TC8 0x20000000U 471 #define DMA_FLAG_HT8 0x40000000U 472 #define DMA_FLAG_TE8 0x80000000U 473 #endif /* DMA1_Channel8 */ 474 /** 475 * @} 476 */ 477 478 /** 479 * @} 480 */ 481 482 /* Exported macros -----------------------------------------------------------*/ 483 /** @defgroup DMA_Exported_Macros DMA Exported Macros 484 * @{ 485 */ 486 487 /** @brief Reset DMA handle state. 488 * @param __HANDLE__ DMA handle 489 * @retval None 490 */ 491 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 492 493 /** 494 * @brief Enable the specified DMA Channel. 495 * @param __HANDLE__ DMA handle 496 * @retval None 497 */ 498 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 499 500 /** 501 * @brief Disable the specified DMA Channel. 502 * @param __HANDLE__ DMA handle 503 * @retval None 504 */ 505 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 506 507 508 /* Interrupt & Flag management */ 509 510 /** 511 * @brief Return the current DMA Channel transfer complete flag. 512 * @param __HANDLE__ DMA handle 513 * @retval The specified transfer complete flag index. 514 */ 515 516 #if defined (DMA1_Channel8) 517 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 518 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\ 532 DMA_FLAG_TC8) 533 #elif defined (DMA1_Channel6) 534 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 535 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 545 DMA_FLAG_TC6) 546 #endif /* DMA1_Channel8 */ 547 548 /** 549 * @brief Return the current DMA Channel half transfer complete flag. 550 * @param __HANDLE__ DMA handle 551 * @retval The specified half transfer complete flag index. 552 */ 553 #if defined (DMA1_Channel8) 554 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 555 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 556 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 563 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 564 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 565 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 566 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 567 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ 568 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\ 569 DMA_FLAG_HT8) 570 #elif defined (DMA1_Channel6) 571 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 572 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 573 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 574 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 575 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 576 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 577 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 578 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 579 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 580 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 581 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 582 DMA_FLAG_HT6) 583 #endif /* DMA1_Channel8 */ 584 585 /** 586 * @brief Return the current DMA Channel transfer error flag. 587 * @param __HANDLE__ DMA handle 588 * @retval The specified transfer error flag index. 589 */ 590 #if defined (DMA1_Channel8) 591 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 592 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 593 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 594 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 595 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 602 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 603 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 604 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ 605 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\ 606 DMA_FLAG_TE8) 607 #elif defined (DMA1_Channel6) 608 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 609 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 610 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 611 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 612 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 613 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 614 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 619 DMA_FLAG_TE6) 620 #endif /* DMA1_Channel8 */ 621 622 /** 623 * @brief Return the current DMA Channel Global interrupt flag. 624 * @param __HANDLE__ DMA handle 625 * @retval The specified transfer error flag index. 626 */ 627 #if defined (DMA1_Channel8) 628 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 629 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 630 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 631 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\ 642 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\ 643 DMA_ISR_GIF8) 644 #elif defined (DMA1_Channel6) 645 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 646 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 647 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 648 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 649 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 650 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 651 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 652 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 656 DMA_ISR_GIF6) 657 #endif /* DMA1_Channel8 */ 658 659 /** 660 * @brief Get the DMA Channel pending flags. 661 * @param __HANDLE__ DMA handle 662 * @param __FLAG__ Get the specified flag. 663 * This parameter can be any combination of the following values: 664 * @arg DMA_FLAG_TCx Transfer complete flag 665 * @arg DMA_FLAG_HTx Half transfer complete flag 666 * @arg DMA_FLAG_TEx Transfer error flag 667 * @arg DMA_FLAG_GLx Global interrupt flag 668 * Where x can be from 1 to 8 to select the DMA Channel x flag. 669 * @retval The state of FLAG (SET or RESET). 670 */ 671 #if defined (DMA1_Channel8) 672 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ 673 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 674 #elif defined (DMA1_Channel6) 675 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ 676 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 677 #endif /* DMA1_Channel8 */ 678 679 /** 680 * @brief Clear the DMA Channel pending flags. 681 * @param __HANDLE__ DMA handle 682 * @param __FLAG__ specifies the flag to clear. 683 * This parameter can be any combination of the following values: 684 * @arg DMA_FLAG_TCx Transfer complete flag 685 * @arg DMA_FLAG_HTx Half transfer complete flag 686 * @arg DMA_FLAG_TEx Transfer error flag 687 * @arg DMA_FLAG_GLx Global interrupt flag 688 * Where x can be from 1 to 8 to select the DMA Channel x flag. 689 * @retval None 690 */ 691 #if defined (DMA1_Channel8) 692 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ 693 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 694 #else 695 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \ 696 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 697 #endif /* DMA1_Channel8 */ 698 699 /** 700 * @brief Enable the specified DMA Channel interrupts. 701 * @param __HANDLE__ DMA handle 702 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 703 * This parameter can be any combination of the following values: 704 * @arg DMA_IT_TC Transfer complete interrupt mask 705 * @arg DMA_IT_HT Half transfer complete interrupt mask 706 * @arg DMA_IT_TE Transfer error interrupt mask 707 * @retval None 708 */ 709 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 710 711 /** 712 * @brief Disable the specified DMA Channel interrupts. 713 * @param __HANDLE__ DMA handle 714 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 715 * This parameter can be any combination of the following values: 716 * @arg DMA_IT_TC Transfer complete interrupt mask 717 * @arg DMA_IT_HT Half transfer complete interrupt mask 718 * @arg DMA_IT_TE Transfer error interrupt mask 719 * @retval None 720 */ 721 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 722 723 /** 724 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 725 * @param __HANDLE__ DMA handle 726 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 727 * This parameter can be one of the following values: 728 * @arg DMA_IT_TC Transfer complete interrupt mask 729 * @arg DMA_IT_HT Half transfer complete interrupt mask 730 * @arg DMA_IT_TE Transfer error interrupt mask 731 * @retval The state of DMA_IT (SET or RESET). 732 */ 733 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 734 735 /** 736 * @brief Return the number of remaining data units in the current DMA Channel transfer. 737 * @param __HANDLE__ DMA handle 738 * @retval The number of remaining data units in the current DMA Channel transfer. 739 */ 740 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 741 742 /** 743 * @} 744 */ 745 746 /* Include DMA HAL Extension module */ 747 #include "stm32g4xx_hal_dma_ex.h" 748 749 /* Exported functions --------------------------------------------------------*/ 750 751 /** @addtogroup DMA_Exported_Functions 752 * @{ 753 */ 754 755 /** @addtogroup DMA_Exported_Functions_Group1 756 * @{ 757 */ 758 /* Initialization and de-initialization functions *****************************/ 759 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 760 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 761 /** 762 * @} 763 */ 764 765 /** @addtogroup DMA_Exported_Functions_Group2 766 * @{ 767 */ 768 /* IO operation functions *****************************************************/ 769 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 770 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, 771 uint32_t DataLength); 772 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 773 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 774 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, 775 uint32_t Timeout); 776 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 777 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 778 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 779 780 /** 781 * @} 782 */ 783 784 /** @addtogroup DMA_Exported_Functions_Group3 785 * @{ 786 */ 787 /* Peripheral State and Error functions ***************************************/ 788 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 789 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 790 /** 791 * @} 792 */ 793 794 /** 795 * @} 796 */ 797 798 /* Private macros ------------------------------------------------------------*/ 799 /** @defgroup DMA_Private_Macros DMA Private Macros 800 * @{ 801 */ 802 803 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 804 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 805 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 806 807 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U)) 808 809 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 810 ((STATE) == DMA_PINC_DISABLE)) 811 812 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 813 ((STATE) == DMA_MINC_DISABLE)) 814 815 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX) 816 817 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 818 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 819 ((SIZE) == DMA_PDATAALIGN_WORD)) 820 821 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 822 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 823 ((SIZE) == DMA_MDATAALIGN_WORD )) 824 825 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 826 ((MODE) == DMA_CIRCULAR)) 827 828 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 829 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 830 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 831 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 832 833 /** 834 * @} 835 */ 836 837 /* Private functions ---------------------------------------------------------*/ 838 839 /** 840 * @} 841 */ 842 843 /** 844 * @} 845 */ 846 847 #ifdef __cplusplus 848 } 849 #endif 850 851 #endif /* __STM32G4xx_HAL_DMA_H */ 852 853
