1 /**
2 ******************************************************************************
3 * @file stm32g0xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G0xx_LL_DAC_H
21 #define STM32G0xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g0xx.h"
29
30 /** @addtogroup STM32G0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 /* - channel register offset of sample-and-hold sample time register SHSRx */
55 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
56 CR, MCR, CCR, SHHR, SHRR of channel 1 */
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60
61 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
62 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
64
65 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
66 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
67 DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 24 bits) */
70
71 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
72 DHR12Rx channel 1 (shifted left of 28 bits) */
73 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77
78 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
79 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
80 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
81 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
82 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83
84 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
85
86 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
87 DORx channel 2 (shifted left of 5 bits) */
88 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
89
90 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
91 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
92 SHSRx channel 2 (shifted left of 6 bits) */
93 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
94
95
96 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
97 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
98 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
99 to position 0 */
100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
101 to position 0 */
102
103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 28 bits) */
106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 20 bits) */
109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 24 bits) */
112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
113 channel 1 or 2 versus DORx channel 1
114 (shifted left of 5 bits) */
115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
116 channel 1 or 2 versus SHSRx channel 1
117 (shifted left of 6 bits) */
118
119 /* DAC registers bits positions */
120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
123
124 /* Miscellaneous data */
125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
126 bits (voltage range determined by analog voltage
127 references Vref+ and Vref-, refer to reference manual) */
128
129 /**
130 * @}
131 */
132
133
134 /* Private macros ------------------------------------------------------------*/
135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
136 * @{
137 */
138
139 /**
140 * @brief Driver macro reserved for internal use: set a pointer to
141 * a register from a register basis from which an offset
142 * is applied.
143 * @param __REG__ Register basis from which the offset is applied.
144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
145 * @retval Pointer to register address
146 */
147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
149
150 /**
151 * @}
152 */
153
154
155 /* Exported types ------------------------------------------------------------*/
156 #if defined(USE_FULL_LL_DRIVER)
157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
158 * @{
159 */
160
161 /**
162 * @brief Structure definition of some features of DAC instance.
163 */
164 typedef struct
165 {
166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
167 internal (SW start) or from external peripheral
168 (timer event, external interrupt line).
169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
170
171 This feature can be modified afterwards using unitary
172 function @ref LL_DAC_SetTriggerSource(). */
173
174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
176
177 This feature can be modified afterwards using unitary
178 function @ref LL_DAC_SetWaveAutoGeneration(). */
179
180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
181 If waveform automatic generation mode is set to noise, this parameter
182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
183 If waveform automatic generation mode is set to triangle,
184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
185 @note If waveform automatic generation mode is disabled,
186 this parameter is discarded.
187
188 This feature can be modified afterwards using unitary
189 function @ref LL_DAC_SetWaveNoiseLFSR(),
190 @ref LL_DAC_SetWaveTriangleAmplitude()
191 depending on the wave automatic generation selected. */
192
193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
195
196 This feature can be modified afterwards using unitary
197 function @ref LL_DAC_SetOutputBuffer(). */
198
199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
201
202 This feature can be modified afterwards using unitary
203 function @ref LL_DAC_SetOutputConnection(). */
204
205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
207
208 This feature can be modified afterwards using unitary
209 function @ref LL_DAC_SetOutputMode(). */
210 } LL_DAC_InitTypeDef;
211
212 /**
213 * @}
214 */
215 #endif /* USE_FULL_LL_DRIVER */
216
217 /* Exported constants --------------------------------------------------------*/
218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
219 * @{
220 */
221
222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
223 * @brief Flags defines which can be used with LL_DAC_ReadReg function
224 * @{
225 */
226 /* DAC channel 1 flags */
227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
230
231 /* DAC channel 2 flags */
232 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
233 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
234 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
235
236 /**
237 * @}
238 */
239
240 /** @defgroup DAC_LL_EC_IT DAC interruptions
241 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
242 * @{
243 */
244 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
245
246 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
247
248 /**
249 * @}
250 */
251
252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
253 * @{
254 */
255 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
256 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
262 * @{
263 */
264 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
265 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
266 /**
267 * @}
268 */
269
270 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
271 * @{
272 */
273 #define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC channel conversion trigger internal (SW start) */
274 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */
275 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
276 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
277 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
278 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
279 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
280 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
281 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
282 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
283 /**
284 * @}
285 */
286
287 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
288 * @{
289 */
290 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
291 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
292 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
293 /**
294 * @}
295 */
296
297 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
298 * @{
299 */
300 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
301 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
302 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
303 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
304 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
305 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
306 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
307 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
308 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
309 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
310 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
311 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
312 /**
313 * @}
314 */
315
316 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
317 * @{
318 */
319 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
320 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
321 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
322 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
323 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
324 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
325 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
326 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
327 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
328 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
329 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
330 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
331 /**
332 * @}
333 */
334
335 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
336 * @{
337 */
338 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
339 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
340 /**
341 * @}
342 */
343
344 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
345 * @{
346 */
347 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
348 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
349 /**
350 * @}
351 */
352
353 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
354 * @{
355 */
356 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
357 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
358 /**
359 * @}
360 */
361
362 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
363 * @{
364 */
365 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
366 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
367 /**
368 * @}
369 */
370
371 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
372 * @{
373 */
374 /* List of DAC registers intended to be used (most commonly) with */
375 /* DMA transfer. */
376 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
377 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
378 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
379 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
380 /**
381 * @}
382 */
383
384 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
385 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
386 * not timeout values.
387 * For details on delays values, refer to descriptions in source code
388 * above each literal definition.
389 * @{
390 */
391
392 /* Delay for DAC channel voltage settling time from DAC channel startup */
393 /* (transition from disable to enable). */
394 /* Note: DAC channel startup time depends on board application environment: */
395 /* impedance connected to DAC channel output. */
396 /* The delay below is specified under conditions: */
397 /* - voltage maximum transition (lowest to highest value) */
398 /* - until voltage reaches final value +-1LSB */
399 /* - DAC channel output buffer enabled */
400 /* - load impedance of 5kOhm (min), 50pF (max) */
401 /* Literal set to maximum value (refer to device datasheet, */
402 /* parameter "tWAKEUP"). */
403 /* Unit: us */
404 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
405
406 /* Delay for DAC channel voltage settling time. */
407 /* Note: DAC channel startup time depends on board application environment: */
408 /* impedance connected to DAC channel output. */
409 /* The delay below is specified under conditions: */
410 /* - voltage maximum transition (lowest to highest value) */
411 /* - until voltage reaches final value +-1LSB */
412 /* - DAC channel output buffer enabled */
413 /* - load impedance of 5kOhm min, 50pF max */
414 /* Literal set to maximum value (refer to device datasheet, */
415 /* parameter "tSETTLING"). */
416 /* Unit: us */
417 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
418
419 /**
420 * @}
421 */
422
423 /**
424 * @}
425 */
426
427 /* Exported macro ------------------------------------------------------------*/
428 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
429 * @{
430 */
431
432 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
433 * @{
434 */
435
436 /**
437 * @brief Write a value in DAC register
438 * @param __INSTANCE__ DAC Instance
439 * @param __REG__ Register to be written
440 * @param __VALUE__ Value to be written in the register
441 * @retval None
442 */
443 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
444
445 /**
446 * @brief Read a value in DAC register
447 * @param __INSTANCE__ DAC Instance
448 * @param __REG__ Register to be read
449 * @retval Register value
450 */
451 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
452
453 /**
454 * @}
455 */
456
457 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
458 * @{
459 */
460
461 /**
462 * @brief Helper macro to get DAC channel number in decimal format
463 * from literals LL_DAC_CHANNEL_x.
464 * Example:
465 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
466 * will return decimal number "1".
467 * @note The input can be a value from functions where a channel
468 * number is returned.
469 * @param __CHANNEL__ This parameter can be one of the following values:
470 * @arg @ref LL_DAC_CHANNEL_1
471 * @arg @ref LL_DAC_CHANNEL_2
472 * @retval 1...2
473 */
474 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
475 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
476
477 /**
478 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
479 * from number in decimal format.
480 * Example:
481 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
482 * will return a data equivalent to "LL_DAC_CHANNEL_1".
483 * @note If the input parameter does not correspond to a DAC channel,
484 * this macro returns value '0'.
485 * @param __DECIMAL_NB__ 1...2
486 * @retval Returned value can be one of the following values:
487 * @arg @ref LL_DAC_CHANNEL_1
488 * @arg @ref LL_DAC_CHANNEL_2
489 */
490 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
491 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
492
493 /**
494 * @brief Helper macro to define the DAC conversion data full-scale digital
495 * value corresponding to the selected DAC resolution.
496 * @note DAC conversion data full-scale corresponds to voltage range
497 * determined by analog voltage references Vref+ and Vref-
498 * (refer to reference manual).
499 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
500 * @arg @ref LL_DAC_RESOLUTION_12B
501 * @arg @ref LL_DAC_RESOLUTION_8B
502 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
503 */
504 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
505 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
506
507 /**
508 * @brief Helper macro to calculate the DAC conversion data (unit: digital
509 * value) corresponding to a voltage (unit: mVolt).
510 * @note This helper macro is intended to provide input data in voltage
511 * rather than digital value,
512 * to be used with LL DAC functions such as
513 * @ref LL_DAC_ConvertData12RightAligned().
514 * @note Analog reference voltage (Vref+) must be either known from
515 * user board environment or can be calculated using ADC measurement
516 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
517 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
518 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
519 * (unit: mVolt).
520 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
521 * @arg @ref LL_DAC_RESOLUTION_12B
522 * @arg @ref LL_DAC_RESOLUTION_8B
523 * @retval DAC conversion data (unit: digital value)
524 */
525 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
526 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
527 / (__VREFANALOG_VOLTAGE__) \
528 )
529
530 /**
531 * @}
532 */
533
534 /**
535 * @}
536 */
537
538
539 /* Exported functions --------------------------------------------------------*/
540 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
541 * @{
542 */
543
544 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
545 * @{
546 */
547
548 /**
549 * @brief Set the operating mode for the selected DAC channel:
550 * calibration or normal operating mode.
551 * @rmtoll CR CEN1 LL_DAC_SetMode\n
552 * CR CEN2 LL_DAC_SetMode
553 * @param DACx DAC instance
554 * @param DAC_Channel This parameter can be one of the following values:
555 * @arg @ref LL_DAC_CHANNEL_1
556 * @arg @ref LL_DAC_CHANNEL_2
557 * @param ChannelMode This parameter can be one of the following values:
558 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
559 * @arg @ref LL_DAC_MODE_CALIBRATION
560 * @retval None
561 */
LL_DAC_SetMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t ChannelMode)562 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
563 {
564 MODIFY_REG(DACx->CR,
565 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
566 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
567 }
568
569 /**
570 * @brief Get the operating mode for the selected DAC channel:
571 * calibration or normal operating mode.
572 * @rmtoll CR CEN1 LL_DAC_GetMode\n
573 * CR CEN2 LL_DAC_GetMode
574 * @param DACx DAC instance
575 * @param DAC_Channel This parameter can be one of the following values:
576 * @arg @ref LL_DAC_CHANNEL_1
577 * @arg @ref LL_DAC_CHANNEL_2
578 * @retval Returned value can be one of the following values:
579 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
580 * @arg @ref LL_DAC_MODE_CALIBRATION
581 */
LL_DAC_GetMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)582 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
583 {
584 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
585 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
586 );
587 }
588
589 /**
590 * @brief Set the offset trimming value for the selected DAC channel.
591 * Trimming has an impact when output buffer is enabled
592 * and is intended to replace factory calibration default values.
593 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
594 * CCR OTRIM2 LL_DAC_SetTrimmingValue
595 * @param DACx DAC instance
596 * @param DAC_Channel This parameter can be one of the following values:
597 * @arg @ref LL_DAC_CHANNEL_1
598 * @arg @ref LL_DAC_CHANNEL_2
599 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
600 * @retval None
601 */
LL_DAC_SetTrimmingValue(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TrimmingValue)602 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
603 {
604 MODIFY_REG(DACx->CCR,
605 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
606 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
607 }
608
609 /**
610 * @brief Get the offset trimming value for the selected DAC channel.
611 * Trimming has an impact when output buffer is enabled
612 * and is intended to replace factory calibration default values.
613 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
614 * CCR OTRIM2 LL_DAC_GetTrimmingValue
615 * @param DACx DAC instance
616 * @param DAC_Channel This parameter can be one of the following values:
617 * @arg @ref LL_DAC_CHANNEL_1
618 * @arg @ref LL_DAC_CHANNEL_2
619 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
620 */
LL_DAC_GetTrimmingValue(const DAC_TypeDef * DACx,uint32_t DAC_Channel)621 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
622 {
623 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
624 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
625 );
626 }
627
628 /**
629 * @brief Set the conversion trigger source for the selected DAC channel.
630 * @note For conversion trigger source to be effective, DAC trigger
631 * must be enabled using function @ref LL_DAC_EnableTrigger().
632 * @note To set conversion trigger source, DAC channel must be disabled.
633 * Otherwise, the setting is discarded.
634 * @note Availability of parameters of trigger sources from timer
635 * depends on timers availability on the selected device.
636 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
637 * CR TSEL2 LL_DAC_SetTriggerSource
638 * @param DACx DAC instance
639 * @param DAC_Channel This parameter can be one of the following values:
640 * @arg @ref LL_DAC_CHANNEL_1
641 * @arg @ref LL_DAC_CHANNEL_2
642 * @param TriggerSource This parameter can be one of the following values:
643 * @arg @ref LL_DAC_TRIG_SOFTWARE
644 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
645 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
646 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
647 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
648 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
649 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
650 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
651 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
652 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
653 * @retval None
654 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)655 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
656 {
657 MODIFY_REG(DACx->CR,
658 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
659 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
660 }
661
662 /**
663 * @brief Get the conversion trigger source for the selected DAC channel.
664 * @note For conversion trigger source to be effective, DAC trigger
665 * must be enabled using function @ref LL_DAC_EnableTrigger().
666 * @note Availability of parameters of trigger sources from timer
667 * depends on timers availability on the selected device.
668 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
669 * CR TSEL2 LL_DAC_GetTriggerSource
670 * @param DACx DAC instance
671 * @param DAC_Channel This parameter can be one of the following values:
672 * @arg @ref LL_DAC_CHANNEL_1
673 * @arg @ref LL_DAC_CHANNEL_2
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_DAC_TRIG_SOFTWARE
676 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO
677 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
678 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
679 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
680 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
681 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
682 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT
683 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT
684 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
685 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)686 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
687 {
688 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
689 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
690 );
691 }
692
693 /**
694 * @brief Set the waveform automatic generation mode
695 * for the selected DAC channel.
696 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
697 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
698 * @param DACx DAC instance
699 * @param DAC_Channel This parameter can be one of the following values:
700 * @arg @ref LL_DAC_CHANNEL_1
701 * @arg @ref LL_DAC_CHANNEL_2
702 * @param WaveAutoGeneration This parameter can be one of the following values:
703 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
704 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
705 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
706 * @retval None
707 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)708 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
709 {
710 MODIFY_REG(DACx->CR,
711 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
712 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
713 }
714
715 /**
716 * @brief Get the waveform automatic generation mode
717 * for the selected DAC channel.
718 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
719 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
720 * @param DACx DAC instance
721 * @param DAC_Channel This parameter can be one of the following values:
722 * @arg @ref LL_DAC_CHANNEL_1
723 * @arg @ref LL_DAC_CHANNEL_2
724 * @retval Returned value can be one of the following values:
725 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
726 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
727 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
728 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)729 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
730 {
731 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
732 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
733 );
734 }
735
736 /**
737 * @brief Set the noise waveform generation for the selected DAC channel:
738 * Noise mode and parameters LFSR (linear feedback shift register).
739 * @note For wave generation to be effective, DAC channel
740 * wave generation mode must be enabled using
741 * function @ref LL_DAC_SetWaveAutoGeneration().
742 * @note This setting can be set when the selected DAC channel is disabled
743 * (otherwise, the setting operation is ignored).
744 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
745 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
746 * @param DACx DAC instance
747 * @param DAC_Channel This parameter can be one of the following values:
748 * @arg @ref LL_DAC_CHANNEL_1
749 * @arg @ref LL_DAC_CHANNEL_2
750 * @param NoiseLFSRMask This parameter can be one of the following values:
751 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
752 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
753 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
754 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
755 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
756 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
757 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
758 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
759 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
760 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
761 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
762 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
763 * @retval None
764 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)765 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
766 {
767 MODIFY_REG(DACx->CR,
768 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
769 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
770 }
771
772 /**
773 * @brief Get the noise waveform generation for the selected DAC channel:
774 * Noise mode and parameters LFSR (linear feedback shift register).
775 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
776 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
777 * @param DACx DAC instance
778 * @param DAC_Channel This parameter can be one of the following values:
779 * @arg @ref LL_DAC_CHANNEL_1
780 * @arg @ref LL_DAC_CHANNEL_2
781 * @retval Returned value can be one of the following values:
782 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
783 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
784 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
785 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
786 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
787 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
788 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
789 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
790 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
791 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
792 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
793 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
794 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)795 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
796 {
797 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
798 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
799 );
800 }
801
802 /**
803 * @brief Set the triangle waveform generation for the selected DAC channel:
804 * triangle mode and amplitude.
805 * @note For wave generation to be effective, DAC channel
806 * wave generation mode must be enabled using
807 * function @ref LL_DAC_SetWaveAutoGeneration().
808 * @note This setting can be set when the selected DAC channel is disabled
809 * (otherwise, the setting operation is ignored).
810 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
811 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
812 * @param DACx DAC instance
813 * @param DAC_Channel This parameter can be one of the following values:
814 * @arg @ref LL_DAC_CHANNEL_1
815 * @arg @ref LL_DAC_CHANNEL_2
816 * @param TriangleAmplitude This parameter can be one of the following values:
817 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
818 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
819 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
820 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
821 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
822 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
823 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
824 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
825 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
826 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
827 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
828 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
829 * @retval None
830 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)831 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
832 uint32_t TriangleAmplitude)
833 {
834 MODIFY_REG(DACx->CR,
835 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
836 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
837 }
838
839 /**
840 * @brief Get the triangle waveform generation for the selected DAC channel:
841 * triangle mode and amplitude.
842 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
843 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
844 * @param DACx DAC instance
845 * @param DAC_Channel This parameter can be one of the following values:
846 * @arg @ref LL_DAC_CHANNEL_1
847 * @arg @ref LL_DAC_CHANNEL_2
848 * @retval Returned value can be one of the following values:
849 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
850 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
851 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
852 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
853 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
854 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
855 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
856 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
857 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
858 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
859 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
860 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
861 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)862 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
863 {
864 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
865 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
866 );
867 }
868
869 /**
870 * @brief Set the output for the selected DAC channel.
871 * @note This function set several features:
872 * - mode normal or sample-and-hold
873 * - buffer
874 * - connection to GPIO or internal path.
875 * These features can also be set individually using
876 * dedicated functions:
877 * - @ref LL_DAC_SetOutputBuffer()
878 * - @ref LL_DAC_SetOutputMode()
879 * - @ref LL_DAC_SetOutputConnection()
880 * @note On this STM32 series, output connection depends on output mode
881 * (normal or sample and hold) and output buffer state.
882 * - if output connection is set to internal path and output buffer
883 * is enabled (whatever output mode):
884 * output connection is also connected to GPIO pin
885 * (both connections to GPIO pin and internal path).
886 * - if output connection is set to GPIO pin, output buffer
887 * is disabled, output mode set to sample and hold:
888 * output connection is also connected to internal path
889 * (both connections to GPIO pin and internal path).
890 * @note Mode sample-and-hold requires an external capacitor
891 * to be connected between DAC channel output and ground.
892 * Capacitor value depends on load on DAC channel output and
893 * sample-and-hold timings configured.
894 * As indication, capacitor typical value is 100nF
895 * (refer to device datasheet, parameter "CSH").
896 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
897 * CR MODE2 LL_DAC_ConfigOutput
898 * @param DACx DAC instance
899 * @param DAC_Channel This parameter can be one of the following values:
900 * @arg @ref LL_DAC_CHANNEL_1
901 * @arg @ref LL_DAC_CHANNEL_2
902 * @param OutputMode This parameter can be one of the following values:
903 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
904 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
905 * @param OutputBuffer This parameter can be one of the following values:
906 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
907 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
908 * @param OutputConnection This parameter can be one of the following values:
909 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
910 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
911 * @retval None
912 */
LL_DAC_ConfigOutput(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode,uint32_t OutputBuffer,uint32_t OutputConnection)913 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
914 uint32_t OutputBuffer, uint32_t OutputConnection)
915 {
916 MODIFY_REG(DACx->MCR,
917 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
918 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
919 }
920
921 /**
922 * @brief Set the output mode normal or sample-and-hold
923 * for the selected DAC channel.
924 * @note Mode sample-and-hold requires an external capacitor
925 * to be connected between DAC channel output and ground.
926 * Capacitor value depends on load on DAC channel output and
927 * sample-and-hold timings configured.
928 * As indication, capacitor typical value is 100nF
929 * (refer to device datasheet, parameter "CSH").
930 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
931 * CR MODE2 LL_DAC_SetOutputMode
932 * @param DACx DAC instance
933 * @param DAC_Channel This parameter can be one of the following values:
934 * @arg @ref LL_DAC_CHANNEL_1
935 * @arg @ref LL_DAC_CHANNEL_2
936 * @param OutputMode This parameter can be one of the following values:
937 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
938 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
939 * @retval None
940 */
LL_DAC_SetOutputMode(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputMode)941 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
942 {
943 MODIFY_REG(DACx->MCR,
944 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
945 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
946 }
947
948 /**
949 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
950 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
951 * CR MODE2 LL_DAC_GetOutputMode
952 * @param DACx DAC instance
953 * @param DAC_Channel This parameter can be one of the following values:
954 * @arg @ref LL_DAC_CHANNEL_1
955 * @arg @ref LL_DAC_CHANNEL_2
956 * @retval Returned value can be one of the following values:
957 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
958 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
959 */
LL_DAC_GetOutputMode(const DAC_TypeDef * DACx,uint32_t DAC_Channel)960 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
961 {
962 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
963 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
964 );
965 }
966
967 /**
968 * @brief Set the output buffer for the selected DAC channel.
969 * @note On this STM32 series, when buffer is enabled, its offset can be
970 * trimmed: factory calibration default values can be
971 * replaced by user trimming values, using function
972 * @ref LL_DAC_SetTrimmingValue().
973 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
974 * CR MODE2 LL_DAC_SetOutputBuffer
975 * @param DACx DAC instance
976 * @param DAC_Channel This parameter can be one of the following values:
977 * @arg @ref LL_DAC_CHANNEL_1
978 * @arg @ref LL_DAC_CHANNEL_2
979 * @param OutputBuffer This parameter can be one of the following values:
980 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
981 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
982 * @retval None
983 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)984 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
985 {
986 MODIFY_REG(DACx->MCR,
987 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
988 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
989 }
990
991 /**
992 * @brief Get the output buffer state for the selected DAC channel.
993 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
994 * CR MODE2 LL_DAC_GetOutputBuffer
995 * @param DACx DAC instance
996 * @param DAC_Channel This parameter can be one of the following values:
997 * @arg @ref LL_DAC_CHANNEL_1
998 * @arg @ref LL_DAC_CHANNEL_2
999 * @retval Returned value can be one of the following values:
1000 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1001 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1002 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1003 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1004 {
1005 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1006 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1007 );
1008 }
1009
1010 /**
1011 * @brief Set the output connection for the selected DAC channel.
1012 * @note On this STM32 series, output connection depends on output mode (normal or
1013 * sample and hold) and output buffer state.
1014 * - if output connection is set to internal path and output buffer
1015 * is enabled (whatever output mode):
1016 * output connection is also connected to GPIO pin
1017 * (both connections to GPIO pin and internal path).
1018 * - if output connection is set to GPIO pin, output buffer
1019 * is disabled, output mode set to sample and hold:
1020 * output connection is also connected to internal path
1021 * (both connections to GPIO pin and internal path).
1022 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1023 * CR MODE2 LL_DAC_SetOutputConnection
1024 * @param DACx DAC instance
1025 * @param DAC_Channel This parameter can be one of the following values:
1026 * @arg @ref LL_DAC_CHANNEL_1
1027 * @arg @ref LL_DAC_CHANNEL_2
1028 * @param OutputConnection This parameter can be one of the following values:
1029 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1030 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1031 * @retval None
1032 */
LL_DAC_SetOutputConnection(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputConnection)1033 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1034 {
1035 MODIFY_REG(DACx->MCR,
1036 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1037 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1038 }
1039
1040 /**
1041 * @brief Get the output connection for the selected DAC channel.
1042 * @note On this STM32 series, output connection depends on output mode (normal or
1043 * sample and hold) and output buffer state.
1044 * - if output connection is set to internal path and output buffer
1045 * is enabled (whatever output mode):
1046 * output connection is also connected to GPIO pin
1047 * (both connections to GPIO pin and internal path).
1048 * - if output connection is set to GPIO pin, output buffer
1049 * is disabled, output mode set to sample and hold:
1050 * output connection is also connected to internal path
1051 * (both connections to GPIO pin and internal path).
1052 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1053 * CR MODE2 LL_DAC_GetOutputConnection
1054 * @param DACx DAC instance
1055 * @param DAC_Channel This parameter can be one of the following values:
1056 * @arg @ref LL_DAC_CHANNEL_1
1057 * @arg @ref LL_DAC_CHANNEL_2
1058 * @retval Returned value can be one of the following values:
1059 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1060 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1061 */
LL_DAC_GetOutputConnection(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1062 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1063 {
1064 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1065 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1066 );
1067 }
1068
1069 /**
1070 * @brief Set the sample-and-hold timing for the selected DAC channel:
1071 * sample time
1072 * @note Sample time must be set when DAC channel is disabled
1073 * or during DAC operation when DAC channel flag BWSTx is reset,
1074 * otherwise the setting is ignored.
1075 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1076 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1077 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1078 * @param DACx DAC instance
1079 * @param DAC_Channel This parameter can be one of the following values:
1080 * @arg @ref LL_DAC_CHANNEL_1
1081 * @arg @ref LL_DAC_CHANNEL_2
1082 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1083 * @retval None
1084 */
LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t SampleTime)1085 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1086 {
1087 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1088 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1089
1090 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1091 }
1092
1093 /**
1094 * @brief Get the sample-and-hold timing for the selected DAC channel:
1095 * sample time
1096 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1097 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1098 * @param DACx DAC instance
1099 * @param DAC_Channel This parameter can be one of the following values:
1100 * @arg @ref LL_DAC_CHANNEL_1
1101 * @arg @ref LL_DAC_CHANNEL_2
1102 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1103 */
LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1104 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1105 {
1106 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1107 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1108
1109 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1110 }
1111
1112 /**
1113 * @brief Set the sample-and-hold timing for the selected DAC channel:
1114 * hold time
1115 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1116 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1117 * @param DACx DAC instance
1118 * @param DAC_Channel This parameter can be one of the following values:
1119 * @arg @ref LL_DAC_CHANNEL_1
1120 * @arg @ref LL_DAC_CHANNEL_2
1121 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1122 * @retval None
1123 */
LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t HoldTime)1124 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1125 {
1126 MODIFY_REG(DACx->SHHR,
1127 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1128 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1129 }
1130
1131 /**
1132 * @brief Get the sample-and-hold timing for the selected DAC channel:
1133 * hold time
1134 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1135 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1136 * @param DACx DAC instance
1137 * @param DAC_Channel This parameter can be one of the following values:
1138 * @arg @ref LL_DAC_CHANNEL_1
1139 * @arg @ref LL_DAC_CHANNEL_2
1140 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1141 */
LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1142 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1143 {
1144 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1145 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1146 );
1147 }
1148
1149 /**
1150 * @brief Set the sample-and-hold timing for the selected DAC channel:
1151 * refresh time
1152 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1153 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1154 * @param DACx DAC instance
1155 * @param DAC_Channel This parameter can be one of the following values:
1156 * @arg @ref LL_DAC_CHANNEL_1
1157 * @arg @ref LL_DAC_CHANNEL_2
1158 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1159 * @retval None
1160 */
LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t RefreshTime)1161 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1162 {
1163 MODIFY_REG(DACx->SHRR,
1164 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1165 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1166 }
1167
1168 /**
1169 * @brief Get the sample-and-hold timing for the selected DAC channel:
1170 * refresh time
1171 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1172 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1173 * @param DACx DAC instance
1174 * @param DAC_Channel This parameter can be one of the following values:
1175 * @arg @ref LL_DAC_CHANNEL_1
1176 * @arg @ref LL_DAC_CHANNEL_2
1177 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1178 */
LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1179 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1180 {
1181 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1182 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1183 );
1184 }
1185
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1191 * @{
1192 */
1193
1194 /**
1195 * @brief Enable DAC DMA transfer request of the selected channel.
1196 * @note To configure DMA source address (peripheral address),
1197 * use function @ref LL_DAC_DMA_GetRegAddr().
1198 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1199 * CR DMAEN2 LL_DAC_EnableDMAReq
1200 * @param DACx DAC instance
1201 * @param DAC_Channel This parameter can be one of the following values:
1202 * @arg @ref LL_DAC_CHANNEL_1
1203 * @arg @ref LL_DAC_CHANNEL_2
1204 * @retval None
1205 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1206 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1207 {
1208 SET_BIT(DACx->CR,
1209 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1210 }
1211
1212 /**
1213 * @brief Disable DAC DMA transfer request of the selected channel.
1214 * @note To configure DMA source address (peripheral address),
1215 * use function @ref LL_DAC_DMA_GetRegAddr().
1216 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1217 * CR DMAEN2 LL_DAC_DisableDMAReq
1218 * @param DACx DAC instance
1219 * @param DAC_Channel This parameter can be one of the following values:
1220 * @arg @ref LL_DAC_CHANNEL_1
1221 * @arg @ref LL_DAC_CHANNEL_2
1222 * @retval None
1223 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)1224 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1225 {
1226 CLEAR_BIT(DACx->CR,
1227 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1228 }
1229
1230 /**
1231 * @brief Get DAC DMA transfer request state of the selected channel.
1232 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1233 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1234 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1235 * @param DACx DAC instance
1236 * @param DAC_Channel This parameter can be one of the following values:
1237 * @arg @ref LL_DAC_CHANNEL_1
1238 * @arg @ref LL_DAC_CHANNEL_2
1239 * @retval State of bit (1 or 0).
1240 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1241 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1242 {
1243 return ((READ_BIT(DACx->CR,
1244 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1245 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1246 }
1247
1248 /**
1249 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1250 * DAC register address from DAC instance and a list of DAC registers
1251 * intended to be used (most commonly) with DMA transfer.
1252 * @note These DAC registers are data holding registers:
1253 * when DAC conversion is requested, DAC generates a DMA transfer
1254 * request to have data available in DAC data holding registers.
1255 * @note This macro is intended to be used with LL DMA driver, refer to
1256 * function "LL_DMA_ConfigAddresses()".
1257 * Example:
1258 * LL_DMA_ConfigAddresses(DMA1,
1259 * LL_DMA_CHANNEL_1,
1260 * (uint32_t)&< array or variable >,
1261 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
1262 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1263 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1264 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1265 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1266 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1267 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1268 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1269 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1270 * @param DACx DAC instance
1271 * @param DAC_Channel This parameter can be one of the following values:
1272 * @arg @ref LL_DAC_CHANNEL_1
1273 * @arg @ref LL_DAC_CHANNEL_2
1274 * @param Register This parameter can be one of the following values:
1275 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1276 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1277 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1278 * @retval DAC register address
1279 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)1280 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1281 {
1282 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1283 /* DAC channel selected. */
1284 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1285 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1286 }
1287 /**
1288 * @}
1289 */
1290
1291 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1292 * @{
1293 */
1294
1295 /**
1296 * @brief Enable DAC selected channel.
1297 * @rmtoll CR EN1 LL_DAC_Enable\n
1298 * CR EN2 LL_DAC_Enable
1299 * @note After enable from off state, DAC channel requires a delay
1300 * for output voltage to reach accuracy +/- 1 LSB.
1301 * Refer to device datasheet, parameter "tWAKEUP".
1302 * @param DACx DAC instance
1303 * @param DAC_Channel This parameter can be one of the following values:
1304 * @arg @ref LL_DAC_CHANNEL_1
1305 * @arg @ref LL_DAC_CHANNEL_2
1306 * @retval None
1307 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1308 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1309 {
1310 SET_BIT(DACx->CR,
1311 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1312 }
1313
1314 /**
1315 * @brief Disable DAC selected channel.
1316 * @rmtoll CR EN1 LL_DAC_Disable\n
1317 * CR EN2 LL_DAC_Disable
1318 * @param DACx DAC instance
1319 * @param DAC_Channel This parameter can be one of the following values:
1320 * @arg @ref LL_DAC_CHANNEL_1
1321 * @arg @ref LL_DAC_CHANNEL_2
1322 * @retval None
1323 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)1324 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1325 {
1326 CLEAR_BIT(DACx->CR,
1327 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1328 }
1329
1330 /**
1331 * @brief Get DAC enable state of the selected channel.
1332 * (0: DAC channel is disabled, 1: DAC channel is enabled)
1333 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
1334 * CR EN2 LL_DAC_IsEnabled
1335 * @param DACx DAC instance
1336 * @param DAC_Channel This parameter can be one of the following values:
1337 * @arg @ref LL_DAC_CHANNEL_1
1338 * @arg @ref LL_DAC_CHANNEL_2
1339 * @retval State of bit (1 or 0).
1340 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1341 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1342 {
1343 return ((READ_BIT(DACx->CR,
1344 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1345 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1346 }
1347
1348 /**
1349 * @brief Enable DAC trigger of the selected channel.
1350 * @note - If DAC trigger is disabled, DAC conversion is performed
1351 * automatically once the data holding register is updated,
1352 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1353 * @ref LL_DAC_ConvertData12RightAligned(), ...
1354 * - If DAC trigger is enabled, DAC conversion is performed
1355 * only when a hardware of software trigger event is occurring.
1356 * Select trigger source using
1357 * function @ref LL_DAC_SetTriggerSource().
1358 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1359 * CR TEN2 LL_DAC_EnableTrigger
1360 * @param DACx DAC instance
1361 * @param DAC_Channel This parameter can be one of the following values:
1362 * @arg @ref LL_DAC_CHANNEL_1
1363 * @arg @ref LL_DAC_CHANNEL_2
1364 * @retval None
1365 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1366 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1367 {
1368 SET_BIT(DACx->CR,
1369 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1370 }
1371
1372 /**
1373 * @brief Disable DAC trigger of the selected channel.
1374 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1375 * CR TEN2 LL_DAC_DisableTrigger
1376 * @param DACx DAC instance
1377 * @param DAC_Channel This parameter can be one of the following values:
1378 * @arg @ref LL_DAC_CHANNEL_1
1379 * @arg @ref LL_DAC_CHANNEL_2
1380 * @retval None
1381 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1382 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1383 {
1384 CLEAR_BIT(DACx->CR,
1385 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1386 }
1387
1388 /**
1389 * @brief Get DAC trigger state of the selected channel.
1390 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1391 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1392 * CR TEN2 LL_DAC_IsTriggerEnabled
1393 * @param DACx DAC instance
1394 * @param DAC_Channel This parameter can be one of the following values:
1395 * @arg @ref LL_DAC_CHANNEL_1
1396 * @arg @ref LL_DAC_CHANNEL_2
1397 * @retval State of bit (1 or 0).
1398 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1399 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1400 {
1401 return ((READ_BIT(DACx->CR,
1402 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1403 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1404 }
1405
1406 /**
1407 * @brief Trig DAC conversion by software for the selected DAC channel.
1408 * @note Preliminarily, DAC trigger must be set to software trigger
1409 * using function
1410 * @ref LL_DAC_Init()
1411 * @ref LL_DAC_SetTriggerSource()
1412 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1413 * and DAC trigger must be enabled using
1414 * function @ref LL_DAC_EnableTrigger().
1415 * @note For devices featuring DAC with 2 channels: this function
1416 * can perform a SW start of both DAC channels simultaneously.
1417 * Two channels can be selected as parameter.
1418 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1419 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1420 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1421 * @param DACx DAC instance
1422 * @param DAC_Channel This parameter can a combination of the following values:
1423 * @arg @ref LL_DAC_CHANNEL_1
1424 * @arg @ref LL_DAC_CHANNEL_2
1425 * @retval None
1426 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1427 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1428 {
1429 SET_BIT(DACx->SWTRIGR,
1430 (DAC_Channel & DAC_SWTR_CHX_MASK));
1431 }
1432
1433 /**
1434 * @brief Set the data to be loaded in the data holding register
1435 * in format 12 bits left alignment (LSB aligned on bit 0),
1436 * for the selected DAC channel.
1437 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1438 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1439 * @param DACx DAC instance
1440 * @param DAC_Channel This parameter can be one of the following values:
1441 * @arg @ref LL_DAC_CHANNEL_1
1442 * @arg @ref LL_DAC_CHANNEL_2
1443 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1444 * @retval None
1445 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1446 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1447 {
1448 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1449 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1450
1451 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1452 }
1453
1454 /**
1455 * @brief Set the data to be loaded in the data holding register
1456 * in format 12 bits left alignment (MSB aligned on bit 15),
1457 * for the selected DAC channel.
1458 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1459 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1460 * @param DACx DAC instance
1461 * @param DAC_Channel This parameter can be one of the following values:
1462 * @arg @ref LL_DAC_CHANNEL_1
1463 * @arg @ref LL_DAC_CHANNEL_2
1464 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1465 * @retval None
1466 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1467 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1468 {
1469 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1470 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1471
1472 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1473 }
1474
1475 /**
1476 * @brief Set the data to be loaded in the data holding register
1477 * in format 8 bits left alignment (LSB aligned on bit 0),
1478 * for the selected DAC channel.
1479 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1480 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1481 * @param DACx DAC instance
1482 * @param DAC_Channel This parameter can be one of the following values:
1483 * @arg @ref LL_DAC_CHANNEL_1
1484 * @arg @ref LL_DAC_CHANNEL_2
1485 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1486 * @retval None
1487 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1488 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1489 {
1490 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1491 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1492
1493 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1494 }
1495
1496
1497 /**
1498 * @brief Set the data to be loaded in the data holding register
1499 * in format 12 bits left alignment (LSB aligned on bit 0),
1500 * for both DAC channels.
1501 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1502 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1503 * @param DACx DAC instance
1504 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1505 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1506 * @retval None
1507 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1508 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1509 uint32_t DataChannel2)
1510 {
1511 MODIFY_REG(DACx->DHR12RD,
1512 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1513 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1514 }
1515
1516 /**
1517 * @brief Set the data to be loaded in the data holding register
1518 * in format 12 bits left alignment (MSB aligned on bit 15),
1519 * for both DAC channels.
1520 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1521 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1522 * @param DACx DAC instance
1523 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1524 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1525 * @retval None
1526 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1527 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1528 uint32_t DataChannel2)
1529 {
1530 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1531 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1532 /* the 4 LSB must be taken into account for the shift value. */
1533 MODIFY_REG(DACx->DHR12LD,
1534 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1535 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1536 }
1537
1538 /**
1539 * @brief Set the data to be loaded in the data holding register
1540 * in format 8 bits left alignment (LSB aligned on bit 0),
1541 * for both DAC channels.
1542 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1543 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1544 * @param DACx DAC instance
1545 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1546 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1547 * @retval None
1548 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1549 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1550 uint32_t DataChannel2)
1551 {
1552 MODIFY_REG(DACx->DHR8RD,
1553 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1554 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1555 }
1556
1557
1558 /**
1559 * @brief Retrieve output data currently generated for the selected DAC channel.
1560 * @note Whatever alignment and resolution settings
1561 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1562 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1563 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1564 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1565 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1566 * @param DACx DAC instance
1567 * @param DAC_Channel This parameter can be one of the following values:
1568 * @arg @ref LL_DAC_CHANNEL_1
1569 * @arg @ref LL_DAC_CHANNEL_2
1570 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1571 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1572 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1573 {
1574 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1575 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1576
1577 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1578 }
1579
1580 /**
1581 * @}
1582 */
1583
1584 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1585 * @{
1586 */
1587
1588 /**
1589 * @brief Get DAC calibration offset flag for DAC channel 1
1590 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
1591 * @param DACx DAC instance
1592 * @retval State of bit (1 or 0).
1593 */
LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef * DACx)1594 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
1595 {
1596 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1597 }
1598
1599
1600 /**
1601 * @brief Get DAC calibration offset flag for DAC channel 2
1602 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
1603 * @param DACx DAC instance
1604 * @retval State of bit (1 or 0).
1605 */
LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef * DACx)1606 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
1607 {
1608 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1609 }
1610
1611
1612 /**
1613 * @brief Get DAC busy writing sample time flag for DAC channel 1
1614 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
1615 * @param DACx DAC instance
1616 * @retval State of bit (1 or 0).
1617 */
LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef * DACx)1618 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
1619 {
1620 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1621 }
1622
1623 /**
1624 * @brief Get DAC busy writing sample time flag for DAC channel 2
1625 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
1626 * @param DACx DAC instance
1627 * @retval State of bit (1 or 0).
1628 */
LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef * DACx)1629 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
1630 {
1631 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1632 }
1633
1634
1635 /**
1636 * @brief Get DAC underrun flag for DAC channel 1
1637 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1638 * @param DACx DAC instance
1639 * @retval State of bit (1 or 0).
1640 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1641 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1642 {
1643 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1644 }
1645
1646
1647 /**
1648 * @brief Get DAC underrun flag for DAC channel 2
1649 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1650 * @param DACx DAC instance
1651 * @retval State of bit (1 or 0).
1652 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1653 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1654 {
1655 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1656 }
1657
1658
1659 /**
1660 * @brief Clear DAC underrun flag for DAC channel 1
1661 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1662 * @param DACx DAC instance
1663 * @retval None
1664 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1665 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1666 {
1667 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1668 }
1669
1670
1671 /**
1672 * @brief Clear DAC underrun flag for DAC channel 2
1673 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1674 * @param DACx DAC instance
1675 * @retval None
1676 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1677 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1678 {
1679 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1680 }
1681
1682
1683 /**
1684 * @}
1685 */
1686
1687 /** @defgroup DAC_LL_EF_IT_Management IT management
1688 * @{
1689 */
1690
1691 /**
1692 * @brief Enable DMA underrun interrupt for DAC channel 1
1693 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1694 * @param DACx DAC instance
1695 * @retval None
1696 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1697 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1698 {
1699 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1700 }
1701
1702
1703 /**
1704 * @brief Enable DMA underrun interrupt for DAC channel 2
1705 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1706 * @param DACx DAC instance
1707 * @retval None
1708 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1709 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1710 {
1711 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1712 }
1713
1714
1715 /**
1716 * @brief Disable DMA underrun interrupt for DAC channel 1
1717 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1718 * @param DACx DAC instance
1719 * @retval None
1720 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1721 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1722 {
1723 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1724 }
1725
1726
1727 /**
1728 * @brief Disable DMA underrun interrupt for DAC channel 2
1729 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1730 * @param DACx DAC instance
1731 * @retval None
1732 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1733 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1734 {
1735 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1736 }
1737
1738
1739 /**
1740 * @brief Get DMA underrun interrupt for DAC channel 1
1741 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1742 * @param DACx DAC instance
1743 * @retval State of bit (1 or 0).
1744 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1745 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1746 {
1747 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1748 }
1749
1750
1751 /**
1752 * @brief Get DMA underrun interrupt for DAC channel 2
1753 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1754 * @param DACx DAC instance
1755 * @retval State of bit (1 or 0).
1756 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)1757 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1758 {
1759 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1760 }
1761
1762
1763 /**
1764 * @}
1765 */
1766
1767 #if defined(USE_FULL_LL_DRIVER)
1768 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1769 * @{
1770 */
1771
1772 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1773 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1774 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1775
1776 /**
1777 * @}
1778 */
1779 #endif /* USE_FULL_LL_DRIVER */
1780
1781 /**
1782 * @}
1783 */
1784
1785 /**
1786 * @}
1787 */
1788
1789 #endif /* DAC1 */
1790
1791 /**
1792 * @}
1793 */
1794
1795 #ifdef __cplusplus
1796 }
1797 #endif
1798
1799 #endif /* STM32G0xx_LL_DAC_H */
1800
