1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #endif /* STM32H7 || STM32MP1 */ 46 /** 47 * @} 48 */ 49 50 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 51 * @{ 52 */ 53 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 54 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 55 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 56 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 57 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 58 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 59 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 60 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 61 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 62 #define REGULAR_GROUP ADC_REGULAR_GROUP 63 #define INJECTED_GROUP ADC_INJECTED_GROUP 64 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 65 #define AWD_EVENT ADC_AWD_EVENT 66 #define AWD1_EVENT ADC_AWD1_EVENT 67 #define AWD2_EVENT ADC_AWD2_EVENT 68 #define AWD3_EVENT ADC_AWD3_EVENT 69 #define OVR_EVENT ADC_OVR_EVENT 70 #define JQOVF_EVENT ADC_JQOVF_EVENT 71 #define ALL_CHANNELS ADC_ALL_CHANNELS 72 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 73 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 74 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 75 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 76 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 77 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 78 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 79 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 80 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 81 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 82 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 83 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 84 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 85 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 86 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 87 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 88 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 89 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 90 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 91 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 92 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 93 94 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 95 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 96 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 97 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 98 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 99 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 100 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 101 102 #if defined(STM32H7) 103 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 104 #endif /* STM32H7 */ 105 106 107 /** 108 * @} 109 */ 110 111 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 112 * @{ 113 */ 114 115 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 116 117 /** 118 * @} 119 */ 120 121 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 122 * @{ 123 */ 124 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 125 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 126 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 127 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 128 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 129 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 130 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 131 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 132 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 133 #if defined(STM32L0) 134 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM 135 input 1 for COMP1, LPTIM input 2 for COMP2 */ 136 #endif 137 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 138 #if defined(STM32F373xC) || defined(STM32F378xx) 139 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 140 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 141 #endif /* STM32F373xC || STM32F378xx */ 142 143 #if defined(STM32L0) || defined(STM32L4) 144 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 145 146 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 147 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 148 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 149 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 150 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 151 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 152 153 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 154 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 155 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 156 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 157 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 158 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 159 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 160 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 161 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 162 #if defined(STM32L0) 163 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 164 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 165 /* to the second dedicated IO (only for COMP2). */ 166 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 168 #else 169 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 170 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 171 #endif 172 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 173 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 174 175 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 176 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 177 178 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 179 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 180 #if defined(COMP_CSR_LOCK) 181 #define COMP_FLAG_LOCK COMP_CSR_LOCK 182 #elif defined(COMP_CSR_COMP1LOCK) 183 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 184 #elif defined(COMP_CSR_COMPxLOCK) 185 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 186 #endif 187 188 #if defined(STM32L4) 189 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 190 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 191 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 192 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 193 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 194 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 195 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 196 #endif 197 198 #if defined(STM32L0) 199 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 200 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 201 #else 202 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 203 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 204 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 205 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 206 #endif 207 208 #endif 209 210 211 /** 212 * @} 213 */ 214 215 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 216 * @{ 217 */ 218 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 219 /** 220 * @} 221 */ 222 223 /** @defgroup CRC_Aliases CRC API aliases 224 * @{ 225 */ 226 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 227 inter STM32 series compatibility */ 228 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 229 inter STM32 series compatibility */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 235 * @{ 236 */ 237 238 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 239 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 240 241 /** 242 * @} 243 */ 244 245 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 246 * @{ 247 */ 248 249 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 250 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 251 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 252 #define DAC_WAVE_NONE 0x00000000U 253 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 254 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 255 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 256 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 257 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 258 259 #if defined(STM32G4) || defined(STM32H7) 260 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 261 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 262 #endif 263 264 265 266 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ 267 defined(STM32F4) || defined(STM32G4) 268 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 269 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 270 #endif 271 272 /** 273 * @} 274 */ 275 276 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 277 * @{ 278 */ 279 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 280 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 281 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 282 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 283 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 284 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 285 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 286 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 287 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 288 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 289 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 290 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 291 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 292 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 293 294 #define IS_HAL_REMAPDMA IS_DMA_REMAP 295 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 296 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 297 298 #if defined(STM32L4) 299 300 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 301 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 302 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 303 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 304 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 305 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 306 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 307 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 308 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 309 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 310 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 311 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 312 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 313 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 314 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 315 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 316 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 317 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 318 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 319 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 320 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 321 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 322 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 323 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 324 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 325 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 326 327 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 328 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 329 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 330 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 331 332 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ 333 defined(STM32L4S7xx) || defined(STM32L4S9xx) 334 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 335 #endif 336 337 #endif /* STM32L4 */ 338 339 #if defined(STM32G0) 340 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 341 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 342 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 343 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 344 345 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 346 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 347 #endif 348 349 #if defined(STM32H7) 350 351 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 352 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 353 354 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 355 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 356 357 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 358 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 359 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 360 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 361 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 362 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 363 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 364 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 365 366 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 367 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 368 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 369 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 370 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 371 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 372 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 373 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 374 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 375 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 376 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 377 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 378 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 379 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 380 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 381 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 382 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 383 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 384 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 385 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 386 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 387 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 388 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 389 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 390 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 391 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 392 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 393 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 394 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 395 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 396 397 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 398 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 399 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 400 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 401 402 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 403 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 404 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 405 406 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 407 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 408 409 #endif /* STM32H7 */ 410 411 /** 412 * @} 413 */ 414 415 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 416 * @{ 417 */ 418 419 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 420 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 421 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 422 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 423 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 424 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 425 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 426 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 427 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 428 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 429 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 430 #define OBEX_PCROP OPTIONBYTE_PCROP 431 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 432 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 433 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 434 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 435 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 436 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 437 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 438 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 439 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 440 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 441 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 442 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 443 /* #define PAGESIZE FLASH_PAGE_SIZE */ 444 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 445 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 446 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 447 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 448 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 449 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 450 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 451 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 452 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 453 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 454 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 455 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 456 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 457 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 458 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 459 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 460 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 461 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 462 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 463 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 464 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 465 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 466 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 467 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 468 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 469 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 470 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 471 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 472 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 473 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 474 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 475 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 476 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 477 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 478 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 479 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 480 #define OB_WDG_SW OB_IWDG_SW 481 #define OB_WDG_HW OB_IWDG_HW 482 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 483 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 484 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 485 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 486 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 487 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 488 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 489 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 490 #if defined(STM32G0) 491 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 492 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 493 #else 494 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 495 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 496 #endif 497 #if defined(STM32H7) 498 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 499 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 500 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 501 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 502 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 503 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 504 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 505 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 506 #endif /* STM32H7 */ 507 508 /** 509 * @} 510 */ 511 512 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 513 * @{ 514 */ 515 516 #if defined(STM32H7) 517 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 518 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 519 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 520 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 521 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 522 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 523 #endif /* STM32H7 */ 524 525 /** 526 * @} 527 */ 528 529 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 530 * @{ 531 */ 532 533 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 534 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 535 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 536 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 537 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 538 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 539 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 540 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 541 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 542 #if defined(STM32G4) 543 544 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 545 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 546 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 547 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 548 #endif /* STM32G4 */ 549 550 551 552 /** 553 * @} 554 */ 555 556 557 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 558 * @{ 559 */ 560 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 561 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 562 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 563 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 564 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 565 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 566 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 567 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 568 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 569 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 570 #endif 571 /** 572 * @} 573 */ 574 575 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 576 * @{ 577 */ 578 579 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 580 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 581 /** 582 * @} 583 */ 584 585 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 586 * @{ 587 */ 588 #define GET_GPIO_SOURCE GPIO_GET_INDEX 589 #define GET_GPIO_INDEX GPIO_GET_INDEX 590 591 #if defined(STM32F4) 592 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 593 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 594 #endif 595 596 #if defined(STM32F7) 597 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 598 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 599 #endif 600 601 #if defined(STM32L4) 602 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 603 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 604 #endif 605 606 #if defined(STM32H7) 607 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 608 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 609 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 610 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 611 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 612 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 613 614 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 615 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 616 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 617 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 618 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 619 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ 620 STM32H757xx */ 621 #endif /* STM32H7 */ 622 623 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 624 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 625 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 626 627 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) 628 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 629 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 630 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 631 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 632 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */ 633 634 #if defined(STM32L1) 635 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 636 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 637 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 638 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 639 #endif /* STM32L1 */ 640 641 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 642 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 643 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 644 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 645 #endif /* STM32F0 || STM32F3 || STM32F1 */ 646 647 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 648 649 /** 650 * @} 651 */ 652 653 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 654 * @{ 655 */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 661 * @{ 662 */ 663 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 664 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 665 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 666 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 667 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 668 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 669 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 670 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 671 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 672 673 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 674 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 675 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 676 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 677 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 678 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 679 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 680 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 681 682 #if defined(STM32G4) 683 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 684 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 685 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 686 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 687 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 688 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 689 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 690 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 691 #endif /* STM32G4 */ 692 693 #if defined(STM32H7) 694 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 695 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 696 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 697 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 698 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 699 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 700 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 701 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 702 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 703 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 704 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 705 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 706 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 707 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 708 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 709 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 710 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 711 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 712 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 713 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 714 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 715 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 716 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 717 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 718 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 719 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 720 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 721 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 722 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 723 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 724 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 725 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 726 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 727 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 728 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 729 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 730 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 731 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 732 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 733 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 734 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 735 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 736 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 737 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 738 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 739 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 740 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 741 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 742 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 743 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 744 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 745 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 746 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 747 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 748 749 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 750 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 751 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 752 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 753 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 754 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 755 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 756 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 757 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 758 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 759 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 760 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 761 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 762 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 763 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 764 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 765 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 766 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 767 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 768 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 769 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 770 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 771 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 772 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 773 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 774 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 775 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 776 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 777 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 778 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 779 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 780 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 781 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 782 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 783 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 784 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 785 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 786 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 787 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 788 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 789 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 790 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 791 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 792 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 793 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 794 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 795 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 796 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 797 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 798 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 799 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 800 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 801 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 802 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 803 #endif /* STM32H7 */ 804 805 #if defined(STM32F3) 806 /** @brief Constants defining available sources associated to external events. 807 */ 808 #define HRTIM_EVENTSRC_1 (0x00000000U) 809 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 810 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 811 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 812 813 /** @brief Constants defining the DLL calibration periods (in micro seconds) 814 */ 815 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 816 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 817 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 818 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 819 820 #endif /* STM32F3 */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 826 * @{ 827 */ 828 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 829 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 830 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 831 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 832 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 833 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 834 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 835 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 836 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ 837 defined(STM32L1) || defined(STM32F7) 838 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 839 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 840 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 841 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 842 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 843 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 844 #endif 845 /** 846 * @} 847 */ 848 849 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 850 * @{ 851 */ 852 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 853 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 854 855 /** 856 * @} 857 */ 858 859 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 860 * @{ 861 */ 862 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 863 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 864 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 865 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 866 /** 867 * @} 868 */ 869 870 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 871 * @{ 872 */ 873 874 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 875 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 876 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 877 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 878 879 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 880 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 881 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 882 883 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 884 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 885 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 886 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 887 888 /* The following 3 definition have also been present in a temporary version of lptim.h */ 889 /* They need to be renamed also to the right name, just in case */ 890 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 891 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 892 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 893 894 895 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 896 * @{ 897 */ 898 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 899 /** 900 * @} 901 */ 902 903 /** 904 * @} 905 */ 906 907 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 908 * @{ 909 */ 910 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 911 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 912 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 913 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 914 915 #define NAND_AddressTypedef NAND_AddressTypeDef 916 917 #define __ARRAY_ADDRESS ARRAY_ADDRESS 918 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 919 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 920 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 921 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 922 /** 923 * @} 924 */ 925 926 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 927 * @{ 928 */ 929 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 930 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 931 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 932 #define NOR_ERROR HAL_NOR_STATUS_ERROR 933 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 934 935 #define __NOR_WRITE NOR_WRITE 936 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 937 /** 938 * @} 939 */ 940 941 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 942 * @{ 943 */ 944 945 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 946 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 947 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 948 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 949 950 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 951 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 952 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 953 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 954 955 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 956 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 957 958 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 959 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 960 961 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 962 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 963 964 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 965 966 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 967 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 968 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 969 970 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 971 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 972 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 973 #endif 974 975 #if defined(STM32L4) || defined(STM32L5) 976 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 977 #elif defined(STM32G4) 978 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 979 #endif 980 981 /** 982 * @} 983 */ 984 985 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 986 * @{ 987 */ 988 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 989 990 #if defined(STM32H7) 991 #define I2S_IT_TXE I2S_IT_TXP 992 #define I2S_IT_RXNE I2S_IT_RXP 993 994 #define I2S_FLAG_TXE I2S_FLAG_TXP 995 #define I2S_FLAG_RXNE I2S_FLAG_RXP 996 #endif 997 998 #if defined(STM32F7) 999 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1000 #endif 1001 /** 1002 * @} 1003 */ 1004 1005 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1006 * @{ 1007 */ 1008 1009 /* Compact Flash-ATA registers description */ 1010 #define CF_DATA ATA_DATA 1011 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1012 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1013 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1014 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1015 #define CF_CARD_HEAD ATA_CARD_HEAD 1016 #define CF_STATUS_CMD ATA_STATUS_CMD 1017 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1018 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1019 1020 /* Compact Flash-ATA commands */ 1021 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1022 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1023 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1024 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1025 1026 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1027 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1028 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1029 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1030 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1031 /** 1032 * @} 1033 */ 1034 1035 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1036 * @{ 1037 */ 1038 1039 #define FORMAT_BIN RTC_FORMAT_BIN 1040 #define FORMAT_BCD RTC_FORMAT_BCD 1041 1042 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1043 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1044 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1045 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1046 1047 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1048 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1049 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1050 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1051 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1052 1053 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1054 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1055 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1056 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1057 1058 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1059 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1060 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1061 1062 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1063 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1064 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1065 1066 1067 1068 1069 #if defined(STM32F7) 1070 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1071 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1072 #endif /* STM32F7 */ 1073 1074 #if defined(STM32H7) 1075 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1076 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1077 #endif /* STM32H7 */ 1078 1079 #if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) 1080 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1081 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1082 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1083 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1084 #endif /* STM32F7 || STM32H7 || STM32L0 */ 1085 1086 /** 1087 * @} 1088 */ 1089 1090 1091 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1092 * @{ 1093 */ 1094 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1095 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1096 1097 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1098 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1099 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1100 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1101 1102 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1103 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1104 1105 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1106 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1107 /** 1108 * @} 1109 */ 1110 1111 1112 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1113 * @{ 1114 */ 1115 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1116 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1117 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1118 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1119 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1120 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1121 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1122 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1123 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1124 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1125 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1126 /** 1127 * @} 1128 */ 1129 1130 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1131 * @{ 1132 */ 1133 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1134 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1135 1136 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1137 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1138 1139 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1140 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1141 1142 #if defined(STM32H7) 1143 1144 #define SPI_FLAG_TXE SPI_FLAG_TXP 1145 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1146 1147 #define SPI_IT_TXE SPI_IT_TXP 1148 #define SPI_IT_RXNE SPI_IT_RXP 1149 1150 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1151 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1152 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1153 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1154 1155 #endif /* STM32H7 */ 1156 1157 /** 1158 * @} 1159 */ 1160 1161 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1162 * @{ 1163 */ 1164 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1165 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1166 1167 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1168 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1169 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1170 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1171 #define TIM_DMABase_SR TIM_DMABASE_SR 1172 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1173 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1174 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1175 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1176 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1177 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1178 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1179 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1180 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1181 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1182 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1183 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1184 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1185 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1186 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1187 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1188 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1189 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1190 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1191 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1192 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1193 #define TIM_DMABase_OR TIM_DMABASE_OR 1194 1195 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1196 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1197 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1198 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1199 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1200 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1201 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1202 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1203 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1204 1205 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1206 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1207 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1208 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1209 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1210 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1211 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1212 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1213 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1214 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1215 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1216 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1217 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1218 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1219 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1220 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1221 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1222 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1223 1224 #if defined(STM32L0) 1225 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1226 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1227 #endif 1228 1229 #if defined(STM32F3) 1230 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1231 #endif 1232 1233 #if defined(STM32H7) 1234 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1235 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1236 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1237 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1238 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1239 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1240 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1241 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1242 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1243 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1244 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1245 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1246 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1247 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1248 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1249 #endif 1250 1251 #if defined(STM32U5) || defined(STM32MP2) 1252 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1253 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1254 #endif 1255 /** 1256 * @} 1257 */ 1258 1259 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1260 * @{ 1261 */ 1262 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1263 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1264 /** 1265 * @} 1266 */ 1267 1268 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1269 * @{ 1270 */ 1271 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1272 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1273 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1274 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1275 1276 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1277 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1278 1279 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1280 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1281 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1282 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1283 1284 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1285 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1286 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1287 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1288 1289 #define __DIV_LPUART UART_DIV_LPUART 1290 1291 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1292 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1293 1294 /** 1295 * @} 1296 */ 1297 1298 1299 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1300 * @{ 1301 */ 1302 1303 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1304 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1305 1306 #define USARTNACK_ENABLED USART_NACK_ENABLE 1307 #define USARTNACK_DISABLED USART_NACK_DISABLE 1308 /** 1309 * @} 1310 */ 1311 1312 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1313 * @{ 1314 */ 1315 #define CFR_BASE WWDG_CFR_BASE 1316 1317 /** 1318 * @} 1319 */ 1320 1321 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1322 * @{ 1323 */ 1324 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1325 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1326 #define CAN_IT_RQCP0 CAN_IT_TME 1327 #define CAN_IT_RQCP1 CAN_IT_TME 1328 #define CAN_IT_RQCP2 CAN_IT_TME 1329 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1330 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1331 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1332 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1333 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1334 1335 /** 1336 * @} 1337 */ 1338 1339 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1340 * @{ 1341 */ 1342 1343 #define VLAN_TAG ETH_VLAN_TAG 1344 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1345 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1346 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1347 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1348 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1349 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1350 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1351 1352 #define ETH_MMCCR 0x00000100U 1353 #define ETH_MMCRIR 0x00000104U 1354 #define ETH_MMCTIR 0x00000108U 1355 #define ETH_MMCRIMR 0x0000010CU 1356 #define ETH_MMCTIMR 0x00000110U 1357 #define ETH_MMCTGFSCCR 0x0000014CU 1358 #define ETH_MMCTGFMSCCR 0x00000150U 1359 #define ETH_MMCTGFCR 0x00000168U 1360 #define ETH_MMCRFCECR 0x00000194U 1361 #define ETH_MMCRFAECR 0x00000198U 1362 #define ETH_MMCRGUFCR 0x000001C4U 1363 1364 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1365 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1366 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1367 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1368 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to 1369 the MAC transmitter) */ 1370 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from 1371 MAC transmitter */ 1372 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus 1373 or flushing the TxFIFO */ 1374 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1375 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1376 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status 1377 of previous frame or IFG/backoff period to be over */ 1378 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and 1379 transmitting a Pause control frame (in full duplex mode) */ 1380 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input 1381 frame for transmission */ 1382 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1383 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1384 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control 1385 de-activate threshold */ 1386 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control 1387 activate threshold */ 1388 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1389 #if defined(STM32F1) 1390 #else 1391 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1392 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1393 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status 1394 (or time-stamp) */ 1395 #endif 1396 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and 1397 status */ 1398 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1399 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1400 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1401 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1402 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1403 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1404 1405 #define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ 1406 1407 /** 1408 * @} 1409 */ 1410 1411 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1412 * @{ 1413 */ 1414 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1415 #define DCMI_IT_OVF DCMI_IT_OVR 1416 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1417 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1418 1419 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1420 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1421 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1422 1423 /** 1424 * @} 1425 */ 1426 1427 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1428 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1429 || defined(STM32H7) 1430 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1431 * @{ 1432 */ 1433 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1434 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1435 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1436 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1437 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1438 1439 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1440 #define CM_RGB888 DMA2D_INPUT_RGB888 1441 #define CM_RGB565 DMA2D_INPUT_RGB565 1442 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1443 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1444 #define CM_L8 DMA2D_INPUT_L8 1445 #define CM_AL44 DMA2D_INPUT_AL44 1446 #define CM_AL88 DMA2D_INPUT_AL88 1447 #define CM_L4 DMA2D_INPUT_L4 1448 #define CM_A8 DMA2D_INPUT_A8 1449 #define CM_A4 DMA2D_INPUT_A4 1450 /** 1451 * @} 1452 */ 1453 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1454 1455 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) 1456 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1457 * @{ 1458 */ 1459 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1460 for compatibility with legacy code */ 1461 /** 1462 * @} 1463 */ 1464 1465 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1466 1467 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1468 * @{ 1469 */ 1470 1471 /** 1472 * @} 1473 */ 1474 1475 /* Exported functions --------------------------------------------------------*/ 1476 1477 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1478 * @{ 1479 */ 1480 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1481 /** 1482 * @} 1483 */ 1484 1485 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1486 * @{ 1487 */ 1488 1489 1490 /** 1491 * @} 1492 */ 1493 1494 #if !defined(STM32F2) 1495 /** @defgroup HASH_alias HASH API alias 1496 * @{ 1497 */ 1498 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1499 /** 1500 * 1501 * @} 1502 */ 1503 #endif /* STM32F2 */ 1504 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1505 * @{ 1506 */ 1507 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1508 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1509 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1510 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1511 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1512 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1513 1514 /*HASH Algorithm Selection*/ 1515 1516 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1517 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1518 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1519 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1520 1521 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1522 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1523 1524 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1525 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1526 1527 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1528 1529 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1530 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1531 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1532 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1533 1534 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1535 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1536 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1537 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1538 1539 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1540 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1541 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1542 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1543 1544 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1545 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1546 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1547 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1548 1549 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1550 /** 1551 * @} 1552 */ 1553 1554 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1555 * @{ 1556 */ 1557 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1558 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1559 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1560 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1561 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1562 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1563 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1564 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ 1565 HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1566 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1567 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1568 #if defined(STM32L0) 1569 #else 1570 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1571 #endif 1572 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1573 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1574 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ 1575 HAL_ADCEx_DisableVREFINTTempSensor()) 1576 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ 1577 defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1578 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1579 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1580 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1581 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1582 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1583 1584 /** 1585 * @} 1586 */ 1587 1588 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1589 * @{ 1590 */ 1591 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1592 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1593 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1594 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1595 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1596 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1597 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1598 1599 /** 1600 * @} 1601 */ 1602 1603 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1604 * @{ 1605 */ 1606 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1607 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1608 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1609 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1610 1611 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ 1612 HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ 1613 HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1614 1615 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ 1616 defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ 1617 defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1618 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1619 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1620 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1621 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1622 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || 1623 STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1624 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ 1625 defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1626 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1627 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1628 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1629 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1630 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1631 1632 #if defined(STM32F4) 1633 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1634 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1635 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1636 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1637 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1638 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1639 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1640 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1641 #endif /* STM32F4 */ 1642 /** 1643 * @} 1644 */ 1645 1646 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1647 * @{ 1648 */ 1649 1650 #if defined(STM32G0) 1651 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1652 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1653 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1654 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1655 #endif 1656 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1657 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1658 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1659 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1660 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1661 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1662 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1663 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1664 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1665 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1666 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1667 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1668 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1669 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1670 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1671 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1672 1673 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1674 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1675 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1676 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1677 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1678 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1679 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1680 1681 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1682 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1683 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1684 #define CR_PMODE_BB CR_VOS_BB 1685 1686 #define DBP_BitNumber DBP_BIT_NUMBER 1687 #define PVDE_BitNumber PVDE_BIT_NUMBER 1688 #define PMODE_BitNumber PMODE_BIT_NUMBER 1689 #define EWUP_BitNumber EWUP_BIT_NUMBER 1690 #define FPDS_BitNumber FPDS_BIT_NUMBER 1691 #define ODEN_BitNumber ODEN_BIT_NUMBER 1692 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1693 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1694 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1695 #define BRE_BitNumber BRE_BIT_NUMBER 1696 1697 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1698 1699 1700 /** 1701 * @} 1702 */ 1703 1704 /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose 1705 * @{ 1706 */ 1707 1708 /** 1709 * @} 1710 */ 1711 1712 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1713 * @{ 1714 */ 1715 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1716 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1717 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1718 /** 1719 * @} 1720 */ 1721 1722 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1723 * @{ 1724 */ 1725 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1726 /** 1727 * @} 1728 */ 1729 1730 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1731 * @{ 1732 */ 1733 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1734 #define HAL_TIM_DMAError TIM_DMAError 1735 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1736 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1737 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ 1738 defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1739 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1740 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1741 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1742 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1743 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1744 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1745 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1746 /** 1747 * @} 1748 */ 1749 1750 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1751 * @{ 1752 */ 1753 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1754 /** 1755 * @} 1756 */ 1757 1758 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1759 * @{ 1760 */ 1761 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1762 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1763 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1764 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1765 /** 1766 * @} 1767 */ 1768 1769 1770 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1771 * @{ 1772 */ 1773 1774 /** 1775 * @} 1776 */ 1777 1778 /* Exported macros ------------------------------------------------------------*/ 1779 1780 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1781 * @{ 1782 */ 1783 #define AES_IT_CC CRYP_IT_CC 1784 #define AES_IT_ERR CRYP_IT_ERR 1785 #define AES_FLAG_CCF CRYP_FLAG_CCF 1786 /** 1787 * @} 1788 */ 1789 1790 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1791 * @{ 1792 */ 1793 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1794 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1795 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1796 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1797 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1798 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1799 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1800 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1801 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1802 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1803 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1804 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1805 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1806 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1807 1808 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1809 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1810 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1811 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1812 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1813 1814 /** 1815 * @} 1816 */ 1817 1818 1819 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1820 * @{ 1821 */ 1822 #define __ADC_ENABLE __HAL_ADC_ENABLE 1823 #define __ADC_DISABLE __HAL_ADC_DISABLE 1824 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1825 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1826 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1827 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1828 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1829 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1830 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1831 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1832 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1833 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1834 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1835 1836 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1837 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1838 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1839 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1840 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1841 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1842 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1843 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1844 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1845 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1846 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1847 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1848 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1849 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1850 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1851 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1852 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1853 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1854 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1855 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1856 1857 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1858 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1859 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1860 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1861 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1862 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1863 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1864 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1865 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1866 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1867 1868 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1869 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1870 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1871 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1872 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1873 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1874 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1875 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1876 1877 #define __HAL_ADC_SQR1 ADC_SQR1 1878 #define __HAL_ADC_SMPR1 ADC_SMPR1 1879 #define __HAL_ADC_SMPR2 ADC_SMPR2 1880 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1881 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1882 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1883 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1884 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1885 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1886 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1887 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1888 #define __HAL_ADC_JSQR ADC_JSQR 1889 1890 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1891 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1892 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1893 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1894 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1895 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1896 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1897 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1898 1899 /** 1900 * @} 1901 */ 1902 1903 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1904 * @{ 1905 */ 1906 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1907 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1908 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1909 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1910 1911 /** 1912 * @} 1913 */ 1914 1915 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 1916 * @{ 1917 */ 1918 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 1919 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 1920 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 1921 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 1922 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 1923 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 1924 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 1925 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 1926 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 1927 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 1928 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 1929 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 1930 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 1931 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 1932 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 1933 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 1934 1935 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 1936 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 1937 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 1938 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 1939 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 1940 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 1941 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 1942 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 1943 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 1944 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 1945 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 1946 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 1947 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 1948 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 1949 1950 1951 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 1952 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 1953 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 1954 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 1955 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 1956 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 1957 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 1958 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 1959 #if defined(STM32H7) 1960 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 1961 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 1962 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 1963 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 1964 #else 1965 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 1966 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 1967 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 1968 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 1969 #endif /* STM32H7 */ 1970 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 1971 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 1972 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 1973 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 1974 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 1975 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 1976 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 1977 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 1978 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 1979 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 1980 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 1981 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 1982 1983 /** 1984 * @} 1985 */ 1986 1987 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 1988 * @{ 1989 */ 1990 #if defined(STM32F3) 1991 #define COMP_START __HAL_COMP_ENABLE 1992 #define COMP_STOP __HAL_COMP_DISABLE 1993 #define COMP_LOCK __HAL_COMP_LOCK 1994 1995 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ 1996 defined(STM32F334x8) || defined(STM32F328xx) 1997 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 1998 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 1999 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2000 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2001 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2002 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2003 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2004 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2005 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2006 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2007 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2008 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2009 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2010 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2011 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2012 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2013 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2014 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2015 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2016 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2017 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2018 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2019 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2020 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2021 # endif 2022 # if defined(STM32F302xE) || defined(STM32F302xC) 2023 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2024 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2025 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2026 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2027 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2028 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2029 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2030 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2031 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2032 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2033 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2034 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2035 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2036 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2037 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2038 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2039 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2040 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2041 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2042 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2043 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2044 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2045 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2046 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2047 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2048 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2049 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2050 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2051 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2052 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2053 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2054 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2055 # endif 2056 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2057 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2058 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2059 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2060 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2061 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2062 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2063 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2064 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2065 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2066 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2067 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2068 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2069 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2070 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2071 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2072 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2073 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2074 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2075 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2076 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2077 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2078 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2079 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2080 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2081 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2082 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2083 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2084 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2085 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2086 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2087 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2088 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2089 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2090 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2091 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2092 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2093 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2094 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2095 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2096 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2097 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2098 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2099 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2100 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2101 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2102 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2103 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2104 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2105 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2106 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2107 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2108 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2109 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2110 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2111 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2112 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2113 # endif 2114 # if defined(STM32F373xC) ||defined(STM32F378xx) 2115 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2116 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2117 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2118 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2119 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2120 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2121 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2122 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2123 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2124 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2125 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2126 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2127 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2128 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2129 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2130 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2131 # endif 2132 #else 2133 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2134 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2135 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2136 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2137 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2138 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2139 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2140 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2141 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2142 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2143 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2144 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2145 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2146 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2147 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2148 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2149 #endif 2150 2151 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2152 2153 #if defined(STM32L0) || defined(STM32L4) 2154 /* Note: On these STM32 families, the only argument of this macro */ 2155 /* is COMP_FLAG_LOCK. */ 2156 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2157 /* argument. */ 2158 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2159 #endif 2160 /** 2161 * @} 2162 */ 2163 2164 #if defined(STM32L0) || defined(STM32L4) 2165 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2166 * @{ 2167 */ 2168 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 2169 done into HAL_COMP_Init() */ 2170 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is 2171 done into HAL_COMP_Init() */ 2172 /** 2173 * @} 2174 */ 2175 #endif 2176 2177 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2178 * @{ 2179 */ 2180 2181 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2182 ((WAVE) == DAC_WAVE_NOISE)|| \ 2183 ((WAVE) == DAC_WAVE_TRIANGLE)) 2184 2185 /** 2186 * @} 2187 */ 2188 2189 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2190 * @{ 2191 */ 2192 2193 #define IS_WRPAREA IS_OB_WRPAREA 2194 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2195 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2196 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2197 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2198 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2199 2200 /** 2201 * @} 2202 */ 2203 2204 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2205 * @{ 2206 */ 2207 2208 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2209 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2210 #if defined(STM32F1) 2211 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2212 #else 2213 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2214 #endif /* STM32F1 */ 2215 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2216 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2217 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2218 #define __HAL_I2C_SPEED I2C_SPEED 2219 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2220 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2221 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2222 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2223 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2224 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2225 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2226 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2227 /** 2228 * @} 2229 */ 2230 2231 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2232 * @{ 2233 */ 2234 2235 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2236 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2237 2238 #if defined(STM32H7) 2239 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2240 #endif 2241 2242 /** 2243 * @} 2244 */ 2245 2246 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2247 * @{ 2248 */ 2249 2250 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2251 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2252 2253 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2254 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2255 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2256 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2257 2258 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2259 2260 2261 /** 2262 * @} 2263 */ 2264 2265 2266 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2267 * @{ 2268 */ 2269 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2270 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2271 /** 2272 * @} 2273 */ 2274 2275 2276 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2277 * @{ 2278 */ 2279 2280 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2281 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2282 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2283 2284 /** 2285 * @} 2286 */ 2287 2288 2289 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2290 * @{ 2291 */ 2292 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2293 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2294 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2295 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2296 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2297 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2298 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2299 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2300 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2301 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2302 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2303 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2304 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2305 2306 /** 2307 * @} 2308 */ 2309 2310 2311 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2312 * @{ 2313 */ 2314 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2315 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2316 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2317 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2318 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2319 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2320 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2321 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2322 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2323 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2324 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2325 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2326 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2327 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2328 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2329 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2330 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 2331 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 2332 } while(0) 2333 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2334 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2335 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2336 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2337 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2338 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2339 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2340 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2341 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ 2342 HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ 2343 } while(0) 2344 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ 2345 HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ 2346 } while(0) 2347 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2348 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2349 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2350 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2351 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2352 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2353 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2354 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2355 2356 #if defined (STM32F4) 2357 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2358 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2359 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2360 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2361 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2362 #else 2363 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2364 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2365 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2366 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2367 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2368 #endif /* STM32F4 */ 2369 /** 2370 * @} 2371 */ 2372 2373 2374 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2375 * @{ 2376 */ 2377 2378 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2379 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2380 2381 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2382 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ 2383 HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2384 2385 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2386 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2387 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2388 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2389 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2390 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2391 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2392 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2393 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2394 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2395 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2396 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2397 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2398 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2399 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2400 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2401 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2402 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2403 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2404 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2405 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2406 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2407 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2408 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2409 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2410 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2411 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2412 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2413 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2414 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2415 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2416 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2417 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2418 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2419 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2420 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2421 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2422 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2423 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2424 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2425 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2426 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2427 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2428 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2429 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2430 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2431 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2432 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2433 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2434 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2435 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2436 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2437 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2438 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2439 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2440 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2441 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2442 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2443 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2444 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2445 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2446 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2447 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2448 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2449 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2450 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2451 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2452 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2453 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2454 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2455 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2456 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2457 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2458 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2459 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2460 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2461 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2462 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2463 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2464 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2465 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2466 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2467 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2468 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2469 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2470 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2471 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2472 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2473 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2474 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2475 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2476 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2477 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2478 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2479 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2480 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2481 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2482 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2483 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2484 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2485 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2486 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2487 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2488 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2489 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2490 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2491 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2492 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2493 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2494 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2495 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2496 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2497 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2498 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2499 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2500 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2501 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2502 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2503 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2504 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2505 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2506 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2507 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2508 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2509 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2510 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2511 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2512 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2513 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2514 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2515 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2516 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2517 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2518 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2519 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2520 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2521 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2522 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2523 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2524 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2525 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2526 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2527 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2528 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2529 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2530 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2531 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2532 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2533 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2534 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2535 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2536 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2537 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2538 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2539 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2540 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2541 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2542 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2543 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2544 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2545 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2546 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2547 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2548 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2549 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2550 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2551 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2552 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2553 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2554 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2555 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2556 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2557 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2558 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2559 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2560 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2561 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2562 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2563 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2564 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2565 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2566 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2567 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2568 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2569 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2570 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2571 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2572 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2573 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2574 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2575 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2576 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2577 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2578 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2579 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2580 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2581 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2582 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2583 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2584 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2585 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2586 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2587 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2588 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2589 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2590 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2591 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2592 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2593 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2594 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2595 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2596 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2597 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2598 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2599 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2600 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2601 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2602 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2603 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2604 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2605 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2606 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2607 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2608 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2609 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2610 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2611 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2612 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2613 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2614 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2615 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2616 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2617 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2618 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2619 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2620 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2621 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2622 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2623 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2624 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2625 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2626 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2627 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2628 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2629 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2630 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2631 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2632 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2633 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2634 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2635 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2636 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2637 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2638 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2639 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2640 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2641 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2642 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2643 2644 #if defined(STM32WB) 2645 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2646 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2647 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2648 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2649 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2650 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2651 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2652 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2653 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2654 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2655 #define QSPI_IRQHandler QUADSPI_IRQHandler 2656 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2657 2658 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2659 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2660 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2661 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2662 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2663 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2664 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2665 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2666 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2667 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2668 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2669 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2670 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2671 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2672 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2673 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2674 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2675 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2676 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2677 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2678 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2679 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2680 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2681 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2682 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2683 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2684 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2685 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2686 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2687 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2688 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2689 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2690 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2691 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2692 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2693 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2694 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2695 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2696 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2697 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2698 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2699 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2700 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2701 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2702 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2703 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2704 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2705 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2706 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2707 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2708 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2709 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2710 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2711 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2712 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2713 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2714 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2715 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2716 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2717 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2718 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2719 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2720 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2721 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2722 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2723 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2724 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2725 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2726 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2727 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2728 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2729 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2730 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2731 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2732 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2733 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2734 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2735 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2736 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2737 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2738 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2739 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2740 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2741 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2742 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2743 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2744 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2745 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2746 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2747 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2748 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2749 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2750 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2751 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2752 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2753 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2754 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2755 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2756 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2757 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2758 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2759 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2760 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2761 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2762 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2763 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2764 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2765 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2766 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2767 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2768 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2769 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2770 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2771 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2772 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2773 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2774 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2775 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2776 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2777 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2778 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2779 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2780 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2781 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2782 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2783 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2784 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2785 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2786 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2787 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2788 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2789 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2790 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2791 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2792 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2793 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2794 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2795 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2796 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2797 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2798 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2799 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2800 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2801 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2802 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2803 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2804 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2805 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2806 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2807 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2808 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2809 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2810 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2811 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2812 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2813 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2814 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2815 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2816 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2817 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2818 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2819 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2820 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2821 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2822 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2823 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2824 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2825 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2826 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2827 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2828 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2829 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2830 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2831 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2832 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2833 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2834 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2835 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2836 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2837 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2838 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2839 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2840 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2841 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2842 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2843 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2844 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2845 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2846 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2847 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2848 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2849 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2850 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2851 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2852 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2853 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2854 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2855 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2856 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2857 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2858 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2859 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2860 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2861 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2862 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2863 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2864 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2865 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2866 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2867 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2868 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2869 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2870 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2871 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2872 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2873 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2874 2875 #if defined(STM32H7) 2876 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2877 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2878 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2879 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2880 2881 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2882 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2883 2884 2885 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2886 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2887 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 2888 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 2889 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 2890 #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 2891 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 2892 #endif 2893 2894 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2895 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2896 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2897 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2898 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2899 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2900 2901 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2902 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2903 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2904 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2905 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2906 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2907 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2908 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2909 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2910 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2911 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2912 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2913 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2914 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2915 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2916 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2917 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2918 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2919 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2920 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2921 2922 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2923 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2924 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2925 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2926 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2927 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2928 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2929 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2930 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2931 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2932 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 2933 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 2934 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 2935 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 2936 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 2937 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 2938 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 2939 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 2940 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 2941 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 2942 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 2943 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 2944 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 2945 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 2946 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 2947 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 2948 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 2949 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 2950 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 2951 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 2952 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 2953 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 2954 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 2955 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 2956 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 2957 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 2958 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 2959 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 2960 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 2961 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 2962 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 2963 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 2964 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 2965 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 2966 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 2967 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 2968 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 2969 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 2970 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 2971 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 2972 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 2973 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 2974 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 2975 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 2976 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 2977 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 2978 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 2979 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 2980 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 2981 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 2982 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 2983 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 2984 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 2985 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 2986 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 2987 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 2988 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 2989 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 2990 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 2991 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 2992 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 2993 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 2994 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 2995 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 2996 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 2997 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 2998 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 2999 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3000 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3001 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3002 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3003 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3004 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3005 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3006 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3007 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3008 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3009 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3010 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3011 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3012 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3013 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3014 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3015 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3016 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3017 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3018 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3019 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3020 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3021 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3022 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3023 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3024 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3025 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3026 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3027 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3028 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3029 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3030 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3031 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3032 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3033 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3034 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3035 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3036 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3037 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3038 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3039 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3040 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3041 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3042 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3043 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3044 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3045 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3046 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3047 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3048 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3049 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3050 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3051 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3052 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3053 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3054 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3055 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3056 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3057 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3058 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3059 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3060 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3061 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3062 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3063 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3064 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3065 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3066 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3067 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3068 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3069 3070 /* alias define maintained for legacy */ 3071 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3072 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3073 3074 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3075 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3076 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3077 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3078 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3079 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3080 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3081 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3082 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3083 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3084 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3085 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3086 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3087 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3088 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3089 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3090 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3091 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3092 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3093 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3094 3095 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3096 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3097 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3098 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3099 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3100 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3101 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3102 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3103 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3104 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3105 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3106 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3107 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3108 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3109 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3110 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3111 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3112 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3113 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3114 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3115 3116 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3117 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3118 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3119 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3120 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3121 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3122 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3123 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3124 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3125 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3126 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3127 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3128 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3129 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3130 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3131 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3132 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3133 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3134 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3135 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3136 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3137 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3138 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3139 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3140 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3141 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3142 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3143 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3144 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3145 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3146 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3147 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3148 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3149 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3150 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3151 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3152 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3153 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3154 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3155 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3156 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3157 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3158 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3159 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3160 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3161 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3162 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3163 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3164 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3165 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3166 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3167 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3168 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3169 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3170 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3171 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3172 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3173 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3174 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3175 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3176 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3177 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3178 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3179 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3180 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3181 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3182 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3183 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3184 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3185 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3186 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3187 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3188 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3189 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3190 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3191 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3192 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3193 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3194 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3195 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3196 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3197 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3198 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3199 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3200 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3201 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3202 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3203 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3204 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3205 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3206 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3207 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3208 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3209 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3210 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3211 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3212 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3213 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3214 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3215 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3216 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3217 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3218 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3219 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3220 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3221 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3222 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3223 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3224 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3225 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3226 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3227 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3228 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3229 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3230 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3231 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3232 3233 #if defined(STM32L1) 3234 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3235 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3236 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3237 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3238 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3239 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3240 #endif /* STM32L1 */ 3241 3242 #if defined(STM32F4) 3243 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3244 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3245 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3246 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3247 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3248 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3249 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3250 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3251 #define Sdmmc1ClockSelection SdioClockSelection 3252 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3253 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3254 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3255 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3256 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3257 #endif 3258 3259 #if defined(STM32F7) || defined(STM32L4) 3260 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3261 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3262 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3263 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3264 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3265 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3266 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3267 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3268 #define SdioClockSelection Sdmmc1ClockSelection 3269 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3270 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3271 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3272 #endif 3273 3274 #if defined(STM32F7) 3275 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3276 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3277 #endif 3278 3279 #if defined(STM32H7) 3280 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3281 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3282 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3283 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3284 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3285 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3286 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3287 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3288 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3289 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3290 3291 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3292 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3293 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3294 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3295 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3296 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3297 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3298 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3299 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3300 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3301 #endif 3302 3303 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3304 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3305 3306 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3307 3308 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3309 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3310 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3311 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3312 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3313 3314 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3315 3316 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3317 #define RCC_IT_CSSHSE RCC_IT_CSS 3318 3319 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3320 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3321 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3322 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3323 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3324 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3325 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3326 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3327 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3328 3329 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3330 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3331 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3332 3333 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3334 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3335 #define RCC_MCO_NODIV RCC_MCODIV_1 3336 #define RCC_MCO_DIV1 RCC_MCODIV_1 3337 #define RCC_MCO_DIV2 RCC_MCODIV_2 3338 #define RCC_MCO_DIV4 RCC_MCODIV_4 3339 #define RCC_MCO_DIV8 RCC_MCODIV_8 3340 #define RCC_MCO_DIV16 RCC_MCODIV_16 3341 #define RCC_MCO_DIV32 RCC_MCODIV_32 3342 #define RCC_MCO_DIV64 RCC_MCODIV_64 3343 #define RCC_MCO_DIV128 RCC_MCODIV_128 3344 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3345 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3346 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3347 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3348 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3349 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3350 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3351 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3352 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3353 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3354 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3355 3356 3357 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) 3358 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3359 #else 3360 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3361 #endif 3362 3363 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3364 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3365 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3366 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3367 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3368 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3369 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3370 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3371 3372 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3373 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3374 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3375 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3376 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3377 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3378 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3379 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3380 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3381 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3382 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3383 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3384 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3385 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3386 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3387 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3388 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3389 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3390 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3391 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3392 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3393 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3394 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3395 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3396 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3397 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3398 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3399 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3400 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3401 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3402 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3403 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3404 3405 #define CR_HSION_BB RCC_CR_HSION_BB 3406 #define CR_CSSON_BB RCC_CR_CSSON_BB 3407 #define CR_PLLON_BB RCC_CR_PLLON_BB 3408 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3409 #define CR_MSION_BB RCC_CR_MSION_BB 3410 #define CSR_LSION_BB RCC_CSR_LSION_BB 3411 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3412 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3413 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3414 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3415 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3416 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3417 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3418 #define CR_HSEON_BB RCC_CR_HSEON_BB 3419 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3420 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3421 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3422 3423 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3424 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3425 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3426 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3427 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3428 3429 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3430 3431 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3432 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3433 3434 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3435 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3436 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3437 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3438 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3439 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3440 3441 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3442 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3443 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3444 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3445 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3446 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3447 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3448 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3449 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3450 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3451 #define DfsdmClockSelection Dfsdm1ClockSelection 3452 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3453 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3454 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3455 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3456 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3457 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3458 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3459 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3460 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3461 3462 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3463 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3464 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3465 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3466 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3467 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3468 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3469 3470 3471 /** 3472 * @} 3473 */ 3474 3475 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3476 * @{ 3477 */ 3478 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3479 3480 /** 3481 * @} 3482 */ 3483 3484 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3485 * @{ 3486 */ 3487 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) 3488 #else 3489 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3490 #endif 3491 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3492 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3493 3494 #if defined (STM32F1) 3495 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3496 3497 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3498 3499 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3500 3501 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3502 3503 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3504 #else 3505 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3506 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3507 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3508 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3509 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3510 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3511 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3512 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3513 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3514 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3515 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3516 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3517 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3518 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3519 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3520 #endif /* STM32F1 */ 3521 3522 #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ 3523 defined (STM32H7) || \ 3524 defined (STM32L0) || defined (STM32L1) || \ 3525 defined (STM32WB) 3526 #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG 3527 #endif 3528 3529 #define IS_ALARM IS_RTC_ALARM 3530 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3531 #define IS_TAMPER IS_RTC_TAMPER 3532 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3533 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3534 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3535 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3536 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3537 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3538 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3539 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3540 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3541 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3542 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3543 3544 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3545 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3546 3547 3548 /** 3549 * @} 3550 */ 3551 3552 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3553 * @{ 3554 */ 3555 3556 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3557 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3558 3559 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3560 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3561 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3562 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3563 3564 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3565 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3566 #endif 3567 3568 #if defined(STM32F4) || defined(STM32F2) 3569 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3570 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3571 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3572 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3573 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3574 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3575 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3576 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3577 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3578 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3579 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3580 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3581 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3582 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3583 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3584 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3585 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3586 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3587 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3588 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3589 /* alias CMSIS */ 3590 #define SDMMC1_IRQn SDIO_IRQn 3591 #define SDMMC1_IRQHandler SDIO_IRQHandler 3592 #endif 3593 3594 #if defined(STM32F7) || defined(STM32L4) 3595 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3596 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3597 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3598 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3599 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3600 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3601 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3602 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3603 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3604 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3605 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3606 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3607 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3608 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3609 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3610 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3611 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3612 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3613 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3614 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3615 /* alias CMSIS for compatibilities */ 3616 #define SDIO_IRQn SDMMC1_IRQn 3617 #define SDIO_IRQHandler SDMMC1_IRQHandler 3618 #endif 3619 3620 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3621 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3622 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3623 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3624 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3625 #endif 3626 3627 #if defined(STM32H7) || defined(STM32L5) 3628 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3629 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3630 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3631 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3632 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3633 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3634 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3635 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3636 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3637 #endif 3638 /** 3639 * @} 3640 */ 3641 3642 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3643 * @{ 3644 */ 3645 3646 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3647 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3648 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3649 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3650 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3651 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3652 3653 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3654 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3655 3656 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3657 3658 /** 3659 * @} 3660 */ 3661 3662 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3663 * @{ 3664 */ 3665 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3666 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3667 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3668 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3669 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3670 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3671 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3672 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3673 /** 3674 * @} 3675 */ 3676 3677 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3678 * @{ 3679 */ 3680 3681 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3682 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3683 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3684 3685 /** 3686 * @} 3687 */ 3688 3689 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3690 * @{ 3691 */ 3692 3693 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3694 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3695 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3696 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3697 3698 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3699 3700 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3701 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3702 3703 /** 3704 * @} 3705 */ 3706 3707 3708 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3709 * @{ 3710 */ 3711 3712 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3713 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3714 #define __USART_ENABLE __HAL_USART_ENABLE 3715 #define __USART_DISABLE __HAL_USART_DISABLE 3716 3717 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3718 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3719 3720 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 3721 #define USART_OVERSAMPLING_16 0x00000000U 3722 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 3723 3724 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 3725 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 3726 #endif /* STM32F0 || STM32F3 || STM32F7 */ 3727 /** 3728 * @} 3729 */ 3730 3731 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3732 * @{ 3733 */ 3734 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3735 3736 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3737 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3738 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3739 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3740 3741 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3742 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3743 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3744 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3745 3746 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3747 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3748 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3749 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3750 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3751 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3752 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3753 3754 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3755 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3756 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3757 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3758 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3759 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3760 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3761 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3762 3763 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3764 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3765 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3766 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3767 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3768 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3769 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3770 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3771 3772 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3773 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3774 3775 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3776 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3777 /** 3778 * @} 3779 */ 3780 3781 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3782 * @{ 3783 */ 3784 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3785 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3786 3787 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3788 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3789 3790 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3791 3792 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3793 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3794 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3795 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3796 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3797 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3798 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3799 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3800 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3801 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3802 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3803 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3804 3805 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3806 3807 #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 3808 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 3809 /** 3810 * @} 3811 */ 3812 3813 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3814 * @{ 3815 */ 3816 3817 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3818 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3819 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3820 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3821 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3822 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3823 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3824 3825 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3826 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3827 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3828 /** 3829 * @} 3830 */ 3831 3832 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3833 * @{ 3834 */ 3835 #define __HAL_LTDC_LAYER LTDC_LAYER 3836 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3837 /** 3838 * @} 3839 */ 3840 3841 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3842 * @{ 3843 */ 3844 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3845 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3846 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3847 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3848 #define SAI_STREOMODE SAI_STEREOMODE 3849 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3850 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3851 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3852 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3853 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3854 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3855 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3856 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3857 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3858 /** 3859 * @} 3860 */ 3861 3862 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3863 * @{ 3864 */ 3865 #if defined(STM32H7) 3866 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3867 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3868 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3869 #endif 3870 /** 3871 * @} 3872 */ 3873 3874 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3875 * @{ 3876 */ 3877 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3878 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3879 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3880 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3881 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3882 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3883 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3884 #endif 3885 /** 3886 * @} 3887 */ 3888 3889 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3890 * @{ 3891 */ 3892 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3893 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3894 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3895 /** 3896 * @} 3897 */ 3898 3899 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 3900 * @{ 3901 */ 3902 #if defined (STM32F7) 3903 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 3904 #endif /* STM32F7 */ 3905 /** 3906 * @} 3907 */ 3908 3909 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 3910 * @{ 3911 */ 3912 3913 /** 3914 * @} 3915 */ 3916 3917 #ifdef __cplusplus 3918 } 3919 #endif 3920 3921 #endif /* STM32_HAL_LEGACY */ 3922 3923
