1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F4xx_LL_DAC_H
21 #define STM32F4xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
55 CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #if defined(DAC_CHANNEL2_SUPPORT)
57 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60 #else
61 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
62 #endif /* DAC_CHANNEL2_SUPPORT */
63
64 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
65 #if defined(DAC_CHANNEL2_SUPPORT)
66 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
67 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
68 #else
69 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
70 #endif /* DAC_CHANNEL2_SUPPORT */
71
72 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
73 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77 #if defined(DAC_CHANNEL2_SUPPORT)
78 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
79 DHR12Rx channel 1 (shifted left of 16 bits) */
80 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
81 DHR12Rx channel 1 (shifted left of 20 bits) */
82 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
83 DHR12Rx channel 1 (shifted left of 24 bits) */
84 #endif /* DAC_CHANNEL2_SUPPORT */
85 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
86 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
87 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
88 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
89 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
90
91 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
92 #if defined(DAC_CHANNEL2_SUPPORT)
93 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
94 DORx channel 2 (shifted left of 28 bits) */
95 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
96 #endif /* DAC_CHANNEL2_SUPPORT */
97
98
99 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
100 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
101 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
102 to position 0 */
103 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
104 to position 0 */
105
106 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 16 bits) */
109 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 20 bits) */
112 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
113 channel 1 or 2 versus DHR12Rx channel 1
114 (shifted left of 24 bits) */
115 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
116 channel 1 or 2 versus DORx channel 1
117 (shifted left of 28 bits) */
118
119 /* DAC registers bits positions */
120 #if defined(DAC_CHANNEL2_SUPPORT)
121 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
122 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
123 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
124 #endif /* DAC_CHANNEL2_SUPPORT */
125
126 /* Miscellaneous data */
127 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
128 bits (voltage range determined by analog voltage
129 references Vref+ and Vref-, refer to reference manual) */
130
131 /**
132 * @}
133 */
134
135
136 /* Private macros ------------------------------------------------------------*/
137 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
138 * @{
139 */
140
141 /**
142 * @brief Driver macro reserved for internal use: set a pointer to
143 * a register from a register basis from which an offset
144 * is applied.
145 * @param __REG__ Register basis from which the offset is applied.
146 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
147 * @retval Pointer to register address
148 */
149 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
150 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
151
152 /**
153 * @}
154 */
155
156
157 /* Exported types ------------------------------------------------------------*/
158 #if defined(USE_FULL_LL_DRIVER)
159 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
160 * @{
161 */
162
163 /**
164 * @brief Structure definition of some features of DAC instance.
165 */
166 typedef struct
167 {
168 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
169 internal (SW start) or from external peripheral
170 (timer event, external interrupt line).
171 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
172
173 This feature can be modified afterwards using unitary
174 function @ref LL_DAC_SetTriggerSource(). */
175
176 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
177 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
178
179 This feature can be modified afterwards using unitary
180 function @ref LL_DAC_SetWaveAutoGeneration(). */
181
182 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
183 If waveform automatic generation mode is set to noise, this parameter
184 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
185 If waveform automatic generation mode is set to triangle,
186 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
187 @note If waveform automatic generation mode is disabled,
188 this parameter is discarded.
189
190 This feature can be modified afterwards using unitary
191 function @ref LL_DAC_SetWaveNoiseLFSR(),
192 @ref LL_DAC_SetWaveTriangleAmplitude()
193 depending on the wave automatic generation selected. */
194
195 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
196 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
197
198 This feature can be modified afterwards using unitary
199 function @ref LL_DAC_SetOutputBuffer(). */
200 } LL_DAC_InitTypeDef;
201
202 /**
203 * @}
204 */
205 #endif /* USE_FULL_LL_DRIVER */
206
207 /* Exported constants --------------------------------------------------------*/
208 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
209 * @{
210 */
211
212 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
213 * @brief Flags defines which can be used with LL_DAC_ReadReg function
214 * @{
215 */
216 /* DAC channel 1 flags */
217 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
218 #if defined(DAC_CHANNEL2_SUPPORT)
219 /* DAC channel 2 flags */
220 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
221 #endif /* DAC_CHANNEL2_SUPPORT */
222 /**
223 * @}
224 */
225
226 /** @defgroup DAC_LL_EC_IT DAC interruptions
227 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
228 * @{
229 */
230 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
231 #if defined(DAC_CHANNEL2_SUPPORT)
232 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
233 #endif /* DAC_CHANNEL2_SUPPORT */
234 /**
235 * @}
236 */
237
238 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
239 * @{
240 */
241 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
242 #if defined(DAC_CHANNEL2_SUPPORT)
243 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
244 #endif /* DAC_CHANNEL2_SUPPORT */
245 /**
246 * @}
247 */
248
249 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
250 * @{
251 */
252 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
253 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
254 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
255 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
256 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
257 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
258 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
259 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
260 /**
261 * @}
262 */
263
264 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
265 * @{
266 */
267 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
268 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
269 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
270 /**
271 * @}
272 */
273
274 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
275 * @{
276 */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
282 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
283 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
284 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
285 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
286 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
287 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
288 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
289 /**
290 * @}
291 */
292
293 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
294 * @{
295 */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
298 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
299 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
300 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
301 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
302 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
303 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
304 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
305 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
306 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
307 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
308 /**
309 * @}
310 */
311
312 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
313 * @{
314 */
315 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
316 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
317 /**
318 * @}
319 */
320
321 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
322 * @{
323 */
324 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
325 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
326 /**
327 * @}
328 */
329
330 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
331 * @{
332 */
333 /* List of DAC registers intended to be used (most commonly) with */
334 /* DMA transfer. */
335 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
336 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
337 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
338 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
339 /**
340 * @}
341 */
342
343 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
344 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
345 * not timeout values.
346 * For details on delays values, refer to descriptions in source code
347 * above each literal definition.
348 * @{
349 */
350
351 /* Delay for DAC channel voltage settling time from DAC channel startup */
352 /* (transition from disable to enable). */
353 /* Note: DAC channel startup time depends on board application environment: */
354 /* impedance connected to DAC channel output. */
355 /* The delay below is specified under conditions: */
356 /* - voltage maximum transition (lowest to highest value) */
357 /* - until voltage reaches final value +-1LSB */
358 /* - DAC channel output buffer enabled */
359 /* - load impedance of 5kOhm (min), 50pF (max) */
360 /* Literal set to maximum value (refer to device datasheet, */
361 /* parameter "tWAKEUP"). */
362 /* Unit: us */
363 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
364
365 /* Delay for DAC channel voltage settling time. */
366 /* Note: DAC channel startup time depends on board application environment: */
367 /* impedance connected to DAC channel output. */
368 /* The delay below is specified under conditions: */
369 /* - voltage maximum transition (lowest to highest value) */
370 /* - until voltage reaches final value +-1LSB */
371 /* - DAC channel output buffer enabled */
372 /* - load impedance of 5kOhm min, 50pF max */
373 /* Literal set to maximum value (refer to device datasheet, */
374 /* parameter "tSETTLING"). */
375 /* Unit: us */
376 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
377
378 /**
379 * @}
380 */
381
382 /**
383 * @}
384 */
385
386 /* Exported macro ------------------------------------------------------------*/
387 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
388 * @{
389 */
390
391 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
392 * @{
393 */
394
395 /**
396 * @brief Write a value in DAC register
397 * @param __INSTANCE__ DAC Instance
398 * @param __REG__ Register to be written
399 * @param __VALUE__ Value to be written in the register
400 * @retval None
401 */
402 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
403
404 /**
405 * @brief Read a value in DAC register
406 * @param __INSTANCE__ DAC Instance
407 * @param __REG__ Register to be read
408 * @retval Register value
409 */
410 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
411
412 /**
413 * @}
414 */
415
416 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
417 * @{
418 */
419
420 /**
421 * @brief Helper macro to get DAC channel number in decimal format
422 * from literals LL_DAC_CHANNEL_x.
423 * Example:
424 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
425 * will return decimal number "1".
426 * @note The input can be a value from functions where a channel
427 * number is returned.
428 * @param __CHANNEL__ This parameter can be one of the following values:
429 * @arg @ref LL_DAC_CHANNEL_1
430 * @arg @ref LL_DAC_CHANNEL_2 (1)
431 *
432 * (1) On this STM32 series, parameter not available on all devices.
433 * Refer to device datasheet for channels availability.
434 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
435 */
436 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
437 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
438
439 /**
440 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
441 * from number in decimal format.
442 * Example:
443 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
444 * will return a data equivalent to "LL_DAC_CHANNEL_1".
445 * @note If the input parameter does not correspond to a DAC channel,
446 * this macro returns value '0'.
447 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
448 * @retval Returned value can be one of the following values:
449 * @arg @ref LL_DAC_CHANNEL_1
450 * @arg @ref LL_DAC_CHANNEL_2 (1)
451 *
452 * (1) On this STM32 series, parameter not available on all devices.
453 * Refer to device datasheet for channels availability.
454 */
455 #if defined(DAC_CHANNEL2_SUPPORT)
456 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
457 (((__DECIMAL_NB__) == 1UL) \
458 ? (LL_DAC_CHANNEL_1) \
459 : \
460 (((__DECIMAL_NB__) == 2UL) \
461 ? (LL_DAC_CHANNEL_2) \
462 : \
463 (0UL) \
464 ) \
465 )
466 #else
467 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
468 (((__DECIMAL_NB__) == 1UL) \
469 ? (LL_DAC_CHANNEL_1) \
470 : \
471 (0UL) \
472 )
473 #endif /* DAC_CHANNEL2_SUPPORT */
474
475 /**
476 * @brief Helper macro to define the DAC conversion data full-scale digital
477 * value corresponding to the selected DAC resolution.
478 * @note DAC conversion data full-scale corresponds to voltage range
479 * determined by analog voltage references Vref+ and Vref-
480 * (refer to reference manual).
481 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
482 * @arg @ref LL_DAC_RESOLUTION_12B
483 * @arg @ref LL_DAC_RESOLUTION_8B
484 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
485 */
486 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
487 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
488
489 /**
490 * @brief Helper macro to calculate the DAC conversion data (unit: digital
491 * value) corresponding to a voltage (unit: mVolt).
492 * @note This helper macro is intended to provide input data in voltage
493 * rather than digital value,
494 * to be used with LL DAC functions such as
495 * @ref LL_DAC_ConvertData12RightAligned().
496 * @note Analog reference voltage (Vref+) must be either known from
497 * user board environment or can be calculated using ADC measurement
498 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
499 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
500 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
501 * (unit: mVolt).
502 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
503 * @arg @ref LL_DAC_RESOLUTION_12B
504 * @arg @ref LL_DAC_RESOLUTION_8B
505 * @retval DAC conversion data (unit: digital value)
506 */
507 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
508 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
509 / (__VREFANALOG_VOLTAGE__) \
510 )
511
512 /**
513 * @}
514 */
515
516 /**
517 * @}
518 */
519
520
521 /* Exported functions --------------------------------------------------------*/
522 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
523 * @{
524 */
525
526 /**
527 * @brief Set the conversion trigger source for the selected DAC channel.
528 * @note For conversion trigger source to be effective, DAC trigger
529 * must be enabled using function @ref LL_DAC_EnableTrigger().
530 * @note To set conversion trigger source, DAC channel must be disabled.
531 * Otherwise, the setting is discarded.
532 * @note Availability of parameters of trigger sources from timer
533 * depends on timers availability on the selected device.
534 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
535 * CR TSEL2 LL_DAC_SetTriggerSource
536 * @param DACx DAC instance
537 * @param DAC_Channel This parameter can be one of the following values:
538 * @arg @ref LL_DAC_CHANNEL_1
539 * @arg @ref LL_DAC_CHANNEL_2 (1)
540 *
541 * (1) On this STM32 series, parameter not available on all devices.
542 * Refer to device datasheet for channels availability.
543 * @param TriggerSource This parameter can be one of the following values:
544 * @arg @ref LL_DAC_TRIG_SOFTWARE
545 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
546 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
547 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
548 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
549 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
550 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
551 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
552 * @retval None
553 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)554 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
555 {
556 MODIFY_REG(DACx->CR,
557 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
558 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
559 }
560
561 /**
562 * @brief Get the conversion trigger source for the selected DAC channel.
563 * @note For conversion trigger source to be effective, DAC trigger
564 * must be enabled using function @ref LL_DAC_EnableTrigger().
565 * @note Availability of parameters of trigger sources from timer
566 * depends on timers availability on the selected device.
567 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
568 * CR TSEL2 LL_DAC_GetTriggerSource
569 * @param DACx DAC instance
570 * @param DAC_Channel This parameter can be one of the following values:
571 * @arg @ref LL_DAC_CHANNEL_1
572 * @arg @ref LL_DAC_CHANNEL_2 (1)
573 *
574 * (1) On this STM32 series, parameter not available on all devices.
575 * Refer to device datasheet for channels availability.
576 * @retval Returned value can be one of the following values:
577 * @arg @ref LL_DAC_TRIG_SOFTWARE
578 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
579 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
580 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
581 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
582 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
583 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
584 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
585 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)586 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
587 {
588 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
589 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
590 );
591 }
592
593 /**
594 * @brief Set the waveform automatic generation mode
595 * for the selected DAC channel.
596 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
597 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
598 * @param DACx DAC instance
599 * @param DAC_Channel This parameter can be one of the following values:
600 * @arg @ref LL_DAC_CHANNEL_1
601 * @arg @ref LL_DAC_CHANNEL_2 (1)
602 *
603 * (1) On this STM32 series, parameter not available on all devices.
604 * Refer to device datasheet for channels availability.
605 * @param WaveAutoGeneration This parameter can be one of the following values:
606 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
607 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
608 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
609 * @retval None
610 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)611 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
612 {
613 MODIFY_REG(DACx->CR,
614 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
615 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
616 }
617
618 /**
619 * @brief Get the waveform automatic generation mode
620 * for the selected DAC channel.
621 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
622 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
623 * @param DACx DAC instance
624 * @param DAC_Channel This parameter can be one of the following values:
625 * @arg @ref LL_DAC_CHANNEL_1
626 * @arg @ref LL_DAC_CHANNEL_2 (1)
627 *
628 * (1) On this STM32 series, parameter not available on all devices.
629 * Refer to device datasheet for channels availability.
630 * @retval Returned value can be one of the following values:
631 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
632 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
633 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
634 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)635 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
636 {
637 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
638 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
639 );
640 }
641
642 /**
643 * @brief Set the noise waveform generation for the selected DAC channel:
644 * Noise mode and parameters LFSR (linear feedback shift register).
645 * @note For wave generation to be effective, DAC channel
646 * wave generation mode must be enabled using
647 * function @ref LL_DAC_SetWaveAutoGeneration().
648 * @note This setting can be set when the selected DAC channel is disabled
649 * (otherwise, the setting operation is ignored).
650 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
651 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
652 * @param DACx DAC instance
653 * @param DAC_Channel This parameter can be one of the following values:
654 * @arg @ref LL_DAC_CHANNEL_1
655 * @arg @ref LL_DAC_CHANNEL_2 (1)
656 *
657 * (1) On this STM32 series, parameter not available on all devices.
658 * Refer to device datasheet for channels availability.
659 * @param NoiseLFSRMask This parameter can be one of the following values:
660 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
661 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
662 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
663 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
664 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
665 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
666 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
667 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
668 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
669 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
670 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
671 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
672 * @retval None
673 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)674 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
675 {
676 MODIFY_REG(DACx->CR,
677 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
678 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
679 }
680
681 /**
682 * @brief Get the noise waveform generation for the selected DAC channel:
683 * Noise mode and parameters LFSR (linear feedback shift register).
684 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
685 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
686 * @param DACx DAC instance
687 * @param DAC_Channel This parameter can be one of the following values:
688 * @arg @ref LL_DAC_CHANNEL_1
689 * @arg @ref LL_DAC_CHANNEL_2 (1)
690 *
691 * (1) On this STM32 series, parameter not available on all devices.
692 * Refer to device datasheet for channels availability.
693 * @retval Returned value can be one of the following values:
694 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
695 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
696 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
697 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
698 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
699 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
700 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
701 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
702 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
703 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
704 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
706 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)707 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
708 {
709 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
710 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
711 );
712 }
713
714 /**
715 * @brief Set the triangle waveform generation for the selected DAC channel:
716 * triangle mode and amplitude.
717 * @note For wave generation to be effective, DAC channel
718 * wave generation mode must be enabled using
719 * function @ref LL_DAC_SetWaveAutoGeneration().
720 * @note This setting can be set when the selected DAC channel is disabled
721 * (otherwise, the setting operation is ignored).
722 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
723 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
724 * @param DACx DAC instance
725 * @param DAC_Channel This parameter can be one of the following values:
726 * @arg @ref LL_DAC_CHANNEL_1
727 * @arg @ref LL_DAC_CHANNEL_2 (1)
728 *
729 * (1) On this STM32 series, parameter not available on all devices.
730 * Refer to device datasheet for channels availability.
731 * @param TriangleAmplitude This parameter can be one of the following values:
732 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
733 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
734 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
735 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
736 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
737 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
738 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
739 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
740 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
741 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
742 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
743 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
744 * @retval None
745 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)746 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
747 uint32_t TriangleAmplitude)
748 {
749 MODIFY_REG(DACx->CR,
750 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
751 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
752 }
753
754 /**
755 * @brief Get the triangle waveform generation for the selected DAC channel:
756 * triangle mode and amplitude.
757 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
758 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
759 * @param DACx DAC instance
760 * @param DAC_Channel This parameter can be one of the following values:
761 * @arg @ref LL_DAC_CHANNEL_1
762 * @arg @ref LL_DAC_CHANNEL_2 (1)
763 *
764 * (1) On this STM32 series, parameter not available on all devices.
765 * Refer to device datasheet for channels availability.
766 * @retval Returned value can be one of the following values:
767 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
768 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
769 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
770 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
771 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
772 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
773 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
774 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
775 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
776 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
777 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
778 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
779 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)780 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
781 {
782 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
783 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
784 );
785 }
786
787 /**
788 * @brief Set the output buffer for the selected DAC channel.
789 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
790 * CR BOFF2 LL_DAC_SetOutputBuffer
791 * @param DACx DAC instance
792 * @param DAC_Channel This parameter can be one of the following values:
793 * @arg @ref LL_DAC_CHANNEL_1
794 * @arg @ref LL_DAC_CHANNEL_2 (1)
795 *
796 * (1) On this STM32 series, parameter not available on all devices.
797 * Refer to device datasheet for channels availability.
798 * @param OutputBuffer This parameter can be one of the following values:
799 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
800 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
801 * @retval None
802 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)803 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
804 {
805 MODIFY_REG(DACx->CR,
806 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
807 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
808 }
809
810 /**
811 * @brief Get the output buffer state for the selected DAC channel.
812 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
813 * CR BOFF2 LL_DAC_GetOutputBuffer
814 * @param DACx DAC instance
815 * @param DAC_Channel This parameter can be one of the following values:
816 * @arg @ref LL_DAC_CHANNEL_1
817 * @arg @ref LL_DAC_CHANNEL_2 (1)
818 *
819 * (1) On this STM32 series, parameter not available on all devices.
820 * Refer to device datasheet for channels availability.
821 * @retval Returned value can be one of the following values:
822 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
823 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
824 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)825 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
826 {
827 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
828 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
829 );
830 }
831
832 /**
833 * @}
834 */
835
836 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
837 * @{
838 */
839
840 /**
841 * @brief Enable DAC DMA transfer request of the selected channel.
842 * @note To configure DMA source address (peripheral address),
843 * use function @ref LL_DAC_DMA_GetRegAddr().
844 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
845 * CR DMAEN2 LL_DAC_EnableDMAReq
846 * @param DACx DAC instance
847 * @param DAC_Channel This parameter can be one of the following values:
848 * @arg @ref LL_DAC_CHANNEL_1
849 * @arg @ref LL_DAC_CHANNEL_2 (1)
850 *
851 * (1) On this STM32 series, parameter not available on all devices.
852 * Refer to device datasheet for channels availability.
853 * @retval None
854 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)855 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
856 {
857 SET_BIT(DACx->CR,
858 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
859 }
860
861 /**
862 * @brief Disable DAC DMA transfer request of the selected channel.
863 * @note To configure DMA source address (peripheral address),
864 * use function @ref LL_DAC_DMA_GetRegAddr().
865 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
866 * CR DMAEN2 LL_DAC_DisableDMAReq
867 * @param DACx DAC instance
868 * @param DAC_Channel This parameter can be one of the following values:
869 * @arg @ref LL_DAC_CHANNEL_1
870 * @arg @ref LL_DAC_CHANNEL_2 (1)
871 *
872 * (1) On this STM32 series, parameter not available on all devices.
873 * Refer to device datasheet for channels availability.
874 * @retval None
875 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)876 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
877 {
878 CLEAR_BIT(DACx->CR,
879 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
880 }
881
882 /**
883 * @brief Get DAC DMA transfer request state of the selected channel.
884 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
885 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
886 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
887 * @param DACx DAC instance
888 * @param DAC_Channel This parameter can be one of the following values:
889 * @arg @ref LL_DAC_CHANNEL_1
890 * @arg @ref LL_DAC_CHANNEL_2 (1)
891 *
892 * (1) On this STM32 series, parameter not available on all devices.
893 * Refer to device datasheet for channels availability.
894 * @retval State of bit (1 or 0).
895 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)896 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
897 {
898 return ((READ_BIT(DACx->CR,
899 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
900 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
901 }
902
903 /**
904 * @brief Function to help to configure DMA transfer to DAC: retrieve the
905 * DAC register address from DAC instance and a list of DAC registers
906 * intended to be used (most commonly) with DMA transfer.
907 * @note These DAC registers are data holding registers:
908 * when DAC conversion is requested, DAC generates a DMA transfer
909 * request to have data available in DAC data holding registers.
910 * @note This macro is intended to be used with LL DMA driver, refer to
911 * function "LL_DMA_ConfigAddresses()".
912 * Example:
913 * LL_DMA_ConfigAddresses(DMA1,
914 * LL_DMA_CHANNEL_1,
915 * (uint32_t)&< array or variable >,
916 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
917 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
918 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
919 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
920 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
921 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
922 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
923 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
924 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
925 * @param DACx DAC instance
926 * @param DAC_Channel This parameter can be one of the following values:
927 * @arg @ref LL_DAC_CHANNEL_1
928 * @arg @ref LL_DAC_CHANNEL_2 (1)
929 *
930 * (1) On this STM32 series, parameter not available on all devices.
931 * Refer to device datasheet for channels availability.
932 * @param Register This parameter can be one of the following values:
933 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
934 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
935 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
936 * @retval DAC register address
937 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)938 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
939 {
940 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
941 /* DAC channel selected. */
942 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
943 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
944 }
945 /**
946 * @}
947 */
948
949 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
950 * @{
951 */
952
953 /**
954 * @brief Enable DAC selected channel.
955 * @rmtoll CR EN1 LL_DAC_Enable\n
956 * CR EN2 LL_DAC_Enable
957 * @note After enable from off state, DAC channel requires a delay
958 * for output voltage to reach accuracy +/- 1 LSB.
959 * Refer to device datasheet, parameter "tWAKEUP".
960 * @param DACx DAC instance
961 * @param DAC_Channel This parameter can be one of the following values:
962 * @arg @ref LL_DAC_CHANNEL_1
963 * @arg @ref LL_DAC_CHANNEL_2 (1)
964 *
965 * (1) On this STM32 series, parameter not available on all devices.
966 * Refer to device datasheet for channels availability.
967 * @retval None
968 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)969 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
970 {
971 SET_BIT(DACx->CR,
972 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
973 }
974
975 /**
976 * @brief Disable DAC selected channel.
977 * @rmtoll CR EN1 LL_DAC_Disable\n
978 * CR EN2 LL_DAC_Disable
979 * @param DACx DAC instance
980 * @param DAC_Channel This parameter can be one of the following values:
981 * @arg @ref LL_DAC_CHANNEL_1
982 * @arg @ref LL_DAC_CHANNEL_2 (1)
983 *
984 * (1) On this STM32 series, parameter not available on all devices.
985 * Refer to device datasheet for channels availability.
986 * @retval None
987 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)988 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
989 {
990 CLEAR_BIT(DACx->CR,
991 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
992 }
993
994 /**
995 * @brief Get DAC enable state of the selected channel.
996 * (0: DAC channel is disabled, 1: DAC channel is enabled)
997 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
998 * CR EN2 LL_DAC_IsEnabled
999 * @param DACx DAC instance
1000 * @param DAC_Channel This parameter can be one of the following values:
1001 * @arg @ref LL_DAC_CHANNEL_1
1002 * @arg @ref LL_DAC_CHANNEL_2 (1)
1003 *
1004 * (1) On this STM32 series, parameter not available on all devices.
1005 * Refer to device datasheet for channels availability.
1006 * @retval State of bit (1 or 0).
1007 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1008 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1009 {
1010 return ((READ_BIT(DACx->CR,
1011 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1012 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1013 }
1014
1015 /**
1016 * @brief Enable DAC trigger of the selected channel.
1017 * @note - If DAC trigger is disabled, DAC conversion is performed
1018 * automatically once the data holding register is updated,
1019 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1020 * @ref LL_DAC_ConvertData12RightAligned(), ...
1021 * - If DAC trigger is enabled, DAC conversion is performed
1022 * only when a hardware of software trigger event is occurring.
1023 * Select trigger source using
1024 * function @ref LL_DAC_SetTriggerSource().
1025 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1026 * CR TEN2 LL_DAC_EnableTrigger
1027 * @param DACx DAC instance
1028 * @param DAC_Channel This parameter can be one of the following values:
1029 * @arg @ref LL_DAC_CHANNEL_1
1030 * @arg @ref LL_DAC_CHANNEL_2 (1)
1031 *
1032 * (1) On this STM32 series, parameter not available on all devices.
1033 * Refer to device datasheet for channels availability.
1034 * @retval None
1035 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1036 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1037 {
1038 SET_BIT(DACx->CR,
1039 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1040 }
1041
1042 /**
1043 * @brief Disable DAC trigger of the selected channel.
1044 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1045 * CR TEN2 LL_DAC_DisableTrigger
1046 * @param DACx DAC instance
1047 * @param DAC_Channel This parameter can be one of the following values:
1048 * @arg @ref LL_DAC_CHANNEL_1
1049 * @arg @ref LL_DAC_CHANNEL_2 (1)
1050 *
1051 * (1) On this STM32 series, parameter not available on all devices.
1052 * Refer to device datasheet for channels availability.
1053 * @retval None
1054 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1055 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1056 {
1057 CLEAR_BIT(DACx->CR,
1058 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1059 }
1060
1061 /**
1062 * @brief Get DAC trigger state of the selected channel.
1063 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1064 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1065 * CR TEN2 LL_DAC_IsTriggerEnabled
1066 * @param DACx DAC instance
1067 * @param DAC_Channel This parameter can be one of the following values:
1068 * @arg @ref LL_DAC_CHANNEL_1
1069 * @arg @ref LL_DAC_CHANNEL_2 (1)
1070 *
1071 * (1) On this STM32 series, parameter not available on all devices.
1072 * Refer to device datasheet for channels availability.
1073 * @retval State of bit (1 or 0).
1074 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1075 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1076 {
1077 return ((READ_BIT(DACx->CR,
1078 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1079 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1080 }
1081
1082 /**
1083 * @brief Trig DAC conversion by software for the selected DAC channel.
1084 * @note Preliminarily, DAC trigger must be set to software trigger
1085 * using function
1086 * @ref LL_DAC_Init()
1087 * @ref LL_DAC_SetTriggerSource()
1088 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1089 * and DAC trigger must be enabled using
1090 * function @ref LL_DAC_EnableTrigger().
1091 * @note For devices featuring DAC with 2 channels: this function
1092 * can perform a SW start of both DAC channels simultaneously.
1093 * Two channels can be selected as parameter.
1094 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1095 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1096 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1097 * @param DACx DAC instance
1098 * @param DAC_Channel This parameter can a combination of the following values:
1099 * @arg @ref LL_DAC_CHANNEL_1
1100 * @arg @ref LL_DAC_CHANNEL_2 (1)
1101 *
1102 * (1) On this STM32 series, parameter not available on all devices.
1103 * Refer to device datasheet for channels availability.
1104 * @retval None
1105 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1106 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1107 {
1108 SET_BIT(DACx->SWTRIGR,
1109 (DAC_Channel & DAC_SWTR_CHX_MASK));
1110 }
1111
1112 /**
1113 * @brief Set the data to be loaded in the data holding register
1114 * in format 12 bits left alignment (LSB aligned on bit 0),
1115 * for the selected DAC channel.
1116 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1117 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1118 * @param DACx DAC instance
1119 * @param DAC_Channel This parameter can be one of the following values:
1120 * @arg @ref LL_DAC_CHANNEL_1
1121 * @arg @ref LL_DAC_CHANNEL_2 (1)
1122 *
1123 * (1) On this STM32 series, parameter not available on all devices.
1124 * Refer to device datasheet for channels availability.
1125 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1126 * @retval None
1127 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1128 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1129 {
1130 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1131 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1132
1133 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1134 }
1135
1136 /**
1137 * @brief Set the data to be loaded in the data holding register
1138 * in format 12 bits left alignment (MSB aligned on bit 15),
1139 * for the selected DAC channel.
1140 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1141 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1142 * @param DACx DAC instance
1143 * @param DAC_Channel This parameter can be one of the following values:
1144 * @arg @ref LL_DAC_CHANNEL_1
1145 * @arg @ref LL_DAC_CHANNEL_2 (1)
1146 *
1147 * (1) On this STM32 series, parameter not available on all devices.
1148 * Refer to device datasheet for channels availability.
1149 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1150 * @retval None
1151 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1152 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1153 {
1154 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1155 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1156
1157 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1158 }
1159
1160 /**
1161 * @brief Set the data to be loaded in the data holding register
1162 * in format 8 bits left alignment (LSB aligned on bit 0),
1163 * for the selected DAC channel.
1164 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1165 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1166 * @param DACx DAC instance
1167 * @param DAC_Channel This parameter can be one of the following values:
1168 * @arg @ref LL_DAC_CHANNEL_1
1169 * @arg @ref LL_DAC_CHANNEL_2 (1)
1170 *
1171 * (1) On this STM32 series, parameter not available on all devices.
1172 * Refer to device datasheet for channels availability.
1173 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1174 * @retval None
1175 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1176 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1177 {
1178 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1179 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1180
1181 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1182 }
1183
1184 #if defined(DAC_CHANNEL2_SUPPORT)
1185 /**
1186 * @brief Set the data to be loaded in the data holding register
1187 * in format 12 bits left alignment (LSB aligned on bit 0),
1188 * for both DAC channels.
1189 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1190 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1191 * @param DACx DAC instance
1192 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1193 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1194 * @retval None
1195 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1196 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1197 uint32_t DataChannel2)
1198 {
1199 MODIFY_REG(DACx->DHR12RD,
1200 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1201 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1202 }
1203
1204 /**
1205 * @brief Set the data to be loaded in the data holding register
1206 * in format 12 bits left alignment (MSB aligned on bit 15),
1207 * for both DAC channels.
1208 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1209 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1210 * @param DACx DAC instance
1211 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1212 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1213 * @retval None
1214 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1215 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1216 uint32_t DataChannel2)
1217 {
1218 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1219 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1220 /* the 4 LSB must be taken into account for the shift value. */
1221 MODIFY_REG(DACx->DHR12LD,
1222 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1223 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1224 }
1225
1226 /**
1227 * @brief Set the data to be loaded in the data holding register
1228 * in format 8 bits left alignment (LSB aligned on bit 0),
1229 * for both DAC channels.
1230 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1231 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1232 * @param DACx DAC instance
1233 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1234 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1235 * @retval None
1236 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1237 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1238 uint32_t DataChannel2)
1239 {
1240 MODIFY_REG(DACx->DHR8RD,
1241 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1242 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1243 }
1244 #endif /* DAC_CHANNEL2_SUPPORT */
1245
1246 /**
1247 * @brief Retrieve output data currently generated for the selected DAC channel.
1248 * @note Whatever alignment and resolution settings
1249 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1250 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1251 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1252 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1253 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1254 * @param DACx DAC instance
1255 * @param DAC_Channel This parameter can be one of the following values:
1256 * @arg @ref LL_DAC_CHANNEL_1
1257 * @arg @ref LL_DAC_CHANNEL_2 (1)
1258 *
1259 * (1) On this STM32 series, parameter not available on all devices.
1260 * Refer to device datasheet for channels availability.
1261 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1262 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1263 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1264 {
1265 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1266 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1267
1268 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1269 }
1270
1271 /**
1272 * @}
1273 */
1274
1275 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1276 * @{
1277 */
1278
1279 /**
1280 * @brief Get DAC underrun flag for DAC channel 1
1281 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1282 * @param DACx DAC instance
1283 * @retval State of bit (1 or 0).
1284 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1285 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1286 {
1287 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1288 }
1289
1290 #if defined(DAC_CHANNEL2_SUPPORT)
1291 /**
1292 * @brief Get DAC underrun flag for DAC channel 2
1293 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1294 * @param DACx DAC instance
1295 * @retval State of bit (1 or 0).
1296 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1297 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1298 {
1299 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1300 }
1301 #endif /* DAC_CHANNEL2_SUPPORT */
1302
1303 /**
1304 * @brief Clear DAC underrun flag for DAC channel 1
1305 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1306 * @param DACx DAC instance
1307 * @retval None
1308 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1309 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1310 {
1311 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1312 }
1313
1314 #if defined(DAC_CHANNEL2_SUPPORT)
1315 /**
1316 * @brief Clear DAC underrun flag for DAC channel 2
1317 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1318 * @param DACx DAC instance
1319 * @retval None
1320 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1321 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1322 {
1323 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1324 }
1325 #endif /* DAC_CHANNEL2_SUPPORT */
1326
1327 /**
1328 * @}
1329 */
1330
1331 /** @defgroup DAC_LL_EF_IT_Management IT management
1332 * @{
1333 */
1334
1335 /**
1336 * @brief Enable DMA underrun interrupt for DAC channel 1
1337 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1338 * @param DACx DAC instance
1339 * @retval None
1340 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1341 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1342 {
1343 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1344 }
1345
1346 #if defined(DAC_CHANNEL2_SUPPORT)
1347 /**
1348 * @brief Enable DMA underrun interrupt for DAC channel 2
1349 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1350 * @param DACx DAC instance
1351 * @retval None
1352 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1353 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1354 {
1355 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1356 }
1357 #endif /* DAC_CHANNEL2_SUPPORT */
1358
1359 /**
1360 * @brief Disable DMA underrun interrupt for DAC channel 1
1361 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1362 * @param DACx DAC instance
1363 * @retval None
1364 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1365 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1366 {
1367 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1368 }
1369
1370 #if defined(DAC_CHANNEL2_SUPPORT)
1371 /**
1372 * @brief Disable DMA underrun interrupt for DAC channel 2
1373 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1374 * @param DACx DAC instance
1375 * @retval None
1376 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1377 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1378 {
1379 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1380 }
1381 #endif /* DAC_CHANNEL2_SUPPORT */
1382
1383 /**
1384 * @brief Get DMA underrun interrupt for DAC channel 1
1385 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1386 * @param DACx DAC instance
1387 * @retval State of bit (1 or 0).
1388 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1389 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1390 {
1391 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1392 }
1393
1394 #if defined(DAC_CHANNEL2_SUPPORT)
1395 /**
1396 * @brief Get DMA underrun interrupt for DAC channel 2
1397 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1398 * @param DACx DAC instance
1399 * @retval State of bit (1 or 0).
1400 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)1401 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1402 {
1403 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1404 }
1405 #endif /* DAC_CHANNEL2_SUPPORT */
1406
1407 /**
1408 * @}
1409 */
1410
1411 #if defined(USE_FULL_LL_DRIVER)
1412 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1413 * @{
1414 */
1415
1416 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1417 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1418 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1419
1420 /**
1421 * @}
1422 */
1423 #endif /* USE_FULL_LL_DRIVER */
1424
1425 /**
1426 * @}
1427 */
1428
1429 /**
1430 * @}
1431 */
1432
1433 #endif /* DAC */
1434
1435 /**
1436 * @}
1437 */
1438
1439 #ifdef __cplusplus
1440 }
1441 #endif
1442
1443 #endif /* STM32F4xx_LL_DAC_H */
1444
