1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F4xx_LL_ADC_H
21 #define __STM32F4xx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx.h"
29
30 /** @addtogroup STM32F4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer register offset */
51 /* - sequencer rank bits position into the selected register */
52
53 /* Internal register offset for ADC group regular sequencer configuration */
54 /* (offset placed into a spare area of literal definition) */
55 #define ADC_SQR1_REGOFFSET 0x00000000UL
56 #define ADC_SQR2_REGOFFSET 0x00000100UL
57 #define ADC_SQR3_REGOFFSET 0x00000200UL
58 #define ADC_SQR4_REGOFFSET 0x00000300UL
59
60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
61 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
62
63 /* Definition of ADC group regular sequencer bits information to be inserted */
64 /* into ADC group regular sequencer ranks literals definition. */
65 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
66 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
67 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
68 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
69 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
70 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
71 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
72 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
73 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
74 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
75 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
76 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
77 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
78 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
79 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
80 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
81
82 /* Internal mask for ADC group injected sequencer: */
83 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
84 /* - data register offset */
85 /* - offset register offset */
86 /* - sequencer rank bits position into the selected register */
87
88 /* Internal register offset for ADC group injected data register */
89 /* (offset placed into a spare area of literal definition) */
90 #define ADC_JDR1_REGOFFSET 0x00000000UL
91 #define ADC_JDR2_REGOFFSET 0x00000100UL
92 #define ADC_JDR3_REGOFFSET 0x00000200UL
93 #define ADC_JDR4_REGOFFSET 0x00000300UL
94
95 /* Internal register offset for ADC group injected offset configuration */
96 /* (offset placed into a spare area of literal definition) */
97 #define ADC_JOFR1_REGOFFSET 0x00000000UL
98 #define ADC_JOFR2_REGOFFSET 0x00001000UL
99 #define ADC_JOFR3_REGOFFSET 0x00002000UL
100 #define ADC_JOFR4_REGOFFSET 0x00003000UL
101
102 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
103 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
104 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
105
106 /* Internal mask for ADC group regular trigger: */
107 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
108 /* - regular trigger source */
109 /* - regular trigger edge */
110 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
111
112 /* Mask containing trigger source masks for each of possible */
113 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
114 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
115 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \
116 ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \
117 ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \
118 ((ADC_CR2_EXTSEL) >> (4UL * 3UL)))
119
120 /* Mask containing trigger edge masks for each of possible */
121 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \
124 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
127
128 /* Definition of ADC group regular trigger bits information. */
129 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
130 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
131
132
133
134 /* Internal mask for ADC group injected trigger: */
135 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
136 /* - injected trigger source */
137 /* - injected trigger edge */
138 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
139
140 /* Mask containing trigger source masks for each of possible */
141 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
143 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \
144 ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \
145 ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \
146 ((ADC_CR2_JEXTSEL) >> (4UL * 3UL)))
147
148 /* Mask containing trigger edge masks for each of possible */
149 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
150 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
151 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \
152 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
155
156 /* Definition of ADC group injected trigger bits information. */
157 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
158 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
159
160 /* Internal mask for ADC channel: */
161 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
162 /* - channel identifier defined by number */
163 /* - channel differentiation between external channels (connected to */
164 /* GPIO pins) and internal channels (connected to internal paths) */
165 /* - channel sampling time defined by SMPRx register offset */
166 /* and SMPx bits positions into SMPRx register */
167 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
168 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
169 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
170 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
171 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
172
173 /* Channel differentiation between external and internal channels */
174 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */
175 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
176 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
177 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
178
179 /* Internal register offset for ADC channel sampling time configuration */
180 /* (offset placed into a spare area of literal definition) */
181 #define ADC_SMPR1_REGOFFSET 0x00000000UL
182 #define ADC_SMPR2_REGOFFSET 0x02000000UL
183 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
184
185 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL
186 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
187
188 /* Definition of channels ID number information to be inserted into */
189 /* channels literals definition. */
190 #define ADC_CHANNEL_0_NUMBER 0x00000000UL
191 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
192 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
193 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
194 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
195 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
196 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
197 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
198 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
199 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
200 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
201 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
202 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
203 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
204 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
205 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
206 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
207 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
208 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
209
210 /* Definition of channels sampling time information to be inserted into */
211 /* channels literals definition. */
212 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
213 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
214 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
215 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
216 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
217 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
218 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
219 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
220 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
221 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
222 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
223 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
224 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
225 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
226 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
227 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
228 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
229 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
230 #define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
231
232 /* Internal mask for ADC analog watchdog: */
233 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
234 /* (concatenation of multiple bits used in different analog watchdogs, */
235 /* (feature of several watchdogs not available on all STM32 families)). */
236 /* - analog watchdog 1: monitored channel defined by number, */
237 /* selection of ADC group (ADC groups regular and-or injected). */
238
239 /* Internal register offset for ADC analog watchdog channel configuration */
240 #define ADC_AWD_CR1_REGOFFSET 0x00000000UL
241
242 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
243
244 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
245 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
246
247 /* Internal register offset for ADC analog watchdog threshold configuration */
248 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL
249 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL
250 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
251
252 /* ADC registers bits positions */
253 #define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
254 #define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
255
256 /* ADC internal channels related definitions */
257 /* Internal voltage reference VrefInt */
258 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
259 #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
260 /* Temperature sensor */
261 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
262 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
263 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
264 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
265 #define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
266
267 /**
268 * @}
269 */
270
271
272 /* Private macros ------------------------------------------------------------*/
273 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
274 * @{
275 */
276
277 /**
278 * @brief Driver macro reserved for internal use: isolate bits with the
279 * selected mask and shift them to the register LSB
280 * (shift mask on register position bit 0).
281 * @param __BITS__ Bits in register 32 bits
282 * @param __MASK__ Mask in register 32 bits
283 * @retval Bits in register 32 bits
284 */
285 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
286 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
287
288 /**
289 * @brief Driver macro reserved for internal use: set a pointer to
290 * a register from a register basis from which an offset
291 * is applied.
292 * @param __REG__ Register basis from which the offset is applied.
293 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers).
294 * @retval Pointer to register address
295 */
296 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
297 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
298
299 /**
300 * @}
301 */
302
303
304 /* Exported types ------------------------------------------------------------*/
305 #if defined(USE_FULL_LL_DRIVER)
306 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
307 * @{
308 */
309
310 /**
311 * @brief Structure definition of some features of ADC common parameters
312 * and multimode
313 * (all ADC instances belonging to the same ADC common instance).
314 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
315 * is conditioned to ADC instances state (all ADC instances
316 * sharing the same ADC common instance):
317 * All ADC instances sharing the same ADC common instance must be
318 * disabled.
319 */
320 typedef struct
321 {
322 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
323 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
324
325 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
326
327 #if defined(ADC_MULTIMODE_SUPPORT)
328 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
329 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
330
331 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
332
333 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
334 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
335
336 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
337
338 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
339 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
340
341 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
342 #endif /* ADC_MULTIMODE_SUPPORT */
343
344 } LL_ADC_CommonInitTypeDef;
345
346 /**
347 * @brief Structure definition of some features of ADC instance.
348 * @note These parameters have an impact on ADC scope: ADC instance.
349 * Affects both group regular and group injected (availability
350 * of ADC group injected depends on STM32 families).
351 * Refer to corresponding unitary functions into
352 * @ref ADC_LL_EF_Configuration_ADC_Instance .
353 * @note The setting of these parameters by function @ref LL_ADC_Init()
354 * is conditioned to ADC state:
355 * ADC instance must be disabled.
356 * This condition is applied to all ADC features, for efficiency
357 * and compatibility over all STM32 families. However, the different
358 * features can be set under different ADC state conditions
359 * (setting possible with ADC enabled without conversion on going,
360 * ADC enabled with conversion on going, ...)
361 * Each feature can be updated afterwards with a unitary function
362 * and potentially with ADC in a different state than disabled,
363 * refer to description of each function for setting
364 * conditioned to ADC state.
365 */
366 typedef struct
367 {
368 uint32_t Resolution; /*!< Set ADC resolution.
369 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
370
371 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
372
373 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
374 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
375
376 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
377
378 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
379 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
380
381 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
382
383 } LL_ADC_InitTypeDef;
384
385 /**
386 * @brief Structure definition of some features of ADC group regular.
387 * @note These parameters have an impact on ADC scope: ADC group regular.
388 * Refer to corresponding unitary functions into
389 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
390 * (functions with prefix "REG").
391 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
392 * is conditioned to ADC state:
393 * ADC instance must be disabled.
394 * This condition is applied to all ADC features, for efficiency
395 * and compatibility over all STM32 families. However, the different
396 * features can be set under different ADC state conditions
397 * (setting possible with ADC enabled without conversion on going,
398 * ADC enabled with conversion on going, ...)
399 * Each feature can be updated afterwards with a unitary function
400 * and potentially with ADC in a different state than disabled,
401 * refer to description of each function for setting
402 * conditioned to ADC state.
403 */
404 typedef struct
405 {
406 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
407 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
408 @note On this STM32 series, setting of external trigger edge is performed
409 using function @ref LL_ADC_REG_StartConversionExtTrig().
410
411 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
412
413 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
414 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
415 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
416
417 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
418
419 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
420 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
421 @note This parameter has an effect only if group regular sequencer is enabled
422 (scan length of 2 ranks or more).
423
424 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
425
426 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
427 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
428 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
429
430 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
431
432 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
433 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
434
435 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
436
437 } LL_ADC_REG_InitTypeDef;
438
439 /**
440 * @brief Structure definition of some features of ADC group injected.
441 * @note These parameters have an impact on ADC scope: ADC group injected.
442 * Refer to corresponding unitary functions into
443 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
444 * (functions with prefix "INJ").
445 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
446 * is conditioned to ADC state:
447 * ADC instance must be disabled.
448 * This condition is applied to all ADC features, for efficiency
449 * and compatibility over all STM32 families. However, the different
450 * features can be set under different ADC state conditions
451 * (setting possible with ADC enabled without conversion on going,
452 * ADC enabled with conversion on going, ...)
453 * Each feature can be updated afterwards with a unitary function
454 * and potentially with ADC in a different state than disabled,
455 * refer to description of each function for setting
456 * conditioned to ADC state.
457 */
458 typedef struct
459 {
460 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
461 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
462 @note On this STM32 series, setting of external trigger edge is performed
463 using function @ref LL_ADC_INJ_StartConversionExtTrig().
464
465 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
466
467 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
468 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
469 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
470
471 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
472
473 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
474 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
475 @note This parameter has an effect only if group injected sequencer is enabled
476 (scan length of 2 ranks or more).
477
478 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
479
480 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
481 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
482 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
483
484 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
485
486 } LL_ADC_INJ_InitTypeDef;
487
488 /**
489 * @}
490 */
491 #endif /* USE_FULL_LL_DRIVER */
492
493 /* Exported constants --------------------------------------------------------*/
494 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
495 * @{
496 */
497
498 /** @defgroup ADC_LL_EC_FLAG ADC flags
499 * @brief Flags defines which can be used with LL_ADC_ReadReg function
500 * @{
501 */
502 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
503 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
504 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
505 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
506 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
507 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
508 #if defined(ADC_MULTIMODE_SUPPORT)
509 #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
510 #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
511 #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
512 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */
513 #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */
514 #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */
515 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
516 #define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
517 #define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
518 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
519 #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */
520 #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */
521 #endif
522 /**
523 * @}
524 */
525
526 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
527 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
528 * @{
529 */
530 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
531 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
532 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
533 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
534 /**
535 * @}
536 */
537
538 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
539 * @{
540 */
541 /* List of ADC registers intended to be used (most commonly) with */
542 /* DMA transfer. */
543 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
544 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
545 #if defined(ADC_MULTIMODE_SUPPORT)
546 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
547 #endif
548 /**
549 * @}
550 */
551
552 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
553 * @{
554 */
555 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
556 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
557 #define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */
558 #define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */
559 /**
560 * @}
561 */
562
563 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
564 * @{
565 */
566 /* Note: Other measurement paths to internal channels may be available */
567 /* (connections to other peripherals). */
568 /* If they are not listed below, they do not require any specific */
569 /* path enable. In this case, Access to measurement path is done */
570 /* only by selecting the corresponding ADC internal channel. */
571 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL /*!< ADC measurement paths all disabled */
572 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
573 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
574 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */
575 /**
576 * @}
577 */
578
579 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
580 * @{
581 */
582 #define LL_ADC_RESOLUTION_12B 0x00000000UL /*!< ADC resolution 12 bits */
583 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
584 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
585 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
586 /**
587 * @}
588 */
589
590 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
591 * @{
592 */
593 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
594 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
595 /**
596 * @}
597 */
598
599 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
600 * @{
601 */
602 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
603 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
604 /**
605 * @}
606 */
607
608 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
609 * @{
610 */
611 #define LL_ADC_GROUP_REGULAR 0x00000001UL /*!< ADC group regular (available on all STM32 devices) */
612 #define LL_ADC_GROUP_INJECTED 0x00000002UL /*!< ADC group injected (not available on all STM32 devices)*/
613 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL /*!< ADC both groups regular and injected */
614 /**
615 * @}
616 */
617
618 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
619 * @{
620 */
621 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
622 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
623 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
624 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
625 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
626 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
627 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
628 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
629 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
630 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
631 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
632 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
633 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
634 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
635 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
636 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
637 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
638 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
639 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
640 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */
641 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */
642 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
643 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */
644 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
645 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
646 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
647 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
648 /**
649 * @}
650 */
651
652 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
653 * @{
654 */
655 #define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL /*!< ADC group regular conversion trigger internal: SW start. */
656 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
657 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
658 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
659 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
660 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
661 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
662 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
663 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
664 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
665 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
666 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
667 #define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
668 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
669 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
670 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
671 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
672 /**
673 * @}
674 */
675
676 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
677 * @{
678 */
679 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
680 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
681 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
682 /**
683 * @}
684 */
685
686 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
687 * @{
688 */
689 #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */
690 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
691 /**
692 * @}
693 */
694
695 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
696 * @{
697 */
698 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL /*!< ADC conversions are not transferred by DMA */
699 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
700 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
701 /**
702 * @}
703 */
704
705 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
706 * @{
707 */
708 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL /*!< ADC flag EOC (end of unitary conversion) selected */
709 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
710 /**
711 * @}
712 */
713
714 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
715 * @{
716 */
717 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
718 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
719 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
720 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
721 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
722 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
723 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
724 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
725 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
726 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
727 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
728 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
729 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
730 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
731 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
732 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
733 /**
734 * @}
735 */
736
737 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
738 * @{
739 */
740 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group regular sequencer discontinuous mode disable */
741 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
742 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
743 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
744 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
745 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
746 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
747 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
748 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
749 /**
750 * @}
751 */
752
753 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
754 * @{
755 */
756 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
757 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
758 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
759 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
760 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
761 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
762 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
763 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
764 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
765 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
766 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
767 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
768 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
769 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
770 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
771 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
772 /**
773 * @}
774 */
775
776 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
777 * @{
778 */
779 #define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL /*!< ADC group injected conversion trigger internal: SW start. */
780 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
781 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
782 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
783 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
784 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
785 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
786 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
787 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
788 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
789 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
790 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
791 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
792 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
793 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
794 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
795 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
796 /**
797 * @}
798 */
799
800 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
801 * @{
802 */
803 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
804 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
805 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
806 /**
807 * @}
808 */
809
810 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
811 * @{
812 */
813 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
814 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
815 /**
816 * @}
817 */
818
819
820 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
821 * @{
822 */
823 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
824 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
825 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
826 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
827 /**
828 * @}
829 */
830
831 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
832 * @{
833 */
834 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group injected sequencer discontinuous mode disable */
835 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
836 /**
837 * @}
838 */
839
840 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
841 * @{
842 */
843 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */
844 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */
845 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */
846 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */
847 /**
848 * @}
849 */
850
851 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
852 * @{
853 */
854 #define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL /*!< Sampling time 3 ADC clock cycles */
855 #define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */
856 #define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */
857 #define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */
858 #define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */
859 #define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */
860 #define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */
861 #define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */
862 /**
863 * @}
864 */
865
866 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
867 * @{
868 */
869 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
870 /**
871 * @}
872 */
873
874 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
875 * @{
876 */
877 #define LL_ADC_AWD_DISABLE 0x00000000UL /*!< ADC analog watchdog monitoring disabled */
878 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
879 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
880 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
881 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
882 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
883 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
884 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
885 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
886 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
887 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
888 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
889 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
890 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
891 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
892 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
893 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
894 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
895 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
896 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
897 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
898 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
899 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
900 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
901 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
902 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
903 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
904 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
905 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
906 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
907 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
908 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
909 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
910 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
911 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
912 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
913 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
914 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
915 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
916 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
917 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
918 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
919 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
920 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
921 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
922 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
923 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
924 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
925 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
926 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
927 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
928 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
929 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
930 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
931 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
932 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
933 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
934 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
935 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
936 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
937 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
938 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
939 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
940 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
941 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
942 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
943 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
944 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
945 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
946 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
947 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
948 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
949 #if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
950 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
951 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
952 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */
953 #endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
954 /**
955 * @}
956 */
957
958 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
959 * @{
960 */
961 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
962 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
963 /**
964 * @}
965 */
966
967 #if defined(ADC_MULTIMODE_SUPPORT)
968 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
969 * @{
970 */
971 #define LL_ADC_MULTI_INDEPENDENT 0x00000000UL /*!< ADC dual mode disabled (ADC independent mode) */
972 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
973 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
974 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */
975 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
976 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
977 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
978 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
979 #if defined(ADC3)
980 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */
981 #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */
982 #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */
983 #define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */
984 #define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */
985 #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
986 #endif
987 /**
988 * @}
989 */
990
991 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
992 * @{
993 */
994 #define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
995 #define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
996 #define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */
997 #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
998 #define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */
999 #define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */
1000 #define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1006 * @{
1007 */
1008 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/
1009 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1010 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1011 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1012 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1013 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1014 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1015 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1016 #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */
1017 #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */
1018 #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */
1019 #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */
1020 #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */
1021 #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */
1022 #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */
1023 #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1029 * @{
1030 */
1031 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1032 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1033 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1034 /**
1035 * @}
1036 */
1037
1038 #endif /* ADC_MULTIMODE_SUPPORT */
1039
1040
1041 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1042 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1043 * not timeout values.
1044 * For details on delays values, refer to descriptions in source code
1045 * above each literal definition.
1046 * @{
1047 */
1048
1049 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1050 /* not timeout values. */
1051 /* Timeout values for ADC operations are dependent to device clock */
1052 /* configuration (system clock versus ADC clock), */
1053 /* and therefore must be defined in user application. */
1054 /* Indications for estimation of ADC timeout delays, for this */
1055 /* STM32 series: */
1056 /* - ADC enable time: maximum delay is 2us */
1057 /* (refer to device datasheet, parameter "tSTAB") */
1058 /* - ADC conversion time: duration depending on ADC clock and ADC */
1059 /* configuration. */
1060 /* (refer to device reference manual, section "Timing") */
1061
1062 /* Delay for internal voltage reference stabilization time. */
1063 /* Delay set to maximum value (refer to device datasheet, */
1064 /* parameter "tSTART"). */
1065 /* Unit: us */
1066 #define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
1067
1068 /* Delay for temperature sensor stabilization time. */
1069 /* Literal set to maximum value (refer to device datasheet, */
1070 /* parameter "tSTART"). */
1071 /* Unit: us */
1072 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */
1073
1074 /**
1075 * @}
1076 */
1077
1078 /**
1079 * @}
1080 */
1081
1082
1083 /* Exported macro ------------------------------------------------------------*/
1084 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1085 * @{
1086 */
1087
1088 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1089 * @{
1090 */
1091
1092 /**
1093 * @brief Write a value in ADC register
1094 * @param __INSTANCE__ ADC Instance
1095 * @param __REG__ Register to be written
1096 * @param __VALUE__ Value to be written in the register
1097 * @retval None
1098 */
1099 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1100
1101 /**
1102 * @brief Read a value in ADC register
1103 * @param __INSTANCE__ ADC Instance
1104 * @param __REG__ Register to be read
1105 * @retval Register value
1106 */
1107 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1108 /**
1109 * @}
1110 */
1111
1112 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1113 * @{
1114 */
1115
1116 /**
1117 * @brief Helper macro to get ADC channel number in decimal format
1118 * from literals LL_ADC_CHANNEL_x.
1119 * @note Example:
1120 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1121 * will return decimal number "4".
1122 * @note The input can be a value from functions where a channel
1123 * number is returned, either defined with number
1124 * or with bitfield (only one bit must be set).
1125 * @param __CHANNEL__ This parameter can be one of the following values:
1126 * @arg @ref LL_ADC_CHANNEL_0
1127 * @arg @ref LL_ADC_CHANNEL_1
1128 * @arg @ref LL_ADC_CHANNEL_2
1129 * @arg @ref LL_ADC_CHANNEL_3
1130 * @arg @ref LL_ADC_CHANNEL_4
1131 * @arg @ref LL_ADC_CHANNEL_5
1132 * @arg @ref LL_ADC_CHANNEL_6
1133 * @arg @ref LL_ADC_CHANNEL_7
1134 * @arg @ref LL_ADC_CHANNEL_8
1135 * @arg @ref LL_ADC_CHANNEL_9
1136 * @arg @ref LL_ADC_CHANNEL_10
1137 * @arg @ref LL_ADC_CHANNEL_11
1138 * @arg @ref LL_ADC_CHANNEL_12
1139 * @arg @ref LL_ADC_CHANNEL_13
1140 * @arg @ref LL_ADC_CHANNEL_14
1141 * @arg @ref LL_ADC_CHANNEL_15
1142 * @arg @ref LL_ADC_CHANNEL_16
1143 * @arg @ref LL_ADC_CHANNEL_17
1144 * @arg @ref LL_ADC_CHANNEL_18
1145 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1146 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1147 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1148 *
1149 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1150 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1151 * @retval Value between Min_Data=0 and Max_Data=18
1152 */
1153 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1154 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1155
1156 /**
1157 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1158 * from number in decimal format.
1159 * @note Example:
1160 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1161 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1162 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1163 * @retval Returned value can be one of the following values:
1164 * @arg @ref LL_ADC_CHANNEL_0
1165 * @arg @ref LL_ADC_CHANNEL_1
1166 * @arg @ref LL_ADC_CHANNEL_2
1167 * @arg @ref LL_ADC_CHANNEL_3
1168 * @arg @ref LL_ADC_CHANNEL_4
1169 * @arg @ref LL_ADC_CHANNEL_5
1170 * @arg @ref LL_ADC_CHANNEL_6
1171 * @arg @ref LL_ADC_CHANNEL_7
1172 * @arg @ref LL_ADC_CHANNEL_8
1173 * @arg @ref LL_ADC_CHANNEL_9
1174 * @arg @ref LL_ADC_CHANNEL_10
1175 * @arg @ref LL_ADC_CHANNEL_11
1176 * @arg @ref LL_ADC_CHANNEL_12
1177 * @arg @ref LL_ADC_CHANNEL_13
1178 * @arg @ref LL_ADC_CHANNEL_14
1179 * @arg @ref LL_ADC_CHANNEL_15
1180 * @arg @ref LL_ADC_CHANNEL_16
1181 * @arg @ref LL_ADC_CHANNEL_17
1182 * @arg @ref LL_ADC_CHANNEL_18
1183 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1184 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1185 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1186 *
1187 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1188 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1189 * (1) For ADC channel read back from ADC register,
1190 * comparison with internal channel parameter to be done
1191 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1192 */
1193 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1194 (((__DECIMAL_NB__) <= 9UL) \
1195 ? ( \
1196 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1197 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1198 ) \
1199 : \
1200 ( \
1201 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1202 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1203 ) \
1204 )
1205
1206 /**
1207 * @brief Helper macro to determine whether the selected channel
1208 * corresponds to literal definitions of driver.
1209 * @note The different literal definitions of ADC channels are:
1210 * - ADC internal channel:
1211 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1212 * - ADC external channel (channel connected to a GPIO pin):
1213 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1214 * @note The channel parameter must be a value defined from literal
1215 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1216 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1217 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1218 * must not be a value from functions where a channel number is
1219 * returned from ADC registers,
1220 * because internal and external channels share the same channel
1221 * number in ADC registers. The differentiation is made only with
1222 * parameters definitions of driver.
1223 * @param __CHANNEL__ This parameter can be one of the following values:
1224 * @arg @ref LL_ADC_CHANNEL_0
1225 * @arg @ref LL_ADC_CHANNEL_1
1226 * @arg @ref LL_ADC_CHANNEL_2
1227 * @arg @ref LL_ADC_CHANNEL_3
1228 * @arg @ref LL_ADC_CHANNEL_4
1229 * @arg @ref LL_ADC_CHANNEL_5
1230 * @arg @ref LL_ADC_CHANNEL_6
1231 * @arg @ref LL_ADC_CHANNEL_7
1232 * @arg @ref LL_ADC_CHANNEL_8
1233 * @arg @ref LL_ADC_CHANNEL_9
1234 * @arg @ref LL_ADC_CHANNEL_10
1235 * @arg @ref LL_ADC_CHANNEL_11
1236 * @arg @ref LL_ADC_CHANNEL_12
1237 * @arg @ref LL_ADC_CHANNEL_13
1238 * @arg @ref LL_ADC_CHANNEL_14
1239 * @arg @ref LL_ADC_CHANNEL_15
1240 * @arg @ref LL_ADC_CHANNEL_16
1241 * @arg @ref LL_ADC_CHANNEL_17
1242 * @arg @ref LL_ADC_CHANNEL_18
1243 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1244 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1245 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1246 *
1247 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1248 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1249 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1250 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1251 */
1252 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1253 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1254
1255 /**
1256 * @brief Helper macro to convert a channel defined from parameter
1257 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1258 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1259 * to its equivalent parameter definition of a ADC external channel
1260 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1261 * @note The channel parameter can be, additionally to a value
1262 * defined from parameter definition of a ADC internal channel
1263 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1264 * a value defined from parameter definition of
1265 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1266 * or a value from functions where a channel number is returned
1267 * from ADC registers.
1268 * @param __CHANNEL__ This parameter can be one of the following values:
1269 * @arg @ref LL_ADC_CHANNEL_0
1270 * @arg @ref LL_ADC_CHANNEL_1
1271 * @arg @ref LL_ADC_CHANNEL_2
1272 * @arg @ref LL_ADC_CHANNEL_3
1273 * @arg @ref LL_ADC_CHANNEL_4
1274 * @arg @ref LL_ADC_CHANNEL_5
1275 * @arg @ref LL_ADC_CHANNEL_6
1276 * @arg @ref LL_ADC_CHANNEL_7
1277 * @arg @ref LL_ADC_CHANNEL_8
1278 * @arg @ref LL_ADC_CHANNEL_9
1279 * @arg @ref LL_ADC_CHANNEL_10
1280 * @arg @ref LL_ADC_CHANNEL_11
1281 * @arg @ref LL_ADC_CHANNEL_12
1282 * @arg @ref LL_ADC_CHANNEL_13
1283 * @arg @ref LL_ADC_CHANNEL_14
1284 * @arg @ref LL_ADC_CHANNEL_15
1285 * @arg @ref LL_ADC_CHANNEL_16
1286 * @arg @ref LL_ADC_CHANNEL_17
1287 * @arg @ref LL_ADC_CHANNEL_18
1288 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1289 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1290 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1291 *
1292 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1293 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1294 * @retval Returned value can be one of the following values:
1295 * @arg @ref LL_ADC_CHANNEL_0
1296 * @arg @ref LL_ADC_CHANNEL_1
1297 * @arg @ref LL_ADC_CHANNEL_2
1298 * @arg @ref LL_ADC_CHANNEL_3
1299 * @arg @ref LL_ADC_CHANNEL_4
1300 * @arg @ref LL_ADC_CHANNEL_5
1301 * @arg @ref LL_ADC_CHANNEL_6
1302 * @arg @ref LL_ADC_CHANNEL_7
1303 * @arg @ref LL_ADC_CHANNEL_8
1304 * @arg @ref LL_ADC_CHANNEL_9
1305 * @arg @ref LL_ADC_CHANNEL_10
1306 * @arg @ref LL_ADC_CHANNEL_11
1307 * @arg @ref LL_ADC_CHANNEL_12
1308 * @arg @ref LL_ADC_CHANNEL_13
1309 * @arg @ref LL_ADC_CHANNEL_14
1310 * @arg @ref LL_ADC_CHANNEL_15
1311 * @arg @ref LL_ADC_CHANNEL_16
1312 * @arg @ref LL_ADC_CHANNEL_17
1313 * @arg @ref LL_ADC_CHANNEL_18
1314 */
1315 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1316 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1317
1318 /**
1319 * @brief Helper macro to determine whether the internal channel
1320 * selected is available on the ADC instance selected.
1321 * @note The channel parameter must be a value defined from parameter
1322 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1323 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1324 * must not be a value defined from parameter definition of
1325 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1326 * or a value from functions where a channel number is
1327 * returned from ADC registers,
1328 * because internal and external channels share the same channel
1329 * number in ADC registers. The differentiation is made only with
1330 * parameters definitions of driver.
1331 * @param __ADC_INSTANCE__ ADC instance
1332 * @param __CHANNEL__ This parameter can be one of the following values:
1333 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1334 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1335 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1336 *
1337 * (1) On STM32F4, parameter available only on ADC instance: ADC1.
1338 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1339 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1340 * Value "1" if the internal channel selected is available on the ADC instance selected.
1341 */
1342 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1343 ( \
1344 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1345 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1346 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1347 )
1348 /**
1349 * @brief Helper macro to define ADC analog watchdog parameter:
1350 * define a single channel to monitor with analog watchdog
1351 * from sequencer channel and groups definition.
1352 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1353 * Example:
1354 * LL_ADC_SetAnalogWDMonitChannels(
1355 * ADC1, LL_ADC_AWD1,
1356 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1357 * @param __CHANNEL__ This parameter can be one of the following values:
1358 * @arg @ref LL_ADC_CHANNEL_0
1359 * @arg @ref LL_ADC_CHANNEL_1
1360 * @arg @ref LL_ADC_CHANNEL_2
1361 * @arg @ref LL_ADC_CHANNEL_3
1362 * @arg @ref LL_ADC_CHANNEL_4
1363 * @arg @ref LL_ADC_CHANNEL_5
1364 * @arg @ref LL_ADC_CHANNEL_6
1365 * @arg @ref LL_ADC_CHANNEL_7
1366 * @arg @ref LL_ADC_CHANNEL_8
1367 * @arg @ref LL_ADC_CHANNEL_9
1368 * @arg @ref LL_ADC_CHANNEL_10
1369 * @arg @ref LL_ADC_CHANNEL_11
1370 * @arg @ref LL_ADC_CHANNEL_12
1371 * @arg @ref LL_ADC_CHANNEL_13
1372 * @arg @ref LL_ADC_CHANNEL_14
1373 * @arg @ref LL_ADC_CHANNEL_15
1374 * @arg @ref LL_ADC_CHANNEL_16
1375 * @arg @ref LL_ADC_CHANNEL_17
1376 * @arg @ref LL_ADC_CHANNEL_18
1377 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1378 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
1379 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
1380 *
1381 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1382 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
1383 * (1) For ADC channel read back from ADC register,
1384 * comparison with internal channel parameter to be done
1385 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1386 * @param __GROUP__ This parameter can be one of the following values:
1387 * @arg @ref LL_ADC_GROUP_REGULAR
1388 * @arg @ref LL_ADC_GROUP_INJECTED
1389 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1390 * @retval Returned value can be one of the following values:
1391 * @arg @ref LL_ADC_AWD_DISABLE
1392 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1393 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1394 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1395 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1396 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1397 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1398 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1399 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1400 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1401 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1402 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1403 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1404 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1405 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1406 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1407 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1408 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1409 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1410 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1411 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1412 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1413 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1414 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1415 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1416 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1417 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1418 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1419 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1420 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1421 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1422 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1423 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1424 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1425 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1426 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1427 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1428 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1429 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1430 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1431 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1432 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1433 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1434 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1435 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1436 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1437 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1438 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1439 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1440 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1441 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1442 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1443 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1444 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1445 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1446 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1447 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1448 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1449 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
1450 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
1451 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1452 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1453 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1454 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1455 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
1456 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
1457 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
1458 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
1459 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
1460 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
1461 *
1462 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
1463 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
1464 */
1465 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1466 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1467 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1468 : \
1469 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1470 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1471 : \
1472 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1473 )
1474
1475 /**
1476 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1477 * or low in function of ADC resolution, when ADC resolution is
1478 * different of 12 bits.
1479 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1480 * Example, with a ADC resolution of 8 bits, to set the value of
1481 * analog watchdog threshold high (on 8 bits):
1482 * LL_ADC_SetAnalogWDThresholds
1483 * (< ADCx param >,
1484 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1485 * );
1486 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1487 * @arg @ref LL_ADC_RESOLUTION_12B
1488 * @arg @ref LL_ADC_RESOLUTION_10B
1489 * @arg @ref LL_ADC_RESOLUTION_8B
1490 * @arg @ref LL_ADC_RESOLUTION_6B
1491 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1492 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1493 */
1494 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1495 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1496
1497 /**
1498 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1499 * or low in function of ADC resolution, when ADC resolution is
1500 * different of 12 bits.
1501 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1502 * Example, with a ADC resolution of 8 bits, to get the value of
1503 * analog watchdog threshold high (on 8 bits):
1504 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1505 * (LL_ADC_RESOLUTION_8B,
1506 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1507 * );
1508 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1509 * @arg @ref LL_ADC_RESOLUTION_12B
1510 * @arg @ref LL_ADC_RESOLUTION_10B
1511 * @arg @ref LL_ADC_RESOLUTION_8B
1512 * @arg @ref LL_ADC_RESOLUTION_6B
1513 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1514 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1515 */
1516 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1517 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1518
1519 #if defined(ADC_MULTIMODE_SUPPORT)
1520 /**
1521 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1522 * or ADC slave from raw value with both ADC conversion data concatenated.
1523 * @note This macro is intended to be used when multimode transfer by DMA
1524 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1525 * In this case the transferred data need to processed with this macro
1526 * to separate the conversion data of ADC master and ADC slave.
1527 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1528 * @arg @ref LL_ADC_MULTI_MASTER
1529 * @arg @ref LL_ADC_MULTI_SLAVE
1530 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1531 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1532 */
1533 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1534 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1535 #endif
1536
1537 /**
1538 * @brief Helper macro to select the ADC common instance
1539 * to which is belonging the selected ADC instance.
1540 * @note ADC common register instance can be used for:
1541 * - Set parameters common to several ADC instances
1542 * - Multimode (for devices with several ADC instances)
1543 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1544 * @param __ADCx__ ADC instance
1545 * @retval ADC common register instance
1546 */
1547 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1548 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1549 (ADC123_COMMON)
1550 #elif defined(ADC1) && defined(ADC2)
1551 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1552 (ADC12_COMMON)
1553 #else
1554 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1555 (ADC1_COMMON)
1556 #endif
1557
1558 /**
1559 * @brief Helper macro to check if all ADC instances sharing the same
1560 * ADC common instance are disabled.
1561 * @note This check is required by functions with setting conditioned to
1562 * ADC state:
1563 * All ADC instances of the ADC common group must be disabled.
1564 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1565 * @note On devices with only 1 ADC common instance, parameter of this macro
1566 * is useless and can be ignored (parameter kept for compatibility
1567 * with devices featuring several ADC common instances).
1568 * @param __ADCXY_COMMON__ ADC common instance
1569 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1570 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1571 * are disabled.
1572 * Value "1" if at least one ADC instance sharing the same ADC common instance
1573 * is enabled.
1574 */
1575 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1576 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1577 (LL_ADC_IsEnabled(ADC1) | \
1578 LL_ADC_IsEnabled(ADC2) | \
1579 LL_ADC_IsEnabled(ADC3) )
1580 #elif defined(ADC1) && defined(ADC2)
1581 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1582 (LL_ADC_IsEnabled(ADC1) | \
1583 LL_ADC_IsEnabled(ADC2) )
1584 #else
1585 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1586 (LL_ADC_IsEnabled(ADC1))
1587 #endif
1588
1589 /**
1590 * @brief Helper macro to define the ADC conversion data full-scale digital
1591 * value corresponding to the selected ADC resolution.
1592 * @note ADC conversion data full-scale corresponds to voltage range
1593 * determined by analog voltage references Vref+ and Vref-
1594 * (refer to reference manual).
1595 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1596 * @arg @ref LL_ADC_RESOLUTION_12B
1597 * @arg @ref LL_ADC_RESOLUTION_10B
1598 * @arg @ref LL_ADC_RESOLUTION_8B
1599 * @arg @ref LL_ADC_RESOLUTION_6B
1600 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1601 */
1602 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1603 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))
1604
1605 /**
1606 * @brief Helper macro to convert the ADC conversion data from
1607 * a resolution to another resolution.
1608 * @param __DATA__ ADC conversion data to be converted
1609 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1610 * This parameter can be one of the following values:
1611 * @arg @ref LL_ADC_RESOLUTION_12B
1612 * @arg @ref LL_ADC_RESOLUTION_10B
1613 * @arg @ref LL_ADC_RESOLUTION_8B
1614 * @arg @ref LL_ADC_RESOLUTION_6B
1615 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1616 * This parameter can be one of the following values:
1617 * @arg @ref LL_ADC_RESOLUTION_12B
1618 * @arg @ref LL_ADC_RESOLUTION_10B
1619 * @arg @ref LL_ADC_RESOLUTION_8B
1620 * @arg @ref LL_ADC_RESOLUTION_6B
1621 * @retval ADC conversion data to the requested resolution
1622 */
1623 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1624 (((__DATA__) \
1625 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \
1626 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \
1627 )
1628
1629 /**
1630 * @brief Helper macro to calculate the voltage (unit: mVolt)
1631 * corresponding to a ADC conversion data (unit: digital value).
1632 * @note Analog reference voltage (Vref+) must be either known from
1633 * user board environment or can be calculated using ADC measurement
1634 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1635 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1636 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1637 * (unit: digital value).
1638 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1639 * @arg @ref LL_ADC_RESOLUTION_12B
1640 * @arg @ref LL_ADC_RESOLUTION_10B
1641 * @arg @ref LL_ADC_RESOLUTION_8B
1642 * @arg @ref LL_ADC_RESOLUTION_6B
1643 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1644 */
1645 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1646 __ADC_DATA__,\
1647 __ADC_RESOLUTION__) \
1648 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1649 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1650 )
1651
1652 /**
1653 * @brief Helper macro to calculate analog reference voltage (Vref+)
1654 * (unit: mVolt) from ADC conversion data of internal voltage
1655 * reference VrefInt.
1656 * @note Computation is using VrefInt calibration value
1657 * stored in system memory for each device during production.
1658 * @note This voltage depends on user board environment: voltage level
1659 * connected to pin Vref+.
1660 * On devices with small package, the pin Vref+ is not present
1661 * and internally bonded to pin Vdda.
1662 * @note On this STM32 series, calibration data of internal voltage reference
1663 * VrefInt corresponds to a resolution of 12 bits,
1664 * this is the recommended ADC resolution to convert voltage of
1665 * internal voltage reference VrefInt.
1666 * Otherwise, this macro performs the processing to scale
1667 * ADC conversion data to 12 bits.
1668 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1669 * of internal voltage reference VrefInt (unit: digital value).
1670 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1671 * @arg @ref LL_ADC_RESOLUTION_12B
1672 * @arg @ref LL_ADC_RESOLUTION_10B
1673 * @arg @ref LL_ADC_RESOLUTION_8B
1674 * @arg @ref LL_ADC_RESOLUTION_6B
1675 * @retval Analog reference voltage (unit: mV)
1676 */
1677 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1678 __ADC_RESOLUTION__) \
1679 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1680 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1681 (__ADC_RESOLUTION__), \
1682 LL_ADC_RESOLUTION_12B))
1683
1684 /* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */
1685 /* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
1686 /* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */
1687 #if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx)
1688 /**
1689 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1690 * from ADC conversion data of internal temperature sensor.
1691 * @note Computation is using temperature sensor calibration values
1692 * stored in system memory for each device during production.
1693 * @note Calculation formula:
1694 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1695 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1696 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1697 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1698 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1699 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1700 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1701 * TEMP_DEGC_CAL1 (calibrated in factory)
1702 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1703 * TEMP_DEGC_CAL2 (calibrated in factory)
1704 * Caution: Calculation relevancy under reserve that calibration
1705 * parameters are correct (address and data).
1706 * To calculate temperature using temperature sensor
1707 * datasheet typical values (generic values less, therefore
1708 * less accurate than calibrated values),
1709 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1710 * @note As calculation input, the analog reference voltage (Vref+) must be
1711 * defined as it impacts the ADC LSB equivalent voltage.
1712 * @note Analog reference voltage (Vref+) must be either known from
1713 * user board environment or can be calculated using ADC measurement
1714 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1715 * @note On this STM32 series, calibration data of temperature sensor
1716 * corresponds to a resolution of 12 bits,
1717 * this is the recommended ADC resolution to convert voltage of
1718 * temperature sensor.
1719 * Otherwise, this macro performs the processing to scale
1720 * ADC conversion data to 12 bits.
1721 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)
1722 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1723 * temperature sensor (unit: digital value).
1724 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1725 * sensor voltage has been measured.
1726 * This parameter can be one of the following values:
1727 * @arg @ref LL_ADC_RESOLUTION_12B
1728 * @arg @ref LL_ADC_RESOLUTION_10B
1729 * @arg @ref LL_ADC_RESOLUTION_8B
1730 * @arg @ref LL_ADC_RESOLUTION_6B
1731 * @retval Temperature (unit: degree Celsius)
1732 */
1733 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1734 __TEMPSENSOR_ADC_DATA__,\
1735 __ADC_RESOLUTION__) \
1736 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1737 (__ADC_RESOLUTION__), \
1738 LL_ADC_RESOLUTION_12B) \
1739 * (__VREFANALOG_VOLTAGE__)) \
1740 / TEMPSENSOR_CAL_VREFANALOG) \
1741 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1742 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1743 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1744 ) + TEMPSENSOR_CAL1_TEMP \
1745 )
1746 #endif
1747
1748 /**
1749 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1750 * from ADC conversion data of internal temperature sensor.
1751 * @note Computation is using temperature sensor typical values
1752 * (refer to device datasheet).
1753 * @note Calculation formula:
1754 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1755 * / Avg_Slope + CALx_TEMP
1756 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1757 * (unit: digital value)
1758 * Avg_Slope = temperature sensor slope
1759 * (unit: uV/Degree Celsius)
1760 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1761 * temperature CALx_TEMP (unit: mV)
1762 * Caution: Calculation relevancy under reserve the temperature sensor
1763 * of the current device has characteristics in line with
1764 * datasheet typical values.
1765 * If temperature sensor calibration values are available on
1766 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1767 * temperature calculation will be more accurate using
1768 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1769 * @note As calculation input, the analog reference voltage (Vref+) must be
1770 * defined as it impacts the ADC LSB equivalent voltage.
1771 * @note Analog reference voltage (Vref+) must be either known from
1772 * user board environment or can be calculated using ADC measurement
1773 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1774 * @note ADC measurement data must correspond to a resolution of 12bits
1775 * (full scale digital value 4095). If not the case, the data must be
1776 * preliminarily rescaled to an equivalent resolution of 12 bits.
1777 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).
1778 * On STM32F4, refer to device datasheet parameter "Avg_Slope".
1779 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).
1780 * On STM32F4, refer to device datasheet parameter "V25".
1781 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)
1782 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV)
1783 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value).
1784 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1785 * This parameter can be one of the following values:
1786 * @arg @ref LL_ADC_RESOLUTION_12B
1787 * @arg @ref LL_ADC_RESOLUTION_10B
1788 * @arg @ref LL_ADC_RESOLUTION_8B
1789 * @arg @ref LL_ADC_RESOLUTION_6B
1790 * @retval Temperature (unit: degree Celsius)
1791 */
1792 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1793 __TEMPSENSOR_TYP_CALX_V__,\
1794 __TEMPSENSOR_CALX_TEMP__,\
1795 __VREFANALOG_VOLTAGE__,\
1796 __TEMPSENSOR_ADC_DATA__,\
1797 __ADC_RESOLUTION__) \
1798 ((( ( \
1799 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1800 * 1000) \
1801 - \
1802 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1803 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1804 * 1000) \
1805 ) \
1806 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1807 ) + (__TEMPSENSOR_CALX_TEMP__) \
1808 )
1809
1810 /**
1811 * @}
1812 */
1813
1814 /**
1815 * @}
1816 */
1817
1818
1819 /* Exported functions --------------------------------------------------------*/
1820 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1821 * @{
1822 */
1823
1824 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1825 * @{
1826 */
1827 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1828 /* configuration of ADC instance, groups and multimode (if available): */
1829 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1830
1831 /**
1832 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1833 * ADC register address from ADC instance and a list of ADC registers
1834 * intended to be used (most commonly) with DMA transfer.
1835 * @note These ADC registers are data registers:
1836 * when ADC conversion data is available in ADC data registers,
1837 * ADC generates a DMA transfer request.
1838 * @note This macro is intended to be used with LL DMA driver, refer to
1839 * function "LL_DMA_ConfigAddresses()".
1840 * Example:
1841 * LL_DMA_ConfigAddresses(DMA1,
1842 * LL_DMA_CHANNEL_1,
1843 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1844 * (uint32_t)&< array or variable >,
1845 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1846 * @note For devices with several ADC: in multimode, some devices
1847 * use a different data register outside of ADC instance scope
1848 * (common data register). This macro manages this register difference,
1849 * only ADC instance has to be set as parameter.
1850 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
1851 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
1852 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
1853 * @param ADCx ADC instance
1854 * @param Register This parameter can be one of the following values:
1855 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1856 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1857 *
1858 * (1) Available on devices with several ADC instances.
1859 * @retval ADC register address
1860 */
1861 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(const ADC_TypeDef * ADCx,uint32_t Register)1862 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
1863 {
1864 uint32_t data_reg_addr = 0UL;
1865
1866 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1867 {
1868 /* Retrieve address of register DR */
1869 data_reg_addr = (uint32_t) & (ADCx->DR);
1870 }
1871 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1872 {
1873 /* Retrieve address of register CDR */
1874 data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1875 }
1876
1877 return data_reg_addr;
1878 }
1879 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1880 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1881 {
1882 /* Prevent unused argument compilation warning */
1883 (void)Register;
1884
1885 /* Retrieve address of register DR */
1886 return (uint32_t) & (ADCx->DR);
1887 }
1888 #endif
1889
1890 /**
1891 * @}
1892 */
1893
1894 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1895 * @{
1896 */
1897
1898 /**
1899 * @brief Set parameter common to several ADC: Clock source and prescaler.
1900 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
1901 * @param ADCxy_COMMON ADC common instance
1902 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1903 * @param CommonClock This parameter can be one of the following values:
1904 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1905 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1906 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1907 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1908 * @retval None
1909 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1910 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1911 {
1912 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1913 }
1914
1915 /**
1916 * @brief Get parameter common to several ADC: Clock source and prescaler.
1917 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
1918 * @param ADCxy_COMMON ADC common instance
1919 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1920 * @retval Returned value can be one of the following values:
1921 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1922 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1923 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
1924 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
1925 */
LL_ADC_GetCommonClock(const ADC_Common_TypeDef * ADCxy_COMMON)1926 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
1927 {
1928 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1929 }
1930
1931 /**
1932 * @brief Set parameter common to several ADC: measurement path to internal
1933 * channels (VrefInt, temperature sensor, ...).
1934 * @note One or several values can be selected.
1935 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1936 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1937 * @note Stabilization time of measurement path to internal channel:
1938 * After enabling internal paths, before starting ADC conversion,
1939 * a delay is required for internal voltage reference and
1940 * temperature sensor stabilization time.
1941 * Refer to device datasheet.
1942 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1943 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1944 * @note ADC internal channel sampling time constraint:
1945 * For ADC conversion of internal channels,
1946 * a sampling time minimum value is required.
1947 * Refer to device datasheet.
1948 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
1949 * CCR VBATE LL_ADC_SetCommonPathInternalCh
1950 * @param ADCxy_COMMON ADC common instance
1951 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1952 * @param PathInternal This parameter can be a combination of the following values:
1953 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1954 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1955 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1956 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1957 * @retval None
1958 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1959 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1960 {
1961 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1962 }
1963
1964 /**
1965 * @brief Get parameter common to several ADC: measurement path to internal
1966 * channels (VrefInt, temperature sensor, ...).
1967 * @note One or several values can be selected.
1968 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1969 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1970 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
1971 * CCR VBATE LL_ADC_GetCommonPathInternalCh
1972 * @param ADCxy_COMMON ADC common instance
1973 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1974 * @retval Returned value can be a combination of the following values:
1975 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1976 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1977 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1978 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1979 */
LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef * ADCxy_COMMON)1980 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
1981 {
1982 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1983 }
1984
1985 /**
1986 * @}
1987 */
1988
1989 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1990 * @{
1991 */
1992
1993 /**
1994 * @brief Set ADC resolution.
1995 * Refer to reference manual for alignments formats
1996 * dependencies to ADC resolutions.
1997 * @rmtoll CR1 RES LL_ADC_SetResolution
1998 * @param ADCx ADC instance
1999 * @param Resolution This parameter can be one of the following values:
2000 * @arg @ref LL_ADC_RESOLUTION_12B
2001 * @arg @ref LL_ADC_RESOLUTION_10B
2002 * @arg @ref LL_ADC_RESOLUTION_8B
2003 * @arg @ref LL_ADC_RESOLUTION_6B
2004 * @retval None
2005 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2006 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2007 {
2008 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
2009 }
2010
2011 /**
2012 * @brief Get ADC resolution.
2013 * Refer to reference manual for alignments formats
2014 * dependencies to ADC resolutions.
2015 * @rmtoll CR1 RES LL_ADC_GetResolution
2016 * @param ADCx ADC instance
2017 * @retval Returned value can be one of the following values:
2018 * @arg @ref LL_ADC_RESOLUTION_12B
2019 * @arg @ref LL_ADC_RESOLUTION_10B
2020 * @arg @ref LL_ADC_RESOLUTION_8B
2021 * @arg @ref LL_ADC_RESOLUTION_6B
2022 */
LL_ADC_GetResolution(const ADC_TypeDef * ADCx)2023 __STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2024 {
2025 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
2026 }
2027
2028 /**
2029 * @brief Set ADC conversion data alignment.
2030 * @note Refer to reference manual for alignments formats
2031 * dependencies to ADC resolutions.
2032 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2033 * @param ADCx ADC instance
2034 * @param DataAlignment This parameter can be one of the following values:
2035 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2036 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2037 * @retval None
2038 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2039 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2040 {
2041 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2042 }
2043
2044 /**
2045 * @brief Get ADC conversion data alignment.
2046 * @note Refer to reference manual for alignments formats
2047 * dependencies to ADC resolutions.
2048 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2049 * @param ADCx ADC instance
2050 * @retval Returned value can be one of the following values:
2051 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2052 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2053 */
LL_ADC_GetDataAlignment(const ADC_TypeDef * ADCx)2054 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2055 {
2056 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2057 }
2058
2059 /**
2060 * @brief Set ADC sequencers scan mode, for all ADC groups
2061 * (group regular, group injected).
2062 * @note According to sequencers scan mode :
2063 * - If disabled: ADC conversion is performed in unitary conversion
2064 * mode (one channel converted, that defined in rank 1).
2065 * Configuration of sequencers of all ADC groups
2066 * (sequencer scan length, ...) is discarded: equivalent to
2067 * scan length of 1 rank.
2068 * - If enabled: ADC conversions are performed in sequence conversions
2069 * mode, according to configuration of sequencers of
2070 * each ADC group (sequencer scan length, ...).
2071 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2072 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2073 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
2074 * @param ADCx ADC instance
2075 * @param ScanMode This parameter can be one of the following values:
2076 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2077 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2078 * @retval None
2079 */
LL_ADC_SetSequencersScanMode(ADC_TypeDef * ADCx,uint32_t ScanMode)2080 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2081 {
2082 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2083 }
2084
2085 /**
2086 * @brief Get ADC sequencers scan mode, for all ADC groups
2087 * (group regular, group injected).
2088 * @note According to sequencers scan mode :
2089 * - If disabled: ADC conversion is performed in unitary conversion
2090 * mode (one channel converted, that defined in rank 1).
2091 * Configuration of sequencers of all ADC groups
2092 * (sequencer scan length, ...) is discarded: equivalent to
2093 * scan length of 1 rank.
2094 * - If enabled: ADC conversions are performed in sequence conversions
2095 * mode, according to configuration of sequencers of
2096 * each ADC group (sequencer scan length, ...).
2097 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2098 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2099 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2100 * @param ADCx ADC instance
2101 * @retval Returned value can be one of the following values:
2102 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2103 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2104 */
LL_ADC_GetSequencersScanMode(const ADC_TypeDef * ADCx)2105 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(const ADC_TypeDef *ADCx)
2106 {
2107 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2108 }
2109
2110 /**
2111 * @}
2112 */
2113
2114 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2115 * @{
2116 */
2117
2118 /**
2119 * @brief Set ADC group regular conversion trigger source:
2120 * internal (SW start) or from external IP (timer event,
2121 * external interrupt line).
2122 * @note On this STM32 series, setting of external trigger edge is performed
2123 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2124 * @note Availability of parameters of trigger sources from timer
2125 * depends on timers availability on the selected device.
2126 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2127 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2128 * @param ADCx ADC instance
2129 * @param TriggerSource This parameter can be one of the following values:
2130 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2131 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2132 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2133 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2134 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2135 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2136 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2137 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2138 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2139 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2140 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2141 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2142 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2143 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2144 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2145 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2146 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2147 * @retval None
2148 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2149 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2150 {
2151 /* Note: On this STM32 series, ADC group regular external trigger edge */
2152 /* is used to perform a ADC conversion start. */
2153 /* This function does not set external trigger edge. */
2154 /* This feature is set using function */
2155 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2156 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2157 }
2158
2159 /**
2160 * @brief Get ADC group regular conversion trigger source:
2161 * internal (SW start) or from external IP (timer event,
2162 * external interrupt line).
2163 * @note To determine whether group regular trigger source is
2164 * internal (SW start) or external, without detail
2165 * of which peripheral is selected as external trigger,
2166 * (equivalent to
2167 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2168 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2169 * @note Availability of parameters of trigger sources from timer
2170 * depends on timers availability on the selected device.
2171 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2172 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2173 * @param ADCx ADC instance
2174 * @retval Returned value can be one of the following values:
2175 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2176 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
2177 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
2178 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
2179 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2180 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2181 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2182 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2183 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2184 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2185 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2186 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1
2187 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2
2188 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3
2189 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1
2190 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
2191 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2192 */
LL_ADC_REG_GetTriggerSource(const ADC_TypeDef * ADCx)2193 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
2194 {
2195 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2196
2197 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2198 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2199 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2200
2201 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2202 /* to match with triggers literals definition. */
2203 return ((TriggerSource
2204 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2205 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2206 );
2207 }
2208
2209 /**
2210 * @brief Get ADC group regular conversion trigger source internal (SW start)
2211 or external.
2212 * @note In case of group regular trigger source set to external trigger,
2213 * to determine which peripheral is selected as external trigger,
2214 * use function @ref LL_ADC_REG_GetTriggerSource().
2215 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2216 * @param ADCx ADC instance
2217 * @retval Value "0" if trigger source external trigger
2218 * Value "1" if trigger source SW start.
2219 */
LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)2220 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2221 {
2222 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2223 }
2224
2225 /**
2226 * @brief Get ADC group regular conversion trigger polarity.
2227 * @note Applicable only for trigger source set to external trigger.
2228 * @note On this STM32 series, setting of external trigger edge is performed
2229 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2230 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2231 * @param ADCx ADC instance
2232 * @retval Returned value can be one of the following values:
2233 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2234 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2235 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2236 */
LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef * ADCx)2237 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
2238 {
2239 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2240 }
2241
2242
2243 /**
2244 * @brief Set ADC group regular sequencer length and scan direction.
2245 * @note Description of ADC group regular sequencer features:
2246 * - For devices with sequencer fully configurable
2247 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2248 * sequencer length and each rank affectation to a channel
2249 * are configurable.
2250 * This function performs configuration of:
2251 * - Sequence length: Number of ranks in the scan sequence.
2252 * - Sequence direction: Unless specified in parameters, sequencer
2253 * scan direction is forward (from rank 1 to rank n).
2254 * Sequencer ranks are selected using
2255 * function "LL_ADC_REG_SetSequencerRanks()".
2256 * - For devices with sequencer not fully configurable
2257 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2258 * sequencer length and each rank affectation to a channel
2259 * are defined by channel number.
2260 * This function performs configuration of:
2261 * - Sequence length: Number of ranks in the scan sequence is
2262 * defined by number of channels set in the sequence,
2263 * rank of each channel is fixed by channel HW number.
2264 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2265 * - Sequence direction: Unless specified in parameters, sequencer
2266 * scan direction is forward (from lowest channel number to
2267 * highest channel number).
2268 * Sequencer ranks are selected using
2269 * function "LL_ADC_REG_SetSequencerChannels()".
2270 * @note On this STM32 series, group regular sequencer configuration
2271 * is conditioned to ADC instance sequencer mode.
2272 * If ADC instance sequencer mode is disabled, sequencers of
2273 * all groups (group regular, group injected) can be configured
2274 * but their execution is disabled (limited to rank 1).
2275 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2276 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2277 * ADC conversion on only 1 channel.
2278 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2279 * @param ADCx ADC instance
2280 * @param SequencerNbRanks This parameter can be one of the following values:
2281 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2282 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2283 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2284 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2285 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2286 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2287 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2288 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2289 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2290 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2291 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2292 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2293 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2294 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2295 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2296 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2297 * @retval None
2298 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2299 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2300 {
2301 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2302 }
2303
2304 /**
2305 * @brief Get ADC group regular sequencer length and scan direction.
2306 * @note Description of ADC group regular sequencer features:
2307 * - For devices with sequencer fully configurable
2308 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2309 * sequencer length and each rank affectation to a channel
2310 * are configurable.
2311 * This function retrieves:
2312 * - Sequence length: Number of ranks in the scan sequence.
2313 * - Sequence direction: Unless specified in parameters, sequencer
2314 * scan direction is forward (from rank 1 to rank n).
2315 * Sequencer ranks are selected using
2316 * function "LL_ADC_REG_SetSequencerRanks()".
2317 * - For devices with sequencer not fully configurable
2318 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2319 * sequencer length and each rank affectation to a channel
2320 * are defined by channel number.
2321 * This function retrieves:
2322 * - Sequence length: Number of ranks in the scan sequence is
2323 * defined by number of channels set in the sequence,
2324 * rank of each channel is fixed by channel HW number.
2325 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2326 * - Sequence direction: Unless specified in parameters, sequencer
2327 * scan direction is forward (from lowest channel number to
2328 * highest channel number).
2329 * Sequencer ranks are selected using
2330 * function "LL_ADC_REG_SetSequencerChannels()".
2331 * @note On this STM32 series, group regular sequencer configuration
2332 * is conditioned to ADC instance sequencer mode.
2333 * If ADC instance sequencer mode is disabled, sequencers of
2334 * all groups (group regular, group injected) can be configured
2335 * but their execution is disabled (limited to rank 1).
2336 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2337 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2338 * ADC conversion on only 1 channel.
2339 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2340 * @param ADCx ADC instance
2341 * @retval Returned value can be one of the following values:
2342 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2343 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2344 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2345 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2346 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2347 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2348 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2349 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2350 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2351 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2352 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2353 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2354 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2355 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2356 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2357 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2358 */
LL_ADC_REG_GetSequencerLength(const ADC_TypeDef * ADCx)2359 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
2360 {
2361 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2362 }
2363
2364 /**
2365 * @brief Set ADC group regular sequencer discontinuous mode:
2366 * sequence subdivided and scan conversions interrupted every selected
2367 * number of ranks.
2368 * @note It is not possible to enable both ADC group regular
2369 * continuous mode and sequencer discontinuous mode.
2370 * @note It is not possible to enable both ADC auto-injected mode
2371 * and ADC group regular sequencer discontinuous mode.
2372 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2373 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2374 * @param ADCx ADC instance
2375 * @param SeqDiscont This parameter can be one of the following values:
2376 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2377 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2378 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2379 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2380 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2381 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2382 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2383 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2384 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2385 * @retval None
2386 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2387 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2388 {
2389 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2390 }
2391
2392 /**
2393 * @brief Get ADC group regular sequencer discontinuous mode:
2394 * sequence subdivided and scan conversions interrupted every selected
2395 * number of ranks.
2396 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2397 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2398 * @param ADCx ADC instance
2399 * @retval Returned value can be one of the following values:
2400 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2401 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2402 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2403 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2404 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2405 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2406 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2407 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2408 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2409 */
LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef * ADCx)2410 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2411 {
2412 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2413 }
2414
2415 /**
2416 * @brief Set ADC group regular sequence: channel on the selected
2417 * scan sequence rank.
2418 * @note This function performs configuration of:
2419 * - Channels ordering into each rank of scan sequence:
2420 * whatever channel can be placed into whatever rank.
2421 * @note On this STM32 series, ADC group regular sequencer is
2422 * fully configurable: sequencer length and each rank
2423 * affectation to a channel are configurable.
2424 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2425 * @note Depending on devices and packages, some channels may not be available.
2426 * Refer to device datasheet for channels availability.
2427 * @note On this STM32 series, to measure internal channels (VrefInt,
2428 * TempSensor, ...), measurement paths to internal channels must be
2429 * enabled separately.
2430 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2431 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2432 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2433 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2434 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2435 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2436 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2437 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2438 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2439 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2440 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2441 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2442 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2443 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2444 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2445 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2446 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2447 * @param ADCx ADC instance
2448 * @param Rank This parameter can be one of the following values:
2449 * @arg @ref LL_ADC_REG_RANK_1
2450 * @arg @ref LL_ADC_REG_RANK_2
2451 * @arg @ref LL_ADC_REG_RANK_3
2452 * @arg @ref LL_ADC_REG_RANK_4
2453 * @arg @ref LL_ADC_REG_RANK_5
2454 * @arg @ref LL_ADC_REG_RANK_6
2455 * @arg @ref LL_ADC_REG_RANK_7
2456 * @arg @ref LL_ADC_REG_RANK_8
2457 * @arg @ref LL_ADC_REG_RANK_9
2458 * @arg @ref LL_ADC_REG_RANK_10
2459 * @arg @ref LL_ADC_REG_RANK_11
2460 * @arg @ref LL_ADC_REG_RANK_12
2461 * @arg @ref LL_ADC_REG_RANK_13
2462 * @arg @ref LL_ADC_REG_RANK_14
2463 * @arg @ref LL_ADC_REG_RANK_15
2464 * @arg @ref LL_ADC_REG_RANK_16
2465 * @param Channel This parameter can be one of the following values:
2466 * @arg @ref LL_ADC_CHANNEL_0
2467 * @arg @ref LL_ADC_CHANNEL_1
2468 * @arg @ref LL_ADC_CHANNEL_2
2469 * @arg @ref LL_ADC_CHANNEL_3
2470 * @arg @ref LL_ADC_CHANNEL_4
2471 * @arg @ref LL_ADC_CHANNEL_5
2472 * @arg @ref LL_ADC_CHANNEL_6
2473 * @arg @ref LL_ADC_CHANNEL_7
2474 * @arg @ref LL_ADC_CHANNEL_8
2475 * @arg @ref LL_ADC_CHANNEL_9
2476 * @arg @ref LL_ADC_CHANNEL_10
2477 * @arg @ref LL_ADC_CHANNEL_11
2478 * @arg @ref LL_ADC_CHANNEL_12
2479 * @arg @ref LL_ADC_CHANNEL_13
2480 * @arg @ref LL_ADC_CHANNEL_14
2481 * @arg @ref LL_ADC_CHANNEL_15
2482 * @arg @ref LL_ADC_CHANNEL_16
2483 * @arg @ref LL_ADC_CHANNEL_17
2484 * @arg @ref LL_ADC_CHANNEL_18
2485 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2486 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2487 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2488 *
2489 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2490 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
2491 * @retval None
2492 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2493 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2494 {
2495 /* Set bits with content of parameter "Channel" with bits position */
2496 /* in register and register position depending on parameter "Rank". */
2497 /* Parameters "Rank" and "Channel" are used with masks because containing */
2498 /* other bits reserved for other purpose. */
2499 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2500
2501 MODIFY_REG(*preg,
2502 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2503 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2504 }
2505
2506 /**
2507 * @brief Get ADC group regular sequence: channel on the selected
2508 * scan sequence rank.
2509 * @note On this STM32 series, ADC group regular sequencer is
2510 * fully configurable: sequencer length and each rank
2511 * affectation to a channel are configurable.
2512 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2513 * @note Depending on devices and packages, some channels may not be available.
2514 * Refer to device datasheet for channels availability.
2515 * @note Usage of the returned channel number:
2516 * - To reinject this channel into another function LL_ADC_xxx:
2517 * the returned channel number is only partly formatted on definition
2518 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2519 * with parts of literals LL_ADC_CHANNEL_x or using
2520 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2521 * Then the selected literal LL_ADC_CHANNEL_x can be used
2522 * as parameter for another function.
2523 * - To get the channel number in decimal format:
2524 * process the returned value with the helper macro
2525 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2526 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2527 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2528 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2529 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2530 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2531 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2532 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2533 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2534 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2535 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2536 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2537 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2538 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2539 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2540 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2541 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2542 * @param ADCx ADC instance
2543 * @param Rank This parameter can be one of the following values:
2544 * @arg @ref LL_ADC_REG_RANK_1
2545 * @arg @ref LL_ADC_REG_RANK_2
2546 * @arg @ref LL_ADC_REG_RANK_3
2547 * @arg @ref LL_ADC_REG_RANK_4
2548 * @arg @ref LL_ADC_REG_RANK_5
2549 * @arg @ref LL_ADC_REG_RANK_6
2550 * @arg @ref LL_ADC_REG_RANK_7
2551 * @arg @ref LL_ADC_REG_RANK_8
2552 * @arg @ref LL_ADC_REG_RANK_9
2553 * @arg @ref LL_ADC_REG_RANK_10
2554 * @arg @ref LL_ADC_REG_RANK_11
2555 * @arg @ref LL_ADC_REG_RANK_12
2556 * @arg @ref LL_ADC_REG_RANK_13
2557 * @arg @ref LL_ADC_REG_RANK_14
2558 * @arg @ref LL_ADC_REG_RANK_15
2559 * @arg @ref LL_ADC_REG_RANK_16
2560 * @retval Returned value can be one of the following values:
2561 * @arg @ref LL_ADC_CHANNEL_0
2562 * @arg @ref LL_ADC_CHANNEL_1
2563 * @arg @ref LL_ADC_CHANNEL_2
2564 * @arg @ref LL_ADC_CHANNEL_3
2565 * @arg @ref LL_ADC_CHANNEL_4
2566 * @arg @ref LL_ADC_CHANNEL_5
2567 * @arg @ref LL_ADC_CHANNEL_6
2568 * @arg @ref LL_ADC_CHANNEL_7
2569 * @arg @ref LL_ADC_CHANNEL_8
2570 * @arg @ref LL_ADC_CHANNEL_9
2571 * @arg @ref LL_ADC_CHANNEL_10
2572 * @arg @ref LL_ADC_CHANNEL_11
2573 * @arg @ref LL_ADC_CHANNEL_12
2574 * @arg @ref LL_ADC_CHANNEL_13
2575 * @arg @ref LL_ADC_CHANNEL_14
2576 * @arg @ref LL_ADC_CHANNEL_15
2577 * @arg @ref LL_ADC_CHANNEL_16
2578 * @arg @ref LL_ADC_CHANNEL_17
2579 * @arg @ref LL_ADC_CHANNEL_18
2580 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2581 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
2582 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
2583 *
2584 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
2585 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
2586 * (1) For ADC channel read back from ADC register,
2587 * comparison with internal channel parameter to be done
2588 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2589 */
LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)2590 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
2591 {
2592 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2593
2594 return (uint32_t)(READ_BIT(*preg,
2595 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2596 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2597 );
2598 }
2599
2600 /**
2601 * @brief Set ADC continuous conversion mode on ADC group regular.
2602 * @note Description of ADC continuous conversion mode:
2603 * - single mode: one conversion per trigger
2604 * - continuous mode: after the first trigger, following
2605 * conversions launched successively automatically.
2606 * @note It is not possible to enable both ADC group regular
2607 * continuous mode and sequencer discontinuous mode.
2608 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2609 * @param ADCx ADC instance
2610 * @param Continuous This parameter can be one of the following values:
2611 * @arg @ref LL_ADC_REG_CONV_SINGLE
2612 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2613 * @retval None
2614 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)2615 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2616 {
2617 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2618 }
2619
2620 /**
2621 * @brief Get ADC continuous conversion mode on ADC group regular.
2622 * @note Description of ADC continuous conversion mode:
2623 * - single mode: one conversion per trigger
2624 * - continuous mode: after the first trigger, following
2625 * conversions launched successively automatically.
2626 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2627 * @param ADCx ADC instance
2628 * @retval Returned value can be one of the following values:
2629 * @arg @ref LL_ADC_REG_CONV_SINGLE
2630 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2631 */
LL_ADC_REG_GetContinuousMode(const ADC_TypeDef * ADCx)2632 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
2633 {
2634 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2635 }
2636
2637 /**
2638 * @brief Set ADC group regular conversion data transfer: no transfer or
2639 * transfer by DMA, and DMA requests mode.
2640 * @note If transfer by DMA selected, specifies the DMA requests
2641 * mode:
2642 * - Limited mode (One shot mode): DMA transfer requests are stopped
2643 * when number of DMA data transfers (number of
2644 * ADC conversions) is reached.
2645 * This ADC mode is intended to be used with DMA mode non-circular.
2646 * - Unlimited mode: DMA transfer requests are unlimited,
2647 * whatever number of DMA data transfers (number of
2648 * ADC conversions).
2649 * This ADC mode is intended to be used with DMA mode circular.
2650 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2651 * mode non-circular:
2652 * when DMA transfers size will be reached, DMA will stop transfers of
2653 * ADC conversions data ADC will raise an overrun error
2654 * (overrun flag and interruption if enabled).
2655 * @note For devices with several ADC instances: ADC multimode DMA
2656 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
2657 * @note To configure DMA source address (peripheral address),
2658 * use function @ref LL_ADC_DMA_GetRegAddr().
2659 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
2660 * CR2 DDS LL_ADC_REG_SetDMATransfer
2661 * @param ADCx ADC instance
2662 * @param DMATransfer This parameter can be one of the following values:
2663 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2664 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2665 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2666 * @retval None
2667 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)2668 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2669 {
2670 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2671 }
2672
2673 /**
2674 * @brief Get ADC group regular conversion data transfer: no transfer or
2675 * transfer by DMA, and DMA requests mode.
2676 * @note If transfer by DMA selected, specifies the DMA requests
2677 * mode:
2678 * - Limited mode (One shot mode): DMA transfer requests are stopped
2679 * when number of DMA data transfers (number of
2680 * ADC conversions) is reached.
2681 * This ADC mode is intended to be used with DMA mode non-circular.
2682 * - Unlimited mode: DMA transfer requests are unlimited,
2683 * whatever number of DMA data transfers (number of
2684 * ADC conversions).
2685 * This ADC mode is intended to be used with DMA mode circular.
2686 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2687 * mode non-circular:
2688 * when DMA transfers size will be reached, DMA will stop transfers of
2689 * ADC conversions data ADC will raise an overrun error
2690 * (overrun flag and interruption if enabled).
2691 * @note For devices with several ADC instances: ADC multimode DMA
2692 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
2693 * @note To configure DMA source address (peripheral address),
2694 * use function @ref LL_ADC_DMA_GetRegAddr().
2695 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
2696 * CR2 DDS LL_ADC_REG_GetDMATransfer
2697 * @param ADCx ADC instance
2698 * @retval Returned value can be one of the following values:
2699 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2700 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
2701 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2702 */
LL_ADC_REG_GetDMATransfer(const ADC_TypeDef * ADCx)2703 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
2704 {
2705 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2706 }
2707
2708 /**
2709 * @brief Specify which ADC flag between EOC (end of unitary conversion)
2710 * or EOS (end of sequence conversions) is used to indicate
2711 * the end of conversion.
2712 * @note This feature is aimed to be set when using ADC with
2713 * programming model by polling or interruption
2714 * (programming model by DMA usually uses DMA interruptions
2715 * to indicate end of conversion and data transfer).
2716 * @note For ADC group injected, end of conversion (flag&IT) is raised
2717 * only at the end of the sequence.
2718 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
2719 * @param ADCx ADC instance
2720 * @param EocSelection This parameter can be one of the following values:
2721 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2722 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2723 * @retval None
2724 */
LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef * ADCx,uint32_t EocSelection)2725 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2726 {
2727 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2728 }
2729
2730 /**
2731 * @brief Get which ADC flag between EOC (end of unitary conversion)
2732 * or EOS (end of sequence conversions) is used to indicate
2733 * the end of conversion.
2734 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
2735 * @param ADCx ADC instance
2736 * @retval Returned value can be one of the following values:
2737 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
2738 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
2739 */
LL_ADC_REG_GetFlagEndOfConversion(const ADC_TypeDef * ADCx)2740 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(const ADC_TypeDef *ADCx)
2741 {
2742 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2743 }
2744
2745 /**
2746 * @}
2747 */
2748
2749 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2750 * @{
2751 */
2752
2753 /**
2754 * @brief Set ADC group injected conversion trigger source:
2755 * internal (SW start) or from external IP (timer event,
2756 * external interrupt line).
2757 * @note On this STM32 series, setting of external trigger edge is performed
2758 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
2759 * @note Availability of parameters of trigger sources from timer
2760 * depends on timers availability on the selected device.
2761 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
2762 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
2763 * @param ADCx ADC instance
2764 * @param TriggerSource This parameter can be one of the following values:
2765 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2766 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2767 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2768 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2769 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2770 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2771 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2772 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2773 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2774 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2775 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2776 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2777 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2778 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2779 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2780 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2781 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2782 * @retval None
2783 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2784 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2785 {
2786 /* Note: On this STM32 series, ADC group injected external trigger edge */
2787 /* is used to perform a ADC conversion start. */
2788 /* This function does not set external trigger edge. */
2789 /* This feature is set using function */
2790 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2791 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2792 }
2793
2794 /**
2795 * @brief Get ADC group injected conversion trigger source:
2796 * internal (SW start) or from external IP (timer event,
2797 * external interrupt line).
2798 * @note To determine whether group injected trigger source is
2799 * internal (SW start) or external, without detail
2800 * of which peripheral is selected as external trigger,
2801 * (equivalent to
2802 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2803 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2804 * @note Availability of parameters of trigger sources from timer
2805 * depends on timers availability on the selected device.
2806 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
2807 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
2808 * @param ADCx ADC instance
2809 * @retval Returned value can be one of the following values:
2810 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2811 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
2812 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
2813 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
2814 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
2815 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2
2816 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
2817 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
2818 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
2819 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
2820 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
2821 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4
2822 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
2823 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2
2824 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3
2825 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
2826 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
2827 */
LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef * ADCx)2828 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
2829 {
2830 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2831
2832 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2833 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2834 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2835
2836 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2837 /* to match with triggers literals definition. */
2838 return ((TriggerSource
2839 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2840 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2841 );
2842 }
2843
2844 /**
2845 * @brief Get ADC group injected conversion trigger source internal (SW start)
2846 or external
2847 * @note In case of group injected trigger source set to external trigger,
2848 * to determine which peripheral is selected as external trigger,
2849 * use function @ref LL_ADC_INJ_GetTriggerSource.
2850 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
2851 * @param ADCx ADC instance
2852 * @retval Value "0" if trigger source external trigger
2853 * Value "1" if trigger source SW start.
2854 */
LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef * ADCx)2855 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2856 {
2857 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2858 }
2859
2860 /**
2861 * @brief Get ADC group injected conversion trigger polarity.
2862 * Applicable only for trigger source set to external trigger.
2863 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
2864 * @param ADCx ADC instance
2865 * @retval Returned value can be one of the following values:
2866 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
2867 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
2868 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
2869 */
LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef * ADCx)2870 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
2871 {
2872 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2873 }
2874
2875 /**
2876 * @brief Set ADC group injected sequencer length and scan direction.
2877 * @note This function performs configuration of:
2878 * - Sequence length: Number of ranks in the scan sequence.
2879 * - Sequence direction: Unless specified in parameters, sequencer
2880 * scan direction is forward (from rank 1 to rank n).
2881 * @note On this STM32 series, group injected sequencer configuration
2882 * is conditioned to ADC instance sequencer mode.
2883 * If ADC instance sequencer mode is disabled, sequencers of
2884 * all groups (group regular, group injected) can be configured
2885 * but their execution is disabled (limited to rank 1).
2886 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2887 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2888 * ADC conversion on only 1 channel.
2889 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2890 * @param ADCx ADC instance
2891 * @param SequencerNbRanks This parameter can be one of the following values:
2892 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2893 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2894 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2895 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2896 * @retval None
2897 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2898 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2899 {
2900 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2901 }
2902
2903 /**
2904 * @brief Get ADC group injected sequencer length and scan direction.
2905 * @note This function retrieves:
2906 * - Sequence length: Number of ranks in the scan sequence.
2907 * - Sequence direction: Unless specified in parameters, sequencer
2908 * scan direction is forward (from rank 1 to rank n).
2909 * @note On this STM32 series, group injected sequencer configuration
2910 * is conditioned to ADC instance sequencer mode.
2911 * If ADC instance sequencer mode is disabled, sequencers of
2912 * all groups (group regular, group injected) can be configured
2913 * but their execution is disabled (limited to rank 1).
2914 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2915 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2916 * ADC conversion on only 1 channel.
2917 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2918 * @param ADCx ADC instance
2919 * @retval Returned value can be one of the following values:
2920 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2921 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2922 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2923 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2924 */
LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef * ADCx)2925 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
2926 {
2927 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2928 }
2929
2930 /**
2931 * @brief Set ADC group injected sequencer discontinuous mode:
2932 * sequence subdivided and scan conversions interrupted every selected
2933 * number of ranks.
2934 * @note It is not possible to enable both ADC group injected
2935 * auto-injected mode and sequencer discontinuous mode.
2936 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2937 * @param ADCx ADC instance
2938 * @param SeqDiscont This parameter can be one of the following values:
2939 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2940 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2941 * @retval None
2942 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2943 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2944 {
2945 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2946 }
2947
2948 /**
2949 * @brief Get ADC group injected sequencer discontinuous mode:
2950 * sequence subdivided and scan conversions interrupted every selected
2951 * number of ranks.
2952 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2953 * @param ADCx ADC instance
2954 * @retval Returned value can be one of the following values:
2955 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2956 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2957 */
LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef * ADCx)2958 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2959 {
2960 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2961 }
2962
2963 /**
2964 * @brief Set ADC group injected sequence: channel on the selected
2965 * sequence rank.
2966 * @note Depending on devices and packages, some channels may not be available.
2967 * Refer to device datasheet for channels availability.
2968 * @note On this STM32 series, to measure internal channels (VrefInt,
2969 * TempSensor, ...), measurement paths to internal channels must be
2970 * enabled separately.
2971 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2972 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2973 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2974 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2975 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2976 * @param ADCx ADC instance
2977 * @param Rank This parameter can be one of the following values:
2978 * @arg @ref LL_ADC_INJ_RANK_1
2979 * @arg @ref LL_ADC_INJ_RANK_2
2980 * @arg @ref LL_ADC_INJ_RANK_3
2981 * @arg @ref LL_ADC_INJ_RANK_4
2982 * @param Channel This parameter can be one of the following values:
2983 * @arg @ref LL_ADC_CHANNEL_0
2984 * @arg @ref LL_ADC_CHANNEL_1
2985 * @arg @ref LL_ADC_CHANNEL_2
2986 * @arg @ref LL_ADC_CHANNEL_3
2987 * @arg @ref LL_ADC_CHANNEL_4
2988 * @arg @ref LL_ADC_CHANNEL_5
2989 * @arg @ref LL_ADC_CHANNEL_6
2990 * @arg @ref LL_ADC_CHANNEL_7
2991 * @arg @ref LL_ADC_CHANNEL_8
2992 * @arg @ref LL_ADC_CHANNEL_9
2993 * @arg @ref LL_ADC_CHANNEL_10
2994 * @arg @ref LL_ADC_CHANNEL_11
2995 * @arg @ref LL_ADC_CHANNEL_12
2996 * @arg @ref LL_ADC_CHANNEL_13
2997 * @arg @ref LL_ADC_CHANNEL_14
2998 * @arg @ref LL_ADC_CHANNEL_15
2999 * @arg @ref LL_ADC_CHANNEL_16
3000 * @arg @ref LL_ADC_CHANNEL_17
3001 * @arg @ref LL_ADC_CHANNEL_18
3002 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3003 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3004 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3005 *
3006 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3007 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3008 * @retval None
3009 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3010 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3011 {
3012 /* Set bits with content of parameter "Channel" with bits position */
3013 /* in register depending on parameter "Rank". */
3014 /* Parameters "Rank" and "Channel" are used with masks because containing */
3015 /* other bits reserved for other purpose. */
3016 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3017
3018 MODIFY_REG(ADCx->JSQR,
3019 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))),
3020 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))));
3021 }
3022
3023 /**
3024 * @brief Get ADC group injected sequence: channel on the selected
3025 * sequence rank.
3026 * @note Depending on devices and packages, some channels may not be available.
3027 * Refer to device datasheet for channels availability.
3028 * @note Usage of the returned channel number:
3029 * - To reinject this channel into another function LL_ADC_xxx:
3030 * the returned channel number is only partly formatted on definition
3031 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3032 * with parts of literals LL_ADC_CHANNEL_x or using
3033 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3034 * Then the selected literal LL_ADC_CHANNEL_x can be used
3035 * as parameter for another function.
3036 * - To get the channel number in decimal format:
3037 * process the returned value with the helper macro
3038 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3039 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
3040 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
3041 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
3042 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
3043 * @param ADCx ADC instance
3044 * @param Rank This parameter can be one of the following values:
3045 * @arg @ref LL_ADC_INJ_RANK_1
3046 * @arg @ref LL_ADC_INJ_RANK_2
3047 * @arg @ref LL_ADC_INJ_RANK_3
3048 * @arg @ref LL_ADC_INJ_RANK_4
3049 * @retval Returned value can be one of the following values:
3050 * @arg @ref LL_ADC_CHANNEL_0
3051 * @arg @ref LL_ADC_CHANNEL_1
3052 * @arg @ref LL_ADC_CHANNEL_2
3053 * @arg @ref LL_ADC_CHANNEL_3
3054 * @arg @ref LL_ADC_CHANNEL_4
3055 * @arg @ref LL_ADC_CHANNEL_5
3056 * @arg @ref LL_ADC_CHANNEL_6
3057 * @arg @ref LL_ADC_CHANNEL_7
3058 * @arg @ref LL_ADC_CHANNEL_8
3059 * @arg @ref LL_ADC_CHANNEL_9
3060 * @arg @ref LL_ADC_CHANNEL_10
3061 * @arg @ref LL_ADC_CHANNEL_11
3062 * @arg @ref LL_ADC_CHANNEL_12
3063 * @arg @ref LL_ADC_CHANNEL_13
3064 * @arg @ref LL_ADC_CHANNEL_14
3065 * @arg @ref LL_ADC_CHANNEL_15
3066 * @arg @ref LL_ADC_CHANNEL_16
3067 * @arg @ref LL_ADC_CHANNEL_17
3068 * @arg @ref LL_ADC_CHANNEL_18
3069 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3070 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3071 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3072 *
3073 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3074 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
3075 * (1) For ADC channel read back from ADC register,
3076 * comparison with internal channel parameter to be done
3077 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3078 */
LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef * ADCx,uint32_t Rank)3079 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
3080 {
3081 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3082
3083 return (uint32_t)(READ_BIT(ADCx->JSQR,
3084 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))))
3085 >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))
3086 );
3087 }
3088
3089 /**
3090 * @brief Set ADC group injected conversion trigger:
3091 * independent or from ADC group regular.
3092 * @note This mode can be used to extend number of data registers
3093 * updated after one ADC conversion trigger and with data
3094 * permanently kept (not erased by successive conversions of scan of
3095 * ADC sequencer ranks), up to 5 data registers:
3096 * 1 data register on ADC group regular, 4 data registers
3097 * on ADC group injected.
3098 * @note If ADC group injected injected trigger source is set to an
3099 * external trigger, this feature must be must be set to
3100 * independent trigger.
3101 * ADC group injected automatic trigger is compliant only with
3102 * group injected trigger source set to SW start, without any
3103 * further action on ADC group injected conversion start or stop:
3104 * in this case, ADC group injected is controlled only
3105 * from ADC group regular.
3106 * @note It is not possible to enable both ADC group injected
3107 * auto-injected mode and sequencer discontinuous mode.
3108 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3109 * @param ADCx ADC instance
3110 * @param TrigAuto This parameter can be one of the following values:
3111 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3112 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3113 * @retval None
3114 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)3115 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3116 {
3117 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3118 }
3119
3120 /**
3121 * @brief Get ADC group injected conversion trigger:
3122 * independent or from ADC group regular.
3123 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3124 * @param ADCx ADC instance
3125 * @retval Returned value can be one of the following values:
3126 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3127 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3128 */
LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef * ADCx)3129 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
3130 {
3131 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3132 }
3133
3134 /**
3135 * @brief Set ADC group injected offset.
3136 * @note It sets:
3137 * - ADC group injected rank to which the offset programmed
3138 * will be applied
3139 * - Offset level (offset to be subtracted from the raw
3140 * converted data).
3141 * Caution: Offset format is dependent to ADC resolution:
3142 * offset has to be left-aligned on bit 11, the LSB (right bits)
3143 * are set to 0.
3144 * @note Offset cannot be enabled or disabled.
3145 * To emulate offset disabled, set an offset value equal to 0.
3146 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3147 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3148 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3149 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3150 * @param ADCx ADC instance
3151 * @param Rank This parameter can be one of the following values:
3152 * @arg @ref LL_ADC_INJ_RANK_1
3153 * @arg @ref LL_ADC_INJ_RANK_2
3154 * @arg @ref LL_ADC_INJ_RANK_3
3155 * @arg @ref LL_ADC_INJ_RANK_4
3156 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3157 * @retval None
3158 */
LL_ADC_INJ_SetOffset(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t OffsetLevel)3159 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3160 {
3161 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3162
3163 MODIFY_REG(*preg,
3164 ADC_JOFR1_JOFFSET1,
3165 OffsetLevel);
3166 }
3167
3168 /**
3169 * @brief Get ADC group injected offset.
3170 * @note It gives offset level (offset to be subtracted from the raw converted data).
3171 * Caution: Offset format is dependent to ADC resolution:
3172 * offset has to be left-aligned on bit 11, the LSB (right bits)
3173 * are set to 0.
3174 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3175 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3176 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3177 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3178 * @param ADCx ADC instance
3179 * @param Rank This parameter can be one of the following values:
3180 * @arg @ref LL_ADC_INJ_RANK_1
3181 * @arg @ref LL_ADC_INJ_RANK_2
3182 * @arg @ref LL_ADC_INJ_RANK_3
3183 * @arg @ref LL_ADC_INJ_RANK_4
3184 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3185 */
LL_ADC_INJ_GetOffset(const ADC_TypeDef * ADCx,uint32_t Rank)3186 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(const ADC_TypeDef *ADCx, uint32_t Rank)
3187 {
3188 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3189
3190 return (uint32_t)(READ_BIT(*preg,
3191 ADC_JOFR1_JOFFSET1)
3192 );
3193 }
3194
3195 /**
3196 * @}
3197 */
3198
3199 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3200 * @{
3201 */
3202
3203 /**
3204 * @brief Set sampling time of the selected ADC channel
3205 * Unit: ADC clock cycles.
3206 * @note On this device, sampling time is on channel scope: independently
3207 * of channel mapped on ADC group regular or injected.
3208 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3209 * converted:
3210 * sampling time constraints must be respected (sampling time can be
3211 * adjusted in function of ADC clock frequency and sampling time
3212 * setting).
3213 * Refer to device datasheet for timings values (parameters TS_vrefint,
3214 * TS_temp, ...).
3215 * @note Conversion time is the addition of sampling time and processing time.
3216 * Refer to reference manual for ADC processing time of
3217 * this STM32 series.
3218 * @note In case of ADC conversion of internal channel (VrefInt,
3219 * temperature sensor, ...), a sampling time minimum value
3220 * is required.
3221 * Refer to device datasheet.
3222 * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
3223 * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
3224 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
3225 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
3226 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
3227 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
3228 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
3229 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
3230 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
3231 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
3232 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
3233 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
3234 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
3235 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
3236 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
3237 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
3238 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
3239 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
3240 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
3241 * @param ADCx ADC instance
3242 * @param Channel This parameter can be one of the following values:
3243 * @arg @ref LL_ADC_CHANNEL_0
3244 * @arg @ref LL_ADC_CHANNEL_1
3245 * @arg @ref LL_ADC_CHANNEL_2
3246 * @arg @ref LL_ADC_CHANNEL_3
3247 * @arg @ref LL_ADC_CHANNEL_4
3248 * @arg @ref LL_ADC_CHANNEL_5
3249 * @arg @ref LL_ADC_CHANNEL_6
3250 * @arg @ref LL_ADC_CHANNEL_7
3251 * @arg @ref LL_ADC_CHANNEL_8
3252 * @arg @ref LL_ADC_CHANNEL_9
3253 * @arg @ref LL_ADC_CHANNEL_10
3254 * @arg @ref LL_ADC_CHANNEL_11
3255 * @arg @ref LL_ADC_CHANNEL_12
3256 * @arg @ref LL_ADC_CHANNEL_13
3257 * @arg @ref LL_ADC_CHANNEL_14
3258 * @arg @ref LL_ADC_CHANNEL_15
3259 * @arg @ref LL_ADC_CHANNEL_16
3260 * @arg @ref LL_ADC_CHANNEL_17
3261 * @arg @ref LL_ADC_CHANNEL_18
3262 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3263 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3264 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3265 *
3266 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3267 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3268 * @param SamplingTime This parameter can be one of the following values:
3269 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3270 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3271 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3272 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3273 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3274 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3275 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3276 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3277 * @retval None
3278 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)3279 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3280 {
3281 /* Set bits with content of parameter "SamplingTime" with bits position */
3282 /* in register and register position depending on parameter "Channel". */
3283 /* Parameter "Channel" is used with masks because containing */
3284 /* other bits reserved for other purpose. */
3285 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3286
3287 MODIFY_REG(*preg,
3288 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3289 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3290 }
3291
3292 /**
3293 * @brief Get sampling time of the selected ADC channel
3294 * Unit: ADC clock cycles.
3295 * @note On this device, sampling time is on channel scope: independently
3296 * of channel mapped on ADC group regular or injected.
3297 * @note Conversion time is the addition of sampling time and processing time.
3298 * Refer to reference manual for ADC processing time of
3299 * this STM32 series.
3300 * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
3301 * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
3302 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
3303 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
3304 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
3305 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
3306 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
3307 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
3308 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
3309 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
3310 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
3311 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
3312 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
3313 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
3314 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
3315 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
3316 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
3317 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
3318 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
3319 * @param ADCx ADC instance
3320 * @param Channel This parameter can be one of the following values:
3321 * @arg @ref LL_ADC_CHANNEL_0
3322 * @arg @ref LL_ADC_CHANNEL_1
3323 * @arg @ref LL_ADC_CHANNEL_2
3324 * @arg @ref LL_ADC_CHANNEL_3
3325 * @arg @ref LL_ADC_CHANNEL_4
3326 * @arg @ref LL_ADC_CHANNEL_5
3327 * @arg @ref LL_ADC_CHANNEL_6
3328 * @arg @ref LL_ADC_CHANNEL_7
3329 * @arg @ref LL_ADC_CHANNEL_8
3330 * @arg @ref LL_ADC_CHANNEL_9
3331 * @arg @ref LL_ADC_CHANNEL_10
3332 * @arg @ref LL_ADC_CHANNEL_11
3333 * @arg @ref LL_ADC_CHANNEL_12
3334 * @arg @ref LL_ADC_CHANNEL_13
3335 * @arg @ref LL_ADC_CHANNEL_14
3336 * @arg @ref LL_ADC_CHANNEL_15
3337 * @arg @ref LL_ADC_CHANNEL_16
3338 * @arg @ref LL_ADC_CHANNEL_17
3339 * @arg @ref LL_ADC_CHANNEL_18
3340 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3341 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
3342 * @arg @ref LL_ADC_CHANNEL_VBAT (1)
3343 *
3344 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3345 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3346 * @retval Returned value can be one of the following values:
3347 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
3348 * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
3349 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
3350 * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
3351 * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
3352 * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
3353 * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
3354 * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
3355 */
LL_ADC_GetChannelSamplingTime(const ADC_TypeDef * ADCx,uint32_t Channel)3356 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
3357 {
3358 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3359
3360 return (uint32_t)(READ_BIT(*preg,
3361 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3362 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3363 );
3364 }
3365
3366 /**
3367 * @}
3368 */
3369
3370 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3371 * @{
3372 */
3373
3374 /**
3375 * @brief Set ADC analog watchdog monitored channels:
3376 * a single channel or all channels,
3377 * on ADC groups regular and-or injected.
3378 * @note Once monitored channels are selected, analog watchdog
3379 * is enabled.
3380 * @note In case of need to define a single channel to monitor
3381 * with analog watchdog from sequencer channel definition,
3382 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3383 * @note On this STM32 series, there is only 1 kind of analog watchdog
3384 * instance:
3385 * - AWD standard (instance AWD1):
3386 * - channels monitored: can monitor 1 channel or all channels.
3387 * - groups monitored: ADC groups regular and-or injected.
3388 * - resolution: resolution is not limited (corresponds to
3389 * ADC resolution configured).
3390 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3391 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3392 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
3393 * @param ADCx ADC instance
3394 * @param AWDChannelGroup This parameter can be one of the following values:
3395 * @arg @ref LL_ADC_AWD_DISABLE
3396 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3397 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3398 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3399 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3400 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3401 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3402 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3403 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3404 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3405 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3406 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3407 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3408 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3409 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3410 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3411 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3412 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3413 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3414 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3415 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3416 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3417 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3418 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3419 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3420 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3421 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3422 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3423 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3424 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3425 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3426 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3427 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3428 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3429 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3430 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3431 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3432 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3433 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3434 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3435 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3436 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3437 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3438 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3439 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3440 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3441 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3442 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3443 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3444 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3445 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3446 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3447 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3448 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3449 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3450 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3451 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3452 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3453 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3454 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3455 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3456 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3457 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3458 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3459 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
3460 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
3461 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
3462 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
3463 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
3464 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
3465 *
3466 * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n
3467 * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
3468 * @retval None
3469 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDChannelGroup)3470 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3471 {
3472 MODIFY_REG(ADCx->CR1,
3473 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3474 AWDChannelGroup);
3475 }
3476
3477 /**
3478 * @brief Get ADC analog watchdog monitored channel.
3479 * @note Usage of the returned channel number:
3480 * - To reinject this channel into another function LL_ADC_xxx:
3481 * the returned channel number is only partly formatted on definition
3482 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3483 * with parts of literals LL_ADC_CHANNEL_x or using
3484 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3485 * Then the selected literal LL_ADC_CHANNEL_x can be used
3486 * as parameter for another function.
3487 * - To get the channel number in decimal format:
3488 * process the returned value with the helper macro
3489 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3490 * Applicable only when the analog watchdog is set to monitor
3491 * one channel.
3492 * @note On this STM32 series, there is only 1 kind of analog watchdog
3493 * instance:
3494 * - AWD standard (instance AWD1):
3495 * - channels monitored: can monitor 1 channel or all channels.
3496 * - groups monitored: ADC groups regular and-or injected.
3497 * - resolution: resolution is not limited (corresponds to
3498 * ADC resolution configured).
3499 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3500 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3501 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3502 * @param ADCx ADC instance
3503 * @retval Returned value can be one of the following values:
3504 * @arg @ref LL_ADC_AWD_DISABLE
3505 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3506 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3507 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3508 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3509 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3510 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3511 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3512 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3513 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3514 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3515 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3516 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3517 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3518 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3519 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3520 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3521 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3522 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3523 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3524 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3525 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3526 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3527 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3528 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3529 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3530 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3531 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3532 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3533 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3534 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3535 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3536 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3537 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3538 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3539 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3540 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3541 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3542 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3543 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3544 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3545 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3546 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3547 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3548 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3549 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3550 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3551 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3552 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3553 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3554 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3555 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3556 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3557 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3558 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3559 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3560 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3561 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3562 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG
3563 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
3564 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
3565 */
LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef * ADCx)3566 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx)
3567 {
3568 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3569 }
3570
3571 /**
3572 * @brief Set ADC analog watchdog threshold value of threshold
3573 * high or low.
3574 * @note In case of ADC resolution different of 12 bits,
3575 * analog watchdog thresholds data require a specific shift.
3576 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3577 * @note On this STM32 series, there is only 1 kind of analog watchdog
3578 * instance:
3579 * - AWD standard (instance AWD1):
3580 * - channels monitored: can monitor 1 channel or all channels.
3581 * - groups monitored: ADC groups regular and-or injected.
3582 * - resolution: resolution is not limited (corresponds to
3583 * ADC resolution configured).
3584 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3585 * LTR LT LL_ADC_SetAnalogWDThresholds
3586 * @param ADCx ADC instance
3587 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3588 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3589 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3590 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3591 * @retval None
3592 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3593 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3594 {
3595 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3596
3597 MODIFY_REG(*preg,
3598 ADC_HTR_HT,
3599 AWDThresholdValue);
3600 }
3601
3602 /**
3603 * @brief Get ADC analog watchdog threshold value of threshold high or
3604 * threshold low.
3605 * @note In case of ADC resolution different of 12 bits,
3606 * analog watchdog thresholds data require a specific shift.
3607 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3608 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3609 * LTR LT LL_ADC_GetAnalogWDThresholds
3610 * @param ADCx ADC instance
3611 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3612 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3613 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3614 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3615 */
LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef * ADCx,uint32_t AWDThresholdsHighLow)3616 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3617 {
3618 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3619
3620 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3621 }
3622
3623 /**
3624 * @}
3625 */
3626
3627 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3628 * @{
3629 */
3630
3631 #if defined(ADC_MULTIMODE_SUPPORT)
3632 /**
3633 * @brief Set ADC multimode configuration to operate in independent mode
3634 * or multimode (for devices with several ADC instances).
3635 * @note If multimode configuration: the selected ADC instance is
3636 * either master or slave depending on hardware.
3637 * Refer to reference manual.
3638 * @rmtoll CCR MULTI LL_ADC_SetMultimode
3639 * @param ADCxy_COMMON ADC common instance
3640 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3641 * @param Multimode This parameter can be one of the following values:
3642 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3643 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3644 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3645 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3646 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3647 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3648 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3649 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3650 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3651 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3652 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3653 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3654 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3655 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3656 * @retval None
3657 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)3658 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3659 {
3660 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3661 }
3662
3663 /**
3664 * @brief Get ADC multimode configuration to operate in independent mode
3665 * or multimode (for devices with several ADC instances).
3666 * @note If multimode configuration: the selected ADC instance is
3667 * either master or slave depending on hardware.
3668 * Refer to reference manual.
3669 * @rmtoll CCR MULTI LL_ADC_GetMultimode
3670 * @param ADCxy_COMMON ADC common instance
3671 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3672 * @retval Returned value can be one of the following values:
3673 * @arg @ref LL_ADC_MULTI_INDEPENDENT
3674 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3675 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
3676 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3677 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3678 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3679 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3680 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
3681 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
3682 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
3683 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
3684 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
3685 * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
3686 * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
3687 */
LL_ADC_GetMultimode(const ADC_Common_TypeDef * ADCxy_COMMON)3688 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
3689 {
3690 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3691 }
3692
3693 /**
3694 * @brief Set ADC multimode conversion data transfer: no transfer
3695 * or transfer by DMA.
3696 * @note If ADC multimode transfer by DMA is not selected:
3697 * each ADC uses its own DMA channel, with its individual
3698 * DMA transfer settings.
3699 * If ADC multimode transfer by DMA is selected:
3700 * One DMA channel is used for both ADC (DMA of ADC master)
3701 * Specifies the DMA requests mode:
3702 * - Limited mode (One shot mode): DMA transfer requests are stopped
3703 * when number of DMA data transfers (number of
3704 * ADC conversions) is reached.
3705 * This ADC mode is intended to be used with DMA mode non-circular.
3706 * - Unlimited mode: DMA transfer requests are unlimited,
3707 * whatever number of DMA data transfers (number of
3708 * ADC conversions).
3709 * This ADC mode is intended to be used with DMA mode circular.
3710 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3711 * mode non-circular:
3712 * when DMA transfers size will be reached, DMA will stop transfers of
3713 * ADC conversions data ADC will raise an overrun error
3714 * (overrun flag and interruption if enabled).
3715 * @note How to retrieve multimode conversion data:
3716 * Whatever multimode transfer by DMA setting: using function
3717 * @ref LL_ADC_REG_ReadMultiConversionData32().
3718 * If ADC multimode transfer by DMA is selected: conversion data
3719 * is a raw data with ADC master and slave concatenated.
3720 * A macro is available to get the conversion data of
3721 * ADC master or ADC slave: see helper macro
3722 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3723 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
3724 * CCR DDS LL_ADC_SetMultiDMATransfer
3725 * @param ADCxy_COMMON ADC common instance
3726 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3727 * @param MultiDMATransfer This parameter can be one of the following values:
3728 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3729 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3730 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3731 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3732 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3733 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3734 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3735 * @retval None
3736 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)3737 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3738 {
3739 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3740 }
3741
3742 /**
3743 * @brief Get ADC multimode conversion data transfer: no transfer
3744 * or transfer by DMA.
3745 * @note If ADC multimode transfer by DMA is not selected:
3746 * each ADC uses its own DMA channel, with its individual
3747 * DMA transfer settings.
3748 * If ADC multimode transfer by DMA is selected:
3749 * One DMA channel is used for both ADC (DMA of ADC master)
3750 * Specifies the DMA requests mode:
3751 * - Limited mode (One shot mode): DMA transfer requests are stopped
3752 * when number of DMA data transfers (number of
3753 * ADC conversions) is reached.
3754 * This ADC mode is intended to be used with DMA mode non-circular.
3755 * - Unlimited mode: DMA transfer requests are unlimited,
3756 * whatever number of DMA data transfers (number of
3757 * ADC conversions).
3758 * This ADC mode is intended to be used with DMA mode circular.
3759 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3760 * mode non-circular:
3761 * when DMA transfers size will be reached, DMA will stop transfers of
3762 * ADC conversions data ADC will raise an overrun error
3763 * (overrun flag and interruption if enabled).
3764 * @note How to retrieve multimode conversion data:
3765 * Whatever multimode transfer by DMA setting: using function
3766 * @ref LL_ADC_REG_ReadMultiConversionData32().
3767 * If ADC multimode transfer by DMA is selected: conversion data
3768 * is a raw data with ADC master and slave concatenated.
3769 * A macro is available to get the conversion data of
3770 * ADC master or ADC slave: see helper macro
3771 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3772 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
3773 * CCR DDS LL_ADC_GetMultiDMATransfer
3774 * @param ADCxy_COMMON ADC common instance
3775 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3776 * @retval Returned value can be one of the following values:
3777 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
3778 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
3779 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
3780 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
3781 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
3782 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
3783 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
3784 */
LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef * ADCxy_COMMON)3785 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
3786 {
3787 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3788 }
3789
3790 /**
3791 * @brief Set ADC multimode delay between 2 sampling phases.
3792 * @note The sampling delay range depends on ADC resolution:
3793 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
3794 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
3795 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
3796 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
3797 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
3798 * @param ADCxy_COMMON ADC common instance
3799 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3800 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
3801 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3802 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3803 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3804 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3805 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3806 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3807 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3808 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3809 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3810 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3811 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3812 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3813 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3814 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3815 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3816 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3817 * @retval None
3818 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)3819 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3820 {
3821 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3822 }
3823
3824 /**
3825 * @brief Get ADC multimode delay between 2 sampling phases.
3826 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
3827 * @param ADCxy_COMMON ADC common instance
3828 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3829 * @retval Returned value can be one of the following values:
3830 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
3831 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
3832 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
3833 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
3834 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
3835 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
3836 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
3837 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
3838 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
3839 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
3840 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
3841 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
3842 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
3843 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
3844 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
3845 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
3846 */
LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef * ADCxy_COMMON)3847 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
3848 {
3849 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3850 }
3851 #endif /* ADC_MULTIMODE_SUPPORT */
3852
3853 /**
3854 * @}
3855 */
3856 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3857 * @{
3858 */
3859
3860 /**
3861 * @brief Enable the selected ADC instance.
3862 * @note On this STM32 series, after ADC enable, a delay for
3863 * ADC internal analog stabilization is required before performing a
3864 * ADC conversion start.
3865 * Refer to device datasheet, parameter tSTAB.
3866 * @rmtoll CR2 ADON LL_ADC_Enable
3867 * @param ADCx ADC instance
3868 * @retval None
3869 */
LL_ADC_Enable(ADC_TypeDef * ADCx)3870 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3871 {
3872 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3873 }
3874
3875 /**
3876 * @brief Disable the selected ADC instance.
3877 * @rmtoll CR2 ADON LL_ADC_Disable
3878 * @param ADCx ADC instance
3879 * @retval None
3880 */
LL_ADC_Disable(ADC_TypeDef * ADCx)3881 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3882 {
3883 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3884 }
3885
3886 /**
3887 * @brief Get the selected ADC instance enable state.
3888 * @rmtoll CR2 ADON LL_ADC_IsEnabled
3889 * @param ADCx ADC instance
3890 * @retval 0: ADC is disabled, 1: ADC is enabled.
3891 */
LL_ADC_IsEnabled(const ADC_TypeDef * ADCx)3892 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
3893 {
3894 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3895 }
3896
3897 /**
3898 * @}
3899 */
3900
3901 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3902 * @{
3903 */
3904
3905 /**
3906 * @brief Start ADC group regular conversion.
3907 * @note On this STM32 series, this function is relevant only for
3908 * internal trigger (SW start), not for external trigger:
3909 * - If ADC trigger has been set to software start, ADC conversion
3910 * starts immediately.
3911 * - If ADC trigger has been set to external trigger, ADC conversion
3912 * start must be performed using function
3913 * @ref LL_ADC_REG_StartConversionExtTrig().
3914 * (if external trigger edge would have been set during ADC other
3915 * settings, ADC conversion would start at trigger event
3916 * as soon as ADC is enabled).
3917 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3918 * @param ADCx ADC instance
3919 * @retval None
3920 */
LL_ADC_REG_StartConversionSWStart(ADC_TypeDef * ADCx)3921 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3922 {
3923 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3924 }
3925
3926 /**
3927 * @brief Start ADC group regular conversion from external trigger.
3928 * @note ADC conversion will start at next trigger event (on the selected
3929 * trigger edge) following the ADC start conversion command.
3930 * @note On this STM32 series, this function is relevant for
3931 * ADC conversion start from external trigger.
3932 * If internal trigger (SW start) is needed, perform ADC conversion
3933 * start using function @ref LL_ADC_REG_StartConversionSWStart().
3934 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3935 * @param ExternalTriggerEdge This parameter can be one of the following values:
3936 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3937 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3938 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3939 * @param ADCx ADC instance
3940 * @retval None
3941 */
LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3942 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3943 {
3944 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3945 }
3946
3947 /**
3948 * @brief Stop ADC group regular conversion from external trigger.
3949 * @note No more ADC conversion will start at next trigger event
3950 * following the ADC stop conversion command.
3951 * If a conversion is on-going, it will be completed.
3952 * @note On this STM32 series, there is no specific command
3953 * to stop a conversion on-going or to stop ADC converting
3954 * in continuous mode. These actions can be performed
3955 * using function @ref LL_ADC_Disable().
3956 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
3957 * @param ADCx ADC instance
3958 * @retval None
3959 */
LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef * ADCx)3960 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3961 {
3962 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3963 }
3964
3965 /**
3966 * @brief Get ADC group regular conversion data, range fit for
3967 * all ADC configurations: all ADC resolutions and
3968 * all oversampling increased data width (for devices
3969 * with feature oversampling).
3970 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3971 * @param ADCx ADC instance
3972 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3973 */
LL_ADC_REG_ReadConversionData32(const ADC_TypeDef * ADCx)3974 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
3975 {
3976 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3977 }
3978
3979 /**
3980 * @brief Get ADC group regular conversion data, range fit for
3981 * ADC resolution 12 bits.
3982 * @note For devices with feature oversampling: Oversampling
3983 * can increase data width, function for extended range
3984 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3985 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3986 * @param ADCx ADC instance
3987 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3988 */
LL_ADC_REG_ReadConversionData12(const ADC_TypeDef * ADCx)3989 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
3990 {
3991 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3992 }
3993
3994 /**
3995 * @brief Get ADC group regular conversion data, range fit for
3996 * ADC resolution 10 bits.
3997 * @note For devices with feature oversampling: Oversampling
3998 * can increase data width, function for extended range
3999 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4000 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
4001 * @param ADCx ADC instance
4002 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4003 */
LL_ADC_REG_ReadConversionData10(const ADC_TypeDef * ADCx)4004 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
4005 {
4006 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4007 }
4008
4009 /**
4010 * @brief Get ADC group regular conversion data, range fit for
4011 * ADC resolution 8 bits.
4012 * @note For devices with feature oversampling: Oversampling
4013 * can increase data width, function for extended range
4014 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4015 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
4016 * @param ADCx ADC instance
4017 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4018 */
LL_ADC_REG_ReadConversionData8(const ADC_TypeDef * ADCx)4019 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
4020 {
4021 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4022 }
4023
4024 /**
4025 * @brief Get ADC group regular conversion data, range fit for
4026 * ADC resolution 6 bits.
4027 * @note For devices with feature oversampling: Oversampling
4028 * can increase data width, function for extended range
4029 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4030 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
4031 * @param ADCx ADC instance
4032 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4033 */
LL_ADC_REG_ReadConversionData6(const ADC_TypeDef * ADCx)4034 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
4035 {
4036 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4037 }
4038
4039 #if defined(ADC_MULTIMODE_SUPPORT)
4040 /**
4041 * @brief Get ADC multimode conversion data of ADC master, ADC slave
4042 * or raw data with ADC master and slave concatenated.
4043 * @note If raw data with ADC master and slave concatenated is retrieved,
4044 * a macro is available to get the conversion data of
4045 * ADC master or ADC slave: see helper macro
4046 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
4047 * (however this macro is mainly intended for multimode
4048 * transfer by DMA, because this function can do the same
4049 * by getting multimode conversion data of ADC master or ADC slave
4050 * separately).
4051 * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
4052 * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
4053 * @param ADCxy_COMMON ADC common instance
4054 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4055 * @param ConversionData This parameter can be one of the following values:
4056 * @arg @ref LL_ADC_MULTI_MASTER
4057 * @arg @ref LL_ADC_MULTI_SLAVE
4058 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
4059 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4060 */
LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)4061 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
4062 {
4063 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
4064 ADC_DR_ADC2DATA)
4065 >> POSITION_VAL(ConversionData)
4066 );
4067 }
4068 #endif /* ADC_MULTIMODE_SUPPORT */
4069
4070 /**
4071 * @}
4072 */
4073
4074 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
4075 * @{
4076 */
4077
4078 /**
4079 * @brief Start ADC group injected conversion.
4080 * @note On this STM32 series, this function is relevant only for
4081 * internal trigger (SW start), not for external trigger:
4082 * - If ADC trigger has been set to software start, ADC conversion
4083 * starts immediately.
4084 * - If ADC trigger has been set to external trigger, ADC conversion
4085 * start must be performed using function
4086 * @ref LL_ADC_INJ_StartConversionExtTrig().
4087 * (if external trigger edge would have been set during ADC other
4088 * settings, ADC conversion would start at trigger event
4089 * as soon as ADC is enabled).
4090 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4091 * @param ADCx ADC instance
4092 * @retval None
4093 */
LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef * ADCx)4094 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4095 {
4096 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4097 }
4098
4099 /**
4100 * @brief Start ADC group injected conversion from external trigger.
4101 * @note ADC conversion will start at next trigger event (on the selected
4102 * trigger edge) following the ADC start conversion command.
4103 * @note On this STM32 series, this function is relevant for
4104 * ADC conversion start from external trigger.
4105 * If internal trigger (SW start) is needed, perform ADC conversion
4106 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4107 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4108 * @param ExternalTriggerEdge This parameter can be one of the following values:
4109 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4110 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4111 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4112 * @param ADCx ADC instance
4113 * @retval None
4114 */
LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)4115 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4116 {
4117 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4118 }
4119
4120 /**
4121 * @brief Stop ADC group injected conversion from external trigger.
4122 * @note No more ADC conversion will start at next trigger event
4123 * following the ADC stop conversion command.
4124 * If a conversion is on-going, it will be completed.
4125 * @note On this STM32 series, there is no specific command
4126 * to stop a conversion on-going or to stop ADC converting
4127 * in continuous mode. These actions can be performed
4128 * using function @ref LL_ADC_Disable().
4129 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4130 * @param ADCx ADC instance
4131 * @retval None
4132 */
LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef * ADCx)4133 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4134 {
4135 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4136 }
4137
4138 /**
4139 * @brief Get ADC group regular conversion data, range fit for
4140 * all ADC configurations: all ADC resolutions and
4141 * all oversampling increased data width (for devices
4142 * with feature oversampling).
4143 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4144 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4145 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4146 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4147 * @param ADCx ADC instance
4148 * @param Rank This parameter can be one of the following values:
4149 * @arg @ref LL_ADC_INJ_RANK_1
4150 * @arg @ref LL_ADC_INJ_RANK_2
4151 * @arg @ref LL_ADC_INJ_RANK_3
4152 * @arg @ref LL_ADC_INJ_RANK_4
4153 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4154 */
LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef * ADCx,uint32_t Rank)4155 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
4156 {
4157 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4158
4159 return (uint32_t)(READ_BIT(*preg,
4160 ADC_JDR1_JDATA)
4161 );
4162 }
4163
4164 /**
4165 * @brief Get ADC group injected conversion data, range fit for
4166 * ADC resolution 12 bits.
4167 * @note For devices with feature oversampling: Oversampling
4168 * can increase data width, function for extended range
4169 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4170 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4171 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4172 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4173 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4174 * @param ADCx ADC instance
4175 * @param Rank This parameter can be one of the following values:
4176 * @arg @ref LL_ADC_INJ_RANK_1
4177 * @arg @ref LL_ADC_INJ_RANK_2
4178 * @arg @ref LL_ADC_INJ_RANK_3
4179 * @arg @ref LL_ADC_INJ_RANK_4
4180 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4181 */
LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef * ADCx,uint32_t Rank)4182 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
4183 {
4184 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4185
4186 return (uint16_t)(READ_BIT(*preg,
4187 ADC_JDR1_JDATA)
4188 );
4189 }
4190
4191 /**
4192 * @brief Get ADC group injected conversion data, range fit for
4193 * ADC resolution 10 bits.
4194 * @note For devices with feature oversampling: Oversampling
4195 * can increase data width, function for extended range
4196 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4197 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4198 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4199 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4200 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4201 * @param ADCx ADC instance
4202 * @param Rank This parameter can be one of the following values:
4203 * @arg @ref LL_ADC_INJ_RANK_1
4204 * @arg @ref LL_ADC_INJ_RANK_2
4205 * @arg @ref LL_ADC_INJ_RANK_3
4206 * @arg @ref LL_ADC_INJ_RANK_4
4207 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4208 */
LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef * ADCx,uint32_t Rank)4209 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
4210 {
4211 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4212
4213 return (uint16_t)(READ_BIT(*preg,
4214 ADC_JDR1_JDATA)
4215 );
4216 }
4217
4218 /**
4219 * @brief Get ADC group injected conversion data, range fit for
4220 * ADC resolution 8 bits.
4221 * @note For devices with feature oversampling: Oversampling
4222 * can increase data width, function for extended range
4223 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4224 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4225 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4226 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4227 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4228 * @param ADCx ADC instance
4229 * @param Rank This parameter can be one of the following values:
4230 * @arg @ref LL_ADC_INJ_RANK_1
4231 * @arg @ref LL_ADC_INJ_RANK_2
4232 * @arg @ref LL_ADC_INJ_RANK_3
4233 * @arg @ref LL_ADC_INJ_RANK_4
4234 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4235 */
LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef * ADCx,uint32_t Rank)4236 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
4237 {
4238 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4239
4240 return (uint8_t)(READ_BIT(*preg,
4241 ADC_JDR1_JDATA)
4242 );
4243 }
4244
4245 /**
4246 * @brief Get ADC group injected conversion data, range fit for
4247 * ADC resolution 6 bits.
4248 * @note For devices with feature oversampling: Oversampling
4249 * can increase data width, function for extended range
4250 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4251 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4252 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4253 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4254 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4255 * @param ADCx ADC instance
4256 * @param Rank This parameter can be one of the following values:
4257 * @arg @ref LL_ADC_INJ_RANK_1
4258 * @arg @ref LL_ADC_INJ_RANK_2
4259 * @arg @ref LL_ADC_INJ_RANK_3
4260 * @arg @ref LL_ADC_INJ_RANK_4
4261 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4262 */
LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef * ADCx,uint32_t Rank)4263 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
4264 {
4265 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4266
4267 return (uint8_t)(READ_BIT(*preg,
4268 ADC_JDR1_JDATA)
4269 );
4270 }
4271
4272 /**
4273 * @}
4274 */
4275
4276 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4277 * @{
4278 */
4279
4280 /**
4281 * @brief Get flag ADC group regular end of unitary conversion
4282 * or end of sequence conversions, depending on
4283 * ADC configuration.
4284 * @note To configure flag of end of conversion,
4285 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4286 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4287 * @param ADCx ADC instance
4288 * @retval State of bit (1 or 0).
4289 */
LL_ADC_IsActiveFlag_EOCS(const ADC_TypeDef * ADCx)4290 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(const ADC_TypeDef *ADCx)
4291 {
4292 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4293 }
4294
4295 /**
4296 * @brief Get flag ADC group regular overrun.
4297 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4298 * @param ADCx ADC instance
4299 * @retval State of bit (1 or 0).
4300 */
LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef * ADCx)4301 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
4302 {
4303 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4304 }
4305
4306
4307 /**
4308 * @brief Get flag ADC group injected end of sequence conversions.
4309 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4310 * @param ADCx ADC instance
4311 * @retval State of bit (1 or 0).
4312 */
LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef * ADCx)4313 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
4314 {
4315 /* Note: on this STM32 series, there is no flag ADC group injected */
4316 /* end of unitary conversion. */
4317 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4318 /* in other STM32 families). */
4319 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4320 }
4321
4322 /**
4323 * @brief Get flag ADC analog watchdog 1 flag
4324 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4325 * @param ADCx ADC instance
4326 * @retval State of bit (1 or 0).
4327 */
LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef * ADCx)4328 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
4329 {
4330 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4331 }
4332
4333 /**
4334 * @brief Clear flag ADC group regular end of unitary conversion
4335 * or end of sequence conversions, depending on
4336 * ADC configuration.
4337 * @note To configure flag of end of conversion,
4338 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4339 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4340 * @param ADCx ADC instance
4341 * @retval None
4342 */
LL_ADC_ClearFlag_EOCS(ADC_TypeDef * ADCx)4343 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4344 {
4345 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4346 }
4347
4348 /**
4349 * @brief Clear flag ADC group regular overrun.
4350 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4351 * @param ADCx ADC instance
4352 * @retval None
4353 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4354 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4355 {
4356 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4357 }
4358
4359
4360 /**
4361 * @brief Clear flag ADC group injected end of sequence conversions.
4362 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4363 * @param ADCx ADC instance
4364 * @retval None
4365 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)4366 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4367 {
4368 /* Note: on this STM32 series, there is no flag ADC group injected */
4369 /* end of unitary conversion. */
4370 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4371 /* in other STM32 families). */
4372 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4373 }
4374
4375 /**
4376 * @brief Clear flag ADC analog watchdog 1.
4377 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4378 * @param ADCx ADC instance
4379 * @retval None
4380 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4381 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4382 {
4383 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4384 }
4385
4386 #if defined(ADC_MULTIMODE_SUPPORT)
4387 /**
4388 * @brief Get flag multimode ADC group regular end of unitary conversion
4389 * or end of sequence conversions, depending on
4390 * ADC configuration, of the ADC master.
4391 * @note To configure flag of end of conversion,
4392 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4393 * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
4394 * @param ADCxy_COMMON ADC common instance
4395 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4396 * @retval State of bit (1 or 0).
4397 */
LL_ADC_IsActiveFlag_MST_EOCS(const ADC_Common_TypeDef * ADCxy_COMMON)4398 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(const ADC_Common_TypeDef *ADCxy_COMMON)
4399 {
4400 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST));
4401 }
4402
4403 /**
4404 * @brief Get flag multimode ADC group regular end of unitary conversion
4405 * or end of sequence conversions, depending on
4406 * ADC configuration, of the ADC slave 1.
4407 * @note To configure flag of end of conversion,
4408 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4409 * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
4410 * @param ADCxy_COMMON ADC common instance
4411 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4412 * @retval State of bit (1 or 0).
4413 */
LL_ADC_IsActiveFlag_SLV1_EOCS(const ADC_Common_TypeDef * ADCxy_COMMON)4414 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(const ADC_Common_TypeDef *ADCxy_COMMON)
4415 {
4416 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4417 }
4418
4419 /**
4420 * @brief Get flag multimode ADC group regular end of unitary conversion
4421 * or end of sequence conversions, depending on
4422 * ADC configuration, of the ADC slave 2.
4423 * @note To configure flag of end of conversion,
4424 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4425 * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
4426 * @param ADCxy_COMMON ADC common instance
4427 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4428 * @retval State of bit (1 or 0).
4429 */
LL_ADC_IsActiveFlag_SLV2_EOCS(const ADC_Common_TypeDef * ADCxy_COMMON)4430 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(const ADC_Common_TypeDef *ADCxy_COMMON)
4431 {
4432 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4433 }
4434 /**
4435 * @brief Get flag multimode ADC group regular overrun of the ADC master.
4436 * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
4437 * @param ADCxy_COMMON ADC common instance
4438 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4439 * @retval State of bit (1 or 0).
4440 */
LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)4441 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
4442 {
4443 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4444 }
4445
4446 /**
4447 * @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
4448 * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
4449 * @param ADCxy_COMMON ADC common instance
4450 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4451 * @retval State of bit (1 or 0).
4452 */
LL_ADC_IsActiveFlag_SLV1_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)4453 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
4454 {
4455 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4456 }
4457
4458 /**
4459 * @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
4460 * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
4461 * @param ADCxy_COMMON ADC common instance
4462 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4463 * @retval State of bit (1 or 0).
4464 */
LL_ADC_IsActiveFlag_SLV2_OVR(const ADC_Common_TypeDef * ADCxy_COMMON)4465 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
4466 {
4467 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4468 }
4469
4470
4471 /**
4472 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
4473 * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_JEOS
4474 * @param ADCxy_COMMON ADC common instance
4475 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4476 * @retval State of bit (1 or 0).
4477 */
LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)4478 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
4479 {
4480 /* Note: on this STM32 series, there is no flag ADC group injected */
4481 /* end of unitary conversion. */
4482 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4483 /* in other STM32 families). */
4484 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4485 }
4486
4487 /**
4488 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
4489 * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
4490 * @param ADCxy_COMMON ADC common instance
4491 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4492 * @retval State of bit (1 or 0).
4493 */
LL_ADC_IsActiveFlag_SLV1_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)4494 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
4495 {
4496 /* Note: on this STM32 series, there is no flag ADC group injected */
4497 /* end of unitary conversion. */
4498 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4499 /* in other STM32 families). */
4500 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4501 }
4502
4503 /**
4504 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
4505 * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
4506 * @param ADCxy_COMMON ADC common instance
4507 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4508 * @retval State of bit (1 or 0).
4509 */
LL_ADC_IsActiveFlag_SLV2_JEOS(const ADC_Common_TypeDef * ADCxy_COMMON)4510 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
4511 {
4512 /* Note: on this STM32 series, there is no flag ADC group injected */
4513 /* end of unitary conversion. */
4514 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4515 /* in other STM32 families). */
4516 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4517 }
4518
4519 /**
4520 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
4521 * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
4522 * @param ADCxy_COMMON ADC common instance
4523 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4524 * @retval State of bit (1 or 0).
4525 */
LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)4526 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
4527 {
4528 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4529 }
4530
4531 /**
4532 * @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
4533 * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
4534 * @param ADCxy_COMMON ADC common instance
4535 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4536 * @retval State of bit (1 or 0).
4537 */
LL_ADC_IsActiveFlag_SLV1_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)4538 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
4539 {
4540 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4541 }
4542
4543 /**
4544 * @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
4545 * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
4546 * @param ADCxy_COMMON ADC common instance
4547 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
4548 * @retval State of bit (1 or 0).
4549 */
LL_ADC_IsActiveFlag_SLV2_AWD1(const ADC_Common_TypeDef * ADCxy_COMMON)4550 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
4551 {
4552 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4553 }
4554
4555 #endif /* ADC_MULTIMODE_SUPPORT */
4556
4557 /**
4558 * @}
4559 */
4560
4561 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4562 * @{
4563 */
4564
4565 /**
4566 * @brief Enable interruption ADC group regular end of unitary conversion
4567 * or end of sequence conversions, depending on
4568 * ADC configuration.
4569 * @note To configure flag of end of conversion,
4570 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4571 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4572 * @param ADCx ADC instance
4573 * @retval None
4574 */
LL_ADC_EnableIT_EOCS(ADC_TypeDef * ADCx)4575 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4576 {
4577 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4578 }
4579
4580 /**
4581 * @brief Enable ADC group regular interruption overrun.
4582 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4583 * @param ADCx ADC instance
4584 * @retval None
4585 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4586 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4587 {
4588 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4589 }
4590
4591
4592 /**
4593 * @brief Enable interruption ADC group injected end of sequence conversions.
4594 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4595 * @param ADCx ADC instance
4596 * @retval None
4597 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)4598 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4599 {
4600 /* Note: on this STM32 series, there is no flag ADC group injected */
4601 /* end of unitary conversion. */
4602 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4603 /* in other STM32 families). */
4604 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4605 }
4606
4607 /**
4608 * @brief Enable interruption ADC analog watchdog 1.
4609 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4610 * @param ADCx ADC instance
4611 * @retval None
4612 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4613 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4614 {
4615 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4616 }
4617
4618 /**
4619 * @brief Disable interruption ADC group regular end of unitary conversion
4620 * or end of sequence conversions, depending on
4621 * ADC configuration.
4622 * @note To configure flag of end of conversion,
4623 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4624 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
4625 * @param ADCx ADC instance
4626 * @retval None
4627 */
LL_ADC_DisableIT_EOCS(ADC_TypeDef * ADCx)4628 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4629 {
4630 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4631 }
4632
4633 /**
4634 * @brief Disable interruption ADC group regular overrun.
4635 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
4636 * @param ADCx ADC instance
4637 * @retval None
4638 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4639 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4640 {
4641 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4642 }
4643
4644
4645 /**
4646 * @brief Disable interruption ADC group injected end of sequence conversions.
4647 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4648 * @param ADCx ADC instance
4649 * @retval None
4650 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)4651 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4652 {
4653 /* Note: on this STM32 series, there is no flag ADC group injected */
4654 /* end of unitary conversion. */
4655 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4656 /* in other STM32 families). */
4657 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4658 }
4659
4660 /**
4661 * @brief Disable interruption ADC analog watchdog 1.
4662 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4663 * @param ADCx ADC instance
4664 * @retval None
4665 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4666 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4667 {
4668 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4669 }
4670
4671 /**
4672 * @brief Get state of interruption ADC group regular end of unitary conversion
4673 * or end of sequence conversions, depending on
4674 * ADC configuration.
4675 * @note To configure flag of end of conversion,
4676 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4677 * (0: interrupt disabled, 1: interrupt enabled)
4678 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
4679 * @param ADCx ADC instance
4680 * @retval State of bit (1 or 0).
4681 */
LL_ADC_IsEnabledIT_EOCS(const ADC_TypeDef * ADCx)4682 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(const ADC_TypeDef *ADCx)
4683 {
4684 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4685 }
4686
4687 /**
4688 * @brief Get state of interruption ADC group regular overrun
4689 * (0: interrupt disabled, 1: interrupt enabled).
4690 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
4691 * @param ADCx ADC instance
4692 * @retval State of bit (1 or 0).
4693 */
LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef * ADCx)4694 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
4695 {
4696 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4697 }
4698
4699
4700 /**
4701 * @brief Get state of interruption ADC group injected end of sequence conversions
4702 * (0: interrupt disabled, 1: interrupt enabled).
4703 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4704 * @param ADCx ADC instance
4705 * @retval State of bit (1 or 0).
4706 */
LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef * ADCx)4707 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
4708 {
4709 /* Note: on this STM32 series, there is no flag ADC group injected */
4710 /* end of unitary conversion. */
4711 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4712 /* in other STM32 families). */
4713 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4714 }
4715
4716 /**
4717 * @brief Get state of interruption ADC analog watchdog 1
4718 * (0: interrupt disabled, 1: interrupt enabled).
4719 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
4720 * @param ADCx ADC instance
4721 * @retval State of bit (1 or 0).
4722 */
LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef * ADCx)4723 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
4724 {
4725 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4726 }
4727
4728 /**
4729 * @}
4730 */
4731
4732 #if defined(USE_FULL_LL_DRIVER)
4733 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
4734 * @{
4735 */
4736
4737 /* Initialization of some features of ADC common parameters and multimode */
4738 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4739 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4740 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4741
4742 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
4743 /* (availability of ADC group injected depends on STM32 families) */
4744 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4745
4746 /* Initialization of some features of ADC instance */
4747 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4748 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4749
4750 /* Initialization of some features of ADC instance and ADC group regular */
4751 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4752 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4753
4754 /* Initialization of some features of ADC instance and ADC group injected */
4755 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4756 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4757
4758 /**
4759 * @}
4760 */
4761 #endif /* USE_FULL_LL_DRIVER */
4762
4763 /**
4764 * @}
4765 */
4766
4767 /**
4768 * @}
4769 */
4770
4771 #endif /* ADC1 || ADC2 || ADC3 */
4772
4773 /**
4774 * @}
4775 */
4776
4777 #ifdef __cplusplus
4778 }
4779 #endif
4780
4781 #endif /* __STM32F4xx_LL_ADC_H */
4782
4783
