1 /**
2   ******************************************************************************
3   * @file    stm32f3xx_hal_cortex.c
4   * @author  MCD Application Team
5   * @brief   CORTEX HAL module driver.
6   *          This file provides firmware functions to manage the following
7   *          functionalities of the CORTEX:
8   *           + Initialization and de-initialization functions
9   *           + Peripheral Control functions
10   *
11   *  @verbatim
12   ==============================================================================
13                         ##### How to use this driver #####
14   ==============================================================================
15 
16     [..]
17     *** How to configure Interrupts using CORTEX HAL driver ***
18     ===========================================================
19     [..]
20     This section provides functions allowing to configure the NVIC interrupts (IRQ).
21     The Cortex-M4 exceptions are managed by CMSIS functions.
22 
23     (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
24 
25      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
26 
27      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
28 
29 
30      -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
31          The pending IRQ priority will be managed only by the sub priority.
32 
33      -@- IRQ priority order (sorted by highest to lowest priority):
34         (+@) Lowest pre-emption priority
35         (+@) Lowest sub priority
36         (+@) Lowest hardware priority (IRQ number)
37 
38     [..]
39     *** How to configure Systick using CORTEX HAL driver ***
40     ========================================================
41     [..]
42     Setup SysTick Timer for time base
43 
44    (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
45        is a CMSIS function that:
46         (++) Configures the SysTick Reload register with value passed as function parameter.
47         (++) Configures the SysTick IRQ priority to the lowest value (0x0FU).
48         (++) Resets the SysTick Counter register.
49         (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
50         (++) Enables the SysTick Interrupt.
51         (++) Starts the SysTick Counter.
52 
53    (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
54        __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
55        HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
56        inside the stm32f3xx_hal_cortex.h file.
57 
58    (+) You can change the SysTick IRQ priority by calling the
59        HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
60        call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
61 
62    (+) To adjust the SysTick time base, use the following formula:
63 
64        Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
65        (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
66        (++) Reload Value should not exceed 0xFFFFFF
67 
68   @endverbatim
69   ******************************************************************************
70   * @attention
71   *
72   * Copyright (c) 2016 STMicroelectronics.
73   * All rights reserved.
74   *
75   * This software is licensed under terms that can be found in the LICENSE file in
76   * the root directory of this software component.
77   * If no LICENSE file comes with this software, it is provided AS-IS.
78   *
79   ******************************************************************************
80   */
81 
82 /*
83   Additional Tables: CORTEX_NVIC_Priority_Table
84      The table below gives the allowed values of the pre-emption priority and subpriority according
85      to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
86        ==========================================================================================================================
87          NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
88        ==========================================================================================================================
89         NVIC_PRIORITYGROUP_0  |                0                  |            0U-15             | 0 bits for pre-emption priority
90                               |                                   |                             | 4 bits for subpriority
91        --------------------------------------------------------------------------------------------------------------------------
92         NVIC_PRIORITYGROUP_1  |                0U-1                |            0U-7              | 1 bits for pre-emption priority
93                               |                                   |                             | 3 bits for subpriority
94        --------------------------------------------------------------------------------------------------------------------------
95         NVIC_PRIORITYGROUP_2  |                0U-3                |            0U-3              | 2 bits for pre-emption priority
96                               |                                   |                             | 2 bits for subpriority
97        --------------------------------------------------------------------------------------------------------------------------
98         NVIC_PRIORITYGROUP_3  |                0U-7                |            0U-1              | 3 bits for pre-emption priority
99                               |                                   |                             | 1 bits for subpriority
100        --------------------------------------------------------------------------------------------------------------------------
101         NVIC_PRIORITYGROUP_4  |                0U-15               |            0                | 4 bits for pre-emption priority
102                               |                                   |                             | 0 bits for subpriority
103        ==========================================================================================================================
104 
105 */
106 
107 /* Includes ------------------------------------------------------------------*/
108 #include "stm32f3xx_hal.h"
109 
110 /** @addtogroup STM32F3xx_HAL_Driver
111   * @{
112   */
113 
114 /** @defgroup CORTEX CORTEX
115   * @brief CORTEX CORTEX HAL module driver
116   * @{
117   */
118 
119 #ifdef HAL_CORTEX_MODULE_ENABLED
120 
121 /* Private typedef -----------------------------------------------------------*/
122 /* Private define ------------------------------------------------------------*/
123 /* Private macro -------------------------------------------------------------*/
124 /* Private variables ---------------------------------------------------------*/
125 /* Private function prototypes -----------------------------------------------*/
126 /* Exported functions ---------------------------------------------------------*/
127 
128 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
129   * @{
130   */
131 
132 
133 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
134  *  @brief    Initialization and Configuration functions
135  *
136 @verbatim
137   ==============================================================================
138               ##### Initialization and de-initialization functions #####
139   ==============================================================================
140     [..]
141       This section provides the CORTEX HAL driver functions allowing to configure Interrupts
142       Systick functionalities
143 
144 @endverbatim
145   * @{
146   */
147 
148 
149 /**
150   * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
151   *         using the required unlock sequence.
152   * @param  PriorityGroup The priority grouping bits length.
153   *         This parameter can be one of the following values:
154   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
155   *                                    4 bits for subpriority
156   *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
157   *                                    3 bits for subpriority
158   *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
159   *                                    2 bits for subpriority
160   *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
161   *                                    1 bits for subpriority
162   *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
163   *                                    0 bits for subpriority
164   * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
165   *         The pending IRQ priority will be managed only by the subpriority.
166   * @retval None
167   */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)168 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
169 {
170   /* Check the parameters */
171   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
172 
173   /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
174   NVIC_SetPriorityGrouping(PriorityGroup);
175 }
176 
177 /**
178   * @brief  Sets the priority of an interrupt.
179   * @param  IRQn External interrupt number
180   *         This parameter can be an enumerator of IRQn_Type enumeration
181   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
182   * @param  PreemptPriority The pre-emption priority for the IRQn channel.
183   *         This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
184   *         A lower priority value indicates a higher priority
185   * @param  SubPriority the subpriority level for the IRQ channel.
186   *         This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
187   *         A lower priority value indicates a higher priority.
188   * @retval None
189   */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)190 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
191 {
192   uint32_t prioritygroup = 0x00U;
193 
194   /* Check the parameters */
195   assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
196   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
197 
198   prioritygroup = NVIC_GetPriorityGrouping();
199 
200   NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
201 }
202 
203 /**
204   * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
205   * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
206   *         function should be called before.
207   * @param  IRQn External interrupt number
208   *         This parameter can be an enumerator of IRQn_Type enumeration
209   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
210   * @retval None
211   */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)212 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
213 {
214   /* Check the parameters */
215   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
216 
217   /* Enable interrupt */
218   NVIC_EnableIRQ(IRQn);
219 }
220 
221 /**
222   * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
223   * @param  IRQn External interrupt number
224   *         This parameter can be an enumerator of IRQn_Type enumeration
225   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
226   * @retval None
227   */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)228 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
229 {
230   /* Check the parameters */
231   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
232 
233   /* Disable interrupt */
234   NVIC_DisableIRQ(IRQn);
235 }
236 
237 /**
238   * @brief  Initiates a system reset request to reset the MCU.
239   * @retval None
240   */
HAL_NVIC_SystemReset(void)241 void HAL_NVIC_SystemReset(void)
242 {
243   /* System Reset */
244   NVIC_SystemReset();
245 }
246 
247 /**
248   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
249   *         Counter is in free running mode to generate periodic interrupts.
250   * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
251   * @retval status:  - 0  Function succeeded.
252   *                  - 1  Function failed.
253   */
HAL_SYSTICK_Config(uint32_t TicksNumb)254 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
255 {
256    return SysTick_Config(TicksNumb);
257 }
258 /**
259   * @}
260   */
261 
262 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
263  *  @brief   Cortex control functions
264  *
265 @verbatim
266   ==============================================================================
267                       ##### Peripheral Control functions #####
268   ==============================================================================
269     [..]
270       This subsection provides a set of functions allowing to control the CORTEX
271       (NVIC, SYSTICK, MPU) functionalities.
272 
273 
274 @endverbatim
275   * @{
276   */
277 
278 #if (__MPU_PRESENT == 1U)
279 
280 /**
281   * @brief  Disables the MPU also clears the HFNMIENA bit (ARM recommendation)
282   * @retval None
283   */
HAL_MPU_Disable(void)284 void HAL_MPU_Disable(void)
285 {
286   /* Disable fault exceptions */
287   SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
288 
289   /* Disable the MPU */
290   MPU->CTRL = 0U;
291 }
292 
293 /**
294   * @brief  Enables the MPU
295   * @param  MPU_Control Specifies the control mode of the MPU during hard fault,
296   *          NMI, FAULTMASK and privileged access to the default memory
297   *          This parameter can be one of the following values:
298   *            @arg MPU_HFNMI_PRIVDEF_NONE
299   *            @arg MPU_HARDFAULT_NMI
300   *            @arg MPU_PRIVILEGED_DEFAULT
301   *            @arg MPU_HFNMI_PRIVDEF
302   * @retval None
303   */
HAL_MPU_Enable(uint32_t MPU_Control)304 void HAL_MPU_Enable(uint32_t MPU_Control)
305 {
306   /* Enable the MPU */
307   MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
308 
309   /* Enable fault exceptions */
310   SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
311 }
312 
313 /**
314   * @brief  Enables the MPU Region.
315   * @retval None
316   */
HAL_MPU_EnableRegion(uint32_t RegionNumber)317 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
318 {
319   /* Check the parameters */
320   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
321 
322   /* Set the Region number */
323   MPU->RNR = RegionNumber;
324 
325   /* Enable the Region */
326   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
327 }
328 
329 /**
330   * @brief  Disables the MPU Region.
331   * @retval None
332   */
HAL_MPU_DisableRegion(uint32_t RegionNumber)333 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
334 {
335   /* Check the parameters */
336   assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
337 
338   /* Set the Region number */
339   MPU->RNR = RegionNumber;
340 
341   /* Disable the Region */
342   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
343 }
344 
345 /**
346   * @brief  Initializes and configures the Region and the memory to be protected.
347   * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
348   *                the initialization and configuration information.
349   * @retval None
350   */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)351 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
352 {
353   /* Check the parameters */
354   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
355   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
356   assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
357   assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
358   assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
359   assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
360   assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
361   assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
362   assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
363   assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
364 
365   /* Set the Region number */
366   MPU->RNR = MPU_Init->Number;
367 
368   /* Disable the Region */
369   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
370 
371   /* Apply configuration */
372   MPU->RBAR = MPU_Init->BaseAddress;
373   MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
374               ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
375               ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
376               ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
377               ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
378               ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
379               ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
380               ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
381               ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
382 }
383 #endif /* __MPU_PRESENT */
384 
385 /**
386   * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
387   * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
388   */
HAL_NVIC_GetPriorityGrouping(void)389 uint32_t HAL_NVIC_GetPriorityGrouping(void)
390 {
391   /* Get the PRIGROUP[10:8] field value */
392   return NVIC_GetPriorityGrouping();
393 }
394 
395 /**
396   * @brief  Gets the priority of an interrupt.
397   * @param  IRQn External interrupt number
398   *         This parameter can be an enumerator of IRQn_Type enumeration
399   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
400   * @param   PriorityGroup: the priority grouping bits length.
401   *         This parameter can be one of the following values:
402   *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
403   *                                      4 bits for subpriority
404   *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
405   *                                      3 bits for subpriority
406   *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
407   *                                      2 bits for subpriority
408   *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
409   *                                      1 bits for subpriority
410   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
411   *                                      0 bits for subpriority
412   * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
413   * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
414   * @retval None
415   */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)416 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
417 {
418   /* Check the parameters */
419   assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
420   /* Get priority for Cortex-M system or device specific interrupts */
421   NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
422 }
423 
424 /**
425   * @brief  Sets Pending bit of an external interrupt.
426   * @param  IRQn External interrupt number
427   *         This parameter can be an enumerator of IRQn_Type enumeration
428   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
429   * @retval None
430   */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)431 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
432 {
433   /* Set interrupt pending */
434   NVIC_SetPendingIRQ(IRQn);
435 }
436 
437 /**
438   * @brief  Gets Pending Interrupt (reads the pending register in the NVIC
439   *         and returns the pending bit for the specified interrupt).
440   * @param  IRQn External interrupt number
441   *         This parameter can be an enumerator of IRQn_Type enumeration
442   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
443   * @retval status: - 0  Interrupt status is not pending.
444   *                 - 1  Interrupt status is pending.
445   */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)446 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
447 {
448   /* Return 1 if pending else 0U */
449   return NVIC_GetPendingIRQ(IRQn);
450 }
451 
452 /**
453   * @brief  Clears the pending bit of an external interrupt.
454   * @param  IRQn External interrupt number
455   *         This parameter can be an enumerator of IRQn_Type enumeration
456   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
457   * @retval None
458   */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)459 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
460 {
461   /* Clear pending interrupt */
462   NVIC_ClearPendingIRQ(IRQn);
463 }
464 
465 /**
466   * @brief  Gets active interrupt ( reads the active register in NVIC and returns the active bit).
467   * @param  IRQn External interrupt number
468   *         This parameter can be an enumerator of IRQn_Type enumeration
469   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
470   * @retval status: - 0  Interrupt status is not pending.
471   *                 - 1  Interrupt status is pending.
472   */
HAL_NVIC_GetActive(IRQn_Type IRQn)473 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
474 {
475   /* Return 1 if active else 0U */
476   return NVIC_GetActive(IRQn);
477 }
478 
479 /**
480   * @brief  Configures the SysTick clock source.
481   * @param  CLKSource specifies the SysTick clock source.
482   *         This parameter can be one of the following values:
483   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
484   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
485   * @retval None
486   */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)487 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
488 {
489   /* Check the parameters */
490   assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
491   if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
492   {
493     SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
494   }
495   else
496   {
497     SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
498   }
499 }
500 
501 /**
502   * @brief  This function handles SYSTICK interrupt request.
503   * @retval None
504   */
HAL_SYSTICK_IRQHandler(void)505 void HAL_SYSTICK_IRQHandler(void)
506 {
507   HAL_SYSTICK_Callback();
508 }
509 
510 /**
511   * @brief  SYSTICK callback.
512   * @retval None
513   */
HAL_SYSTICK_Callback(void)514 __weak void HAL_SYSTICK_Callback(void)
515 {
516   /* NOTE : This function Should not be modified, when the callback is needed,
517             the HAL_SYSTICK_Callback could be implemented in the user file
518    */
519 }
520 
521 /**
522   * @}
523   */
524 
525 /**
526   * @}
527   */
528 
529 #endif /* HAL_CORTEX_MODULE_ENABLED */
530 /**
531   * @}
532   */
533 
534 /**
535   * @}
536   */
537 
538