1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_can_legacy.h 4 * @author MCD Application Team 5 * @brief Header file of CAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F3xx_HAL_CAN_LEGACY_H 21 #define __STM32F3xx_HAL_CAN_LEGACY_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ 28 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ 29 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ 30 defined(STM32F302x8) || \ 31 defined(STM32F373xC) || defined(STM32F378xx) 32 33 /* Includes ------------------------------------------------------------------*/ 34 #include "stm32f3xx_hal_def.h" 35 36 /** @addtogroup STM32F3xx_HAL_Driver 37 * @{ 38 */ 39 40 /** @addtogroup CAN 41 * @{ 42 */ 43 44 /* Exported types ------------------------------------------------------------*/ 45 /** @defgroup CAN_Exported_Types CAN Exported Types 46 * @{ 47 */ 48 /** 49 * @brief HAL State structures definition 50 */ 51 typedef enum 52 { 53 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ 54 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ 55 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ 56 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ 57 HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ 58 HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ 59 HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ 60 HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ 61 HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ 62 HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ 63 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ 64 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ 65 66 }HAL_CAN_StateTypeDef; 67 68 /** 69 * @brief CAN init structure definition 70 */ 71 typedef struct 72 { 73 uint32_t Prescaler; /*!< Specifies the length of a time quantum. 74 This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ 75 76 uint32_t Mode; /*!< Specifies the CAN operating mode. 77 This parameter can be a value of @ref CAN_operating_mode */ 78 79 uint32_t SJW; /*!< Specifies the maximum number of time quanta 80 the CAN hardware is allowed to lengthen or 81 shorten a bit to perform resynchronization. 82 This parameter can be a value of @ref CAN_synchronisation_jump_width */ 83 84 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. 85 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ 86 87 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. 88 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ 89 90 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. 91 This parameter can be set to ENABLE or DISABLE. */ 92 93 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. 94 This parameter can be set to ENABLE or DISABLE. */ 95 96 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. 97 This parameter can be set to ENABLE or DISABLE. */ 98 99 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. 100 This parameter can be set to ENABLE or DISABLE. */ 101 102 uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode. 103 This parameter can be set to ENABLE or DISABLE. */ 104 105 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. 106 This parameter can be set to ENABLE or DISABLE. */ 107 }CAN_InitTypeDef; 108 109 /** 110 * @brief CAN filter configuration structure definition 111 */ 112 typedef struct 113 { 114 uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit 115 configuration, first one for a 16-bit configuration). 116 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 117 118 uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit 119 configuration, second one for a 16-bit configuration). 120 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 121 122 uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, 123 according to the mode (MSBs for a 32-bit configuration, 124 first one for a 16-bit configuration). 125 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 126 127 uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, 128 according to the mode (LSBs for a 32-bit configuration, 129 second one for a 16-bit configuration). 130 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 131 132 uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. 133 This parameter can be a value of @ref CAN_filter_FIFO */ 134 135 uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. 136 This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ 137 138 uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. 139 This parameter can be a value of @ref CAN_filter_mode */ 140 141 uint32_t FilterScale; /*!< Specifies the filter scale. 142 This parameter can be a value of @ref CAN_filter_scale */ 143 144 uint32_t FilterActivation; /*!< Enable or disable the filter. 145 This parameter can be set to ENABLE or DISABLE. */ 146 147 uint32_t BankNumber; /*!< Select the start slave bank filter 148 F3 devices don't support CAN2 interface (Slave). Therefore this parameter 149 is meaningless but it has been kept for compatibility across STM32 families */ 150 151 }CAN_FilterConfTypeDef; 152 153 /** 154 * @brief CAN Tx message structure definition 155 */ 156 typedef struct 157 { 158 uint32_t StdId; /*!< Specifies the standard identifier. 159 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 160 161 uint32_t ExtId; /*!< Specifies the extended identifier. 162 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 163 164 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. 165 This parameter can be a value of @ref CAN_identifier_type */ 166 167 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. 168 This parameter can be a value of @ref CAN_remote_transmission_request */ 169 170 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. 171 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ 172 173 uint8_t Data[8]; /*!< Contains the data to be transmitted. 174 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 175 176 }CanTxMsgTypeDef; 177 178 /** 179 * @brief CAN Rx message structure definition 180 */ 181 typedef struct 182 { 183 uint32_t StdId; /*!< Specifies the standard identifier. 184 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ 185 186 uint32_t ExtId; /*!< Specifies the extended identifier. 187 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ 188 189 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. 190 This parameter can be a value of @ref CAN_identifier_type */ 191 192 uint32_t RTR; /*!< Specifies the type of frame for the received message. 193 This parameter can be a value of @ref CAN_remote_transmission_request */ 194 195 uint32_t DLC; /*!< Specifies the length of the frame that will be received. 196 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ 197 198 uint8_t Data[8]; /*!< Contains the data to be received. 199 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 200 201 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. 202 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ 203 204 uint32_t FIFONumber; /*!< Specifies the receive FIFO number. 205 This parameter can be CAN_FIFO0 or CAN_FIFO1 */ 206 207 }CanRxMsgTypeDef; 208 209 /** 210 * @brief CAN handle Structure definition 211 */ 212 typedef struct 213 { 214 CAN_TypeDef *Instance; /*!< Register base address */ 215 216 CAN_InitTypeDef Init; /*!< CAN required parameters */ 217 218 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ 219 220 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ 221 222 CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ 223 224 HAL_LockTypeDef Lock; /*!< CAN locking object */ 225 226 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ 227 228 __IO uint32_t ErrorCode; /*!< CAN Error code 229 This parameter can be a value of @ref CAN_Error_Code */ 230 231 }CAN_HandleTypeDef; 232 /** 233 * @} 234 */ 235 236 /* Exported constants --------------------------------------------------------*/ 237 238 /** @defgroup CAN_Exported_Constants CAN Exported Constants 239 * @{ 240 */ 241 242 /** @defgroup CAN_Error_Code CAN Error Code 243 * @{ 244 */ 245 #define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ 246 #define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */ 247 #define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */ 248 #define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */ 249 #define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ 250 #define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ 251 #define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ 252 #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */ 253 #define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */ 254 #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */ 255 #define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */ 256 #define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */ 257 #define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup CAN_InitStatus CAN InitStatus 263 * @{ 264 */ 265 #define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ 266 #define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup CAN_operating_mode CAN Operating Mode 272 * @{ 273 */ 274 #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ 275 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ 276 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ 277 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ 278 /** 279 * @} 280 */ 281 282 283 /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width 284 * @{ 285 */ 286 #define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ 287 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ 288 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ 289 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ 290 /** 291 * @} 292 */ 293 294 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 295 * @{ 296 */ 297 #define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ 298 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ 299 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ 300 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ 301 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ 302 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ 303 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ 304 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ 305 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ 306 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ 307 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ 308 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ 309 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ 310 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ 311 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ 312 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 318 * @{ 319 */ 320 #define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ 321 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ 322 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ 323 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ 324 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ 325 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ 326 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ 327 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup CAN_filter_mode CAN Filter Mode 333 * @{ 334 */ 335 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */ 336 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup CAN_filter_scale CAN Filter Scale 342 * @{ 343 */ 344 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */ 345 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup CAN_filter_FIFO CAN Filter FIFO 351 * @{ 352 */ 353 #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */ 354 #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */ 355 /** 356 * @} 357 */ 358 359 /** @defgroup CAN_identifier_type CAN Identifier Type 360 * @{ 361 */ 362 #define CAN_ID_STD (0x00000000U) /*!< Standard Id */ 363 #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request 369 * @{ 370 */ 371 #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ 372 #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number 378 * @{ 379 */ 380 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */ 381 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup CAN_flags CAN Flags 387 * @{ 388 */ 389 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() 390 and CAN_ClearFlag() functions. */ 391 /* If the flag is 0x1XXXXXXX, it means that it can only be used with 392 CAN_GetFlagStatus() function. */ 393 394 /* Transmit Flags */ 395 #define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */ 396 #define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */ 397 #define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */ 398 #define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */ 399 #define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */ 400 #define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */ 401 #define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ 402 #define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */ 403 #define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */ 404 405 /* Receive Flags */ 406 #define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */ 407 #define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */ 408 409 #define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */ 410 #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */ 411 412 /* Operating Mode Flags */ 413 #define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ 414 #define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ 415 #define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ 416 #define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */ 417 #define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */ 418 /* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. 419 In this case the SLAK bit can be polled.*/ 420 421 /* Error Flags */ 422 #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ 423 #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ 424 #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ 425 426 /** 427 * @} 428 */ 429 430 431 /** @defgroup CAN_interrupts CAN Interrupts 432 * @{ 433 */ 434 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ 435 436 /* Receive Interrupts */ 437 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ 438 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ 439 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ 440 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ 441 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ 442 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ 443 444 /* Operating Mode Interrupts */ 445 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ 446 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ 447 448 /* Error Interrupts */ 449 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ 450 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ 451 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ 452 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ 453 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ 454 455 /** 456 * @} 457 */ 458 459 /** @defgroup CAN_Mailboxes CAN Mailboxes 460 * @{ 461 */ 462 /* Mailboxes definition */ 463 #define CAN_TXMAILBOX_0 ((uint8_t)0x00U) 464 #define CAN_TXMAILBOX_1 ((uint8_t)0x01U) 465 #define CAN_TXMAILBOX_2 ((uint8_t)0x02U) 466 /** 467 * @} 468 */ 469 470 /** 471 * @} 472 */ 473 474 /* Exported macros -----------------------------------------------------------*/ 475 /** @defgroup CAN_Exported_Macros CAN Exported Macros 476 * @{ 477 */ 478 479 /** @brief Reset CAN handle state 480 * @param __HANDLE__ CAN handle. 481 * @retval None 482 */ 483 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) 484 485 /** 486 * @brief Enable the specified CAN interrupts. 487 * @param __HANDLE__ CAN handle. 488 * @param __INTERRUPT__ CAN Interrupt 489 * @retval None 490 */ 491 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 492 493 /** 494 * @brief Disable the specified CAN interrupts. 495 * @param __HANDLE__ CAN handle. 496 * @param __INTERRUPT__ CAN Interrupt 497 * @retval None 498 */ 499 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 500 501 /** 502 * @brief Return the number of pending received messages. 503 * @param __HANDLE__ CAN handle. 504 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. 505 * @retval The number of pending message. 506 */ 507 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ 508 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) 509 510 /** @brief Check whether the specified CAN flag is set or not. 511 * @param __HANDLE__ specifies the CAN Handle. 512 * @param __FLAG__ specifies the flag to check. 513 * This parameter can be one of the following values: 514 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag 515 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag 516 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag 517 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag 518 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag 519 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag 520 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag 521 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag 522 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag 523 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag 524 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag 525 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 526 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag 527 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag 528 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag 529 * @arg CAN_FLAG_WKU: Wake up Flag 530 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 531 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag 532 * @arg CAN_FLAG_EWG: Error Warning Flag 533 * @arg CAN_FLAG_EPV: Error Passive Flag 534 * @arg CAN_FLAG_BOF: Bus-Off Flag 535 * @retval The new state of __FLAG__ (TRUE or FALSE). 536 */ 537 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ 538 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 539 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 540 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 541 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 542 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) 543 544 /** @brief Clear the specified CAN pending flag. 545 * @param __HANDLE__ specifies the CAN Handle. 546 * @param __FLAG__ specifies the flag to check. 547 * This parameter can be one of the following values: 548 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag 549 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag 550 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag 551 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag 552 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag 553 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag 554 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag 555 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag 556 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag 557 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag 558 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag 559 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 560 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag 561 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag 562 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag 563 * @arg CAN_FLAG_WKU: Wake up Flag 564 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag 565 * @arg CAN_FLAG_EWG: Error Warning Flag 566 * @arg CAN_FLAG_EPV: Error Passive Flag 567 * @arg CAN_FLAG_BOF: Bus-Off Flag 568 * @retval The new state of __FLAG__ (TRUE or FALSE). 569 */ 570 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 571 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 572 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 573 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ 574 (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) 575 576 577 /** @brief Check if the specified CAN interrupt source is enabled or disabled. 578 * @param __HANDLE__ specifies the CAN Handle. 579 * @param __INTERRUPT__ specifies the CAN interrupt source to check. 580 * This parameter can be one of the following values: 581 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable 582 * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev 583 * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable 584 * @retval The new state of __IT__ (TRUE or FALSE). 585 */ 586 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 587 588 /** 589 * @brief Check the transmission status of a CAN Frame. 590 * @param __HANDLE__ CAN handle. 591 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. 592 * @retval The new status of transmission (TRUE or FALSE). 593 */ 594 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ 595 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ 596 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ 597 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) 598 599 /** 600 * @brief Release the specified receive FIFO. 601 * @param __HANDLE__ CAN handle. 602 * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. 603 * @retval None 604 */ 605 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ 606 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 607 608 /** 609 * @brief Cancel a transmit request. 610 * @param __HANDLE__ specifies the CAN Handle. 611 * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. 612 * @retval None 613 */ 614 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ 615 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ 616 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ 617 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) 618 619 /** 620 * @brief Enable or disables the DBG Freeze for CAN. 621 * @param __HANDLE__ specifies the CAN Handle. 622 * @param __NEWSTATE__ new state of the CAN peripheral. 623 * This parameter can be: ENABLE (CAN reception/transmission is frozen 624 * during debug. Reception FIFOs can still be accessed/controlled normally) 625 * or DISABLE (CAN is working during debug). 626 * @retval None 627 */ 628 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ 629 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 630 631 /** 632 * @} 633 */ 634 635 /* Exported functions --------------------------------------------------------*/ 636 /** @addtogroup CAN_Exported_Functions CAN Exported Functions 637 * @{ 638 */ 639 640 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 641 * @brief Initialization and Configuration functions 642 * @{ 643 */ 644 645 /* Initialization and de-initialization functions *****************************/ 646 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); 647 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); 648 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); 649 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); 650 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); 651 /** 652 * @} 653 */ 654 655 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions 656 * @brief I/O operation functions 657 * @{ 658 */ 659 /* IO operation functions *****************************************************/ 660 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); 661 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); 662 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); 663 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); 664 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); 665 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); 666 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); 667 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); 668 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); 669 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); 670 /** 671 * @} 672 */ 673 674 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions 675 * @brief CAN Peripheral State functions 676 * @{ 677 */ 678 /* Peripheral State and Error functions ***************************************/ 679 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); 680 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); 681 /** 682 * @} 683 */ 684 685 /** 686 * @} 687 */ 688 689 /* Private types -------------------------------------------------------------*/ 690 /** @defgroup CAN_Private_Types CAN Private Types 691 * @{ 692 */ 693 694 /** 695 * @} 696 */ 697 698 /* Private variables ---------------------------------------------------------*/ 699 /** @defgroup CAN_Private_Variables CAN Private Variables 700 * @{ 701 */ 702 703 /** 704 * @} 705 */ 706 707 /* Private constants ---------------------------------------------------------*/ 708 /** @defgroup CAN_Private_Constants CAN Private Constants 709 * @{ 710 */ 711 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ 712 #define CAN_FLAG_MASK (0x000000FFU) 713 /** 714 * @} 715 */ 716 717 /* Private Macros -----------------------------------------------------------*/ 718 /** @defgroup CAN_Private_Macros CAN Private Macros 719 * @{ 720 */ 721 722 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ 723 ((MODE) == CAN_MODE_LOOPBACK)|| \ 724 ((MODE) == CAN_MODE_SILENT) || \ 725 ((MODE) == CAN_MODE_SILENT_LOOPBACK)) 726 727 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ 728 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) 729 730 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) 731 732 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) 733 734 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) 735 736 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) 737 738 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ 739 ((MODE) == CAN_FILTERMODE_IDLIST)) 740 741 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ 742 ((SCALE) == CAN_FILTERSCALE_32BIT)) 743 744 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ 745 ((FIFO) == CAN_FILTER_FIFO1)) 746 747 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) 748 749 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U)) 750 #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU)) 751 #define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU)) 752 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U)) 753 754 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ 755 ((IDTYPE) == CAN_ID_EXT)) 756 757 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) 758 759 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) 760 761 #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ 762 ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ 763 ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ 764 ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ 765 ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ 766 ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ 767 ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) 768 769 #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ 770 ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ 771 ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ 772 ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ 773 ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ 774 ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) 775 776 /** 777 * @} 778 */ 779 /* End of private macros -----------------------------------------------------*/ 780 781 /** 782 * @} 783 */ 784 785 /** 786 * @} 787 */ 788 789 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ 790 /* STM32F302xC || STM32F303xC || STM32F358xx || */ 791 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ 792 /* STM32F302x8 || */ 793 /* STM32F373xC || STM32F378xx */ 794 795 #ifdef __cplusplus 796 } 797 #endif 798 799 #endif /* __STM32F3xx_HAL_CAN_LEGACY_H */ 800
