1 /**
2 ******************************************************************************
3 * @file stm32f2xx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 @verbatim
12 ==============================================================================
13 ##### How to use this driver #####
14 ==============================================================================
15
16 [..]
17 *** How to configure Interrupts using CORTEX HAL driver ***
18 ===========================================================
19 [..]
20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
21 The Cortex-M3 exceptions are managed by CMSIS functions.
22
23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
24 function according to the following table.
25 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
26 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
27 (#) please refer to programming manual for details in how to configure priority.
28
29 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
30 The pending IRQ priority will be managed only by the sub priority.
31
32 -@- IRQ priority order (sorted by highest to lowest priority):
33 (+@) Lowest preemption priority
34 (+@) Lowest sub priority
35 (+@) Lowest hardware priority (IRQ number)
36
37 [..]
38 *** How to configure Systick using CORTEX HAL driver ***
39 ========================================================
40 [..]
41 Setup SysTick Timer for time base.
42
43 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
44 is a CMSIS function that:
45 (++) Configures the SysTick Reload register with value passed as function parameter.
46 (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
47 (++) Resets the SysTick Counter register.
48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
49 (++) Enables the SysTick Interrupt.
50 (++) Starts the SysTick Counter.
51
52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
53 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
54 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
55 inside the stm32f2xx_hal_cortex.h file.
56
57 (+) You can change the SysTick IRQ priority by calling the
58 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
59 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
60
61 (+) To adjust the SysTick time base, use the following formula:
62
63 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
64 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
65 (++) Reload Value should not exceed 0xFFFFFF
66
67 @endverbatim
68 ******************************************************************************
69 * @attention
70 *
71 * Copyright (c) 2017 STMicroelectronics.
72 * All rights reserved.
73 *
74 * This software is licensed under terms that can be found in the LICENSE file in
75 * the root directory of this software component.
76 * If no LICENSE file comes with this software, it is provided AS-IS.
77 *
78 ******************************************************************************
79 */
80
81 /* Includes ------------------------------------------------------------------*/
82 #include "stm32f2xx_hal.h"
83
84 /** @addtogroup STM32F2xx_HAL_Driver
85 * @{
86 */
87
88 /** @defgroup CORTEX CORTEX
89 * @brief CORTEX HAL module driver
90 * @{
91 */
92
93 #ifdef HAL_CORTEX_MODULE_ENABLED
94
95 /* Private types -------------------------------------------------------------*/
96 /* Private variables ---------------------------------------------------------*/
97 /* Private constants ---------------------------------------------------------*/
98 /* Private macros ------------------------------------------------------------*/
99 /* Private functions ---------------------------------------------------------*/
100 /* Exported functions --------------------------------------------------------*/
101
102 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
103 * @{
104 */
105
106
107 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
108 * @brief Initialization and Configuration functions
109 *
110 @verbatim
111 ==============================================================================
112 ##### Initialization and de-initialization functions #####
113 ==============================================================================
114 [..]
115 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
116 Systick functionalities
117
118 @endverbatim
119 * @{
120 */
121
122
123 /**
124 * @brief Sets the priority grouping field (preemption priority and subpriority)
125 * using the required unlock sequence.
126 * @param PriorityGroup The priority grouping bits length.
127 * This parameter can be one of the following values:
128 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
129 * 4 bits for subpriority
130 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
131 * 3 bits for subpriority
132 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
133 * 2 bits for subpriority
134 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
135 * 1 bits for subpriority
136 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
137 * 0 bits for subpriority
138 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
139 * The pending IRQ priority will be managed only by the subpriority.
140 * @retval None
141 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)142 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
143 {
144 /* Check the parameters */
145 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
146
147 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
148 NVIC_SetPriorityGrouping(PriorityGroup);
149 }
150
151 /**
152 * @brief Sets the priority of an interrupt.
153 * @param IRQn External interrupt number.
154 * This parameter can be an enumerator of IRQn_Type enumeration
155 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
156 * @param PreemptPriority The preemption priority for the IRQn channel.
157 * This parameter can be a value between 0 and 15
158 * A lower priority value indicates a higher priority
159 * @param SubPriority the subpriority level for the IRQ channel.
160 * This parameter can be a value between 0 and 15
161 * A lower priority value indicates a higher priority.
162 * @retval None
163 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)164 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
165 {
166 uint32_t prioritygroup = 0x00U;
167
168 /* Check the parameters */
169 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
170 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
171
172 prioritygroup = NVIC_GetPriorityGrouping();
173
174 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
175 }
176
177 /**
178 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
179 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
180 * function should be called before.
181 * @param IRQn External interrupt number.
182 * This parameter can be an enumerator of IRQn_Type enumeration
183 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
184 * @retval None
185 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)186 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
187 {
188 /* Check the parameters */
189 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
190
191 /* Enable interrupt */
192 NVIC_EnableIRQ(IRQn);
193 }
194
195 /**
196 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
197 * @param IRQn External interrupt number.
198 * This parameter can be an enumerator of IRQn_Type enumeration
199 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
200 * @retval None
201 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)202 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
203 {
204 /* Check the parameters */
205 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
206
207 /* Disable interrupt */
208 NVIC_DisableIRQ(IRQn);
209 }
210
211 /**
212 * @brief Initiates a system reset request to reset the MCU.
213 * @retval None
214 */
HAL_NVIC_SystemReset(void)215 void HAL_NVIC_SystemReset(void)
216 {
217 /* System Reset */
218 NVIC_SystemReset();
219 }
220
221 /**
222 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
223 * Counter is in free running mode to generate periodic interrupts.
224 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
225 * @retval status: - 0 Function succeeded.
226 * - 1 Function failed.
227 */
HAL_SYSTICK_Config(uint32_t TicksNumb)228 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
229 {
230 return SysTick_Config(TicksNumb);
231 }
232 /**
233 * @}
234 */
235
236 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
237 * @brief Cortex control functions
238 *
239 @verbatim
240 ==============================================================================
241 ##### Peripheral Control functions #####
242 ==============================================================================
243 [..]
244 This subsection provides a set of functions allowing to control the CORTEX
245 (NVIC, SYSTICK, MPU) functionalities.
246
247
248 @endverbatim
249 * @{
250 */
251
252 #if (__MPU_PRESENT == 1U)
253 /**
254 * @brief Disables the MPU
255 * @retval None
256 */
HAL_MPU_Disable(void)257 void HAL_MPU_Disable(void)
258 {
259 /* Make sure outstanding transfers are done */
260 __DMB();
261
262 /* Disable fault exceptions */
263 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
264
265 /* Disable the MPU and clear the control register*/
266 MPU->CTRL = 0U;
267 }
268
269 /**
270 * @brief Enable the MPU.
271 * @param MPU_Control Specifies the control mode of the MPU during hard fault,
272 * NMI, FAULTMASK and privileged access to the default memory
273 * This parameter can be one of the following values:
274 * @arg MPU_HFNMI_PRIVDEF_NONE
275 * @arg MPU_HARDFAULT_NMI
276 * @arg MPU_PRIVILEGED_DEFAULT
277 * @arg MPU_HFNMI_PRIVDEF
278 * @retval None
279 */
HAL_MPU_Enable(uint32_t MPU_Control)280 void HAL_MPU_Enable(uint32_t MPU_Control)
281 {
282 /* Enable the MPU */
283 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
284
285 /* Enable fault exceptions */
286 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
287
288 /* Ensure MPU setting take effects */
289 __DSB();
290 __ISB();
291 }
292
293 /**
294 * @brief Enable the MPU Region.
295 * @retval None
296 */
HAL_MPU_EnableRegion(uint32_t RegionNumber)297 void HAL_MPU_EnableRegion(uint32_t RegionNumber)
298 {
299 /* Check the parameters */
300 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
301
302 /* Set the Region number */
303 MPU->RNR = RegionNumber;
304
305 /* Enable the Region */
306 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
307 }
308
309 /**
310 * @brief Disable the MPU Region.
311 * @retval None
312 */
HAL_MPU_DisableRegion(uint32_t RegionNumber)313 void HAL_MPU_DisableRegion(uint32_t RegionNumber)
314 {
315 /* Check the parameters */
316 assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
317
318 /* Set the Region number */
319 MPU->RNR = RegionNumber;
320
321 /* Disable the Region */
322 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
323 }
324
325 /**
326 * @brief Initializes and configures the Region and the memory to be protected.
327 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
328 * the initialization and configuration information.
329 * @retval None
330 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)331 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
332 {
333 /* Check the parameters */
334 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
335 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
336 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
337 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
338 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
339 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
340 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
341 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
342 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
343 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
344
345 /* Set the Region number */
346 MPU->RNR = MPU_Init->Number;
347
348 /* Disable the Region */
349 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
350
351 /* Apply configuration */
352 MPU->RBAR = MPU_Init->BaseAddress;
353 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
354 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
355 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
356 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
357 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
358 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
359 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
360 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
361 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
362 }
363 #endif /* __MPU_PRESENT */
364
365 /**
366 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
367 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
368 */
HAL_NVIC_GetPriorityGrouping(void)369 uint32_t HAL_NVIC_GetPriorityGrouping(void)
370 {
371 /* Get the PRIGROUP[10:8] field value */
372 return NVIC_GetPriorityGrouping();
373 }
374
375 /**
376 * @brief Gets the priority of an interrupt.
377 * @param IRQn External interrupt number.
378 * This parameter can be an enumerator of IRQn_Type enumeration
379 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
380 * @param PriorityGroup the priority grouping bits length.
381 * This parameter can be one of the following values:
382 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
383 * 4 bits for subpriority
384 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
385 * 3 bits for subpriority
386 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
387 * 2 bits for subpriority
388 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
389 * 1 bits for subpriority
390 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
391 * 0 bits for subpriority
392 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
393 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
394 * @retval None
395 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)396 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
397 {
398 /* Check the parameters */
399 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
400 /* Get priority for Cortex-M system or device specific interrupts */
401 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
402 }
403
404 /**
405 * @brief Sets Pending bit of an external interrupt.
406 * @param IRQn External interrupt number
407 * This parameter can be an enumerator of IRQn_Type enumeration
408 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
409 * @retval None
410 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)411 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
412 {
413 /* Check the parameters */
414 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
415
416 /* Set interrupt pending */
417 NVIC_SetPendingIRQ(IRQn);
418 }
419
420 /**
421 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
422 * and returns the pending bit for the specified interrupt).
423 * @param IRQn External interrupt number.
424 * This parameter can be an enumerator of IRQn_Type enumeration
425 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
426 * @retval status: - 0 Interrupt status is not pending.
427 * - 1 Interrupt status is pending.
428 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)429 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
430 {
431 /* Check the parameters */
432 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
433
434 /* Return 1 if pending else 0 */
435 return NVIC_GetPendingIRQ(IRQn);
436 }
437
438 /**
439 * @brief Clears the pending bit of an external interrupt.
440 * @param IRQn External interrupt number.
441 * This parameter can be an enumerator of IRQn_Type enumeration
442 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
443 * @retval None
444 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)445 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
446 {
447 /* Check the parameters */
448 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
449
450 /* Clear pending interrupt */
451 NVIC_ClearPendingIRQ(IRQn);
452 }
453
454 /**
455 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
456 * @param IRQn External interrupt number
457 * This parameter can be an enumerator of IRQn_Type enumeration
458 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f2xxxx.h))
459 * @retval status: - 0 Interrupt status is not pending.
460 * - 1 Interrupt status is pending.
461 */
HAL_NVIC_GetActive(IRQn_Type IRQn)462 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
463 {
464 /* Check the parameters */
465 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
466
467 /* Return 1 if active else 0 */
468 return NVIC_GetActive(IRQn);
469 }
470
471 /**
472 * @brief Configures the SysTick clock source.
473 * @param CLKSource specifies the SysTick clock source.
474 * This parameter can be one of the following values:
475 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
476 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
477 * @retval None
478 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)479 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
480 {
481 /* Check the parameters */
482 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
483 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
484 {
485 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
486 }
487 else
488 {
489 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
490 }
491 }
492
493 /**
494 * @brief This function handles SYSTICK interrupt request.
495 * @retval None
496 */
HAL_SYSTICK_IRQHandler(void)497 void HAL_SYSTICK_IRQHandler(void)
498 {
499 HAL_SYSTICK_Callback();
500 }
501
502 /**
503 * @brief SYSTICK callback.
504 * @retval None
505 */
HAL_SYSTICK_Callback(void)506 __weak void HAL_SYSTICK_Callback(void)
507 {
508 /* NOTE : This function Should not be modified, when the callback is needed,
509 the HAL_SYSTICK_Callback could be implemented in the user file
510 */
511 }
512
513 /**
514 * @}
515 */
516
517 /**
518 * @}
519 */
520
521 #endif /* HAL_CORTEX_MODULE_ENABLED */
522 /**
523 * @}
524 */
525
526 /**
527 * @}
528 */
529
530