1 /**
2 ******************************************************************************
3 * @file stm32f2xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32F2xx_LL_PWR_H
21 #define __STM32F2xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f2xx.h"
29
30 /** @addtogroup STM32F2xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /* Exported constants --------------------------------------------------------*/
46 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
47 * @{
48 */
49
50 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
51 * @brief Flags defines which can be used with LL_PWR_WriteReg function
52 * @{
53 */
54 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
55 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
56 /**
57 * @}
58 */
59
60 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
61 * @brief Flags defines which can be used with LL_PWR_ReadReg function
62 * @{
63 */
64 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
65 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
66 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
67 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
68 /**
69 * @}
70 */
71
72
73 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
74 * @{
75 */
76 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
77 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power regulator ON) when the CPU enters deepsleep */
78 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
79 /**
80 * @}
81 */
82
83 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
84 * @{
85 */
86 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */
87 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */
88 /**
89 * @}
90 */
91
92 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
93 * @{
94 */
95 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
96 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
97 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
98 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
99 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
100 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
101 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
102 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
103 /**
104 * @}
105 */
106 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
107 * @{
108 */
109 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
110 /**
111 * @}
112 */
113
114 /**
115 * @}
116 */
117
118
119 /* Exported macro ------------------------------------------------------------*/
120 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
121 * @{
122 */
123
124 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
125 * @{
126 */
127
128 /**
129 * @brief Write a value in PWR register
130 * @param __REG__ Register to be written
131 * @param __VALUE__ Value to be written in the register
132 * @retval None
133 */
134 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
135
136 /**
137 * @brief Read a value in PWR register
138 * @param __REG__ Register to be read
139 * @retval Register value
140 */
141 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
142 /**
143 * @}
144 */
145
146 /**
147 * @}
148 */
149
150 /* Exported functions --------------------------------------------------------*/
151 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
152 * @{
153 */
154
155 /** @defgroup PWR_LL_EF_Configuration Configuration
156 * @{
157 */
158 /**
159 * @brief Enable the Flash Power Down in Stop Mode
160 * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
161 * @retval None
162 */
LL_PWR_EnableFlashPowerDown(void)163 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
164 {
165 SET_BIT(PWR->CR, PWR_CR_FPDS);
166 }
167
168 /**
169 * @brief Disable the Flash Power Down in Stop Mode
170 * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
171 * @retval None
172 */
LL_PWR_DisableFlashPowerDown(void)173 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
174 {
175 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
176 }
177
178 /**
179 * @brief Check if the Flash Power Down in Stop Mode is enabled
180 * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
181 * @retval State of bit (1 or 0).
182 */
LL_PWR_IsEnabledFlashPowerDown(void)183 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
184 {
185 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
186 }
187
188 /**
189 * @brief Enable access to the backup domain
190 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
191 * @retval None
192 */
LL_PWR_EnableBkUpAccess(void)193 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
194 {
195 SET_BIT(PWR->CR, PWR_CR_DBP);
196 }
197
198 /**
199 * @brief Disable access to the backup domain
200 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
201 * @retval None
202 */
LL_PWR_DisableBkUpAccess(void)203 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
204 {
205 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
206 }
207
208 /**
209 * @brief Check if the backup domain is enabled
210 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
211 * @retval State of bit (1 or 0).
212 */
LL_PWR_IsEnabledBkUpAccess(void)213 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
214 {
215 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
216 }
217 /**
218 * @brief Enable the backup regulator
219 * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
220 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
221 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
222 * @retval None
223 */
LL_PWR_EnableBkUpRegulator(void)224 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
225 {
226 SET_BIT(PWR->CSR, PWR_CSR_BRE);
227 }
228
229 /**
230 * @brief Disable the backup Regulator
231 * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
232 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
233 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
234 * @retval None
235 */
LL_PWR_DisableBkUpRegulator(void)236 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
237 {
238 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
239 }
240
241 /**
242 * @brief Check if the backup Regulator is enabled
243 * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
244 * @retval State of bit (1 or 0).
245 */
LL_PWR_IsEnabledBkUpRegulator(void)246 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
247 {
248 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
249 }
250
251 /**
252 * @brief Set voltage regulator mode during deep sleep mode
253 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
254 * @param RegulMode This parameter can be one of the following values:
255 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
256 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
257 * @retval None
258 */
LL_PWR_SetRegulModeDS(uint32_t RegulMode)259 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
260 {
261 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
262 }
263
264 /**
265 * @brief Get voltage regulator mode during deep sleep mode
266 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
267 * @retval Returned value can be one of the following values:
268 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
269 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
270 */
LL_PWR_GetRegulModeDS(void)271 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
272 {
273 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
274 }
275
276 /**
277 * @brief Set power down mode when CPU enters deepsleep
278 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
279 * @rmtoll CR LPDS LL_PWR_SetPowerMode
280 * @param PDMode This parameter can be one of the following values:
281 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
282 * @arg @ref LL_PWR_MODE_STOP_LPREGU
283 * @arg @ref LL_PWR_MODE_STANDBY
284 * @retval None
285 */
LL_PWR_SetPowerMode(uint32_t PDMode)286 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
287 {
288 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
289 }
290
291 /**
292 * @brief Get power down mode when CPU enters deepsleep
293 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
294 * @rmtoll CR LPDS LL_PWR_GetPowerMode
295 * @retval Returned value can be one of the following values:
296 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
297 * @arg @ref LL_PWR_MODE_STOP_LPREGU
298 * @arg @ref LL_PWR_MODE_STANDBY
299 */
LL_PWR_GetPowerMode(void)300 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
301 {
302 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
303 }
304
305 /**
306 * @brief Configure the voltage threshold detected by the Power Voltage Detector
307 * @rmtoll CR PLS LL_PWR_SetPVDLevel
308 * @param PVDLevel This parameter can be one of the following values:
309 * @arg @ref LL_PWR_PVDLEVEL_0
310 * @arg @ref LL_PWR_PVDLEVEL_1
311 * @arg @ref LL_PWR_PVDLEVEL_2
312 * @arg @ref LL_PWR_PVDLEVEL_3
313 * @arg @ref LL_PWR_PVDLEVEL_4
314 * @arg @ref LL_PWR_PVDLEVEL_5
315 * @arg @ref LL_PWR_PVDLEVEL_6
316 * @arg @ref LL_PWR_PVDLEVEL_7
317 * @retval None
318 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)319 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
320 {
321 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
322 }
323
324 /**
325 * @brief Get the voltage threshold detection
326 * @rmtoll CR PLS LL_PWR_GetPVDLevel
327 * @retval Returned value can be one of the following values:
328 * @arg @ref LL_PWR_PVDLEVEL_0
329 * @arg @ref LL_PWR_PVDLEVEL_1
330 * @arg @ref LL_PWR_PVDLEVEL_2
331 * @arg @ref LL_PWR_PVDLEVEL_3
332 * @arg @ref LL_PWR_PVDLEVEL_4
333 * @arg @ref LL_PWR_PVDLEVEL_5
334 * @arg @ref LL_PWR_PVDLEVEL_6
335 * @arg @ref LL_PWR_PVDLEVEL_7
336 */
LL_PWR_GetPVDLevel(void)337 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
338 {
339 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
340 }
341
342 /**
343 * @brief Enable Power Voltage Detector
344 * @rmtoll CR PVDE LL_PWR_EnablePVD
345 * @retval None
346 */
LL_PWR_EnablePVD(void)347 __STATIC_INLINE void LL_PWR_EnablePVD(void)
348 {
349 SET_BIT(PWR->CR, PWR_CR_PVDE);
350 }
351
352 /**
353 * @brief Disable Power Voltage Detector
354 * @rmtoll CR PVDE LL_PWR_DisablePVD
355 * @retval None
356 */
LL_PWR_DisablePVD(void)357 __STATIC_INLINE void LL_PWR_DisablePVD(void)
358 {
359 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
360 }
361
362 /**
363 * @brief Check if Power Voltage Detector is enabled
364 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
365 * @retval State of bit (1 or 0).
366 */
LL_PWR_IsEnabledPVD(void)367 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
368 {
369 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
370 }
371
372 /**
373 * @brief Enable the WakeUp PINx functionality
374 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
375 * @param WakeUpPin This parameter can be one of the following values:
376 * @arg @ref LL_PWR_WAKEUP_PIN1
377 * @retval None
378 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)379 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
380 {
381 SET_BIT(PWR->CSR, WakeUpPin);
382 }
383
384 /**
385 * @brief Disable the WakeUp PINx functionality
386 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
387 * @param WakeUpPin This parameter can be one of the following values:
388 * @arg @ref LL_PWR_WAKEUP_PIN1
389 * @retval None
390 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)391 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
392 {
393 CLEAR_BIT(PWR->CSR, WakeUpPin);
394 }
395
396 /**
397 * @brief Check if the WakeUp PINx functionality is enabled
398 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
399 * @param WakeUpPin This parameter can be one of the following values:
400 * @arg @ref LL_PWR_WAKEUP_PIN1
401 * @retval State of bit (1 or 0).
402 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)403 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
404 {
405 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
406 }
407
408
409 /**
410 * @}
411 */
412
413 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
414 * @{
415 */
416
417 /**
418 * @brief Get Wake-up Flag
419 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
420 * @retval State of bit (1 or 0).
421 */
LL_PWR_IsActiveFlag_WU(void)422 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
423 {
424 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
425 }
426
427 /**
428 * @brief Get Standby Flag
429 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
430 * @retval State of bit (1 or 0).
431 */
LL_PWR_IsActiveFlag_SB(void)432 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
433 {
434 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
435 }
436
437 /**
438 * @brief Get Backup regulator ready Flag
439 * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
440 * @retval State of bit (1 or 0).
441 */
LL_PWR_IsActiveFlag_BRR(void)442 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
443 {
444 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
445 }
446 /**
447 * @brief Indicate whether VDD voltage is below the selected PVD threshold
448 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
449 * @retval State of bit (1 or 0).
450 */
LL_PWR_IsActiveFlag_PVDO(void)451 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
452 {
453 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
454 }
455
456 /**
457 * @brief Clear Standby Flag
458 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
459 * @retval None
460 */
LL_PWR_ClearFlag_SB(void)461 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
462 {
463 SET_BIT(PWR->CR, PWR_CR_CSBF);
464 }
465
466 /**
467 * @brief Clear Wake-up Flags
468 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
469 * @retval None
470 */
LL_PWR_ClearFlag_WU(void)471 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
472 {
473 SET_BIT(PWR->CR, PWR_CR_CWUF);
474 }
475 #if defined(USE_FULL_LL_DRIVER)
476 /** @defgroup PWR_LL_EF_Init De-initialization function
477 * @{
478 */
479 ErrorStatus LL_PWR_DeInit(void);
480 /**
481 * @}
482 */
483 #endif /* USE_FULL_LL_DRIVER */
484
485 /**
486 * @}
487 */
488
489 /**
490 * @}
491 */
492
493 /**
494 * @}
495 */
496
497 #endif /* defined(PWR) */
498
499 /**
500 * @}
501 */
502
503 #ifdef __cplusplus
504 }
505 #endif
506
507 #endif /* __STM32F2xx_LL_PWR_H */
508
