1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F1xx_LL_SDMMC_H 21 #define STM32F1xx_LL_SDMMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(SDIO) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32f1xx_hal_def.h" 31 32 /** @addtogroup STM32F1xx_Driver 33 * @{ 34 */ 35 36 /** @addtogroup SDMMC_LL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief SDMMC Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 51 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 52 53 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 54 enabled or disabled. 55 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 56 57 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 58 disabled when the bus is idle. 59 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 60 61 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 62 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 63 64 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 65 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 66 67 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 68 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 69 70 }SDIO_InitTypeDef; 71 72 73 /** 74 * @brief SDMMC Command Control structure 75 */ 76 typedef struct 77 { 78 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 79 to a card as part of a command message. If a command 80 contains an argument, it must be loaded into this register 81 before writing the command to the command register. */ 82 83 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 84 Max_Data = 64 */ 85 86 uint32_t Response; /*!< Specifies the SDMMC response type. 87 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 88 89 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 90 enabled or disabled. 91 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 92 93 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 94 is enabled or disabled. 95 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 96 }SDIO_CmdInitTypeDef; 97 98 99 /** 100 * @brief SDMMC Data Control structure 101 */ 102 typedef struct 103 { 104 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 105 106 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 107 108 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 109 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 110 111 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 112 is a read or write. 113 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 114 115 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 116 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 117 118 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 119 is enabled or disabled. 120 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 121 }SDIO_DataInitTypeDef; 122 123 /** 124 * @} 125 */ 126 127 /* Exported constants --------------------------------------------------------*/ 128 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 129 * @{ 130 */ 131 #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ 132 #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ 133 #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ 134 #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ 135 #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ 136 #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ 137 #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ 138 #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ 139 #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the 140 number of transferred bytes does not match the block length */ 141 #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ 142 #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ 143 #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ 144 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock 145 command or if there was an attempt to access a locked card */ 146 #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ 147 #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ 148 #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ 149 #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ 150 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ 151 #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ 152 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ 153 #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ 154 #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ 155 #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ 156 #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out 157 of erase sequence command was received */ 158 #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ 159 #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ 160 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ 161 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ 162 #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ 163 #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ 164 #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ 165 #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ 166 #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ 167 168 /** 169 * @brief SDMMC Commands Index 170 */ 171 #define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ 172 #define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ 173 #define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 174 #define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ 175 #define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ 176 #define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 177 operating condition register (OCR) content in the response on the CMD line. */ 178 #define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 179 #define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ 180 #define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 181 and asks the card whether card supports voltage. */ 182 #define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 183 #define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ 184 #define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ 185 #define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ 186 #define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ 187 #define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ 188 #define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ 189 #define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands 190 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 191 for SDHS and SDXC. */ 192 #define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 193 fixed 512 bytes in case of SDHC and SDXC. */ 194 #define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by 195 STOP_TRANSMISSION command. */ 196 #define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 197 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ 198 #define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ 199 #define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 200 fixed 512 bytes in case of SDHC and SDXC. */ 201 #define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 202 #define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ 203 #define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ 204 #define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ 205 #define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ 206 #define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ 207 #define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ 208 #define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ 209 #define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command 210 system set by switch function command (CMD6). */ 211 #define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. 212 Reserved for each command system set by switch function command (CMD6). */ 213 #define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ 214 #define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ 215 #define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ 216 #define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 217 the SET_BLOCK_LEN command. */ 218 #define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather 219 than a standard command. */ 220 #define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card 221 for general purpose/application specific commands. */ 222 #define SDMMC_CMD_NO_CMD 64U /*!< No command */ 223 224 /** 225 * @brief Following commands are SD Card Specific commands. 226 * SDMMC_APP_CMD should be sent before sending these commands. 227 */ 228 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 229 widths are given in SCR register. */ 230 #define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ 231 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 232 32bit+CRC data block. */ 233 #define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 234 send its operating condition register (OCR) content in the response on the CMD line. */ 235 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 236 #define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ 237 #define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ 238 #define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ 239 240 /** 241 * @brief Following commands are SD Card Specific security commands. 242 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 243 */ 244 #define SDMMC_CMD_SD_APP_GET_MKB 43U 245 #define SDMMC_CMD_SD_APP_GET_MID 44U 246 #define SDMMC_CMD_SD_APP_SET_CER_RN1 45U 247 #define SDMMC_CMD_SD_APP_GET_CER_RN2 46U 248 #define SDMMC_CMD_SD_APP_SET_CER_RES2 47U 249 #define SDMMC_CMD_SD_APP_GET_CER_RES1 48U 250 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U 251 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U 252 #define SDMMC_CMD_SD_APP_SECURE_ERASE 38U 253 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U 254 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U 255 256 /** 257 * @brief Masks for errors Card Status R1 (OCR Register) 258 */ 259 #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U 260 #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U 261 #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U 262 #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U 263 #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U 264 #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U 265 #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U 266 #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U 267 #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U 268 #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U 269 #define SDMMC_OCR_CC_ERROR 0x00100000U 270 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U 271 #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U 272 #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U 273 #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U 274 #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U 275 #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U 276 #define SDMMC_OCR_ERASE_RESET 0x00002000U 277 #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U 278 #define SDMMC_OCR_ERRORBITS 0xFDFFE008U 279 280 /** 281 * @brief Masks for R6 Response 282 */ 283 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U 284 #define SDMMC_R6_ILLEGAL_CMD 0x00004000U 285 #define SDMMC_R6_COM_CRC_FAILED 0x00008000U 286 287 #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U 288 #define SDMMC_HIGH_CAPACITY 0x40000000U 289 #define SDMMC_STD_CAPACITY 0x00000000U 290 #define SDMMC_CHECK_PATTERN 0x000001AAU 291 #define SD_SWITCH_1_8V_CAPACITY 0x01000000U 292 293 #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU 294 295 #define SDMMC_MAX_TRIAL 0x0000FFFFU 296 297 #define SDMMC_ALLZERO 0x00000000U 298 299 #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U 300 #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U 301 #define SDMMC_CARD_LOCKED 0x02000000U 302 303 #ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ 304 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 305 #endif /* SDMMC_DATATIMEOUT */ 306 307 #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ 308 #define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT 309 #endif /* SDMMC_SWDATATIMEOUT */ 310 311 #define SDMMC_0TO7BITS 0x000000FFU 312 #define SDMMC_8TO15BITS 0x0000FF00U 313 #define SDMMC_16TO23BITS 0x00FF0000U 314 #define SDMMC_24TO31BITS 0xFF000000U 315 #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU 316 317 #define SDMMC_HALFFIFO 0x00000008U 318 #define SDMMC_HALFFIFOBYTES 0x00000020U 319 320 /** 321 * @brief Command Class supported 322 */ 323 #define SDIO_CCCC_ERASE 0x00000020U 324 325 #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ 326 #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ 327 #define SDIO_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ 328 329 /** @defgroup SDIO_LL_Clock_Edge Clock Edge 330 * @{ 331 */ 332 #define SDIO_CLOCK_EDGE_RISING 0x00000000U 333 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE 334 335 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ 336 ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) 337 /** 338 * @} 339 */ 340 341 /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass 342 * @{ 343 */ 344 #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U 345 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS 346 347 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ 348 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) 349 /** 350 * @} 351 */ 352 353 /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving 354 * @{ 355 */ 356 #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U 357 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV 358 359 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ 360 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) 361 /** 362 * @} 363 */ 364 365 /** @defgroup SDIO_LL_Bus_Wide Bus Width 366 * @{ 367 */ 368 #define SDIO_BUS_WIDE_1B 0x00000000U 369 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 370 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 371 372 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ 373 ((WIDE) == SDIO_BUS_WIDE_4B) || \ 374 ((WIDE) == SDIO_BUS_WIDE_8B)) 375 /** 376 * @} 377 */ 378 379 /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control 380 * @{ 381 */ 382 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U 383 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN 384 385 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ 386 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) 387 /** 388 * @} 389 */ 390 391 /** @defgroup SDIO_LL_Clock_Division Clock Division 392 * @{ 393 */ 394 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) 395 /** 396 * @} 397 */ 398 399 /** @defgroup SDIO_LL_Command_Index Command Index 400 * @{ 401 */ 402 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 403 /** 404 * @} 405 */ 406 407 /** @defgroup SDIO_LL_Response_Type Response Type 408 * @{ 409 */ 410 #define SDIO_RESPONSE_NO 0x00000000U 411 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 412 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP 413 414 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ 415 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ 416 ((RESPONSE) == SDIO_RESPONSE_LONG)) 417 /** 418 * @} 419 */ 420 421 /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt 422 * @{ 423 */ 424 #define SDIO_WAIT_NO 0x00000000U 425 #define SDIO_WAIT_IT SDIO_CMD_WAITINT 426 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND 427 428 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ 429 ((WAIT) == SDIO_WAIT_IT) || \ 430 ((WAIT) == SDIO_WAIT_PEND)) 431 /** 432 * @} 433 */ 434 435 /** @defgroup SDIO_LL_CPSM_State CPSM State 436 * @{ 437 */ 438 #define SDIO_CPSM_DISABLE 0x00000000U 439 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN 440 441 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ 442 ((CPSM) == SDIO_CPSM_ENABLE)) 443 /** 444 * @} 445 */ 446 447 /** @defgroup SDIO_LL_Response_Registers Response Register 448 * @{ 449 */ 450 #define SDIO_RESP1 0x00000000U 451 #define SDIO_RESP2 0x00000004U 452 #define SDIO_RESP3 0x00000008U 453 #define SDIO_RESP4 0x0000000CU 454 455 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ 456 ((RESP) == SDIO_RESP2) || \ 457 ((RESP) == SDIO_RESP3) || \ 458 ((RESP) == SDIO_RESP4)) 459 /** 460 * @} 461 */ 462 463 /** @defgroup SDIO_LL_Data_Length Data Length 464 * @{ 465 */ 466 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 467 /** 468 * @} 469 */ 470 471 /** @defgroup SDIO_LL_Data_Block_Size Data Block Size 472 * @{ 473 */ 474 #define SDIO_DATABLOCK_SIZE_1B 0x00000000U 475 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 476 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 477 #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) 478 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 479 #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) 480 #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) 481 #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) 482 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 483 #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) 484 #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 485 #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 486 #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) 487 #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) 488 #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) 489 490 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ 491 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ 492 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ 493 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ 494 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ 495 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ 496 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ 497 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ 498 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ 499 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ 500 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ 501 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ 502 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ 503 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ 504 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 505 /** 506 * @} 507 */ 508 509 /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction 510 * @{ 511 */ 512 #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U 513 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR 514 515 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ 516 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) 517 /** 518 * @} 519 */ 520 521 /** @defgroup SDIO_LL_Transfer_Type Transfer Type 522 * @{ 523 */ 524 #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U 525 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE 526 527 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ 528 ((MODE) == SDIO_TRANSFER_MODE_STREAM)) 529 /** 530 * @} 531 */ 532 533 /** @defgroup SDIO_LL_DPSM_State DPSM State 534 * @{ 535 */ 536 #define SDIO_DPSM_DISABLE 0x00000000U 537 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN 538 539 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ 540 ((DPSM) == SDIO_DPSM_ENABLE)) 541 /** 542 * @} 543 */ 544 545 /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode 546 * @{ 547 */ 548 #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U 549 #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) 550 551 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ 552 ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) 553 /** 554 * @} 555 */ 556 557 /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources 558 * @{ 559 */ 560 #define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE 561 #define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE 562 #define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE 563 #define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE 564 #define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE 565 #define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE 566 #define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE 567 #define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE 568 #define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE 569 #define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE 570 #define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE 571 #define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE 572 #define SDIO_IT_TXACT SDIO_MASK_TXACTIE 573 #define SDIO_IT_RXACT SDIO_MASK_RXACTIE 574 #define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE 575 #define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE 576 #define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE 577 #define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE 578 #define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE 579 #define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE 580 #define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE 581 #define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE 582 #define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE 583 #define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE 584 /** 585 * @} 586 */ 587 588 /** @defgroup SDIO_LL_Flags Flags 589 * @{ 590 */ 591 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL 592 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL 593 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT 594 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT 595 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR 596 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR 597 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND 598 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT 599 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND 600 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR 601 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND 602 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT 603 #define SDIO_FLAG_TXACT SDIO_STA_TXACT 604 #define SDIO_FLAG_RXACT SDIO_STA_RXACT 605 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE 606 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF 607 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF 608 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF 609 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE 610 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE 611 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL 612 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL 613 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT 614 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND 615 #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ 616 SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ 617 SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ 618 SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT)) 619 620 #define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\ 621 SDIO_FLAG_CMDSENT)) 622 623 #define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\ 624 SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND)) 625 /** 626 * @} 627 */ 628 629 /** 630 * @} 631 */ 632 633 /* Exported macro ------------------------------------------------------------*/ 634 /** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros 635 * @{ 636 */ 637 638 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region 639 * @{ 640 */ 641 /* ------------ SDIO registers bit address in the alias region -------------- */ 642 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) 643 644 /* --- CLKCR Register ---*/ 645 /* Alias word address of CLKEN bit */ 646 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) 647 #define CLKEN_BITNUMBER 0x08U 648 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) 649 650 /* --- CMD Register ---*/ 651 /* Alias word address of SDIOSUSPEND bit */ 652 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU) 653 #define SDIOSUSPEND_BITNUMBER 0x0BU 654 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) 655 656 /* Alias word address of ENCMDCOMPL bit */ 657 #define ENCMDCOMPL_BITNUMBER 0x0CU 658 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) 659 660 /* Alias word address of NIEN bit */ 661 #define NIEN_BITNUMBER 0x0DU 662 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) 663 664 /* Alias word address of ATACMD bit */ 665 #define ATACMD_BITNUMBER 0x0EU 666 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) 667 668 /* --- DCTRL Register ---*/ 669 /* Alias word address of DMAEN bit */ 670 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) 671 #define DMAEN_BITNUMBER 0x03U 672 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) 673 674 /* Alias word address of RWSTART bit */ 675 #define RWSTART_BITNUMBER 0x08U 676 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) 677 678 /* Alias word address of RWSTOP bit */ 679 #define RWSTOP_BITNUMBER 0x09U 680 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) 681 682 /* Alias word address of RWMOD bit */ 683 #define RWMOD_BITNUMBER 0x0AU 684 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) 685 686 /* Alias word address of SDIOEN bit */ 687 #define SDIOEN_BITNUMBER 0x0BU 688 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) 689 /** 690 * @} 691 */ 692 693 /** @defgroup SDIO_LL_Register Bits And Addresses Definitions 694 * @brief SDIO_LL registers bit address in the alias region 695 * @{ 696 */ 697 /* ---------------------- SDIO registers bit mask --------------------------- */ 698 /* --- CLKCR Register ---*/ 699 /* CLKCR register clear mask */ 700 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ 701 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ 702 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) 703 704 /* --- DCTRL Register ---*/ 705 /* SDIO DCTRL Clear Mask */ 706 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ 707 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) 708 709 /* --- CMD Register ---*/ 710 /* CMD Register clear mask */ 711 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ 712 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ 713 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) 714 715 /* SDIO Initialization Frequency (400KHz max) */ 716 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ 717 718 /* SDIO Data Transfer Frequency (25MHz max) */ 719 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) 720 /** 721 * @} 722 */ 723 724 /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration 725 * @brief macros to handle interrupts and specific clock configurations 726 * @{ 727 */ 728 729 /** 730 * @brief Enable the SDIO device. 731 * @param __INSTANCE__: SDIO Instance 732 * @retval None 733 */ 734 #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) 735 736 /** 737 * @brief Disable the SDIO device. 738 * @param __INSTANCE__: SDIO Instance 739 * @retval None 740 */ 741 #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) 742 743 /** 744 * @brief Enable the SDIO DMA transfer. 745 * @param __INSTANCE__: SDIO Instance 746 * @retval None 747 */ 748 #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) 749 750 /** 751 * @brief Disable the SDIO DMA transfer. 752 * @param __INSTANCE__: SDIO Instance 753 * @retval None 754 */ 755 #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) 756 757 /** 758 * @brief Enable the SDIO device interrupt. 759 * @param __INSTANCE__ : Pointer to SDIO register base 760 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. 761 * This parameter can be one or a combination of the following values: 762 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 763 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 764 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 765 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 766 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 767 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 768 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 769 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 770 * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 771 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 772 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 773 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 774 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 775 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 776 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 777 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 778 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 779 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 780 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 781 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 782 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 783 * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt 784 * @retval None 785 */ 786 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 787 788 /** 789 * @brief Disable the SDIO device interrupt. 790 * @param __INSTANCE__ : Pointer to SDIO register base 791 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. 792 * This parameter can be one or a combination of the following values: 793 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 794 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 795 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 796 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 797 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 798 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 799 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 800 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 801 * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 802 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 803 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 804 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 805 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 806 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 807 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 808 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 809 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 810 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 811 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 812 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 813 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 814 * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt 815 * @retval None 816 */ 817 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 818 819 /** 820 * @brief Checks whether the specified SDIO flag is set or not. 821 * @param __INSTANCE__ : Pointer to SDIO register base 822 * @param __FLAG__: specifies the flag to check. 823 * This parameter can be one of the following values: 824 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) 825 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 826 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout 827 * @arg SDIO_FLAG_DTIMEOUT: Data timeout 828 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error 829 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error 830 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) 831 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) 832 * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 833 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) 834 * @arg SDIO_FLAG_CMDACT: Command transfer in progress 835 * @arg SDIO_FLAG_TXACT: Data transmit in progress 836 * @arg SDIO_FLAG_RXACT: Data receive in progress 837 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty 838 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full 839 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full 840 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full 841 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty 842 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty 843 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO 844 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO 845 * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received 846 * @retval The new state of SDIO_FLAG (SET or RESET). 847 */ 848 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 849 850 851 /** 852 * @brief Clears the SDIO pending flags. 853 * @param __INSTANCE__ : Pointer to SDIO register base 854 * @param __FLAG__: specifies the flag to clear. 855 * This parameter can be one or a combination of the following values: 856 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) 857 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 858 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout 859 * @arg SDIO_FLAG_DTIMEOUT: Data timeout 860 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error 861 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error 862 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) 863 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) 864 * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 865 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) 866 * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received 867 * @retval None 868 */ 869 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 870 871 /** 872 * @brief Checks whether the specified SDIO interrupt has occurred or not. 873 * @param __INSTANCE__ : Pointer to SDIO register base 874 * @param __INTERRUPT__: specifies the SDIO interrupt source to check. 875 * This parameter can be one of the following values: 876 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 877 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 878 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 879 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 880 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 881 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 882 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 883 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 884 * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 885 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 886 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt 887 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt 888 * @arg SDIO_IT_RXACT: Data receive in progress interrupt 889 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 890 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt 891 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt 892 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt 893 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt 894 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt 895 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt 896 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt 897 * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt 898 * @retval The new state of SDIO_IT (SET or RESET). 899 */ 900 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 901 902 /** 903 * @brief Clears the SDIO's interrupt pending bits. 904 * @param __INSTANCE__ : Pointer to SDIO register base 905 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 906 * This parameter can be one or a combination of the following values: 907 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 908 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 909 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt 910 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt 911 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt 912 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt 913 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt 914 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt 915 * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 916 * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt 917 * @retval None 918 */ 919 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 920 921 /** 922 * @brief Enable Start the SD I/O Read Wait operation. 923 * @param __INSTANCE__ : Pointer to SDIO register base 924 * @retval None 925 */ 926 #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) 927 928 /** 929 * @brief Disable Start the SD I/O Read Wait operations. 930 * @param __INSTANCE__ : Pointer to SDIO register base 931 * @retval None 932 */ 933 #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) 934 935 /** 936 * @brief Enable Start the SD I/O Read Wait operation. 937 * @param __INSTANCE__ : Pointer to SDIO register base 938 * @retval None 939 */ 940 #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) 941 942 /** 943 * @brief Disable Stop the SD I/O Read Wait operations. 944 * @param __INSTANCE__ : Pointer to SDIO register base 945 * @retval None 946 */ 947 #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) 948 949 /** 950 * @brief Enable the SD I/O Mode Operation. 951 * @param __INSTANCE__ : Pointer to SDIO register base 952 * @retval None 953 */ 954 #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) 955 956 /** 957 * @brief Disable the SD I/O Mode Operation. 958 * @param __INSTANCE__ : Pointer to SDIO register base 959 * @retval None 960 */ 961 #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) 962 963 /** 964 * @brief Enable the SD I/O Suspend command sending. 965 * @param __INSTANCE__ : Pointer to SDIO register base 966 * @retval None 967 */ 968 #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) 969 970 /** 971 * @brief Disable the SD I/O Suspend command sending. 972 * @param __INSTANCE__ : Pointer to SDIO register base 973 * @retval None 974 */ 975 #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) 976 977 /** 978 * @brief Enable the command completion signal. 979 * @retval None 980 */ 981 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) 982 983 /** 984 * @brief Disable the command completion signal. 985 * @retval None 986 */ 987 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) 988 989 /** 990 * @brief Enable the CE-ATA interrupt. 991 * @retval None 992 */ 993 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) 994 995 /** 996 * @brief Disable the CE-ATA interrupt. 997 * @retval None 998 */ 999 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) 1000 1001 /** 1002 * @brief Enable send CE-ATA command (CMD61). 1003 * @retval None 1004 */ 1005 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) 1006 1007 /** 1008 * @brief Disable send CE-ATA command (CMD61). 1009 * @retval None 1010 */ 1011 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) 1012 1013 /** 1014 * @} 1015 */ 1016 1017 /** 1018 * @} 1019 */ 1020 1021 /* Exported functions --------------------------------------------------------*/ 1022 /** @addtogroup SDMMC_LL_Exported_Functions 1023 * @{ 1024 */ 1025 1026 /* Initialization/de-initialization functions **********************************/ 1027 /** @addtogroup HAL_SDMMC_LL_Group1 1028 * @{ 1029 */ 1030 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); 1031 /** 1032 * @} 1033 */ 1034 1035 /* I/O operation functions *****************************************************/ 1036 /** @addtogroup HAL_SDMMC_LL_Group2 1037 * @{ 1038 */ 1039 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); 1040 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); 1041 /** 1042 * @} 1043 */ 1044 1045 /* Peripheral Control functions ************************************************/ 1046 /** @addtogroup HAL_SDMMC_LL_Group3 1047 * @{ 1048 */ 1049 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); 1050 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); 1051 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); 1052 1053 /* Command path state machine (CPSM) management functions */ 1054 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); 1055 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); 1056 uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); 1057 1058 /* Data path state machine (DPSM) management functions */ 1059 HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); 1060 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); 1061 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); 1062 1063 /* SDMMC Cards mode management functions */ 1064 HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); 1065 /** 1066 * @} 1067 */ 1068 1069 /* SDMMC Commands management functions */ 1070 /** @addtogroup HAL_SDMMC_LL_Group4 1071 * @{ 1072 */ 1073 uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); 1074 uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); 1075 uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); 1076 uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); 1077 uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); 1078 uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); 1079 uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); 1080 uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); 1081 uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); 1082 uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); 1083 uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); 1084 uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); 1085 uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); 1086 uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); 1087 uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); 1088 uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); 1089 uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); 1090 uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); 1091 uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); 1092 uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); 1093 uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); 1094 uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA); 1095 uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); 1096 uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); 1097 uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); 1098 uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); 1099 uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); 1100 /** 1101 * @} 1102 */ 1103 1104 /* SDMMC Responses management functions *****************************************/ 1105 /** @addtogroup HAL_SDMMC_LL_Group5 1106 * @{ 1107 */ 1108 uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); 1109 uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); 1110 uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); 1111 uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); 1112 uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); 1113 /** 1114 * @} 1115 */ 1116 1117 /** 1118 * @} 1119 */ 1120 1121 /** 1122 * @} 1123 */ 1124 1125 /** 1126 * @} 1127 */ 1128 1129 #endif /* SDIO */ 1130 1131 #ifdef __cplusplus 1132 } 1133 #endif 1134 1135 #endif /* STM32F1xx_LL_SDMMC_H */ 1136
