1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F1xx_LL_DAC_H
21 #define STM32F1xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f1xx.h"
29
30 /** @addtogroup STM32F1xx_LL_Driver
31 * @{
32 */
33
34 #if defined(DAC)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
55 CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
57 CR, MCR, CCR, SHHR, SHRR of channel 2 */
58 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
59
60 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
61 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
62 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
63
64 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
65 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
66 DHR12Rx channel 1 (shifted left of 20 bits) */
67 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
68 DHR12Rx channel 1 (shifted left of 24 bits) */
69
70 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
71 DHR12Rx channel 1 (shifted left of 16 bits) */
72 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
73 DHR12Rx channel 1 (shifted left of 20 bits) */
74 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
75 DHR12Rx channel 1 (shifted left of 24 bits) */
76
77 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
78 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
79 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
80 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
81 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
82
83 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
84
85 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
86 DORx channel 2 (shifted left of 28 bits) */
87 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
88
89
90 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
91 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
92 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
93 to position 0 */
94 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
95 to position 0 */
96
97 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
98 channel 1 or 2 versus DHR12Rx channel 1
99 (shifted left of 16 bits) */
100 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
101 channel 1 or 2 versus DHR12Rx channel 1
102 (shifted left of 20 bits) */
103 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
104 channel 1 or 2 versus DHR12Rx channel 1
105 (shifted left of 24 bits) */
106 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
107 channel 1 or 2 versus DORx channel 1
108 (shifted left of 28 bits) */
109
110 /* DAC registers bits positions */
111 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
112 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
113 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
114
115 /* Miscellaneous data */
116 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
117 bits (voltage range determined by analog voltage
118 references Vref+ and Vref-, refer to reference manual) */
119
120 /**
121 * @}
122 */
123
124
125 /* Private macros ------------------------------------------------------------*/
126 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
127 * @{
128 */
129
130 /**
131 * @brief Driver macro reserved for internal use: set a pointer to
132 * a register from a register basis from which an offset
133 * is applied.
134 * @param __REG__ Register basis from which the offset is applied.
135 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
136 * @retval Pointer to register address
137 */
138 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
139 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
140
141 /**
142 * @}
143 */
144
145
146 /* Exported types ------------------------------------------------------------*/
147 #if defined(USE_FULL_LL_DRIVER)
148 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
149 * @{
150 */
151
152 /**
153 * @brief Structure definition of some features of DAC instance.
154 */
155 typedef struct
156 {
157 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
158 internal (SW start) or from external peripheral
159 (timer event, external interrupt line).
160 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
161
162 This feature can be modified afterwards using unitary
163 function @ref LL_DAC_SetTriggerSource(). */
164
165 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
166 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
167
168 This feature can be modified afterwards using unitary
169 function @ref LL_DAC_SetWaveAutoGeneration(). */
170
171 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
172 If waveform automatic generation mode is set to noise, this parameter
173 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
174 If waveform automatic generation mode is set to triangle,
175 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
176 @note If waveform automatic generation mode is disabled,
177 this parameter is discarded.
178
179 This feature can be modified afterwards using unitary
180 function @ref LL_DAC_SetWaveNoiseLFSR(),
181 @ref LL_DAC_SetWaveTriangleAmplitude()
182 depending on the wave automatic generation selected. */
183
184 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
185 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
186
187 This feature can be modified afterwards using unitary
188 function @ref LL_DAC_SetOutputBuffer(). */
189 } LL_DAC_InitTypeDef;
190
191 /**
192 * @}
193 */
194 #endif /* USE_FULL_LL_DRIVER */
195
196 /* Exported constants --------------------------------------------------------*/
197 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
198 * @{
199 */
200
201 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
202 * @brief Flags defines which can be used with LL_DAC_ReadReg function
203 * @{
204 */
205 /* DAC channel 1 flags */
206 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
207
208 /* DAC channel 2 flags */
209 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
210
211 /**
212 * @}
213 */
214
215 /** @defgroup DAC_LL_EC_IT DAC interruptions
216 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
217 * @{
218 */
219 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
220
221 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
222
223 /**
224 * @}
225 */
226
227 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
228 * @{
229 */
230 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
231
232 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
233
234 /**
235 * @}
236 */
237
238 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
239 * @{
240 */
241 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
242 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */
243 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */
244 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */
245 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */
246 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */
247 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */
248 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */
249 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */
250 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
251 /**
252 * @}
253 */
254
255 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
256 * @{
257 */
258 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
259 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
260 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
261 /**
262 * @}
263 */
264
265 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
266 * @{
267 */
268 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
280 /**
281 * @}
282 */
283
284 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
285 * @{
286 */
287 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
288 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
289 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
290 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
291 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
292 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
293 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
294 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
295 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
296 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
297 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
298 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
299 /**
300 * @}
301 */
302
303 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
304 * @{
305 */
306 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
307 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
308 /**
309 * @}
310 */
311
312 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
313 * @{
314 */
315 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
316 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
317 /**
318 * @}
319 */
320
321 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
322 * @{
323 */
324 /* List of DAC registers intended to be used (most commonly) with */
325 /* DMA transfer. */
326 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
327 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
328 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
329 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
330 /**
331 * @}
332 */
333
334 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
335 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
336 * not timeout values.
337 * For details on delays values, refer to descriptions in source code
338 * above each literal definition.
339 * @{
340 */
341
342 /* Delay for DAC channel voltage settling time from DAC channel startup */
343 /* (transition from disable to enable). */
344 /* Note: DAC channel startup time depends on board application environment: */
345 /* impedance connected to DAC channel output. */
346 /* The delay below is specified under conditions: */
347 /* - voltage maximum transition (lowest to highest value) */
348 /* - until voltage reaches final value +-1LSB */
349 /* - DAC channel output buffer enabled */
350 /* - load impedance of 5kOhm (min), 50pF (max) */
351 /* Literal set to maximum value (refer to device datasheet, */
352 /* parameter "tWAKEUP"). */
353 /* Unit: us */
354 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
355
356 /* Delay for DAC channel voltage settling time. */
357 /* Note: DAC channel startup time depends on board application environment: */
358 /* impedance connected to DAC channel output. */
359 /* The delay below is specified under conditions: */
360 /* - voltage maximum transition (lowest to highest value) */
361 /* - until voltage reaches final value +-1LSB */
362 /* - DAC channel output buffer enabled */
363 /* - load impedance of 5kOhm min, 50pF max */
364 /* Literal set to maximum value (refer to device datasheet, */
365 /* parameter "tSETTLING"). */
366 /* Unit: us */
367 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */
368
369 /**
370 * @}
371 */
372
373 /**
374 * @}
375 */
376
377 /* Exported macro ------------------------------------------------------------*/
378 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
379 * @{
380 */
381
382 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
383 * @{
384 */
385
386 /**
387 * @brief Write a value in DAC register
388 * @param __INSTANCE__ DAC Instance
389 * @param __REG__ Register to be written
390 * @param __VALUE__ Value to be written in the register
391 * @retval None
392 */
393 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
394
395 /**
396 * @brief Read a value in DAC register
397 * @param __INSTANCE__ DAC Instance
398 * @param __REG__ Register to be read
399 * @retval Register value
400 */
401 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
402
403 /**
404 * @}
405 */
406
407 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
408 * @{
409 */
410
411 /**
412 * @brief Helper macro to get DAC channel number in decimal format
413 * from literals LL_DAC_CHANNEL_x.
414 * Example:
415 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
416 * will return decimal number "1".
417 * @note The input can be a value from functions where a channel
418 * number is returned.
419 * @param __CHANNEL__ This parameter can be one of the following values:
420 * @arg @ref LL_DAC_CHANNEL_1
421 * @arg @ref LL_DAC_CHANNEL_2
422 * @retval 1...2
423 */
424 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
425 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
426
427 /**
428 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
429 * from number in decimal format.
430 * Example:
431 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
432 * will return a data equivalent to "LL_DAC_CHANNEL_1".
433 * @note If the input parameter does not correspond to a DAC channel,
434 * this macro returns value '0'.
435 * @param __DECIMAL_NB__ 1...2
436 * @retval Returned value can be one of the following values:
437 * @arg @ref LL_DAC_CHANNEL_1
438 * @arg @ref LL_DAC_CHANNEL_2
439 */
440 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
441 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
442
443 /**
444 * @brief Helper macro to define the DAC conversion data full-scale digital
445 * value corresponding to the selected DAC resolution.
446 * @note DAC conversion data full-scale corresponds to voltage range
447 * determined by analog voltage references Vref+ and Vref-
448 * (refer to reference manual).
449 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
450 * @arg @ref LL_DAC_RESOLUTION_12B
451 * @arg @ref LL_DAC_RESOLUTION_8B
452 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
453 */
454 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
455 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
456
457 /**
458 * @brief Helper macro to calculate the DAC conversion data (unit: digital
459 * value) corresponding to a voltage (unit: mVolt).
460 * @note This helper macro is intended to provide input data in voltage
461 * rather than digital value,
462 * to be used with LL DAC functions such as
463 * @ref LL_DAC_ConvertData12RightAligned().
464 * @note Analog reference voltage (Vref+) must be either known from
465 * user board environment or can be calculated using ADC measurement
466 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
467 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
468 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
469 * (unit: mVolt).
470 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
471 * @arg @ref LL_DAC_RESOLUTION_12B
472 * @arg @ref LL_DAC_RESOLUTION_8B
473 * @retval DAC conversion data (unit: digital value)
474 */
475 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
476 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
477 / (__VREFANALOG_VOLTAGE__) \
478 )
479
480 /**
481 * @}
482 */
483
484 /**
485 * @}
486 */
487
488
489 /* Exported functions --------------------------------------------------------*/
490 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
491 * @{
492 */
493
494 /**
495 * @brief Set the conversion trigger source for the selected DAC channel.
496 * @note For conversion trigger source to be effective, DAC trigger
497 * must be enabled using function @ref LL_DAC_EnableTrigger().
498 * @note To set conversion trigger source, DAC channel must be disabled.
499 * Otherwise, the setting is discarded.
500 * @note Availability of parameters of trigger sources from timer
501 * depends on timers availability on the selected device.
502 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
503 * CR TSEL2 LL_DAC_SetTriggerSource
504 * @param DACx DAC instance
505 * @param DAC_Channel This parameter can be one of the following values:
506 * @arg @ref LL_DAC_CHANNEL_1
507 * @arg @ref LL_DAC_CHANNEL_2
508 * @param TriggerSource This parameter can be one of the following values:
509 * @arg @ref LL_DAC_TRIG_SOFTWARE
510 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
511 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
512 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
513 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
514 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
515 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
516 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
517 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
518 * @retval None
519 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)520 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
521 {
522 MODIFY_REG(DACx->CR,
523 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
524 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
525 }
526
527 /**
528 * @brief Get the conversion trigger source for the selected DAC channel.
529 * @note For conversion trigger source to be effective, DAC trigger
530 * must be enabled using function @ref LL_DAC_EnableTrigger().
531 * @note Availability of parameters of trigger sources from timer
532 * depends on timers availability on the selected device.
533 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
534 * CR TSEL2 LL_DAC_GetTriggerSource
535 * @param DACx DAC instance
536 * @param DAC_Channel This parameter can be one of the following values:
537 * @arg @ref LL_DAC_CHANNEL_1
538 * @arg @ref LL_DAC_CHANNEL_2
539 * @retval Returned value can be one of the following values:
540 * @arg @ref LL_DAC_TRIG_SOFTWARE
541 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
542 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
543 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
544 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
545 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
546 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
547 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
548 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
549 */
LL_DAC_GetTriggerSource(const DAC_TypeDef * DACx,uint32_t DAC_Channel)550 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
551 {
552 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
553 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
554 );
555 }
556
557 /**
558 * @brief Set the waveform automatic generation mode
559 * for the selected DAC channel.
560 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
561 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
562 * @param DACx DAC instance
563 * @param DAC_Channel This parameter can be one of the following values:
564 * @arg @ref LL_DAC_CHANNEL_1
565 * @arg @ref LL_DAC_CHANNEL_2
566 * @param WaveAutoGeneration This parameter can be one of the following values:
567 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
568 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
569 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
570 * @retval None
571 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)572 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
573 {
574 MODIFY_REG(DACx->CR,
575 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
576 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
577 }
578
579 /**
580 * @brief Get the waveform automatic generation mode
581 * for the selected DAC channel.
582 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
583 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
584 * @param DACx DAC instance
585 * @param DAC_Channel This parameter can be one of the following values:
586 * @arg @ref LL_DAC_CHANNEL_1
587 * @arg @ref LL_DAC_CHANNEL_2
588 * @retval Returned value can be one of the following values:
589 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
590 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
591 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
592 */
LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef * DACx,uint32_t DAC_Channel)593 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
594 {
595 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
596 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
597 );
598 }
599
600 /**
601 * @brief Set the noise waveform generation for the selected DAC channel:
602 * Noise mode and parameters LFSR (linear feedback shift register).
603 * @note For wave generation to be effective, DAC channel
604 * wave generation mode must be enabled using
605 * function @ref LL_DAC_SetWaveAutoGeneration().
606 * @note This setting can be set when the selected DAC channel is disabled
607 * (otherwise, the setting operation is ignored).
608 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
609 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
610 * @param DACx DAC instance
611 * @param DAC_Channel This parameter can be one of the following values:
612 * @arg @ref LL_DAC_CHANNEL_1
613 * @arg @ref LL_DAC_CHANNEL_2
614 * @param NoiseLFSRMask This parameter can be one of the following values:
615 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
616 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
617 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
619 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
620 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
621 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
622 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
623 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
624 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
625 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
626 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
627 * @retval None
628 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)629 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
630 {
631 MODIFY_REG(DACx->CR,
632 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
633 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
634 }
635
636 /**
637 * @brief Get the noise waveform generation for the selected DAC channel:
638 * Noise mode and parameters LFSR (linear feedback shift register).
639 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
640 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
641 * @param DACx DAC instance
642 * @param DAC_Channel This parameter can be one of the following values:
643 * @arg @ref LL_DAC_CHANNEL_1
644 * @arg @ref LL_DAC_CHANNEL_2
645 * @retval Returned value can be one of the following values:
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
652 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
654 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
655 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
656 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
657 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
658 */
LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef * DACx,uint32_t DAC_Channel)659 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
660 {
661 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
662 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
663 );
664 }
665
666 /**
667 * @brief Set the triangle waveform generation for the selected DAC channel:
668 * triangle mode and amplitude.
669 * @note For wave generation to be effective, DAC channel
670 * wave generation mode must be enabled using
671 * function @ref LL_DAC_SetWaveAutoGeneration().
672 * @note This setting can be set when the selected DAC channel is disabled
673 * (otherwise, the setting operation is ignored).
674 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
675 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
676 * @param DACx DAC instance
677 * @param DAC_Channel This parameter can be one of the following values:
678 * @arg @ref LL_DAC_CHANNEL_1
679 * @arg @ref LL_DAC_CHANNEL_2
680 * @param TriangleAmplitude This parameter can be one of the following values:
681 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
682 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
683 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
685 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
686 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
687 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
688 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
689 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
690 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
691 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
692 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
693 * @retval None
694 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)695 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
696 uint32_t TriangleAmplitude)
697 {
698 MODIFY_REG(DACx->CR,
699 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
700 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
701 }
702
703 /**
704 * @brief Get the triangle waveform generation for the selected DAC channel:
705 * triangle mode and amplitude.
706 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
707 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
708 * @param DACx DAC instance
709 * @param DAC_Channel This parameter can be one of the following values:
710 * @arg @ref LL_DAC_CHANNEL_1
711 * @arg @ref LL_DAC_CHANNEL_2
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
724 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
725 */
LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef * DACx,uint32_t DAC_Channel)726 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
727 {
728 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
729 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
730 );
731 }
732
733 /**
734 * @brief Set the output buffer for the selected DAC channel.
735 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
736 * CR BOFF2 LL_DAC_SetOutputBuffer
737 * @param DACx DAC instance
738 * @param DAC_Channel This parameter can be one of the following values:
739 * @arg @ref LL_DAC_CHANNEL_1
740 * @arg @ref LL_DAC_CHANNEL_2
741 * @param OutputBuffer This parameter can be one of the following values:
742 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
743 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
744 * @retval None
745 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)746 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
747 {
748 MODIFY_REG(DACx->CR,
749 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
750 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
751 }
752
753 /**
754 * @brief Get the output buffer state for the selected DAC channel.
755 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
756 * CR BOFF2 LL_DAC_GetOutputBuffer
757 * @param DACx DAC instance
758 * @param DAC_Channel This parameter can be one of the following values:
759 * @arg @ref LL_DAC_CHANNEL_1
760 * @arg @ref LL_DAC_CHANNEL_2
761 * @retval Returned value can be one of the following values:
762 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
763 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
764 */
LL_DAC_GetOutputBuffer(const DAC_TypeDef * DACx,uint32_t DAC_Channel)765 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
766 {
767 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
768 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
769 );
770 }
771
772 /**
773 * @}
774 */
775
776 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
777 * @{
778 */
779
780 /**
781 * @brief Enable DAC DMA transfer request of the selected channel.
782 * @note To configure DMA source address (peripheral address),
783 * use function @ref LL_DAC_DMA_GetRegAddr().
784 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
785 * CR DMAEN2 LL_DAC_EnableDMAReq
786 * @param DACx DAC instance
787 * @param DAC_Channel This parameter can be one of the following values:
788 * @arg @ref LL_DAC_CHANNEL_1
789 * @arg @ref LL_DAC_CHANNEL_2
790 * @retval None
791 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)792 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
793 {
794 SET_BIT(DACx->CR,
795 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
796 }
797
798 /**
799 * @brief Disable DAC DMA transfer request of the selected channel.
800 * @note To configure DMA source address (peripheral address),
801 * use function @ref LL_DAC_DMA_GetRegAddr().
802 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
803 * CR DMAEN2 LL_DAC_DisableDMAReq
804 * @param DACx DAC instance
805 * @param DAC_Channel This parameter can be one of the following values:
806 * @arg @ref LL_DAC_CHANNEL_1
807 * @arg @ref LL_DAC_CHANNEL_2
808 * @retval None
809 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)810 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
811 {
812 CLEAR_BIT(DACx->CR,
813 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
814 }
815
816 /**
817 * @brief Get DAC DMA transfer request state of the selected channel.
818 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
819 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
820 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
821 * @param DACx DAC instance
822 * @param DAC_Channel This parameter can be one of the following values:
823 * @arg @ref LL_DAC_CHANNEL_1
824 * @arg @ref LL_DAC_CHANNEL_2
825 * @retval State of bit (1 or 0).
826 */
LL_DAC_IsDMAReqEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)827 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
828 {
829 return ((READ_BIT(DACx->CR,
830 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
831 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
832 }
833
834 /**
835 * @brief Function to help to configure DMA transfer to DAC: retrieve the
836 * DAC register address from DAC instance and a list of DAC registers
837 * intended to be used (most commonly) with DMA transfer.
838 * @note These DAC registers are data holding registers:
839 * when DAC conversion is requested, DAC generates a DMA transfer
840 * request to have data available in DAC data holding registers.
841 * @note This macro is intended to be used with LL DMA driver, refer to
842 * function "LL_DMA_ConfigAddresses()".
843 * Example:
844 * LL_DMA_ConfigAddresses(DMA1,
845 * LL_DMA_CHANNEL_1,
846 * (uint32_t)&< array or variable >,
847 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
848 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
849 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
850 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
851 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
852 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
853 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
854 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
855 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
856 * @param DACx DAC instance
857 * @param DAC_Channel This parameter can be one of the following values:
858 * @arg @ref LL_DAC_CHANNEL_1
859 * @arg @ref LL_DAC_CHANNEL_2
860 * @param Register This parameter can be one of the following values:
861 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
862 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
863 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
864 * @retval DAC register address
865 */
LL_DAC_DMA_GetRegAddr(const DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)866 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
867 {
868 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
869 /* DAC channel selected. */
870 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
871 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
872 }
873 /**
874 * @}
875 */
876
877 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
878 * @{
879 */
880
881 /**
882 * @brief Enable DAC selected channel.
883 * @rmtoll CR EN1 LL_DAC_Enable\n
884 * CR EN2 LL_DAC_Enable
885 * @note After enable from off state, DAC channel requires a delay
886 * for output voltage to reach accuracy +/- 1 LSB.
887 * Refer to device datasheet, parameter "tWAKEUP".
888 * @param DACx DAC instance
889 * @param DAC_Channel This parameter can be one of the following values:
890 * @arg @ref LL_DAC_CHANNEL_1
891 * @arg @ref LL_DAC_CHANNEL_2
892 * @retval None
893 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)894 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
895 {
896 SET_BIT(DACx->CR,
897 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
898 }
899
900 /**
901 * @brief Disable DAC selected channel.
902 * @rmtoll CR EN1 LL_DAC_Disable\n
903 * CR EN2 LL_DAC_Disable
904 * @param DACx DAC instance
905 * @param DAC_Channel This parameter can be one of the following values:
906 * @arg @ref LL_DAC_CHANNEL_1
907 * @arg @ref LL_DAC_CHANNEL_2
908 * @retval None
909 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)910 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
911 {
912 CLEAR_BIT(DACx->CR,
913 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
914 }
915
916 /**
917 * @brief Get DAC enable state of the selected channel.
918 * (0: DAC channel is disabled, 1: DAC channel is enabled)
919 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
920 * CR EN2 LL_DAC_IsEnabled
921 * @param DACx DAC instance
922 * @param DAC_Channel This parameter can be one of the following values:
923 * @arg @ref LL_DAC_CHANNEL_1
924 * @arg @ref LL_DAC_CHANNEL_2
925 * @retval State of bit (1 or 0).
926 */
LL_DAC_IsEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)927 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
928 {
929 return ((READ_BIT(DACx->CR,
930 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
931 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
932 }
933
934 /**
935 * @brief Enable DAC trigger of the selected channel.
936 * @note - If DAC trigger is disabled, DAC conversion is performed
937 * automatically once the data holding register is updated,
938 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
939 * @ref LL_DAC_ConvertData12RightAligned(), ...
940 * - If DAC trigger is enabled, DAC conversion is performed
941 * only when a hardware of software trigger event is occurring.
942 * Select trigger source using
943 * function @ref LL_DAC_SetTriggerSource().
944 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
945 * CR TEN2 LL_DAC_EnableTrigger
946 * @param DACx DAC instance
947 * @param DAC_Channel This parameter can be one of the following values:
948 * @arg @ref LL_DAC_CHANNEL_1
949 * @arg @ref LL_DAC_CHANNEL_2
950 * @retval None
951 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)952 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
953 {
954 SET_BIT(DACx->CR,
955 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
956 }
957
958 /**
959 * @brief Disable DAC trigger of the selected channel.
960 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
961 * CR TEN2 LL_DAC_DisableTrigger
962 * @param DACx DAC instance
963 * @param DAC_Channel This parameter can be one of the following values:
964 * @arg @ref LL_DAC_CHANNEL_1
965 * @arg @ref LL_DAC_CHANNEL_2
966 * @retval None
967 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)968 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
969 {
970 CLEAR_BIT(DACx->CR,
971 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
972 }
973
974 /**
975 * @brief Get DAC trigger state of the selected channel.
976 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
977 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
978 * CR TEN2 LL_DAC_IsTriggerEnabled
979 * @param DACx DAC instance
980 * @param DAC_Channel This parameter can be one of the following values:
981 * @arg @ref LL_DAC_CHANNEL_1
982 * @arg @ref LL_DAC_CHANNEL_2
983 * @retval State of bit (1 or 0).
984 */
LL_DAC_IsTriggerEnabled(const DAC_TypeDef * DACx,uint32_t DAC_Channel)985 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
986 {
987 return ((READ_BIT(DACx->CR,
988 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
989 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
990 }
991
992 /**
993 * @brief Trig DAC conversion by software for the selected DAC channel.
994 * @note Preliminarily, DAC trigger must be set to software trigger
995 * using function
996 * @ref LL_DAC_Init()
997 * @ref LL_DAC_SetTriggerSource()
998 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
999 * and DAC trigger must be enabled using
1000 * function @ref LL_DAC_EnableTrigger().
1001 * @note For devices featuring DAC with 2 channels: this function
1002 * can perform a SW start of both DAC channels simultaneously.
1003 * Two channels can be selected as parameter.
1004 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1005 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1006 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1007 * @param DACx DAC instance
1008 * @param DAC_Channel This parameter can a combination of the following values:
1009 * @arg @ref LL_DAC_CHANNEL_1
1010 * @arg @ref LL_DAC_CHANNEL_2
1011 * @retval None
1012 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1013 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1014 {
1015 SET_BIT(DACx->SWTRIGR,
1016 (DAC_Channel & DAC_SWTR_CHX_MASK));
1017 }
1018
1019 /**
1020 * @brief Set the data to be loaded in the data holding register
1021 * in format 12 bits left alignment (LSB aligned on bit 0),
1022 * for the selected DAC channel.
1023 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1024 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1025 * @param DACx DAC instance
1026 * @param DAC_Channel This parameter can be one of the following values:
1027 * @arg @ref LL_DAC_CHANNEL_1
1028 * @arg @ref LL_DAC_CHANNEL_2
1029 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1030 * @retval None
1031 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1032 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1033 {
1034 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1035 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1036
1037 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1038 }
1039
1040 /**
1041 * @brief Set the data to be loaded in the data holding register
1042 * in format 12 bits left alignment (MSB aligned on bit 15),
1043 * for the selected DAC channel.
1044 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1045 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1046 * @param DACx DAC instance
1047 * @param DAC_Channel This parameter can be one of the following values:
1048 * @arg @ref LL_DAC_CHANNEL_1
1049 * @arg @ref LL_DAC_CHANNEL_2
1050 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1051 * @retval None
1052 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1053 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1054 {
1055 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1056 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1057
1058 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1059 }
1060
1061 /**
1062 * @brief Set the data to be loaded in the data holding register
1063 * in format 8 bits left alignment (LSB aligned on bit 0),
1064 * for the selected DAC channel.
1065 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1066 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1067 * @param DACx DAC instance
1068 * @param DAC_Channel This parameter can be one of the following values:
1069 * @arg @ref LL_DAC_CHANNEL_1
1070 * @arg @ref LL_DAC_CHANNEL_2
1071 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1072 * @retval None
1073 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1074 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1075 {
1076 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1077 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1078
1079 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1080 }
1081
1082
1083 /**
1084 * @brief Set the data to be loaded in the data holding register
1085 * in format 12 bits left alignment (LSB aligned on bit 0),
1086 * for both DAC channels.
1087 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1088 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1089 * @param DACx DAC instance
1090 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1091 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1092 * @retval None
1093 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1094 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1095 uint32_t DataChannel2)
1096 {
1097 MODIFY_REG(DACx->DHR12RD,
1098 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1099 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1100 }
1101
1102 /**
1103 * @brief Set the data to be loaded in the data holding register
1104 * in format 12 bits left alignment (MSB aligned on bit 15),
1105 * for both DAC channels.
1106 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1107 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1108 * @param DACx DAC instance
1109 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1110 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1111 * @retval None
1112 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1113 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1114 uint32_t DataChannel2)
1115 {
1116 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1117 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1118 /* the 4 LSB must be taken into account for the shift value. */
1119 MODIFY_REG(DACx->DHR12LD,
1120 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1121 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1122 }
1123
1124 /**
1125 * @brief Set the data to be loaded in the data holding register
1126 * in format 8 bits left alignment (LSB aligned on bit 0),
1127 * for both DAC channels.
1128 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1129 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1130 * @param DACx DAC instance
1131 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1132 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1133 * @retval None
1134 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1135 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1136 uint32_t DataChannel2)
1137 {
1138 MODIFY_REG(DACx->DHR8RD,
1139 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1140 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1141 }
1142
1143
1144 /**
1145 * @brief Retrieve output data currently generated for the selected DAC channel.
1146 * @note Whatever alignment and resolution settings
1147 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1148 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1149 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1150 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1151 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1152 * @param DACx DAC instance
1153 * @param DAC_Channel This parameter can be one of the following values:
1154 * @arg @ref LL_DAC_CHANNEL_1
1155 * @arg @ref LL_DAC_CHANNEL_2
1156 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1157 */
LL_DAC_RetrieveOutputData(const DAC_TypeDef * DACx,uint32_t DAC_Channel)1158 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1159 {
1160 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1161 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1162
1163 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1164 }
1165
1166 /**
1167 * @}
1168 */
1169
1170 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1171 * @{
1172 */
1173
1174 #if defined(DAC_SR_DMAUDR1)
1175 /**
1176 * @brief Get DAC underrun flag for DAC channel 1
1177 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1178 * @param DACx DAC instance
1179 * @retval State of bit (1 or 0).
1180 */
LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef * DACx)1181 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1182 {
1183 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1184 }
1185 #endif /* DAC_SR_DMAUDR1 */
1186
1187 #if defined(DAC_SR_DMAUDR2)
1188 /**
1189 * @brief Get DAC underrun flag for DAC channel 2
1190 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1191 * @param DACx DAC instance
1192 * @retval State of bit (1 or 0).
1193 */
LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef * DACx)1194 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1195 {
1196 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1197 }
1198 #endif /* DAC_SR_DMAUDR2 */
1199
1200 #if defined(DAC_SR_DMAUDR1)
1201 /**
1202 * @brief Clear DAC underrun flag for DAC channel 1
1203 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1204 * @param DACx DAC instance
1205 * @retval None
1206 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1207 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1208 {
1209 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1210 }
1211 #endif /* DAC_SR_DMAUDR1 */
1212
1213 #if defined(DAC_SR_DMAUDR2)
1214 /**
1215 * @brief Clear DAC underrun flag for DAC channel 2
1216 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1217 * @param DACx DAC instance
1218 * @retval None
1219 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1220 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1221 {
1222 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1223 }
1224 #endif /* DAC_SR_DMAUDR2 */
1225
1226 /**
1227 * @}
1228 */
1229
1230 /** @defgroup DAC_LL_EF_IT_Management IT management
1231 * @{
1232 */
1233
1234 #if defined(DAC_CR_DMAUDRIE1)
1235 /**
1236 * @brief Enable DMA underrun interrupt for DAC channel 1
1237 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1238 * @param DACx DAC instance
1239 * @retval None
1240 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1241 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1242 {
1243 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1244 }
1245 #endif /* DAC_CR_DMAUDRIE1 */
1246
1247 #if defined(DAC_CR_DMAUDRIE2)
1248 /**
1249 * @brief Enable DMA underrun interrupt for DAC channel 2
1250 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1251 * @param DACx DAC instance
1252 * @retval None
1253 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1254 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1255 {
1256 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1257 }
1258 #endif /* DAC_CR_DMAUDRIE2 */
1259
1260 #if defined(DAC_CR_DMAUDRIE1)
1261 /**
1262 * @brief Disable DMA underrun interrupt for DAC channel 1
1263 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1264 * @param DACx DAC instance
1265 * @retval None
1266 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1267 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1268 {
1269 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1270 }
1271 #endif /* DAC_CR_DMAUDRIE1 */
1272
1273 #if defined(DAC_CR_DMAUDRIE2)
1274 /**
1275 * @brief Disable DMA underrun interrupt for DAC channel 2
1276 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1277 * @param DACx DAC instance
1278 * @retval None
1279 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1280 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1281 {
1282 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1283 }
1284 #endif /* DAC_CR_DMAUDRIE2 */
1285
1286 #if defined(DAC_CR_DMAUDRIE1)
1287 /**
1288 * @brief Get DMA underrun interrupt for DAC channel 1
1289 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1290 * @param DACx DAC instance
1291 * @retval State of bit (1 or 0).
1292 */
LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef * DACx)1293 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1294 {
1295 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1296 }
1297 #endif /* DAC_CR_DMAUDRIE1 */
1298
1299 #if defined(DAC_CR_DMAUDRIE2)
1300 /**
1301 * @brief Get DMA underrun interrupt for DAC channel 2
1302 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1303 * @param DACx DAC instance
1304 * @retval State of bit (1 or 0).
1305 */
LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef * DACx)1306 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1307 {
1308 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1309 }
1310 #endif /* DAC_CR_DMAUDRIE2 */
1311
1312 /**
1313 * @}
1314 */
1315
1316 #if defined(USE_FULL_LL_DRIVER)
1317 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1318 * @{
1319 */
1320
1321 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1322 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1323 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1324
1325 /**
1326 * @}
1327 */
1328 #endif /* USE_FULL_LL_DRIVER */
1329
1330 /**
1331 * @}
1332 */
1333
1334 /**
1335 * @}
1336 */
1337
1338 #endif /* DAC */
1339
1340 /**
1341 * @}
1342 */
1343
1344 #ifdef __cplusplus
1345 }
1346 #endif
1347
1348 #endif /* STM32F1xx_LL_DAC_H */
1349
