1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #endif /* STM32H7 || STM32MP1 */ 46 /** 47 * @} 48 */ 49 50 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 51 * @{ 52 */ 53 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 54 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 55 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 56 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 57 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 58 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 59 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 60 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 61 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 62 #define REGULAR_GROUP ADC_REGULAR_GROUP 63 #define INJECTED_GROUP ADC_INJECTED_GROUP 64 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 65 #define AWD_EVENT ADC_AWD_EVENT 66 #define AWD1_EVENT ADC_AWD1_EVENT 67 #define AWD2_EVENT ADC_AWD2_EVENT 68 #define AWD3_EVENT ADC_AWD3_EVENT 69 #define OVR_EVENT ADC_OVR_EVENT 70 #define JQOVF_EVENT ADC_JQOVF_EVENT 71 #define ALL_CHANNELS ADC_ALL_CHANNELS 72 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 73 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 74 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 75 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 76 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 77 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 78 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 79 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 80 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 81 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 82 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 83 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 84 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 85 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 86 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 87 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 88 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 89 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 90 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 91 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 92 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 93 94 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 95 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 96 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 97 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 98 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 99 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 100 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 101 102 #if defined(STM32H7) 103 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 104 #endif /* STM32H7 */ 105 106 #if defined(STM32U5) 107 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 108 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 109 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 110 #endif /* STM32U5 */ 111 112 #if defined(STM32H5) 113 #define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE 114 #endif /* STM32H5 */ 115 /** 116 * @} 117 */ 118 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 120 * @{ 121 */ 122 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 130 * @{ 131 */ 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 141 #if defined(STM32L0) 142 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM 143 input 1 for COMP1, LPTIM input 2 for COMP2 */ 144 #endif 145 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 146 #if defined(STM32F373xC) || defined(STM32F378xx) 147 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 148 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 149 #endif /* STM32F373xC || STM32F378xx */ 150 151 #if defined(STM32L0) || defined(STM32L4) 152 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 153 154 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 155 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 156 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 157 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 158 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 159 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 160 161 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 162 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 163 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 164 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 165 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 166 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 168 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 169 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 170 #if defined(STM32L0) 171 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 172 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 173 /* to the second dedicated IO (only for COMP2). */ 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 176 #else 177 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 178 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 179 #endif 180 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 181 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 182 183 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 184 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 185 186 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 187 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 188 #if defined(COMP_CSR_LOCK) 189 #define COMP_FLAG_LOCK COMP_CSR_LOCK 190 #elif defined(COMP_CSR_COMP1LOCK) 191 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 192 #elif defined(COMP_CSR_COMPxLOCK) 193 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 194 #endif 195 196 #if defined(STM32L4) 197 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 198 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 199 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 200 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 201 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 202 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 203 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 204 #endif 205 206 #if defined(STM32L0) 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 208 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 209 #else 210 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 211 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 212 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 213 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 214 #endif 215 216 #endif 217 218 #if defined(STM32U5) 219 #define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG 220 #endif 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 227 * @{ 228 */ 229 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 230 #if defined(STM32U5) 231 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 232 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 233 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 234 #endif /* STM32U5 */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup CRC_Aliases CRC API aliases 240 * @{ 241 */ 242 #if defined(STM32H5) || defined(STM32C0) 243 #else 244 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 245 inter STM32 series compatibility */ 246 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 247 inter STM32 series compatibility */ 248 #endif 249 /** 250 * @} 251 */ 252 253 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 254 * @{ 255 */ 256 257 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 258 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 259 260 /** 261 * @} 262 */ 263 264 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 265 * @{ 266 */ 267 268 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 269 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 270 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 271 #define DAC_WAVE_NONE 0x00000000U 272 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 273 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 274 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 275 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 276 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 277 278 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 279 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 280 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 281 #endif 282 283 #if defined(STM32U5) 284 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 285 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 286 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 287 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 288 #endif 289 290 #if defined(STM32H5) 291 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 292 #define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 293 #endif 294 295 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ 296 defined(STM32F4) || defined(STM32G4) 297 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 298 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 299 #endif 300 301 /** 302 * @} 303 */ 304 305 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 306 * @{ 307 */ 308 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 309 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 310 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 311 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 312 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 313 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 314 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 315 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 316 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 317 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 318 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 319 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 320 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 321 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 322 323 #define IS_HAL_REMAPDMA IS_DMA_REMAP 324 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 325 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 326 327 #if defined(STM32L4) 328 329 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 330 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 331 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 332 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 333 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 334 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 335 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 336 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 337 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 338 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 339 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 340 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 341 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 342 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 343 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 344 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 345 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 346 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 347 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 348 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 349 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 350 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 351 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 352 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 353 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 354 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 355 356 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 357 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 358 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 359 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 360 361 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ 362 defined(STM32L4S7xx) || defined(STM32L4S9xx) 363 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 364 #endif 365 366 #endif /* STM32L4 */ 367 368 #if defined(STM32G0) 369 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 370 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 371 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 372 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 373 374 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 375 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 376 #endif 377 378 #if defined(STM32H7) 379 380 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 381 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 382 383 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 384 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 385 386 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 387 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 388 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 389 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 390 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 391 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 392 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 393 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 394 395 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 396 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 397 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 398 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 399 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 400 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 401 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 402 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 403 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 404 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 405 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 406 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 407 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 408 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 409 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 410 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 411 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 412 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 413 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 414 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 415 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 416 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 417 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 418 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 419 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 420 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 421 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 422 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 423 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 424 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 425 426 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 427 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 428 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 429 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 430 431 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 432 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 433 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 434 435 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 436 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 437 438 #endif /* STM32H7 */ 439 440 #if defined(STM32U5) 441 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 442 #endif /* STM32U5 */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 448 * @{ 449 */ 450 451 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 452 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 453 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 454 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 455 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 456 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 457 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 458 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 459 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 460 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 461 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 462 #define OBEX_PCROP OPTIONBYTE_PCROP 463 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 464 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 465 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 466 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 467 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 468 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 469 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 470 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 471 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 472 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 473 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 474 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 475 /* #define PAGESIZE FLASH_PAGE_SIZE */ 476 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 477 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 478 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 479 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 480 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 481 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 482 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 483 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 484 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 485 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 486 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 487 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 488 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 489 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 490 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 491 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 492 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 493 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 494 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 495 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 496 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 497 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 498 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 499 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 500 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 501 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 502 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 503 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 504 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 505 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 506 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 507 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 508 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 509 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 510 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 511 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 512 #define OB_WDG_SW OB_IWDG_SW 513 #define OB_WDG_HW OB_IWDG_HW 514 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 515 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 516 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 517 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 518 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 519 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 520 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 521 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 522 #if defined(STM32G0) || defined(STM32C0) 523 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 524 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 525 #else 526 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 527 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 528 #endif 529 #if defined(STM32H7) 530 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 531 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 532 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 533 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 534 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 535 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 536 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 537 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 538 #endif /* STM32H7 */ 539 #if defined(STM32U5) 540 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 541 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 542 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 543 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 544 #define OB_USER_nBOOT0 OB_USER_NBOOT0 545 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 546 #define OB_nBOOT0_SET OB_NBOOT0_SET 547 #define OB_USER_SRAM134_RST OB_USER_SRAM_RST 548 #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE 549 #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE 550 #endif /* STM32U5 */ 551 #if defined(STM32U0) 552 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 553 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 554 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 555 #define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL 556 #define OB_USER_nBOOT0 OB_USER_NBOOT0 557 #define OB_USER_nBOOT1 OB_USER_NBOOT1 558 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 559 #define OB_nBOOT0_SET OB_NBOOT0_SET 560 #endif /* STM32U0 */ 561 562 /** 563 * @} 564 */ 565 566 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 567 * @{ 568 */ 569 570 #if defined(STM32H7) 571 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 572 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 573 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 574 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 575 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 576 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 577 #endif /* STM32H7 */ 578 579 /** 580 * @} 581 */ 582 583 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 584 * @{ 585 */ 586 587 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 588 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 589 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 590 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 591 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 592 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 593 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 594 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 595 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 596 #if defined(STM32G4) 597 598 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 599 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 600 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 601 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 602 #endif /* STM32G4 */ 603 604 #if defined(STM32H5) 605 #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC 606 #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC 607 #define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC 608 #define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC 609 #define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC 610 #define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC 611 612 #define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC 613 #define SYSCFG_BREAK_PVD SBS_BREAK_PVD 614 #define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC 615 #define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP 616 617 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 618 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 619 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 620 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 621 622 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE 623 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE 624 625 #define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 626 #define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 627 #define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 628 #define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 629 630 #define SYSCFG_ETH_MII SBS_ETH_MII 631 #define SYSCFG_ETH_RMII SBS_ETH_RMII 632 #define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG 633 634 #define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE 635 #define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR 636 #define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG 637 638 #define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG 639 640 #define SYSCFG_MPU_NSEC SBS_MPU_NSEC 641 #define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC 642 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 643 #define SYSCFG_SAU SBS_SAU 644 #define SYSCFG_MPU_SEC SBS_MPU_SEC 645 #define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC 646 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 647 #else 648 #define SYSCFG_LOCK_ALL SBS_LOCK_ALL 649 #endif /* __ARM_FEATURE_CMSE */ 650 651 #define SYSCFG_CLK SBS_CLK 652 #define SYSCFG_CLASSB SBS_CLASSB 653 #define SYSCFG_FPU SBS_FPU 654 #define SYSCFG_ALL SBS_ALL 655 656 #define SYSCFG_SEC SBS_SEC 657 #define SYSCFG_NSEC SBS_NSEC 658 659 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE 660 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE 661 662 #define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK 663 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK 664 #define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK 665 #define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK 666 667 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE 668 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE 669 670 #define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS 671 #define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS 672 673 #define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT 674 #define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG 675 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE 676 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE 677 #define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING 678 #define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS 679 #define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES 680 #define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES 681 #define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS 682 683 #define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig 684 #define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig 685 #define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig 686 #define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF 687 #define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF 688 689 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster 690 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster 691 #define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect 692 693 #define HAL_SYSCFG_Lock HAL_SBS_Lock 694 #define HAL_SYSCFG_GetLock HAL_SBS_GetLock 695 696 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 697 #define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes 698 #define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes 699 #endif /* __ARM_FEATURE_CMSE */ 700 701 #endif /* STM32H5 */ 702 703 704 /** 705 * @} 706 */ 707 708 709 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 710 * @{ 711 */ 712 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 713 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 714 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 715 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 716 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 717 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 718 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 719 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 720 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 721 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 722 #endif 723 /** 724 * @} 725 */ 726 727 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 728 * @{ 729 */ 730 731 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 732 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 733 /** 734 * @} 735 */ 736 737 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 738 * @{ 739 */ 740 #define GET_GPIO_SOURCE GPIO_GET_INDEX 741 #define GET_GPIO_INDEX GPIO_GET_INDEX 742 743 #if defined(STM32F4) 744 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 745 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 746 #endif 747 748 #if defined(STM32F7) 749 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 750 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 751 #endif 752 753 #if defined(STM32L4) 754 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 755 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 756 #endif 757 758 #if defined(STM32H7) 759 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 760 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 761 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 762 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 763 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 764 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 765 766 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 767 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 768 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 769 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 770 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 771 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ 772 STM32H757xx */ 773 #endif /* STM32H7 */ 774 775 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 776 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 777 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 778 779 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ 780 defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 781 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 782 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 783 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 784 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 785 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 786 787 #if defined(STM32L1) 788 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 789 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 790 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 791 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 792 #endif /* STM32L1 */ 793 794 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 795 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 796 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 797 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 798 #endif /* STM32F0 || STM32F3 || STM32F1 */ 799 800 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 801 802 #if defined(STM32U5) || defined(STM32H5) 803 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 804 #endif /* STM32U5 || STM32H5 */ 805 #if defined(STM32U5) 806 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 807 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 808 #endif /* STM32U5 */ 809 /** 810 * @} 811 */ 812 813 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 814 * @{ 815 */ 816 #if defined(STM32U5) 817 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 818 #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB 819 #endif /* STM32U5 */ 820 #if defined(STM32H5) 821 #define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 822 #define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC 823 #define GTZC_PERIPH_USBFS GTZC_PERIPH_USB 824 #endif /* STM32H5 */ 825 #if defined(STM32H5) || defined(STM32U5) 826 #define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX 827 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 828 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED 829 #define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED 830 #define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC 831 #define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC 832 #define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV 833 #define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV 834 #define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF 835 #define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON 836 #endif /* STM32H5 || STM32U5 */ 837 /** 838 * @} 839 */ 840 841 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 842 * @{ 843 */ 844 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 845 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 846 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 847 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 848 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 849 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 850 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 851 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 852 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 853 854 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 855 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 856 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 857 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 858 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 859 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 860 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 861 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 862 863 #if defined(STM32G4) 864 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 865 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 866 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 867 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 868 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 869 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 870 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 871 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 872 #endif /* STM32G4 */ 873 874 #if defined(STM32H7) 875 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 876 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 877 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 878 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 879 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 880 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 881 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 882 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 883 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 884 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 885 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 886 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 887 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 888 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 889 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 890 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 891 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 892 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 893 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 894 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 895 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 896 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 897 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 898 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 899 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 900 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 901 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 902 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 903 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 904 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 905 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 906 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 907 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 908 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 909 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 910 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 911 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 912 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 913 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 914 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 915 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 916 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 917 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 918 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 919 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 920 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 921 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 922 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 923 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 924 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 925 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 926 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 927 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 928 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 929 930 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 931 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 932 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 933 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 934 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 935 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 936 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 937 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 938 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 939 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 940 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 941 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 942 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 943 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 944 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 945 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 946 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 947 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 948 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 949 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 950 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 951 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 952 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 953 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 954 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 955 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 956 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 957 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 958 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 959 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 960 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 961 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 962 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 963 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 964 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 965 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 966 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 967 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 968 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 969 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 970 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 971 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 972 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 973 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 974 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 975 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 976 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 977 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 978 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 979 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 980 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 981 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 982 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 983 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 984 #endif /* STM32H7 */ 985 986 #if defined(STM32F3) 987 /** @brief Constants defining available sources associated to external events. 988 */ 989 #define HRTIM_EVENTSRC_1 (0x00000000U) 990 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 991 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 992 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 993 994 /** @brief Constants defining the DLL calibration periods (in micro seconds) 995 */ 996 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 997 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 998 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 999 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 1000 1001 #endif /* STM32F3 */ 1002 /** 1003 * @} 1004 */ 1005 1006 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 1007 * @{ 1008 */ 1009 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 1010 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 1011 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 1012 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 1013 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 1014 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 1015 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 1016 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 1017 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ 1018 defined(STM32L1) || defined(STM32F7) 1019 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 1020 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 1021 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 1022 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 1023 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 1024 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 1025 #endif 1026 /** 1027 * @} 1028 */ 1029 1030 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 1031 * @{ 1032 */ 1033 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 1034 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 1035 1036 /** 1037 * @} 1038 */ 1039 1040 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 1041 * @{ 1042 */ 1043 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 1044 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 1045 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 1046 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 1047 /** 1048 * @} 1049 */ 1050 1051 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1052 * @{ 1053 */ 1054 1055 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 1056 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 1057 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 1058 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 1059 1060 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 1061 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 1062 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 1063 1064 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 1065 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1066 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1067 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1068 1069 /* The following 3 definition have also been present in a temporary version of lptim.h */ 1070 /* They need to be renamed also to the right name, just in case */ 1071 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 1072 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 1073 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 1074 1075 1076 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 1077 * @{ 1078 */ 1079 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 1080 /** 1081 * @} 1082 */ 1083 1084 #if defined(STM32U5) 1085 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 1086 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 1087 #define LPTIM_CHANNEL_ALL 0x00000000U 1088 #endif /* STM32U5 */ 1089 /** 1090 * @} 1091 */ 1092 1093 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 1094 * @{ 1095 */ 1096 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 1097 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 1098 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 1099 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 1100 1101 #define NAND_AddressTypedef NAND_AddressTypeDef 1102 1103 #define __ARRAY_ADDRESS ARRAY_ADDRESS 1104 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 1105 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 1106 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 1107 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 1108 /** 1109 * @} 1110 */ 1111 1112 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 1113 * @{ 1114 */ 1115 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 1116 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 1117 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 1118 #define NOR_ERROR HAL_NOR_STATUS_ERROR 1119 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 1120 1121 #define __NOR_WRITE NOR_WRITE 1122 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 1123 /** 1124 * @} 1125 */ 1126 1127 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 1128 * @{ 1129 */ 1130 1131 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 1132 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 1133 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 1134 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 1135 1136 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 1137 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 1138 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 1139 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 1140 1141 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1142 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1143 1144 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1145 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1146 1147 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 1148 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 1149 1150 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1151 1152 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1153 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1154 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1155 1156 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) 1157 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1158 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1159 #endif 1160 1161 #if defined(STM32L4) || defined(STM32L5) 1162 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1163 #elif defined(STM32G4) 1164 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1165 #endif 1166 1167 /** 1168 * @} 1169 */ 1170 1171 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1172 * @{ 1173 */ 1174 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1175 1176 #if defined(STM32H7) 1177 #define I2S_IT_TXE I2S_IT_TXP 1178 #define I2S_IT_RXNE I2S_IT_RXP 1179 1180 #define I2S_FLAG_TXE I2S_FLAG_TXP 1181 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1182 #endif 1183 1184 #if defined(STM32F7) 1185 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1186 #endif 1187 /** 1188 * @} 1189 */ 1190 1191 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1192 * @{ 1193 */ 1194 1195 /* Compact Flash-ATA registers description */ 1196 #define CF_DATA ATA_DATA 1197 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1198 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1199 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1200 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1201 #define CF_CARD_HEAD ATA_CARD_HEAD 1202 #define CF_STATUS_CMD ATA_STATUS_CMD 1203 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1204 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1205 1206 /* Compact Flash-ATA commands */ 1207 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1208 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1209 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1210 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1211 1212 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1213 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1214 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1215 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1216 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1217 /** 1218 * @} 1219 */ 1220 1221 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1222 * @{ 1223 */ 1224 1225 #define FORMAT_BIN RTC_FORMAT_BIN 1226 #define FORMAT_BCD RTC_FORMAT_BCD 1227 1228 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1229 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1230 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1231 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1232 1233 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1234 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1235 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1236 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1237 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1238 1239 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1240 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1241 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1242 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1243 1244 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1245 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1246 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1247 1248 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1249 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1250 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1251 1252 #if defined(STM32H5) || defined(STM32H7RS) 1253 #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE 1254 #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM 1255 #endif /* STM32H5 || STM32H7RS */ 1256 1257 #if defined(STM32WBA) 1258 #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE 1259 #define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 1260 #define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK 1261 #define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE 1262 #define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH 1263 #define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM 1264 #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL 1265 #endif /* STM32WBA */ 1266 1267 #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) 1268 #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE 1269 #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL 1270 #endif /* STM32H5 || STM32WBA || STM32H7RS */ 1271 1272 #if defined(STM32F7) 1273 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1274 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1275 #endif /* STM32F7 */ 1276 1277 #if defined(STM32H7) 1278 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1279 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1280 #endif /* STM32H7 */ 1281 1282 #if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) 1283 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1284 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1285 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1286 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1287 #endif /* STM32F7 || STM32H7 || STM32L0 */ 1288 1289 /** 1290 * @} 1291 */ 1292 1293 1294 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1295 * @{ 1296 */ 1297 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1298 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1299 1300 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1301 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1302 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1303 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1304 1305 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1306 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1307 1308 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1309 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1310 /** 1311 * @} 1312 */ 1313 1314 1315 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1316 * @{ 1317 */ 1318 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1319 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1320 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1321 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1322 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1323 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1324 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1325 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1326 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1327 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1328 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1329 /** 1330 * @} 1331 */ 1332 1333 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1334 * @{ 1335 */ 1336 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1337 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1338 1339 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1340 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1341 1342 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1343 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1344 1345 #if defined(STM32H7) 1346 1347 #define SPI_FLAG_TXE SPI_FLAG_TXP 1348 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1349 1350 #define SPI_IT_TXE SPI_IT_TXP 1351 #define SPI_IT_RXNE SPI_IT_RXP 1352 1353 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1354 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1355 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1356 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1357 1358 #endif /* STM32H7 */ 1359 1360 /** 1361 * @} 1362 */ 1363 1364 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1365 * @{ 1366 */ 1367 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1368 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1369 1370 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1371 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1372 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1373 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1374 #define TIM_DMABase_SR TIM_DMABASE_SR 1375 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1376 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1377 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1378 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1379 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1380 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1381 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1382 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1383 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1384 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1385 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1386 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1387 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1388 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1389 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1390 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1391 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1392 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1393 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1394 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1395 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1396 #define TIM_DMABase_OR TIM_DMABASE_OR 1397 1398 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1399 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1400 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1401 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1402 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1403 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1404 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1405 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1406 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1407 1408 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1409 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1410 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1411 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1412 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1413 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1414 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1415 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1416 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1417 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1418 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1419 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1420 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1421 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1422 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1423 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1424 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1425 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1426 1427 #if defined(STM32L0) 1428 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1429 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1430 #endif 1431 1432 #if defined(STM32F3) 1433 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1434 #endif 1435 1436 #if defined(STM32H7) 1437 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1438 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1439 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1440 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1441 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1442 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1443 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1444 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1445 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1446 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1447 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1448 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1449 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1450 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1451 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1452 #endif 1453 1454 #if defined(STM32U5) 1455 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1456 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1457 #endif 1458 /** 1459 * @} 1460 */ 1461 1462 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1463 * @{ 1464 */ 1465 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1466 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1467 /** 1468 * @} 1469 */ 1470 1471 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1472 * @{ 1473 */ 1474 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1475 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1476 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1477 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1478 1479 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1480 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1481 1482 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1483 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1484 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1485 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1486 1487 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1488 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1489 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1490 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1491 1492 #define __DIV_LPUART UART_DIV_LPUART 1493 1494 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1495 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1496 1497 /** 1498 * @} 1499 */ 1500 1501 1502 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1503 * @{ 1504 */ 1505 1506 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1507 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1508 1509 #define USARTNACK_ENABLED USART_NACK_ENABLE 1510 #define USARTNACK_DISABLED USART_NACK_DISABLE 1511 /** 1512 * @} 1513 */ 1514 1515 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1516 * @{ 1517 */ 1518 #define CFR_BASE WWDG_CFR_BASE 1519 1520 /** 1521 * @} 1522 */ 1523 1524 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1525 * @{ 1526 */ 1527 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1528 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1529 #define CAN_IT_RQCP0 CAN_IT_TME 1530 #define CAN_IT_RQCP1 CAN_IT_TME 1531 #define CAN_IT_RQCP2 CAN_IT_TME 1532 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1533 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1534 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1535 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1536 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1537 1538 /** 1539 * @} 1540 */ 1541 1542 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1543 * @{ 1544 */ 1545 1546 #define VLAN_TAG ETH_VLAN_TAG 1547 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1548 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1549 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1550 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1551 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1552 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1553 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1554 1555 #define ETH_MMCCR 0x00000100U 1556 #define ETH_MMCRIR 0x00000104U 1557 #define ETH_MMCTIR 0x00000108U 1558 #define ETH_MMCRIMR 0x0000010CU 1559 #define ETH_MMCTIMR 0x00000110U 1560 #define ETH_MMCTGFSCCR 0x0000014CU 1561 #define ETH_MMCTGFMSCCR 0x00000150U 1562 #define ETH_MMCTGFCR 0x00000168U 1563 #define ETH_MMCRFCECR 0x00000194U 1564 #define ETH_MMCRFAECR 0x00000198U 1565 #define ETH_MMCRGUFCR 0x000001C4U 1566 1567 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1568 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1569 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1570 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1571 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to 1572 the MAC transmitter) */ 1573 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from 1574 MAC transmitter */ 1575 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus 1576 or flushing the TxFIFO */ 1577 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1578 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1579 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status 1580 of previous frame or IFG/backoff period to be over */ 1581 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and 1582 transmitting a Pause control frame (in full duplex mode) */ 1583 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input 1584 frame for transmission */ 1585 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1586 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1587 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control 1588 de-activate threshold */ 1589 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control 1590 activate threshold */ 1591 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1592 #if defined(STM32F1) 1593 #else 1594 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1595 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1596 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status 1597 (or time-stamp) */ 1598 #endif 1599 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and 1600 status */ 1601 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1602 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1603 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1604 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1605 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1606 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1607 1608 #define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ 1609 1610 /** 1611 * @} 1612 */ 1613 1614 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1615 * @{ 1616 */ 1617 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1618 #define DCMI_IT_OVF DCMI_IT_OVR 1619 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1620 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1621 1622 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1623 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1624 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1625 1626 /** 1627 * @} 1628 */ 1629 1630 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1631 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1632 || defined(STM32H7) 1633 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1634 * @{ 1635 */ 1636 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1637 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1638 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1639 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1640 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1641 1642 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1643 #define CM_RGB888 DMA2D_INPUT_RGB888 1644 #define CM_RGB565 DMA2D_INPUT_RGB565 1645 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1646 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1647 #define CM_L8 DMA2D_INPUT_L8 1648 #define CM_AL44 DMA2D_INPUT_AL44 1649 #define CM_AL88 DMA2D_INPUT_AL88 1650 #define CM_L4 DMA2D_INPUT_L4 1651 #define CM_A8 DMA2D_INPUT_A8 1652 #define CM_A4 DMA2D_INPUT_A4 1653 /** 1654 * @} 1655 */ 1656 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1657 1658 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1659 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1660 || defined(STM32H7) || defined(STM32U5) 1661 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1662 * @{ 1663 */ 1664 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1665 for compatibility with legacy code */ 1666 /** 1667 * @} 1668 */ 1669 1670 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1671 1672 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1673 * @{ 1674 */ 1675 1676 /** 1677 * @} 1678 */ 1679 1680 /* Exported functions --------------------------------------------------------*/ 1681 1682 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1683 * @{ 1684 */ 1685 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1686 /** 1687 * @} 1688 */ 1689 1690 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1691 * @{ 1692 */ 1693 1694 #if defined(STM32U5) 1695 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1696 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1697 #endif /* STM32U5 */ 1698 1699 /** 1700 * @} 1701 */ 1702 1703 #if !defined(STM32F2) 1704 /** @defgroup HASH_alias HASH API alias 1705 * @{ 1706 */ 1707 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1708 /** 1709 * 1710 * @} 1711 */ 1712 #endif /* STM32F2 */ 1713 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1714 * @{ 1715 */ 1716 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1717 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1718 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1719 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1720 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1721 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1722 1723 /*HASH Algorithm Selection*/ 1724 1725 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1726 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1727 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1728 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1729 1730 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1731 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1732 1733 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1734 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1735 1736 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1737 1738 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1739 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1740 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1741 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1742 1743 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1744 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1745 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1746 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1747 1748 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1749 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1750 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1751 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1752 1753 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1754 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1755 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1756 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1757 1758 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1759 /** 1760 * @} 1761 */ 1762 1763 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1764 * @{ 1765 */ 1766 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1767 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1768 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1769 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1770 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1771 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1772 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1773 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ 1774 HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1775 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1776 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1777 #if defined(STM32L0) 1778 #else 1779 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1780 #endif 1781 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1782 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1783 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ 1784 HAL_ADCEx_DisableVREFINTTempSensor()) 1785 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ 1786 defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1787 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1788 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1789 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1790 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1791 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1792 1793 /** 1794 * @} 1795 */ 1796 1797 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1798 * @{ 1799 */ 1800 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1801 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1802 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1803 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1804 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1805 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1806 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1807 1808 /** 1809 * @} 1810 */ 1811 1812 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1813 * @{ 1814 */ 1815 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1816 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1817 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1818 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1819 1820 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ 1821 HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ 1822 HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1823 1824 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ 1825 defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ 1826 defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1827 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1828 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1829 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1830 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1831 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || 1832 STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1833 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ 1834 defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1835 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1836 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1837 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1838 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1839 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1840 1841 #if defined(STM32F4) 1842 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1843 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1844 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1845 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1846 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1847 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1848 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1849 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1850 #endif /* STM32F4 */ 1851 /** 1852 * @} 1853 */ 1854 1855 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1856 * @{ 1857 */ 1858 1859 #if defined(STM32G0) 1860 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1861 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1862 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1863 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1864 #endif 1865 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1866 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1867 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1868 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1869 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1870 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1871 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1872 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1873 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1874 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1875 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1876 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1877 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1878 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1879 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1880 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1881 1882 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1883 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1884 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1885 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1886 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1887 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1888 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1889 1890 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1891 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1892 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1893 #define CR_PMODE_BB CR_VOS_BB 1894 1895 #define DBP_BitNumber DBP_BIT_NUMBER 1896 #define PVDE_BitNumber PVDE_BIT_NUMBER 1897 #define PMODE_BitNumber PMODE_BIT_NUMBER 1898 #define EWUP_BitNumber EWUP_BIT_NUMBER 1899 #define FPDS_BitNumber FPDS_BIT_NUMBER 1900 #define ODEN_BitNumber ODEN_BIT_NUMBER 1901 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1902 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1903 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1904 #define BRE_BitNumber BRE_BIT_NUMBER 1905 1906 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1907 1908 #if defined (STM32U5) 1909 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1910 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1911 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1912 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1913 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1914 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1915 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1916 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1917 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1918 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1919 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1920 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1921 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1922 1923 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1924 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1925 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1926 1927 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1928 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1929 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1930 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1931 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1932 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1933 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1934 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1935 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1936 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1937 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1938 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1939 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1940 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1941 1942 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1943 1944 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1945 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1946 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1947 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1948 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1949 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1950 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1951 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1952 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1953 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1954 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1955 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1956 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1957 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1958 1959 #define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP 1960 #define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP 1961 #define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP 1962 #define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP 1963 #define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP 1964 #define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP 1965 #define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP 1966 #define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP 1967 #define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP 1968 1969 1970 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 1971 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 1972 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 1973 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 1974 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 1975 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 1976 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 1977 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 1978 #define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP 1979 1980 1981 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 1982 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 1983 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 1984 1985 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 1986 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 1987 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 1988 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 1989 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 1990 #define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN 1991 1992 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 1993 #endif 1994 1995 /** 1996 * @} 1997 */ 1998 1999 /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose 2000 * @{ 2001 */ 2002 #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) 2003 #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey 2004 #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock 2005 #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock 2006 #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets 2007 #endif /* STM32H5 || STM32WBA || STM32H7RS */ 2008 2009 /** 2010 * @} 2011 */ 2012 2013 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 2014 * @{ 2015 */ 2016 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 2017 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 2018 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 2019 /** 2020 * @} 2021 */ 2022 2023 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 2024 * @{ 2025 */ 2026 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 2027 /** 2028 * @} 2029 */ 2030 2031 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 2032 * @{ 2033 */ 2034 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 2035 #define HAL_TIM_DMAError TIM_DMAError 2036 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 2037 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 2038 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ 2039 defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 2040 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 2041 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 2042 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 2043 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 2044 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 2045 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 2046 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 2047 /** 2048 * @} 2049 */ 2050 2051 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 2052 * @{ 2053 */ 2054 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 2055 /** 2056 * @} 2057 */ 2058 2059 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 2060 * @{ 2061 */ 2062 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 2063 #define HAL_LTDC_Relaod HAL_LTDC_Reload 2064 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 2065 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 2066 /** 2067 * @} 2068 */ 2069 2070 2071 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 2072 * @{ 2073 */ 2074 2075 /** 2076 * @} 2077 */ 2078 2079 /* Exported macros ------------------------------------------------------------*/ 2080 2081 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 2082 * @{ 2083 */ 2084 #define AES_IT_CC CRYP_IT_CC 2085 #define AES_IT_ERR CRYP_IT_ERR 2086 #define AES_FLAG_CCF CRYP_FLAG_CCF 2087 /** 2088 * @} 2089 */ 2090 2091 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 2092 * @{ 2093 */ 2094 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 2095 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 2096 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 2097 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 2098 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 2099 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 2100 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 2101 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 2102 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 2103 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 2104 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 2105 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 2106 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 2107 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 2108 2109 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 2110 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 2111 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 2112 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 2113 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 2114 2115 /** 2116 * @} 2117 */ 2118 2119 2120 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 2121 * @{ 2122 */ 2123 #define __ADC_ENABLE __HAL_ADC_ENABLE 2124 #define __ADC_DISABLE __HAL_ADC_DISABLE 2125 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 2126 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 2127 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 2128 #define __ADC_IS_ENABLED ADC_IS_ENABLE 2129 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 2130 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 2131 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 2132 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 2133 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 2134 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 2135 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 2136 2137 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 2138 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 2139 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 2140 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 2141 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 2142 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 2143 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 2144 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 2145 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 2146 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 2147 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 2148 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 2149 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 2150 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 2151 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 2152 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 2153 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 2154 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 2155 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 2156 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 2157 2158 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 2159 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 2160 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 2161 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 2162 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 2163 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2164 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 2165 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 2166 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 2167 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 2168 2169 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 2170 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 2171 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 2172 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 2173 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 2174 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 2175 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 2176 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 2177 2178 #define __HAL_ADC_SQR1 ADC_SQR1 2179 #define __HAL_ADC_SMPR1 ADC_SMPR1 2180 #define __HAL_ADC_SMPR2 ADC_SMPR2 2181 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 2182 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 2183 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 2184 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 2185 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 2186 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 2187 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 2188 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 2189 #define __HAL_ADC_JSQR ADC_JSQR 2190 2191 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 2192 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 2193 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 2194 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 2195 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 2196 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 2197 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 2198 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 2199 2200 /** 2201 * @} 2202 */ 2203 2204 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2205 * @{ 2206 */ 2207 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 2208 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 2209 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 2210 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 2211 2212 /** 2213 * @} 2214 */ 2215 2216 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 2217 * @{ 2218 */ 2219 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2220 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2221 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2222 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2223 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2224 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2225 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2226 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2227 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2228 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2229 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2230 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2231 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2232 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2233 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2234 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2235 2236 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2237 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2238 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2239 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2240 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2241 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2242 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2243 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2244 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2245 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2246 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2247 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2248 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2249 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2250 2251 2252 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2253 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2254 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2255 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2256 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2257 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2258 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2259 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2260 #if defined(STM32H7) 2261 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2262 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2263 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2264 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2265 #else 2266 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2267 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2268 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2269 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2270 #endif /* STM32H7 */ 2271 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2272 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2273 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2274 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2275 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2276 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2277 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2278 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2279 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2280 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2281 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2282 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2283 2284 /** 2285 * @} 2286 */ 2287 2288 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2289 * @{ 2290 */ 2291 #if defined(STM32F3) 2292 #define COMP_START __HAL_COMP_ENABLE 2293 #define COMP_STOP __HAL_COMP_DISABLE 2294 #define COMP_LOCK __HAL_COMP_LOCK 2295 2296 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ 2297 defined(STM32F334x8) || defined(STM32F328xx) 2298 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2299 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2300 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2301 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2302 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2303 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2304 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2305 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2306 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2307 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2308 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2309 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2310 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2311 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2312 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2313 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2314 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2315 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2316 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2317 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2318 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2319 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2320 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2321 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2322 #endif 2323 #if defined(STM32F302xE) || defined(STM32F302xC) 2324 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2325 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2326 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2327 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2328 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2329 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2330 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2331 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2332 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2333 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2334 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2335 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2336 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2337 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2338 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2339 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2340 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2341 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2342 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2343 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2344 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2345 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2346 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2347 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2348 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2349 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2350 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2351 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2352 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2353 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2354 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2355 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2356 #endif 2357 #if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2358 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2359 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2360 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2361 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2362 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2363 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2364 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2365 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2366 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2367 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2368 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2369 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2370 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2371 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2372 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2373 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2374 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2375 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2376 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2377 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2378 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2379 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2380 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2381 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2382 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2383 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2384 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2385 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2386 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2387 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2388 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2389 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2390 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2391 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2392 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2393 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2394 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2395 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2396 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2397 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2398 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2399 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2400 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2401 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2402 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2403 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2404 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2405 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2406 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2407 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2408 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2409 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2410 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2411 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2412 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2413 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2414 #endif 2415 #if defined(STM32F373xC) ||defined(STM32F378xx) 2416 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2417 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2418 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2419 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2420 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2421 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2422 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2423 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2424 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2425 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2426 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2427 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2428 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2429 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2430 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2431 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2432 #endif 2433 #else 2434 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2435 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2436 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2437 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2438 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2439 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2440 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2441 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2442 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2443 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2444 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2445 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2446 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2447 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2448 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2449 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2450 #endif 2451 2452 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2453 2454 #if defined(STM32L0) || defined(STM32L4) 2455 /* Note: On these STM32 families, the only argument of this macro */ 2456 /* is COMP_FLAG_LOCK. */ 2457 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2458 /* argument. */ 2459 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2460 #endif 2461 /** 2462 * @} 2463 */ 2464 2465 #if defined(STM32L0) || defined(STM32L4) 2466 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2467 * @{ 2468 */ 2469 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 2470 done into HAL_COMP_Init() */ 2471 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is 2472 done into HAL_COMP_Init() */ 2473 /** 2474 * @} 2475 */ 2476 #endif 2477 2478 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2479 * @{ 2480 */ 2481 2482 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2483 ((WAVE) == DAC_WAVE_NOISE)|| \ 2484 ((WAVE) == DAC_WAVE_TRIANGLE)) 2485 2486 /** 2487 * @} 2488 */ 2489 2490 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2491 * @{ 2492 */ 2493 2494 #define IS_WRPAREA IS_OB_WRPAREA 2495 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2496 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2497 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2498 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2499 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2500 2501 /** 2502 * @} 2503 */ 2504 2505 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2506 * @{ 2507 */ 2508 2509 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2510 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2511 #if defined(STM32F1) 2512 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2513 #else 2514 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2515 #endif /* STM32F1 */ 2516 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2517 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2518 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2519 #define __HAL_I2C_SPEED I2C_SPEED 2520 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2521 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2522 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2523 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2524 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2525 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2526 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2527 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2528 /** 2529 * @} 2530 */ 2531 2532 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2533 * @{ 2534 */ 2535 2536 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2537 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2538 2539 #if defined(STM32H7) 2540 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2541 #endif 2542 2543 /** 2544 * @} 2545 */ 2546 2547 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2548 * @{ 2549 */ 2550 2551 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2552 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2553 2554 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2555 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2556 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2557 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2558 2559 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2560 2561 2562 /** 2563 * @} 2564 */ 2565 2566 2567 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2568 * @{ 2569 */ 2570 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2571 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2572 /** 2573 * @} 2574 */ 2575 2576 2577 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2578 * @{ 2579 */ 2580 2581 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2582 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2583 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2584 2585 /** 2586 * @} 2587 */ 2588 2589 2590 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2591 * @{ 2592 */ 2593 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2594 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2595 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2596 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2597 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2598 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2599 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2600 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2601 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2602 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2603 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2604 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2605 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2606 2607 /** 2608 * @} 2609 */ 2610 2611 2612 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2613 * @{ 2614 */ 2615 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2616 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2617 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2618 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2619 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2620 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2621 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2622 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2623 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2624 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2625 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2626 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2627 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2628 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2629 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2630 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2631 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 2632 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 2633 } while(0) 2634 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2635 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2636 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2637 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2638 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2639 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2640 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2641 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2642 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ 2643 HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ 2644 } while(0) 2645 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ 2646 HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ 2647 } while(0) 2648 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2649 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2650 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2651 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2652 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2653 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2654 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2655 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2656 2657 #if defined (STM32F4) 2658 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2659 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2660 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2661 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2662 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2663 #else 2664 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2665 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2666 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2667 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2668 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2669 #endif /* STM32F4 */ 2670 /** 2671 * @} 2672 */ 2673 2674 2675 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2676 * @{ 2677 */ 2678 2679 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2680 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2681 2682 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2683 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ 2684 HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2685 2686 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2687 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2688 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2689 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2690 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2691 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2692 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2693 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2694 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2695 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2696 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2697 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2698 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2699 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2700 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2701 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2702 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2703 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2704 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2705 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2706 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2707 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2708 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2709 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2710 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2711 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2712 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2713 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2714 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2715 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2716 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2717 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2718 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2719 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2720 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2721 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2722 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2723 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2724 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2725 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2726 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2727 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2728 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2729 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2730 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2731 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2732 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2733 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2734 #if defined(STM32C0) 2735 #define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET 2736 #define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET 2737 #define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET 2738 #define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET 2739 #endif /* STM32C0 */ 2740 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2741 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2742 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2743 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2744 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2745 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2746 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2747 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2748 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2749 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2750 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2751 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2752 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2753 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2754 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2755 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2756 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2757 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2758 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2759 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2760 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2761 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2762 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2763 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2764 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2765 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2766 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2767 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2768 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2769 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2770 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2771 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2772 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2773 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2774 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2775 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2776 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2777 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2778 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2779 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2780 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2781 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2782 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2783 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2784 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2785 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2786 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2787 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2788 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2789 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2790 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2791 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2792 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2793 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2794 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2795 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2796 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2797 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2798 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2799 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2800 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2801 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2802 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2803 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2804 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2805 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2806 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2807 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2808 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2809 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2810 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2811 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2812 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2813 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2814 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2815 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2816 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2817 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2818 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2819 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2820 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2821 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2822 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2823 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2824 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2825 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2826 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2827 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2828 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2829 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2830 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2831 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2832 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2833 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2834 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2835 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2836 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2837 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2838 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2839 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2840 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2841 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2842 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2843 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2844 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2845 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2846 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2847 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2848 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2849 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2850 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2851 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2852 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2853 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2854 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2855 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2856 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2857 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2858 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2859 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2860 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2861 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2862 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2863 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2864 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2865 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2866 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2867 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2868 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2869 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2870 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2871 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2872 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2873 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2874 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2875 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2876 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2877 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2878 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2879 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2880 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2881 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2882 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2883 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2884 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2885 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2886 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2887 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2888 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2889 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2890 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2891 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2892 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2893 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2894 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2895 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2896 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2897 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2898 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2899 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2900 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2901 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2902 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2903 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2904 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2905 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2906 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2907 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2908 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2909 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2910 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2911 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2912 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2913 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2914 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2915 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2916 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2917 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2918 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2919 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2920 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2921 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2922 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2923 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2924 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2925 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2926 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2927 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2928 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2929 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2930 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2931 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2932 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2933 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2934 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2935 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2936 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2937 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2938 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2939 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2940 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2941 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2942 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2943 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2944 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2945 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2946 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2947 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2948 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2949 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2950 2951 #if defined(STM32WB) 2952 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2953 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2954 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2955 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2956 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2957 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2958 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2959 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2960 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2961 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2962 #define QSPI_IRQHandler QUADSPI_IRQHandler 2963 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2964 2965 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2966 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2967 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2968 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2969 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2970 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2971 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2972 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2973 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2974 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2975 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2976 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2977 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2978 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2979 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2980 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2981 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2982 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2983 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2984 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2985 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2986 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2987 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2988 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2989 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2990 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2991 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2992 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2993 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2994 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2995 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2996 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2997 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2998 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2999 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 3000 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 3001 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 3002 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 3003 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 3004 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 3005 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 3006 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 3007 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 3008 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 3009 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 3010 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 3011 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 3012 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 3013 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 3014 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 3015 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 3016 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 3017 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 3018 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 3019 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 3020 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 3021 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 3022 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 3023 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 3024 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 3025 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 3026 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 3027 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 3028 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 3029 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 3030 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 3031 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 3032 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 3033 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 3034 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 3035 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 3036 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 3037 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 3038 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 3039 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 3040 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 3041 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 3042 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 3043 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 3044 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 3045 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 3046 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 3047 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 3048 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 3049 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 3050 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 3051 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 3052 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 3053 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 3054 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 3055 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 3056 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 3057 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 3058 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 3059 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 3060 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 3061 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 3062 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 3063 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 3064 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 3065 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 3066 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 3067 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 3068 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 3069 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 3070 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 3071 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 3072 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 3073 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 3074 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 3075 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 3076 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 3077 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 3078 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 3079 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 3080 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 3081 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 3082 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 3083 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 3084 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 3085 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 3086 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 3087 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 3088 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 3089 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 3090 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 3091 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 3092 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 3093 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 3094 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 3095 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 3096 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 3097 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 3098 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 3099 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 3100 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 3101 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 3102 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 3103 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 3104 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 3105 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 3106 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 3107 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 3108 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 3109 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 3110 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 3111 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 3112 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 3113 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 3114 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 3115 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 3116 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 3117 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 3118 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 3119 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 3120 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 3121 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 3122 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 3123 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3124 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3125 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3126 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3127 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3128 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3129 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3130 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3131 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3132 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3133 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3134 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3135 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 3136 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 3137 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 3138 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 3139 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 3140 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 3141 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 3142 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 3143 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 3144 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 3145 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 3146 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 3147 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 3148 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 3149 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 3150 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 3151 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 3152 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 3153 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 3154 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 3155 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 3156 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 3157 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 3158 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 3159 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 3160 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 3161 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 3162 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 3163 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 3164 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 3165 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3166 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3167 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3168 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3169 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3170 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3171 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3172 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3173 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 3174 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 3175 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 3176 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 3177 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 3178 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 3179 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 3180 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 3181 3182 #if defined(STM32H7) 3183 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 3184 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 3185 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 3186 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 3187 3188 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 3189 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 3190 3191 3192 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 3193 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 3194 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 3195 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 3196 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 3197 #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 3198 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 3199 #endif 3200 3201 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 3202 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 3203 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 3204 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 3205 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 3206 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 3207 3208 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 3209 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 3210 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 3211 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 3212 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 3213 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 3214 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 3215 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 3216 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 3217 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 3218 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 3219 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 3220 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 3221 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 3222 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 3223 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 3224 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 3225 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 3226 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 3227 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 3228 3229 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3230 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3231 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 3232 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 3233 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 3234 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 3235 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 3236 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 3237 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 3238 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 3239 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3240 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3241 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3242 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3243 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3244 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3245 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3246 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3247 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3248 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3249 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3250 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3251 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3252 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3253 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3254 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3255 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3256 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3257 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3258 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3259 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3260 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3261 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3262 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3263 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3264 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3265 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3266 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3267 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3268 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3269 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3270 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3271 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3272 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3273 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3274 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3275 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3276 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3277 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3278 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3279 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3280 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3281 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3282 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3283 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3284 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3285 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3286 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3287 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3288 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3289 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3290 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3291 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3292 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3293 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3294 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3295 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3296 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3297 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3298 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3299 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3300 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3301 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3302 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3303 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3304 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3305 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3306 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3307 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3308 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3309 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3310 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3311 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3312 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3313 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3314 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3315 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3316 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3317 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3318 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3319 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3320 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3321 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3322 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3323 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3324 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3325 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3326 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3327 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3328 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3329 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3330 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3331 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3332 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3333 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3334 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3335 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3336 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3337 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3338 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3339 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3340 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3341 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3342 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3343 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3344 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3345 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3346 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3347 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3348 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3349 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3350 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3351 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3352 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3353 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3354 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3355 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3356 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3357 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3358 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3359 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3360 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3361 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3362 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3363 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3364 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3365 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3366 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3367 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3368 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3369 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3370 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3371 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3372 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3373 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3374 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3375 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3376 3377 /* alias define maintained for legacy */ 3378 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3379 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3380 3381 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3382 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3383 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3384 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3385 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3386 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3387 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3388 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3389 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3390 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3391 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3392 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3393 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3394 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3395 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3396 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3397 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3398 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3399 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3400 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3401 3402 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3403 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3404 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3405 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3406 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3407 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3408 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3409 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3410 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3411 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3412 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3413 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3414 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3415 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3416 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3417 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3418 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3419 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3420 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3421 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3422 3423 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3424 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3425 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3426 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3427 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3428 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3429 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3430 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3431 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3432 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3433 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3434 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3435 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3436 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3437 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3438 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3439 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3440 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3441 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3442 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3443 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3444 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3445 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3446 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3447 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3448 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3449 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3450 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3451 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3452 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3453 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3454 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3455 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3456 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3457 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3458 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3459 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3460 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3461 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3462 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3463 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3464 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3465 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3466 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3467 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3468 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3469 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3470 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3471 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3472 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3473 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3474 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3475 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3476 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3477 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3478 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3479 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3480 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3481 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3482 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3483 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3484 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3485 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3486 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3487 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3488 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3489 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3490 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3491 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3492 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3493 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3494 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3495 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3496 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3497 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3498 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3499 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3500 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3501 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3502 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3503 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3504 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3505 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3506 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3507 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3508 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3509 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3510 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3511 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3512 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3513 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3514 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3515 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3516 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3517 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3518 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3519 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3520 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3521 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3522 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3523 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3524 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3525 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3526 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3527 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3528 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3529 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3530 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3531 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3532 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3533 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3534 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3535 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3536 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3537 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3538 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3539 3540 #if defined(STM32L1) 3541 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3542 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3543 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3544 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3545 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3546 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3547 #endif /* STM32L1 */ 3548 3549 #if defined(STM32F4) 3550 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3551 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3552 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3553 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3554 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3555 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3556 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3557 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3558 #define Sdmmc1ClockSelection SdioClockSelection 3559 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3560 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3561 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3562 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3563 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3564 #endif 3565 3566 #if defined(STM32F7) || defined(STM32L4) 3567 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3568 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3569 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3570 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3571 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3572 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3573 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3574 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3575 #define SdioClockSelection Sdmmc1ClockSelection 3576 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3577 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3578 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3579 #endif 3580 3581 #if defined(STM32F7) 3582 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3583 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3584 #endif 3585 3586 #if defined(STM32H7) 3587 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3588 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3589 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3590 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3591 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3592 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3593 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3594 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3595 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3596 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3597 3598 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3599 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3600 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3601 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3602 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3603 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3604 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3605 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3606 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3607 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3608 #endif 3609 3610 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3611 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3612 3613 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3614 3615 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3616 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3617 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3618 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3619 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3620 3621 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3622 3623 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3624 #define RCC_IT_CSSHSE RCC_IT_CSS 3625 3626 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3627 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3628 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3629 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3630 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3631 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3632 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3633 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3634 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3635 3636 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3637 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3638 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3639 3640 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3641 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3642 #define RCC_MCO_NODIV RCC_MCODIV_1 3643 #define RCC_MCO_DIV1 RCC_MCODIV_1 3644 #define RCC_MCO_DIV2 RCC_MCODIV_2 3645 #define RCC_MCO_DIV4 RCC_MCODIV_4 3646 #define RCC_MCO_DIV8 RCC_MCODIV_8 3647 #define RCC_MCO_DIV16 RCC_MCODIV_16 3648 #define RCC_MCO_DIV32 RCC_MCODIV_32 3649 #define RCC_MCO_DIV64 RCC_MCODIV_64 3650 #define RCC_MCO_DIV128 RCC_MCODIV_128 3651 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3652 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3653 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3654 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3655 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3656 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3657 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3658 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3659 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3660 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3661 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3662 3663 #if defined(STM32U0) 3664 #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK 3665 #endif 3666 3667 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ 3668 defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) 3669 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3670 #else 3671 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3672 #endif 3673 3674 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3675 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3676 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3677 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3678 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3679 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3680 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3681 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3682 3683 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3684 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3685 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3686 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3687 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3688 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3689 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3690 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3691 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3692 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3693 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3694 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3695 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3696 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3697 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3698 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3699 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3700 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3701 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3702 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3703 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3704 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3705 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3706 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3707 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3708 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3709 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3710 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3711 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3712 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3713 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3714 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3715 3716 #define CR_HSION_BB RCC_CR_HSION_BB 3717 #define CR_CSSON_BB RCC_CR_CSSON_BB 3718 #define CR_PLLON_BB RCC_CR_PLLON_BB 3719 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3720 #define CR_MSION_BB RCC_CR_MSION_BB 3721 #define CSR_LSION_BB RCC_CSR_LSION_BB 3722 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3723 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3724 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3725 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3726 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3727 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3728 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3729 #define CR_HSEON_BB RCC_CR_HSEON_BB 3730 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3731 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3732 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3733 3734 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3735 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3736 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3737 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3738 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3739 3740 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3741 3742 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3743 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3744 3745 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3746 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3747 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3748 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3749 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3750 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3751 3752 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3753 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3754 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3755 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3756 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3757 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3758 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3759 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3760 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3761 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3762 #define DfsdmClockSelection Dfsdm1ClockSelection 3763 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3764 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3765 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3766 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3767 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3768 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3769 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3770 #if !defined(STM32U0) 3771 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3772 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3773 #endif 3774 3775 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3776 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3777 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3778 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3779 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3780 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3781 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3782 #if defined(STM32U5) 3783 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3784 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3785 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3786 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3787 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3788 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3789 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3790 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3791 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3792 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3793 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3794 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3795 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3796 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3797 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3798 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3799 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3800 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3801 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3802 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3803 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3804 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3805 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3806 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3807 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3808 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3809 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3810 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3811 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3812 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3813 #endif /* STM32U5 */ 3814 3815 #if defined(STM32H5) 3816 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3817 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3818 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3819 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3820 3821 #define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE 3822 #define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI 3823 #define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI 3824 #define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE 3825 #define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 3826 #define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 3827 #define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 3828 #define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 3829 #define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE 3830 #define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM 3831 3832 #define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE 3833 #define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE 3834 #define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE 3835 #define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE 3836 #define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE 3837 #define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE 3838 #define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE 3839 #define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE 3840 #define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE 3841 #define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE 3842 3843 #define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE 3844 #define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE 3845 #define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE 3846 #define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE 3847 #define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG 3848 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG 3849 #define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG 3850 #define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG 3851 #define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE 3852 #define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE 3853 #define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE 3854 #define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE 3855 #define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE 3856 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG 3857 3858 #define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE 3859 #define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE 3860 #define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE 3861 #define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE 3862 #define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG 3863 #define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG 3864 3865 #define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE 3866 #define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE 3867 #define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE 3868 #define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE 3869 #define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG 3870 #define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG 3871 3872 #define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 3873 #define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 3874 #define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 3875 #define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 3876 3877 #define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE 3878 #define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM 3879 3880 #define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE 3881 #define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI 3882 #define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI 3883 #define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE 3884 3885 #define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 3886 #define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 3887 #define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 3888 #define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 3889 3890 #define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE 3891 #define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM 3892 3893 #define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE 3894 #define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI 3895 #define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI 3896 #define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE 3897 3898 3899 #endif /* STM32H5 */ 3900 3901 /** 3902 * @} 3903 */ 3904 3905 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3906 * @{ 3907 */ 3908 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3909 3910 /** 3911 * @} 3912 */ 3913 3914 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3915 * @{ 3916 */ 3917 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ 3918 defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ 3919 defined (STM32WBA) || defined (STM32H5) || \ 3920 defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) 3921 #else 3922 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3923 #endif 3924 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3925 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3926 3927 #if defined (STM32F1) 3928 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3929 3930 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3931 3932 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3933 3934 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3935 3936 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3937 #else 3938 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3939 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3940 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3941 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3942 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3943 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3944 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3945 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3946 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3947 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3948 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3949 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3950 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3951 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3952 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3953 #endif /* STM32F1 */ 3954 3955 #if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ 3956 defined (STM32H7) || \ 3957 defined (STM32L0) || defined (STM32L1) || \ 3958 defined (STM32WB) 3959 #define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG 3960 #endif 3961 3962 #define IS_ALARM IS_RTC_ALARM 3963 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3964 #define IS_TAMPER IS_RTC_TAMPER 3965 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3966 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3967 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3968 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3969 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3970 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3971 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3972 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3973 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3974 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3975 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3976 3977 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3978 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3979 3980 #if defined (STM32H5) 3981 #define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE 3982 #define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE 3983 #endif /* STM32H5 */ 3984 3985 /** 3986 * @} 3987 */ 3988 3989 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3990 * @{ 3991 */ 3992 3993 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3994 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3995 3996 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3997 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3998 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3999 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 4000 4001 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 4002 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 4003 #endif 4004 4005 #if defined(STM32F4) || defined(STM32F2) 4006 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 4007 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 4008 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 4009 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 4010 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 4011 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 4012 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 4013 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 4014 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 4015 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 4016 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 4017 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 4018 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 4019 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 4020 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 4021 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 4022 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 4023 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 4024 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 4025 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 4026 /* alias CMSIS */ 4027 #define SDMMC1_IRQn SDIO_IRQn 4028 #define SDMMC1_IRQHandler SDIO_IRQHandler 4029 #endif 4030 4031 #if defined(STM32F7) || defined(STM32L4) 4032 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 4033 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 4034 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 4035 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 4036 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 4037 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 4038 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 4039 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 4040 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 4041 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 4042 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 4043 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 4044 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 4045 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 4046 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 4047 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 4048 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 4049 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 4050 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 4051 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 4052 /* alias CMSIS for compatibilities */ 4053 #define SDIO_IRQn SDMMC1_IRQn 4054 #define SDIO_IRQHandler SDMMC1_IRQHandler 4055 #endif 4056 4057 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 4058 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 4059 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 4060 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 4061 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 4062 #endif 4063 4064 #if defined(STM32H7) || defined(STM32L5) 4065 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 4066 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 4067 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 4068 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 4069 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 4070 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 4071 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 4072 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 4073 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 4074 #endif 4075 /** 4076 * @} 4077 */ 4078 4079 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 4080 * @{ 4081 */ 4082 4083 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 4084 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 4085 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 4086 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 4087 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 4088 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 4089 4090 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 4091 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 4092 4093 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 4094 4095 /** 4096 * @} 4097 */ 4098 4099 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 4100 * @{ 4101 */ 4102 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 4103 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 4104 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 4105 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 4106 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 4107 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 4108 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 4109 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 4110 /** 4111 * @} 4112 */ 4113 4114 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 4115 * @{ 4116 */ 4117 4118 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 4119 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 4120 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 4121 4122 /** 4123 * @} 4124 */ 4125 4126 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 4127 * @{ 4128 */ 4129 4130 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 4131 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 4132 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 4133 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 4134 4135 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 4136 4137 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 4138 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 4139 4140 /** 4141 * @} 4142 */ 4143 4144 4145 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 4146 * @{ 4147 */ 4148 4149 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 4150 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 4151 #define __USART_ENABLE __HAL_USART_ENABLE 4152 #define __USART_DISABLE __HAL_USART_DISABLE 4153 4154 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4155 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 4156 4157 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 4158 #define USART_OVERSAMPLING_16 0x00000000U 4159 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 4160 4161 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 4162 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 4163 #endif /* STM32F0 || STM32F3 || STM32F7 */ 4164 /** 4165 * @} 4166 */ 4167 4168 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 4169 * @{ 4170 */ 4171 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 4172 4173 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 4174 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 4175 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 4176 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 4177 4178 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 4179 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 4180 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 4181 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 4182 4183 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 4184 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 4185 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 4186 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 4187 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 4188 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4189 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4190 4191 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 4192 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 4193 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 4194 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 4195 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4196 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4197 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4198 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 4199 4200 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 4201 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 4202 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 4203 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 4204 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 4205 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 4206 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 4207 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 4208 4209 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 4210 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 4211 4212 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 4213 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 4214 /** 4215 * @} 4216 */ 4217 4218 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 4219 * @{ 4220 */ 4221 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 4222 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 4223 4224 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4225 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 4226 4227 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 4228 4229 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 4230 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 4231 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 4232 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 4233 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 4234 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 4235 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 4236 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 4237 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 4238 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 4239 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 4240 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 4241 4242 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 4243 4244 #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 4245 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 4246 /** 4247 * @} 4248 */ 4249 4250 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 4251 * @{ 4252 */ 4253 4254 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 4255 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 4256 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 4257 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 4258 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 4259 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 4260 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 4261 4262 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 4263 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 4264 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 4265 /** 4266 * @} 4267 */ 4268 4269 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 4270 * @{ 4271 */ 4272 #define __HAL_LTDC_LAYER LTDC_LAYER 4273 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 4274 /** 4275 * @} 4276 */ 4277 4278 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 4279 * @{ 4280 */ 4281 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 4282 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 4283 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 4284 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 4285 #define SAI_STREOMODE SAI_STEREOMODE 4286 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 4287 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 4288 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 4289 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 4290 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 4291 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 4292 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 4293 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 4294 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 4295 /** 4296 * @} 4297 */ 4298 4299 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 4300 * @{ 4301 */ 4302 #if defined(STM32H7) 4303 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 4304 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 4305 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 4306 #endif 4307 /** 4308 * @} 4309 */ 4310 4311 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 4312 * @{ 4313 */ 4314 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 4315 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 4316 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 4317 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 4318 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 4319 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 4320 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 4321 #endif 4322 /** 4323 * @} 4324 */ 4325 4326 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 4327 * @{ 4328 */ 4329 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 4330 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 4331 #endif /* STM32L4 || STM32F4 || STM32F7 */ 4332 /** 4333 * @} 4334 */ 4335 4336 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 4337 * @{ 4338 */ 4339 #if defined (STM32F7) 4340 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 4341 #endif /* STM32F7 */ 4342 /** 4343 * @} 4344 */ 4345 4346 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 4347 * @{ 4348 */ 4349 4350 /** 4351 * @} 4352 */ 4353 4354 #ifdef __cplusplus 4355 } 4356 #endif 4357 4358 #endif /* STM32_HAL_LEGACY */ 4359
