1 /** 2 ****************************************************************************** 3 * @file stm32wlxx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2020 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32WLxx_HAL_DMA_H 21 #define STM32WLxx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32wlxx_hal_def.h" 29 #include "stm32wlxx_ll_dma.h" 30 31 /** @addtogroup STM32WLxx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 } HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 } HAL_DMA_LevelCompleteTypeDef; 96 97 /** 98 * @brief HAL DMA Callback ID structure definition 99 */ 100 typedef enum 101 { 102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 107 108 } HAL_DMA_CallbackIDTypeDef; 109 110 /** 111 * @brief DMA handle Structure definition 112 */ 113 typedef struct __DMA_HandleTypeDef 114 { 115 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 116 117 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 118 119 HAL_LockTypeDef Lock; /*!< DMA locking object */ 120 121 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 122 123 void *Parent; /*!< Parent object state */ 124 125 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 126 127 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 128 129 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 130 131 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 132 133 __IO uint32_t ErrorCode; /*!< DMA Error code */ 134 135 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 136 137 uint32_t ChannelIndex; /*!< DMA Channel Index */ 138 139 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 140 141 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 142 143 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 144 145 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 146 147 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 148 149 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 150 } DMA_HandleTypeDef; 151 /** 152 * @} 153 */ 154 155 /* Exported constants --------------------------------------------------------*/ 156 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants 158 * @{ 159 */ 160 161 /** @defgroup DMA_Error_Code DMA Error Code 162 * @{ 163 */ 164 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 165 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 166 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 167 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 168 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 169 #define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ 170 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 171 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 172 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 173 174 /** 175 * @} 176 */ 177 178 /** @defgroup DMA_request DMA request 179 * @{ 180 */ 181 #define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ 182 #define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ 183 #define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ 184 #define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ 185 #define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ 186 #define DMA_REQUEST_ADC LL_DMAMUX_REQ_ADC /*!< DMAMUX ADC request */ 187 #define DMA_REQUEST_DAC_OUT1 LL_DMAMUX_REQ_DAC_OUT1 /*!< DMAMUX DAC OUT request */ 188 #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ 189 #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ 190 #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ 191 #define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ 192 #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ 193 #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ 194 #define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ 195 #define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ 196 #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ 197 #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ 198 #define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ 199 #define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ 200 #define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ 201 #define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ 202 #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ 203 #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ 204 #define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ 205 #define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ 206 #define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ 207 #define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ 208 #define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ 209 #define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */ 210 #define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */ 211 #define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ 212 #define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ 213 #define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ 214 #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ 215 #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ 216 #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ 217 #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ 218 #define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ 219 #define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ 220 #define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ 221 #define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ 222 #define DMA_REQUEST_SUBGHZSPI_RX LL_DMAMUX_REQ_SUBGHZSPI_RX /*!< DMAMUX SUBGHZSPI RX request*/ 223 #define DMA_REQUEST_SUBGHZSPI_TX LL_DMAMUX_REQ_SUBGHZSPI_TX /*!< DMAMUX SUBGHZSPI TX request*/ 224 225 #define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ 226 /** 227 * @} 228 */ 229 230 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 231 * @{ 232 */ 233 #define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ 234 #define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ 235 #define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ 236 237 /** 238 * @} 239 */ 240 241 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 242 * @{ 243 */ 244 #define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ 245 #define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 251 * @{ 252 */ 253 #define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ 254 #define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ 255 /** 256 * @} 257 */ 258 259 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 260 * @{ 261 */ 262 #define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ 263 #define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ 264 #define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ 265 /** 266 * @} 267 */ 268 269 /** @defgroup DMA_Memory_data_size DMA Memory data size 270 * @{ 271 */ 272 #define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ 273 #define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ 274 #define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup DMA_mode DMA mode 280 * @{ 281 */ 282 #define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ 283 #define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ 284 /** 285 * @} 286 */ 287 288 /** @defgroup DMA_Priority_level DMA Priority level 289 * @{ 290 */ 291 #define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ 292 #define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ 293 #define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ 294 #define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 300 * @{ 301 */ 302 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ 303 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ 304 #define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ 305 /** 306 * @} 307 */ 308 309 /** @defgroup DMA_flag_definitions DMA flag definitions 310 * @{ 311 */ 312 313 #define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ 314 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ 315 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ 316 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ 317 #define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ 318 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ 319 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ 320 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ 321 #define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ 322 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ 323 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ 324 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ 325 #define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ 326 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ 327 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ 328 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ 329 #define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ 330 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ 331 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ 332 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ 333 #define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ 334 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ 335 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ 336 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ 337 #define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ 338 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ 339 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ 340 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ 341 /** 342 * @} 343 */ 344 345 #if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) 346 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 347 * @brief DMA channel secure or non-secure and privileged or non-privileged attributes 348 * @note Secure and non-secure attributes are only available from secure when the system 349 * implements the security (ESE=1) 350 * @{ 351 */ 352 353 #define DMA_CHANNEL_ATTR_PRIV_MASK (DMA_CCR_PRIV >> 16U) 354 #define DMA_CHANNEL_ATTR_SEC_MASK (DMA_CCR_SECM >> 16U) 355 #if defined (CORE_CM0PLUS) 356 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (DMA_CCR_SSEC >> 16U) 357 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (DMA_CCR_DSEC >> 16U) 358 #endif /* CORE_CM0PLUS */ 359 360 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV) /*!< Channel is privileged */ 361 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 362 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM) /*!< Channel is secure */ 363 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 364 #if defined (CORE_CM0PLUS) 365 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC) /*!< Channel source is secure */ 366 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 367 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure */ 368 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 369 #endif /* CORE_CM0PLUS */ 370 /** 371 * @} 372 */ 373 374 #endif /* DMA_SECURE_SWITCH */ 375 /** 376 * @} 377 */ 378 379 /* Exported macros -----------------------------------------------------------*/ 380 /** @defgroup DMA_Exported_Macros DMA Exported Macros 381 * @{ 382 */ 383 384 /** @brief Reset DMA handle state 385 * @param __HANDLE__ DMA handle 386 * @retval None 387 */ 388 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 389 390 /** 391 * @brief Enable the specified DMA Channel. 392 * @param __HANDLE__ DMA handle 393 * @retval None 394 */ 395 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 396 397 /** 398 * @brief Disable the specified DMA Channel. 399 * @param __HANDLE__ DMA handle 400 * @retval None 401 */ 402 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 403 404 /** 405 * @brief Return the current DMA Channel transfer complete flag. 406 * @param __HANDLE__ DMA handle 407 * @retval The specified transfer complete flag index. 408 */ 409 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 410 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 411 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 412 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 413 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 414 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 415 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 416 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 417 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 418 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 419 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 420 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 421 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 422 DMA_FLAG_TC7) 423 424 /** 425 * @brief Return the current DMA Channel half transfer complete flag. 426 * @param __HANDLE__ DMA handle 427 * @retval The specified half transfer complete flag index. 428 */ 429 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ 430 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 442 DMA_FLAG_HT7) 443 444 /** 445 * @brief Return the current DMA Channel transfer error flag. 446 * @param __HANDLE__ DMA handle 447 * @retval The specified transfer error flag index. 448 */ 449 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ 450 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 462 DMA_FLAG_TE7) 463 464 /** 465 * @brief Return the current DMA Channel Global interrupt flag. 466 * @param __HANDLE__ DMA handle 467 * @retval The specified transfer error flag index. 468 */ 469 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ 470 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_GI6 :\ 482 DMA_FLAG_GI7) 483 484 /** 485 * @brief Get the DMA Channel pending flags. 486 * @param __HANDLE__ DMA handle 487 * @param __FLAG__ Get the specified flag. 488 * This parameter can be any combination of the following values: 489 * @arg DMA_FLAG_TCx: Transfer complete flag 490 * @arg DMA_FLAG_HTx: Half transfer complete flag 491 * @arg DMA_FLAG_TEx: Transfer error flag 492 * @arg DMA_FLAG_GIx: Global interrupt flag 493 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 494 * @retval The state of FLAG (SET or RESET). 495 */ 496 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 497 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 498 499 /** 500 * @brief Clear the DMA Channel pending flags. 501 * @param __HANDLE__ DMA handle 502 * @param __FLAG__ specifies the flag to clear. 503 * This parameter can be any combination of the following values: 504 * @arg DMA_FLAG_TCx: Transfer complete flag 505 * @arg DMA_FLAG_HTx: Half transfer complete flag 506 * @arg DMA_FLAG_TEx: Transfer error flag 507 * @arg DMA_FLAG_GIx: Global interrupt flag 508 * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. 509 * @retval None 510 */ 511 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 512 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 513 514 /** 515 * @brief Enable the specified DMA Channel interrupts. 516 * @param __HANDLE__ DMA handle 517 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 518 * This parameter can be any combination of the following values: 519 * @arg DMA_IT_TC: Transfer complete interrupt mask 520 * @arg DMA_IT_HT: Half transfer complete interrupt mask 521 * @arg DMA_IT_TE: Transfer error interrupt mask 522 * @retval None 523 */ 524 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 525 526 /** 527 * @brief Disable the specified DMA Channel interrupts. 528 * @param __HANDLE__ DMA handle 529 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 530 * This parameter can be any combination of the following values: 531 * @arg DMA_IT_TC: Transfer complete interrupt mask 532 * @arg DMA_IT_HT: Half transfer complete interrupt mask 533 * @arg DMA_IT_TE: Transfer error interrupt mask 534 * @retval None 535 */ 536 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 537 538 /** 539 * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. 540 * @param __HANDLE__ DMA handle 541 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 542 * This parameter can be one of the following values: 543 * @arg DMA_IT_TC: Transfer complete interrupt mask 544 * @arg DMA_IT_HT: Half transfer complete interrupt mask 545 * @arg DMA_IT_TE: Transfer error interrupt mask 546 * @retval The state of DMA_IT (SET or RESET). 547 */ 548 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 549 550 /** 551 * @brief Returns the number of remaining data units in the current DMA Channel transfer. 552 * @param __HANDLE__ DMA handle 553 * @retval The number of remaining data units in the current DMA Channel transfer. 554 */ 555 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 556 557 /** 558 * @} 559 */ 560 561 /* Include DMA HAL Extension module */ 562 #include "stm32wlxx_hal_dma_ex.h" 563 564 /* Exported functions --------------------------------------------------------*/ 565 566 /** @addtogroup DMA_Exported_Functions 567 * @{ 568 */ 569 570 /** @addtogroup DMA_Exported_Functions_Group1 571 * @{ 572 */ 573 /* Initialization and de-initialization functions *****************************/ 574 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 575 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 576 /** 577 * @} 578 */ 579 580 /** @addtogroup DMA_Exported_Functions_Group2 581 * @{ 582 */ 583 /* IO operation functions *****************************************************/ 584 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 585 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 586 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 587 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 588 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 589 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 590 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 591 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 592 593 /** 594 * @} 595 */ 596 597 /** @addtogroup DMA_Exported_Functions_Group3 598 * @{ 599 */ 600 /* Peripheral State and Error functions ***************************************/ 601 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 602 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 603 /** 604 * @} 605 */ 606 607 #if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) 608 /** @addtogroup DMA_Exported_Functions_Group4 609 * @{ 610 */ 611 /* DMA Attributes functions ********************************************/ 612 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes); 613 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes); 614 /** 615 * @} 616 */ 617 618 #endif /* DMA_SECURE_SWITCH */ 619 /** 620 * @} 621 */ 622 623 /* Private macros ------------------------------------------------------------*/ 624 /** @defgroup DMA_Private_Macros DMA Private Macros 625 * @{ 626 */ 627 628 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 629 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 630 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 631 632 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) 633 634 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 635 ((STATE) == DMA_PINC_DISABLE)) 636 637 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 638 ((STATE) == DMA_MINC_DISABLE)) 639 640 #define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) 641 642 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 643 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 644 ((SIZE) == DMA_PDATAALIGN_WORD)) 645 646 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 647 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 648 ((SIZE) == DMA_MDATAALIGN_WORD )) 649 650 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 651 ((MODE) == DMA_CIRCULAR)) 652 653 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 654 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 655 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 656 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 657 658 #if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) 659 #if defined (CORE_CM0PLUS) 660 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U)) 661 #else 662 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x00100010U))) == 0U) && (((ATTRIBUTE) & 0x00000010U) != 0U)) 663 #endif /* CORE_CM0PLUS */ 664 #endif /* DMA_SECURE_SWITCH */ 665 /** 666 * @} 667 */ 668 669 /* Private functions ---------------------------------------------------------*/ 670 671 /** 672 * @} 673 */ 674 675 /** 676 * @} 677 */ 678 679 #ifdef __cplusplus 680 } 681 #endif 682 683 #endif /* STM32WLxx_HAL_DMA_H */ 684
