1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WBxx_LL_TIM_H
21 #define __STM32WBxx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM16) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_AF1 register */
122 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
124
125 /* Remap mask definitions */
126 #define TIMx_OR_RMP_SHIFT 16U
127 #define TIMx_OR_RMP_MASK 0x0000FFFFU
128 #define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
129 #define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP) << TIMx_OR_RMP_SHIFT)
130 #if defined(TIM16)
131 #define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
132 #endif /* TIM16 */
133 #if defined(TIM17)
134 #define TIM17_OR_RMP_MASK (TIM17_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
135 #endif /* TIM17 */
136
137 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
138 #define DT_DELAY_1 ((uint8_t)0x7F)
139 #define DT_DELAY_2 ((uint8_t)0x3F)
140 #define DT_DELAY_3 ((uint8_t)0x1F)
141 #define DT_DELAY_4 ((uint8_t)0x1F)
142
143 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
144 #define DT_RANGE_1 ((uint8_t)0x00)
145 #define DT_RANGE_2 ((uint8_t)0x80)
146 #define DT_RANGE_3 ((uint8_t)0xC0)
147 #define DT_RANGE_4 ((uint8_t)0xE0)
148
149 /** Legacy definitions for compatibility purpose
150 @cond 0
151 */
152 /**
153 @endcond
154 */
155
156 /**
157 * @}
158 */
159
160 /* Private macros ------------------------------------------------------------*/
161 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
162 * @{
163 */
164 /** @brief Convert channel id into channel index.
165 * @param __CHANNEL__ This parameter can be one of the following values:
166 * @arg @ref LL_TIM_CHANNEL_CH1
167 * @arg @ref LL_TIM_CHANNEL_CH1N
168 * @arg @ref LL_TIM_CHANNEL_CH2
169 * @arg @ref LL_TIM_CHANNEL_CH2N
170 * @arg @ref LL_TIM_CHANNEL_CH3
171 * @arg @ref LL_TIM_CHANNEL_CH3N
172 * @arg @ref LL_TIM_CHANNEL_CH4
173 * @arg @ref LL_TIM_CHANNEL_CH5
174 * @arg @ref LL_TIM_CHANNEL_CH6
175 * @retval none
176 */
177 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
178 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
186
187 /** @brief Calculate the deadtime sampling period(in ps).
188 * @param __TIMCLK__ timer input clock frequency (in Hz).
189 * @param __CKD__ This parameter can be one of the following values:
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
192 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
193 * @retval none
194 */
195 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
196 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
197 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
198 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
199 /**
200 * @}
201 */
202
203
204 /* Exported types ------------------------------------------------------------*/
205 #if defined(USE_FULL_LL_DRIVER)
206 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
207 * @{
208 */
209
210 /**
211 * @brief TIM Time Base configuration structure definition.
212 */
213 typedef struct
214 {
215 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
216 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
217
218 This feature can be modified afterwards using unitary function
219 @ref LL_TIM_SetPrescaler().*/
220
221 uint32_t CounterMode; /*!< Specifies the counter mode.
222 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
223
224 This feature can be modified afterwards using unitary function
225 @ref LL_TIM_SetCounterMode().*/
226
227 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
228 Auto-Reload Register at the next update event.
229 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
230 Some timer instances may support 32 bits counters. In that case this parameter must
231 be a number between 0x0000 and 0xFFFFFFFF.
232
233 This feature can be modified afterwards using unitary function
234 @ref LL_TIM_SetAutoReload().*/
235
236 uint32_t ClockDivision; /*!< Specifies the clock division.
237 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
238
239 This feature can be modified afterwards using unitary function
240 @ref LL_TIM_SetClockDivision().*/
241
242 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
243 reaches zero, an update event is generated and counting restarts
244 from the RCR value (N).
245 This means in PWM mode that (N+1) corresponds to:
246 - the number of PWM periods in edge-aligned mode
247 - the number of half PWM period in center-aligned mode
248 GP timers: this parameter must be a number between Min_Data = 0x00 and
249 Max_Data = 0xFF.
250 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
251 Max_Data = 0xFFFF.
252
253 This feature can be modified afterwards using unitary function
254 @ref LL_TIM_SetRepetitionCounter().*/
255 } LL_TIM_InitTypeDef;
256
257 /**
258 * @brief TIM Output Compare configuration structure definition.
259 */
260 typedef struct
261 {
262 uint32_t OCMode; /*!< Specifies the output mode.
263 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
264
265 This feature can be modified afterwards using unitary function
266 @ref LL_TIM_OC_SetMode().*/
267
268 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
269 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
270
271 This feature can be modified afterwards using unitary functions
272 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
273
274 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
275 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
276
277 This feature can be modified afterwards using unitary functions
278 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
279
280 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
281 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
282
283 This feature can be modified afterwards using unitary function
284 LL_TIM_OC_SetCompareCHx (x=1..6).*/
285
286 uint32_t OCPolarity; /*!< Specifies the output polarity.
287 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
288
289 This feature can be modified afterwards using unitary function
290 @ref LL_TIM_OC_SetPolarity().*/
291
292 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
293 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
294
295 This feature can be modified afterwards using unitary function
296 @ref LL_TIM_OC_SetPolarity().*/
297
298
299 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
300 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
301
302 This feature can be modified afterwards using unitary function
303 @ref LL_TIM_OC_SetIdleState().*/
304
305 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
306 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
307
308 This feature can be modified afterwards using unitary function
309 @ref LL_TIM_OC_SetIdleState().*/
310 } LL_TIM_OC_InitTypeDef;
311
312 /**
313 * @brief TIM Input Capture configuration structure definition.
314 */
315
316 typedef struct
317 {
318
319 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
320 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_IC_SetPolarity().*/
324
325 uint32_t ICActiveInput; /*!< Specifies the input.
326 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
327
328 This feature can be modified afterwards using unitary function
329 @ref LL_TIM_IC_SetActiveInput().*/
330
331 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
332 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
333
334 This feature can be modified afterwards using unitary function
335 @ref LL_TIM_IC_SetPrescaler().*/
336
337 uint32_t ICFilter; /*!< Specifies the input capture filter.
338 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
339
340 This feature can be modified afterwards using unitary function
341 @ref LL_TIM_IC_SetFilter().*/
342 } LL_TIM_IC_InitTypeDef;
343
344
345 /**
346 * @brief TIM Encoder interface configuration structure definition.
347 */
348 typedef struct
349 {
350 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
351 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
352
353 This feature can be modified afterwards using unitary function
354 @ref LL_TIM_SetEncoderMode().*/
355
356 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
357 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
358
359 This feature can be modified afterwards using unitary function
360 @ref LL_TIM_IC_SetPolarity().*/
361
362 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
363 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
364
365 This feature can be modified afterwards using unitary function
366 @ref LL_TIM_IC_SetActiveInput().*/
367
368 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
369 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
370
371 This feature can be modified afterwards using unitary function
372 @ref LL_TIM_IC_SetPrescaler().*/
373
374 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
375 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
376
377 This feature can be modified afterwards using unitary function
378 @ref LL_TIM_IC_SetFilter().*/
379
380 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
381 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
382
383 This feature can be modified afterwards using unitary function
384 @ref LL_TIM_IC_SetPolarity().*/
385
386 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
387 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
388
389 This feature can be modified afterwards using unitary function
390 @ref LL_TIM_IC_SetActiveInput().*/
391
392 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
393 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
394
395 This feature can be modified afterwards using unitary function
396 @ref LL_TIM_IC_SetPrescaler().*/
397
398 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
399 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
400
401 This feature can be modified afterwards using unitary function
402 @ref LL_TIM_IC_SetFilter().*/
403
404 } LL_TIM_ENCODER_InitTypeDef;
405
406 /**
407 * @brief TIM Hall sensor interface configuration structure definition.
408 */
409 typedef struct
410 {
411
412 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
413 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
414
415 This feature can be modified afterwards using unitary function
416 @ref LL_TIM_IC_SetPolarity().*/
417
418 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
419 Prescaler must be set to get a maximum counter period longer than the
420 time interval between 2 consecutive changes on the Hall inputs.
421 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
422
423 This feature can be modified afterwards using unitary function
424 @ref LL_TIM_IC_SetPrescaler().*/
425
426 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
427 This parameter can be a value of
428 @ref TIM_LL_EC_IC_FILTER.
429
430 This feature can be modified afterwards using unitary function
431 @ref LL_TIM_IC_SetFilter().*/
432
433 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
434 A positive pulse (TRGO event) is generated with a programmable delay every time
435 a change occurs on the Hall inputs.
436 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
437
438 This feature can be modified afterwards using unitary function
439 @ref LL_TIM_OC_SetCompareCH2().*/
440 } LL_TIM_HALLSENSOR_InitTypeDef;
441
442 /**
443 * @brief BDTR (Break and Dead Time) structure definition
444 */
445 typedef struct
446 {
447 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
448 This parameter can be a value of @ref TIM_LL_EC_OSSR
449
450 This feature can be modified afterwards using unitary function
451 @ref LL_TIM_SetOffStates()
452
453 @note This bit-field cannot be modified as long as LOCK level 2 has been
454 programmed. */
455
456 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
457 This parameter can be a value of @ref TIM_LL_EC_OSSI
458
459 This feature can be modified afterwards using unitary function
460 @ref LL_TIM_SetOffStates()
461
462 @note This bit-field cannot be modified as long as LOCK level 2 has been
463 programmed. */
464
465 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
466 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
467
468 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
469 register has been written, their content is frozen until the next reset.*/
470
471 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
472 switching-on of the outputs.
473 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
474
475 This feature can be modified afterwards using unitary function
476 @ref LL_TIM_OC_SetDeadTime()
477
478 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
479 programmed. */
480
481 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
483
484 This feature can be modified afterwards using unitary functions
485 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
486
487 @note This bit-field can not be modified as long as LOCK level 1 has been
488 programmed. */
489
490 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
491 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
492
493 This feature can be modified afterwards using unitary function
494 @ref LL_TIM_ConfigBRK()
495
496 @note This bit-field can not be modified as long as LOCK level 1 has been
497 programmed. */
498
499 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
500 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
501
502 This feature can be modified afterwards using unitary function
503 @ref LL_TIM_ConfigBRK()
504
505 @note This bit-field can not be modified as long as LOCK level 1 has been
506 programmed. */
507
508 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
509 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
510
511 This feature can be modified afterwards using unitary functions
512 @ref LL_TIM_ConfigBRK()
513
514 @note Bidirectional break input is only supported by advanced timers instances.
515
516 @note This bit-field can not be modified as long as LOCK level 1 has been
517 programmed. */
518
519 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
520 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
521
522 This feature can be modified afterwards using unitary functions
523 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
524
525 @note This bit-field can not be modified as long as LOCK level 1 has been
526 programmed. */
527
528 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
529 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
530
531 This feature can be modified afterwards using unitary function
532 @ref LL_TIM_ConfigBRK2()
533
534 @note This bit-field can not be modified as long as LOCK level 1 has been
535 programmed. */
536
537 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
538 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
539
540 This feature can be modified afterwards using unitary function
541 @ref LL_TIM_ConfigBRK2()
542
543 @note This bit-field can not be modified as long as LOCK level 1 has been
544 programmed. */
545
546 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
547 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
548
549 This feature can be modified afterwards using unitary functions
550 @ref LL_TIM_ConfigBRK2()
551
552 @note Bidirectional break input is only supported by advanced timers instances.
553
554 @note This bit-field can not be modified as long as LOCK level 1 has been
555 programmed. */
556
557 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
558 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
559
560 This feature can be modified afterwards using unitary functions
561 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
562
563 @note This bit-field can not be modified as long as LOCK level 1 has been
564 programmed. */
565 } LL_TIM_BDTR_InitTypeDef;
566
567 /**
568 * @}
569 */
570 #endif /* USE_FULL_LL_DRIVER */
571
572 /* Exported constants --------------------------------------------------------*/
573 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
574 * @{
575 */
576
577 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
578 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
579 * @{
580 */
581 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
582 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
583 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
584 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
585 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
586 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
587 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
588 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
589 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
590 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
591 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
592 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
593 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
594 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
595 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
596 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
597 /**
598 * @}
599 */
600
601 #if defined(USE_FULL_LL_DRIVER)
602 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
603 * @{
604 */
605 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
606 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
607 /**
608 * @}
609 */
610
611 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
612 * @{
613 */
614 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
615 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
616 /**
617 * @}
618 */
619
620 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
621 * @{
622 */
623 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
624 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
625 /**
626 * @}
627 */
628 #endif /* USE_FULL_LL_DRIVER */
629
630 /** @defgroup TIM_LL_EC_IT IT Defines
631 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
632 * @{
633 */
634 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
635 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
636 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
637 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
638 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
639 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
640 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
641 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
642 /**
643 * @}
644 */
645
646 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
647 * @{
648 */
649 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
650 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
651 /**
652 * @}
653 */
654
655 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
656 * @{
657 */
658 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
659 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
665 * @{
666 */
667 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
668 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
669 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
670 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
671 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
672 /**
673 * @}
674 */
675
676 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
677 * @{
678 */
679 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
680 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
681 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
687 * @{
688 */
689 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
690 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
691 /**
692 * @}
693 */
694
695 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
696 * @{
697 */
698 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
699 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
705 * @{
706 */
707 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
708 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
714 * @{
715 */
716 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
717 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
718 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
719 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
720 /**
721 * @}
722 */
723
724 /** @defgroup TIM_LL_EC_CHANNEL Channel
725 * @{
726 */
727 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
728 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
729 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
730 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
731 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
732 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
733 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
734 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
735 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
736 /**
737 * @}
738 */
739
740 #if defined(USE_FULL_LL_DRIVER)
741 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
742 * @{
743 */
744 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
745 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
746 /**
747 * @}
748 */
749 #endif /* USE_FULL_LL_DRIVER */
750
751 /** Legacy definitions for compatibility purpose
752 @cond 0
753 */
754 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
755 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
756 /**
757 @endcond
758 */
759
760 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
761 * @{
762 */
763 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
764 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
765 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
766 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
767 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
768 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
769 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
770 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
771 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
772 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
773 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
774 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
775 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
776 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
782 * @{
783 */
784 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
785 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
786 /**
787 * @}
788 */
789
790 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
791 * @{
792 */
793 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
794 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
795 /**
796 * @}
797 */
798
799 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
800 * @{
801 */
802 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
803 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
804 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
805 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
806 /**
807 * @}
808 */
809
810 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
811 * @{
812 */
813 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
814 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
815 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
821 * @{
822 */
823 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
824 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
825 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
826 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
827 /**
828 * @}
829 */
830
831 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
832 * @{
833 */
834 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
835 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
836 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
837 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
838 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
839 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
840 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
841 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
842 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
843 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
844 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
845 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
846 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
847 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
848 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
849 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
850 /**
851 * @}
852 */
853
854 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
855 * @{
856 */
857 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
858 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
859 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
860 /**
861 * @}
862 */
863
864 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
865 * @{
866 */
867 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
868 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
869 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
870 /**
871 * @}
872 */
873
874 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
875 * @{
876 */
877 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
878 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
879 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
880 /**
881 * @}
882 */
883
884 /** @defgroup TIM_LL_EC_TRGO Trigger Output
885 * @{
886 */
887 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
888 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
889 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
890 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
891 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
892 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
893 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
894 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
895 /**
896 * @}
897 */
898
899 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
900 * @{
901 */
902 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
903 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
904 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
905 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
909 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
910 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
911 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
912 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
913 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
915 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
916 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
917 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
918 /**
919 * @}
920 */
921
922 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
923 * @{
924 */
925 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
926 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
927 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
928 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
929 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
930 /**
931 * @}
932 */
933
934 /** @defgroup TIM_LL_EC_TS Trigger Selection
935 * @{
936 */
937 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
938 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
939 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
940 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
941 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
942 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
943 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
944 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
945 /**
946 * @}
947 */
948
949 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
950 * @{
951 */
952 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
953 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
954 /**
955 * @}
956 */
957
958 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
959 * @{
960 */
961 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
962 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
963 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
964 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
965 /**
966 * @}
967 */
968
969 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
970 * @{
971 */
972 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
973 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
974 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
975 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
976 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
977 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
978 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
979 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
980 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
981 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
982 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
983 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
984 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
985 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
986 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
987 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
988 /**
989 * @}
990 */
991
992 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
993 * @{
994 */
995 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */
996 #if defined(COMP1)
997 #define LL_TIM_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
998 #endif /* COMP1 */
999 #if defined(COMP2)
1000 #define LL_TIM_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1001 #endif /* COMP2 */
1002 #define LL_TIM_ETRSOURCE_GPIO LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to GPIO through TIMx ETR remapping capability */
1003 #define LL_TIM_ETRSOURCE_ADC1_AWD1 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 1 through TIMx ETR remapping capability */
1004 #if defined(ADC_SUPPORT_5_MSPS)
1005 #define LL_TIM_ETRSOURCE_ADC1_AWD2 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 2 through TIMx ETR remapping capability */
1006 #define LL_TIM_ETRSOURCE_ADC1_AWD3 LL_TIM_ETRSOURCE_LEGACY /*!< ETR input is connected to ADC1 analog watchdog 3 through TIMx ETR remapping capability */
1007 #endif
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1013 * @{
1014 */
1015 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1016 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1017 /**
1018 * @}
1019 */
1020
1021 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1022 * @{
1023 */
1024 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1025 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1026 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1027 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1028 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1029 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1030 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1031 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1032 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1033 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1034 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1035 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1036 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1037 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1038 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1039 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1045 * @{
1046 */
1047 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1048 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1049 /**
1050 * @}
1051 */
1052
1053 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1054 * @{
1055 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1057 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1059 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1061 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1063 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1064 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1065 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1066 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1067 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1068 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1069 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1070 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1071 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup TIM_LL_EC_OSSI OSSI
1077 * @{
1078 */
1079 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1080 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup TIM_LL_EC_OSSR OSSR
1086 * @{
1087 */
1088 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1089 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1090 /**
1091 * @}
1092 */
1093
1094 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1095 * @{
1096 */
1097 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1098 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1099 /**
1100 * @}
1101 */
1102
1103 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1104 * @{
1105 */
1106 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1107 #if defined(COMP1)
1108 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1109 #endif /* COMP1 */
1110 #if defined(COMP2)
1111 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1112 #endif /* COMP2 */
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1118 * @{
1119 */
1120 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1121 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1127 * @{
1128 */
1129 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1130 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1131 /**
1132 * @}
1133 */
1134
1135 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1136 * @{
1137 */
1138 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1139 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1140 /**
1141 * @}
1142 */
1143
1144 /** Legacy definitions for compatibility purpose
1145 @cond 0
1146 */
1147 #define LL_TIM_ReArmBRK(_PARAM_)
1148 #define LL_TIM_ReArmBRK2(_PARAM_)
1149 /**
1150 @endcond
1151 */
1152
1153 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1154 * @{
1155 */
1156 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1157 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1158 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1159 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1161 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1162 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1163 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1164 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1165 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1166 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1167 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1168 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1169 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1170 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1171 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1172 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1173 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1174 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR register is the DMA base address for DMA burst */
1175 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1176 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1177 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1178 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1179 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1185 * @{
1186 */
1187 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1188 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1189 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1190 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1191 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1192 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1193 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1194 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1195 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1196 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1197 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1198 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1199 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1200 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1201 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1202 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1203 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1204 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1205 /**
1206 * @}
1207 */
1208
1209 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1210 * @{
1211 */
1212 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1213 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1214 #if defined(ADC_SUPPORT_5_MSPS)
1215 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR_ETR_ADC1_RMP_1 | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1216 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1217 #endif
1218 /**
1219 * @}
1220 */
1221
1222 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1223 * @{
1224 */
1225 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1226 #if defined(COMP1)
1227 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR_TI1_RMP | TIM1_OR_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1228 #endif /* COMP1 */
1229 /**
1230 * @}
1231 */
1232
1233 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1234 * @{
1235 */
1236 #define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /*!< No internal trigger on TIM2_ITR1 */
1237 #if defined(USB)
1238 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /*!< TIM2_ITR1 is connected to USB SOF */
1239 #endif /* USB */
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup TIM_LL_EC_TIM2_ETR_RMP TIM2 External Trigger Remap
1245 * @{
1246 */
1247 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1248 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR_ETR_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1254 * @{
1255 */
1256 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1257 #if defined(COMP1)
1258 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR_TI4_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1259 #endif /* COMP1 */
1260 #if defined(COMP2)
1261 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR_TI4_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1262 #endif /* COMP2 */
1263 #if defined(COMP1) && defined(COMP2)
1264 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR_TI4_RMP | TIM2_OR_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1265 #endif /* COMP1 && COMP2 */
1266 /**
1267 * @}
1268 */
1269
1270 #if defined(TIM16)
1271 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1272 * @{
1273 */
1274 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1275 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1276 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR_TI1_RMP_1 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1277 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR_TI1_RMP_1 | TIM16_OR_TI1_RMP_0 | TIM16_OR_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1278 /**
1279 * @}
1280 */
1281 #endif /* TIM16 */
1282
1283 #if defined(TIM17)
1284 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1285 * @{
1286 */
1287 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1288 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR_TI1_RMP_0 | TIM17_OR_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1289 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR_TI1_RMP_1 | TIM17_OR_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1290 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR_TI1_RMP | TIM17_OR_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1291 /**
1292 * @}
1293 */
1294 #endif /* TIM17 */
1295
1296 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1297 * @{
1298 */
1299 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1300 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1301 /**
1302 * @}
1303 */
1304
1305 /** Legacy definitions for compatibility purpose
1306 @cond 0
1307 */
1308 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1309 /**
1310 @endcond
1311 */
1312
1313 /**
1314 * @}
1315 */
1316
1317 /* Exported macro ------------------------------------------------------------*/
1318 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1319 * @{
1320 */
1321
1322 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1323 * @{
1324 */
1325 /**
1326 * @brief Write a value in TIM register.
1327 * @param __INSTANCE__ TIM Instance
1328 * @param __REG__ Register to be written
1329 * @param __VALUE__ Value to be written in the register
1330 * @retval None
1331 */
1332 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1333
1334 /**
1335 * @brief Read a value in TIM register.
1336 * @param __INSTANCE__ TIM Instance
1337 * @param __REG__ Register to be read
1338 * @retval Register value
1339 */
1340 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1341 /**
1342 * @}
1343 */
1344
1345 /**
1346 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1347 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1348 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1349 * to TIMx_CNT register bit 31)
1350 * @param __CNT__ Counter value
1351 * @retval UIF status bit
1352 */
1353 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1354 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1355
1356 /**
1357 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1358 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1359 * @param __TIMCLK__ timer input clock frequency (in Hz)
1360 * @param __CKD__ This parameter can be one of the following values:
1361 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1362 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1363 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1364 * @param __DT__ deadtime duration (in ns)
1365 * @retval DTG[0:7]
1366 */
1367 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1368 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1369 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1370 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1371 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1372 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1373 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1374 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1375 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1376 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1377 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1378 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1379 0U)
1380
1381 /**
1382 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1383 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1384 * @param __TIMCLK__ timer input clock frequency (in Hz)
1385 * @param __CNTCLK__ counter clock frequency (in Hz)
1386 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1387 */
1388 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1389 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1390
1391 /**
1392 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1393 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1394 * @param __TIMCLK__ timer input clock frequency (in Hz)
1395 * @param __PSC__ prescaler
1396 * @param __FREQ__ output signal frequency (in Hz)
1397 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1398 */
1399 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1400 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1401
1402 /**
1403 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1404 * active/inactive delay.
1405 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1406 * @param __TIMCLK__ timer input clock frequency (in Hz)
1407 * @param __PSC__ prescaler
1408 * @param __DELAY__ timer output compare active/inactive delay (in us)
1409 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1410 */
1411 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1412 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1413 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1414
1415 /**
1416 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1417 * (when the timer operates in one pulse mode).
1418 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1419 * @param __TIMCLK__ timer input clock frequency (in Hz)
1420 * @param __PSC__ prescaler
1421 * @param __DELAY__ timer output compare active/inactive delay (in us)
1422 * @param __PULSE__ pulse duration (in us)
1423 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1424 */
1425 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1426 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1427 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1428
1429 /**
1430 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1431 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1432 * @param __ICPSC__ This parameter can be one of the following values:
1433 * @arg @ref LL_TIM_ICPSC_DIV1
1434 * @arg @ref LL_TIM_ICPSC_DIV2
1435 * @arg @ref LL_TIM_ICPSC_DIV4
1436 * @arg @ref LL_TIM_ICPSC_DIV8
1437 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1438 */
1439 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1440 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1441
1442
1443 /**
1444 * @}
1445 */
1446
1447 /* Exported functions --------------------------------------------------------*/
1448 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1449 * @{
1450 */
1451
1452 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1453 * @{
1454 */
1455 /**
1456 * @brief Enable timer counter.
1457 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1458 * @param TIMx Timer instance
1459 * @retval None
1460 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1461 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1462 {
1463 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1464 }
1465
1466 /**
1467 * @brief Disable timer counter.
1468 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1469 * @param TIMx Timer instance
1470 * @retval None
1471 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1472 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1473 {
1474 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1475 }
1476
1477 /**
1478 * @brief Indicates whether the timer counter is enabled.
1479 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1480 * @param TIMx Timer instance
1481 * @retval State of bit (1 or 0).
1482 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1483 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1484 {
1485 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1486 }
1487
1488 /**
1489 * @brief Enable update event generation.
1490 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1491 * @param TIMx Timer instance
1492 * @retval None
1493 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1494 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1495 {
1496 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1497 }
1498
1499 /**
1500 * @brief Disable update event generation.
1501 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1502 * @param TIMx Timer instance
1503 * @retval None
1504 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1505 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1506 {
1507 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1508 }
1509
1510 /**
1511 * @brief Indicates whether update event generation is enabled.
1512 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1513 * @param TIMx Timer instance
1514 * @retval Inverted state of bit (0 or 1).
1515 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1516 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1517 {
1518 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1519 }
1520
1521 /**
1522 * @brief Set update event source
1523 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1524 * generate an update interrupt or DMA request if enabled:
1525 * - Counter overflow/underflow
1526 * - Setting the UG bit
1527 * - Update generation through the slave mode controller
1528 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1529 * overflow/underflow generates an update interrupt or DMA request if enabled.
1530 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1531 * @param TIMx Timer instance
1532 * @param UpdateSource This parameter can be one of the following values:
1533 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1534 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1535 * @retval None
1536 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1537 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1538 {
1539 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1540 }
1541
1542 /**
1543 * @brief Get actual event update source
1544 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1545 * @param TIMx Timer instance
1546 * @retval Returned value can be one of the following values:
1547 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1548 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1549 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1550 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1551 {
1552 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1553 }
1554
1555 /**
1556 * @brief Set one pulse mode (one shot v.s. repetitive).
1557 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1558 * @param TIMx Timer instance
1559 * @param OnePulseMode This parameter can be one of the following values:
1560 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1561 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1562 * @retval None
1563 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1564 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1565 {
1566 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1567 }
1568
1569 /**
1570 * @brief Get actual one pulse mode.
1571 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1572 * @param TIMx Timer instance
1573 * @retval Returned value can be one of the following values:
1574 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1575 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1576 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1577 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1578 {
1579 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1580 }
1581
1582 /**
1583 * @brief Set the timer counter counting mode.
1584 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1585 * check whether or not the counter mode selection feature is supported
1586 * by a timer instance.
1587 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1588 * requires a timer reset to avoid unexpected direction
1589 * due to DIR bit readonly in center aligned mode.
1590 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1591 * CR1 CMS LL_TIM_SetCounterMode
1592 * @param TIMx Timer instance
1593 * @param CounterMode This parameter can be one of the following values:
1594 * @arg @ref LL_TIM_COUNTERMODE_UP
1595 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1596 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1597 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1598 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1599 * @retval None
1600 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1601 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1602 {
1603 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1604 }
1605
1606 /**
1607 * @brief Get actual counter mode.
1608 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1609 * check whether or not the counter mode selection feature is supported
1610 * by a timer instance.
1611 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1612 * CR1 CMS LL_TIM_GetCounterMode
1613 * @param TIMx Timer instance
1614 * @retval Returned value can be one of the following values:
1615 * @arg @ref LL_TIM_COUNTERMODE_UP
1616 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1617 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1618 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1619 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1620 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1621 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1622 {
1623 uint32_t counter_mode;
1624
1625 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1626
1627 if (counter_mode == 0U)
1628 {
1629 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1630 }
1631
1632 return counter_mode;
1633 }
1634
1635 /**
1636 * @brief Enable auto-reload (ARR) preload.
1637 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1638 * @param TIMx Timer instance
1639 * @retval None
1640 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1641 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1642 {
1643 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1644 }
1645
1646 /**
1647 * @brief Disable auto-reload (ARR) preload.
1648 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1649 * @param TIMx Timer instance
1650 * @retval None
1651 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1652 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1653 {
1654 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1655 }
1656
1657 /**
1658 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1659 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1660 * @param TIMx Timer instance
1661 * @retval State of bit (1 or 0).
1662 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1663 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1664 {
1665 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1666 }
1667
1668 /**
1669 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1670 * (when supported) and the digital filters.
1671 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1672 * whether or not the clock division feature is supported by the timer
1673 * instance.
1674 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1675 * @param TIMx Timer instance
1676 * @param ClockDivision This parameter can be one of the following values:
1677 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1678 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1679 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1680 * @retval None
1681 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1682 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1683 {
1684 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1685 }
1686
1687 /**
1688 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1689 * generators (when supported) and the digital filters.
1690 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1691 * whether or not the clock division feature is supported by the timer
1692 * instance.
1693 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1694 * @param TIMx Timer instance
1695 * @retval Returned value can be one of the following values:
1696 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1697 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1698 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1699 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1700 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1701 {
1702 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1703 }
1704
1705 /**
1706 * @brief Set the counter value.
1707 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1708 * whether or not a timer instance supports a 32 bits counter.
1709 * @rmtoll CNT CNT LL_TIM_SetCounter
1710 * @param TIMx Timer instance
1711 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1712 * @retval None
1713 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1714 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1715 {
1716 WRITE_REG(TIMx->CNT, Counter);
1717 }
1718
1719 /**
1720 * @brief Get the counter value.
1721 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1722 * whether or not a timer instance supports a 32 bits counter.
1723 * @rmtoll CNT CNT LL_TIM_GetCounter
1724 * @param TIMx Timer instance
1725 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1726 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1727 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1728 {
1729 return (uint32_t)(READ_REG(TIMx->CNT));
1730 }
1731
1732 /**
1733 * @brief Get the current direction of the counter
1734 * @rmtoll CR1 DIR LL_TIM_GetDirection
1735 * @param TIMx Timer instance
1736 * @retval Returned value can be one of the following values:
1737 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1738 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1739 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1740 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1741 {
1742 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1743 }
1744
1745 /**
1746 * @brief Set the prescaler value.
1747 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1748 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1749 * prescaler ratio is taken into account at the next update event.
1750 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1751 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1752 * @param TIMx Timer instance
1753 * @param Prescaler between Min_Data=0 and Max_Data=65535
1754 * @retval None
1755 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1756 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1757 {
1758 WRITE_REG(TIMx->PSC, Prescaler);
1759 }
1760
1761 /**
1762 * @brief Get the prescaler value.
1763 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1764 * @param TIMx Timer instance
1765 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1766 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1767 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1768 {
1769 return (uint32_t)(READ_REG(TIMx->PSC));
1770 }
1771
1772 /**
1773 * @brief Set the auto-reload value.
1774 * @note The counter is blocked while the auto-reload value is null.
1775 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1776 * whether or not a timer instance supports a 32 bits counter.
1777 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1778 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1779 * @param TIMx Timer instance
1780 * @param AutoReload between Min_Data=0 and Max_Data=65535
1781 * @retval None
1782 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1783 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1784 {
1785 WRITE_REG(TIMx->ARR, AutoReload);
1786 }
1787
1788 /**
1789 * @brief Get the auto-reload value.
1790 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1791 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1792 * whether or not a timer instance supports a 32 bits counter.
1793 * @param TIMx Timer instance
1794 * @retval Auto-reload value
1795 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1796 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1797 {
1798 return (uint32_t)(READ_REG(TIMx->ARR));
1799 }
1800
1801 /**
1802 * @brief Set the repetition counter value.
1803 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1804 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1805 * whether or not a timer instance supports a repetition counter.
1806 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1807 * @param TIMx Timer instance
1808 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1809 * @retval None
1810 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1811 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1812 {
1813 WRITE_REG(TIMx->RCR, RepetitionCounter);
1814 }
1815
1816 /**
1817 * @brief Get the repetition counter value.
1818 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1819 * whether or not a timer instance supports a repetition counter.
1820 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1821 * @param TIMx Timer instance
1822 * @retval Repetition counter value
1823 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1824 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1825 {
1826 return (uint32_t)(READ_REG(TIMx->RCR));
1827 }
1828
1829 /**
1830 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1831 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1832 * in an atomic way.
1833 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1834 * @param TIMx Timer instance
1835 * @retval None
1836 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1837 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1838 {
1839 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1840 }
1841
1842 /**
1843 * @brief Disable update interrupt flag (UIF) remapping.
1844 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1845 * @param TIMx Timer instance
1846 * @retval None
1847 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1848 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1849 {
1850 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1851 }
1852
1853 /**
1854 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1855 * @param Counter Counter value
1856 * @retval State of bit (1 or 0).
1857 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1858 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1859 {
1860 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1861 }
1862
1863 /**
1864 * @}
1865 */
1866
1867 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1868 * @{
1869 */
1870 /**
1871 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1872 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1873 * they are updated only when a commutation event (COM) occurs.
1874 * @note Only on channels that have a complementary output.
1875 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1876 * whether or not a timer instance is able to generate a commutation event.
1877 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1878 * @param TIMx Timer instance
1879 * @retval None
1880 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1881 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1882 {
1883 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1884 }
1885
1886 /**
1887 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1888 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1889 * whether or not a timer instance is able to generate a commutation event.
1890 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1891 * @param TIMx Timer instance
1892 * @retval None
1893 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1894 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1895 {
1896 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1897 }
1898
1899 /**
1900 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1901 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1902 * @param TIMx Timer instance
1903 * @retval State of bit (1 or 0).
1904 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1905 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1906 {
1907 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1908 }
1909
1910 /**
1911 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1912 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1913 * whether or not a timer instance is able to generate a commutation event.
1914 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1915 * @param TIMx Timer instance
1916 * @param CCUpdateSource This parameter can be one of the following values:
1917 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1918 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1919 * @retval None
1920 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1921 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1922 {
1923 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1924 }
1925
1926 /**
1927 * @brief Set the trigger of the capture/compare DMA request.
1928 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1929 * @param TIMx Timer instance
1930 * @param DMAReqTrigger This parameter can be one of the following values:
1931 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1932 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1933 * @retval None
1934 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1935 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1936 {
1937 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1938 }
1939
1940 /**
1941 * @brief Get actual trigger of the capture/compare DMA request.
1942 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1943 * @param TIMx Timer instance
1944 * @retval Returned value can be one of the following values:
1945 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1946 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1947 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1948 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1949 {
1950 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1951 }
1952
1953 /**
1954 * @brief Set the lock level to freeze the
1955 * configuration of several capture/compare parameters.
1956 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1957 * the lock mechanism is supported by a timer instance.
1958 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1959 * @param TIMx Timer instance
1960 * @param LockLevel This parameter can be one of the following values:
1961 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1962 * @arg @ref LL_TIM_LOCKLEVEL_1
1963 * @arg @ref LL_TIM_LOCKLEVEL_2
1964 * @arg @ref LL_TIM_LOCKLEVEL_3
1965 * @retval None
1966 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1967 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1968 {
1969 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1970 }
1971
1972 /**
1973 * @brief Enable capture/compare channels.
1974 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1975 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1976 * CCER CC2E LL_TIM_CC_EnableChannel\n
1977 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1978 * CCER CC3E LL_TIM_CC_EnableChannel\n
1979 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1980 * CCER CC4E LL_TIM_CC_EnableChannel\n
1981 * CCER CC5E LL_TIM_CC_EnableChannel\n
1982 * CCER CC6E LL_TIM_CC_EnableChannel
1983 * @param TIMx Timer instance
1984 * @param Channels This parameter can be a combination of the following values:
1985 * @arg @ref LL_TIM_CHANNEL_CH1
1986 * @arg @ref LL_TIM_CHANNEL_CH1N
1987 * @arg @ref LL_TIM_CHANNEL_CH2
1988 * @arg @ref LL_TIM_CHANNEL_CH2N
1989 * @arg @ref LL_TIM_CHANNEL_CH3
1990 * @arg @ref LL_TIM_CHANNEL_CH3N
1991 * @arg @ref LL_TIM_CHANNEL_CH4
1992 * @arg @ref LL_TIM_CHANNEL_CH5
1993 * @arg @ref LL_TIM_CHANNEL_CH6
1994 * @retval None
1995 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1996 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1997 {
1998 SET_BIT(TIMx->CCER, Channels);
1999 }
2000
2001 /**
2002 * @brief Disable capture/compare channels.
2003 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2004 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2005 * CCER CC2E LL_TIM_CC_DisableChannel\n
2006 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2007 * CCER CC3E LL_TIM_CC_DisableChannel\n
2008 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2009 * CCER CC4E LL_TIM_CC_DisableChannel\n
2010 * CCER CC5E LL_TIM_CC_DisableChannel\n
2011 * CCER CC6E LL_TIM_CC_DisableChannel
2012 * @param TIMx Timer instance
2013 * @param Channels This parameter can be a combination of the following values:
2014 * @arg @ref LL_TIM_CHANNEL_CH1
2015 * @arg @ref LL_TIM_CHANNEL_CH1N
2016 * @arg @ref LL_TIM_CHANNEL_CH2
2017 * @arg @ref LL_TIM_CHANNEL_CH2N
2018 * @arg @ref LL_TIM_CHANNEL_CH3
2019 * @arg @ref LL_TIM_CHANNEL_CH3N
2020 * @arg @ref LL_TIM_CHANNEL_CH4
2021 * @arg @ref LL_TIM_CHANNEL_CH5
2022 * @arg @ref LL_TIM_CHANNEL_CH6
2023 * @retval None
2024 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2025 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2026 {
2027 CLEAR_BIT(TIMx->CCER, Channels);
2028 }
2029
2030 /**
2031 * @brief Indicate whether channel(s) is(are) enabled.
2032 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2033 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2034 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2035 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2036 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2037 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2038 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2039 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2040 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2041 * @param TIMx Timer instance
2042 * @param Channels This parameter can be a combination of the following values:
2043 * @arg @ref LL_TIM_CHANNEL_CH1
2044 * @arg @ref LL_TIM_CHANNEL_CH1N
2045 * @arg @ref LL_TIM_CHANNEL_CH2
2046 * @arg @ref LL_TIM_CHANNEL_CH2N
2047 * @arg @ref LL_TIM_CHANNEL_CH3
2048 * @arg @ref LL_TIM_CHANNEL_CH3N
2049 * @arg @ref LL_TIM_CHANNEL_CH4
2050 * @arg @ref LL_TIM_CHANNEL_CH5
2051 * @arg @ref LL_TIM_CHANNEL_CH6
2052 * @retval State of bit (1 or 0).
2053 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2054 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2055 {
2056 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2057 }
2058
2059 /**
2060 * @}
2061 */
2062
2063 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2064 * @{
2065 */
2066 /**
2067 * @brief Configure an output channel.
2068 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2069 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2070 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2071 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2072 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2073 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2074 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2075 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2076 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2077 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2078 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2079 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2080 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2081 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2082 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2083 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2084 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2085 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2086 * @param TIMx Timer instance
2087 * @param Channel This parameter can be one of the following values:
2088 * @arg @ref LL_TIM_CHANNEL_CH1
2089 * @arg @ref LL_TIM_CHANNEL_CH2
2090 * @arg @ref LL_TIM_CHANNEL_CH3
2091 * @arg @ref LL_TIM_CHANNEL_CH4
2092 * @arg @ref LL_TIM_CHANNEL_CH5
2093 * @arg @ref LL_TIM_CHANNEL_CH6
2094 * @param Configuration This parameter must be a combination of all the following values:
2095 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2096 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2097 * @retval None
2098 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2099 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2100 {
2101 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2102 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2103 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2104 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2105 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2106 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2107 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2108 }
2109
2110 /**
2111 * @brief Define the behavior of the output reference signal OCxREF from which
2112 * OCx and OCxN (when relevant) are derived.
2113 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2114 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2115 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2116 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2117 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2118 * CCMR3 OC6M LL_TIM_OC_SetMode
2119 * @param TIMx Timer instance
2120 * @param Channel This parameter can be one of the following values:
2121 * @arg @ref LL_TIM_CHANNEL_CH1
2122 * @arg @ref LL_TIM_CHANNEL_CH2
2123 * @arg @ref LL_TIM_CHANNEL_CH3
2124 * @arg @ref LL_TIM_CHANNEL_CH4
2125 * @arg @ref LL_TIM_CHANNEL_CH5
2126 * @arg @ref LL_TIM_CHANNEL_CH6
2127 * @param Mode This parameter can be one of the following values:
2128 * @arg @ref LL_TIM_OCMODE_FROZEN
2129 * @arg @ref LL_TIM_OCMODE_ACTIVE
2130 * @arg @ref LL_TIM_OCMODE_INACTIVE
2131 * @arg @ref LL_TIM_OCMODE_TOGGLE
2132 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2133 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2134 * @arg @ref LL_TIM_OCMODE_PWM1
2135 * @arg @ref LL_TIM_OCMODE_PWM2
2136 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2137 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2138 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2139 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2140 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2141 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2142 * @retval None
2143 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2144 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2145 {
2146 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2147 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2148 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2149 }
2150
2151 /**
2152 * @brief Get the output compare mode of an output channel.
2153 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2154 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2155 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2156 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2157 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2158 * CCMR3 OC6M LL_TIM_OC_GetMode
2159 * @param TIMx Timer instance
2160 * @param Channel This parameter can be one of the following values:
2161 * @arg @ref LL_TIM_CHANNEL_CH1
2162 * @arg @ref LL_TIM_CHANNEL_CH2
2163 * @arg @ref LL_TIM_CHANNEL_CH3
2164 * @arg @ref LL_TIM_CHANNEL_CH4
2165 * @arg @ref LL_TIM_CHANNEL_CH5
2166 * @arg @ref LL_TIM_CHANNEL_CH6
2167 * @retval Returned value can be one of the following values:
2168 * @arg @ref LL_TIM_OCMODE_FROZEN
2169 * @arg @ref LL_TIM_OCMODE_ACTIVE
2170 * @arg @ref LL_TIM_OCMODE_INACTIVE
2171 * @arg @ref LL_TIM_OCMODE_TOGGLE
2172 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2173 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2174 * @arg @ref LL_TIM_OCMODE_PWM1
2175 * @arg @ref LL_TIM_OCMODE_PWM2
2176 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2177 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2178 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2179 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2180 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2181 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2182 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2183 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2184 {
2185 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2186 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2187 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2188 }
2189
2190 /**
2191 * @brief Set the polarity of an output channel.
2192 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2193 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2194 * CCER CC2P LL_TIM_OC_SetPolarity\n
2195 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2196 * CCER CC3P LL_TIM_OC_SetPolarity\n
2197 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2198 * CCER CC4P LL_TIM_OC_SetPolarity\n
2199 * CCER CC5P LL_TIM_OC_SetPolarity\n
2200 * CCER CC6P LL_TIM_OC_SetPolarity
2201 * @param TIMx Timer instance
2202 * @param Channel This parameter can be one of the following values:
2203 * @arg @ref LL_TIM_CHANNEL_CH1
2204 * @arg @ref LL_TIM_CHANNEL_CH1N
2205 * @arg @ref LL_TIM_CHANNEL_CH2
2206 * @arg @ref LL_TIM_CHANNEL_CH2N
2207 * @arg @ref LL_TIM_CHANNEL_CH3
2208 * @arg @ref LL_TIM_CHANNEL_CH3N
2209 * @arg @ref LL_TIM_CHANNEL_CH4
2210 * @arg @ref LL_TIM_CHANNEL_CH5
2211 * @arg @ref LL_TIM_CHANNEL_CH6
2212 * @param Polarity This parameter can be one of the following values:
2213 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2214 * @arg @ref LL_TIM_OCPOLARITY_LOW
2215 * @retval None
2216 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2217 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2218 {
2219 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2220 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2221 }
2222
2223 /**
2224 * @brief Get the polarity of an output channel.
2225 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2226 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2227 * CCER CC2P LL_TIM_OC_GetPolarity\n
2228 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2229 * CCER CC3P LL_TIM_OC_GetPolarity\n
2230 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2231 * CCER CC4P LL_TIM_OC_GetPolarity\n
2232 * CCER CC5P LL_TIM_OC_GetPolarity\n
2233 * CCER CC6P LL_TIM_OC_GetPolarity
2234 * @param TIMx Timer instance
2235 * @param Channel This parameter can be one of the following values:
2236 * @arg @ref LL_TIM_CHANNEL_CH1
2237 * @arg @ref LL_TIM_CHANNEL_CH1N
2238 * @arg @ref LL_TIM_CHANNEL_CH2
2239 * @arg @ref LL_TIM_CHANNEL_CH2N
2240 * @arg @ref LL_TIM_CHANNEL_CH3
2241 * @arg @ref LL_TIM_CHANNEL_CH3N
2242 * @arg @ref LL_TIM_CHANNEL_CH4
2243 * @arg @ref LL_TIM_CHANNEL_CH5
2244 * @arg @ref LL_TIM_CHANNEL_CH6
2245 * @retval Returned value can be one of the following values:
2246 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2247 * @arg @ref LL_TIM_OCPOLARITY_LOW
2248 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2249 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2250 {
2251 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2252 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2253 }
2254
2255 /**
2256 * @brief Set the IDLE state of an output channel
2257 * @note This function is significant only for the timer instances
2258 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2259 * can be used to check whether or not a timer instance provides
2260 * a break input.
2261 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2262 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2263 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2264 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2265 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2266 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2267 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2268 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2269 * CR2 OIS6 LL_TIM_OC_SetIdleState
2270 * @param TIMx Timer instance
2271 * @param Channel This parameter can be one of the following values:
2272 * @arg @ref LL_TIM_CHANNEL_CH1
2273 * @arg @ref LL_TIM_CHANNEL_CH1N
2274 * @arg @ref LL_TIM_CHANNEL_CH2
2275 * @arg @ref LL_TIM_CHANNEL_CH2N
2276 * @arg @ref LL_TIM_CHANNEL_CH3
2277 * @arg @ref LL_TIM_CHANNEL_CH3N
2278 * @arg @ref LL_TIM_CHANNEL_CH4
2279 * @arg @ref LL_TIM_CHANNEL_CH5
2280 * @arg @ref LL_TIM_CHANNEL_CH6
2281 * @param IdleState This parameter can be one of the following values:
2282 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2283 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2284 * @retval None
2285 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2286 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2287 {
2288 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2289 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2290 }
2291
2292 /**
2293 * @brief Get the IDLE state of an output channel
2294 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2295 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2296 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2297 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2298 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2299 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2300 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2301 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2302 * CR2 OIS6 LL_TIM_OC_GetIdleState
2303 * @param TIMx Timer instance
2304 * @param Channel This parameter can be one of the following values:
2305 * @arg @ref LL_TIM_CHANNEL_CH1
2306 * @arg @ref LL_TIM_CHANNEL_CH1N
2307 * @arg @ref LL_TIM_CHANNEL_CH2
2308 * @arg @ref LL_TIM_CHANNEL_CH2N
2309 * @arg @ref LL_TIM_CHANNEL_CH3
2310 * @arg @ref LL_TIM_CHANNEL_CH3N
2311 * @arg @ref LL_TIM_CHANNEL_CH4
2312 * @arg @ref LL_TIM_CHANNEL_CH5
2313 * @arg @ref LL_TIM_CHANNEL_CH6
2314 * @retval Returned value can be one of the following values:
2315 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2316 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2317 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2318 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2319 {
2320 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2321 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2322 }
2323
2324 /**
2325 * @brief Enable fast mode for the output channel.
2326 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2327 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2328 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2329 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2330 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2331 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2332 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2333 * @param TIMx Timer instance
2334 * @param Channel This parameter can be one of the following values:
2335 * @arg @ref LL_TIM_CHANNEL_CH1
2336 * @arg @ref LL_TIM_CHANNEL_CH2
2337 * @arg @ref LL_TIM_CHANNEL_CH3
2338 * @arg @ref LL_TIM_CHANNEL_CH4
2339 * @arg @ref LL_TIM_CHANNEL_CH5
2340 * @arg @ref LL_TIM_CHANNEL_CH6
2341 * @retval None
2342 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2343 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2344 {
2345 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2346 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2347 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2348
2349 }
2350
2351 /**
2352 * @brief Disable fast mode for the output channel.
2353 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2354 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2355 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2356 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2357 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2358 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2359 * @param TIMx Timer instance
2360 * @param Channel This parameter can be one of the following values:
2361 * @arg @ref LL_TIM_CHANNEL_CH1
2362 * @arg @ref LL_TIM_CHANNEL_CH2
2363 * @arg @ref LL_TIM_CHANNEL_CH3
2364 * @arg @ref LL_TIM_CHANNEL_CH4
2365 * @arg @ref LL_TIM_CHANNEL_CH5
2366 * @arg @ref LL_TIM_CHANNEL_CH6
2367 * @retval None
2368 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2369 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2370 {
2371 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2372 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2373 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2374
2375 }
2376
2377 /**
2378 * @brief Indicates whether fast mode is enabled for the output channel.
2379 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2380 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2381 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2382 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2383 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2384 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2385 * @param TIMx Timer instance
2386 * @param Channel This parameter can be one of the following values:
2387 * @arg @ref LL_TIM_CHANNEL_CH1
2388 * @arg @ref LL_TIM_CHANNEL_CH2
2389 * @arg @ref LL_TIM_CHANNEL_CH3
2390 * @arg @ref LL_TIM_CHANNEL_CH4
2391 * @arg @ref LL_TIM_CHANNEL_CH5
2392 * @arg @ref LL_TIM_CHANNEL_CH6
2393 * @retval State of bit (1 or 0).
2394 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2395 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2396 {
2397 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2398 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2399 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2400 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2401 }
2402
2403 /**
2404 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2405 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2406 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2407 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2408 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2409 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2410 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2411 * @param TIMx Timer instance
2412 * @param Channel This parameter can be one of the following values:
2413 * @arg @ref LL_TIM_CHANNEL_CH1
2414 * @arg @ref LL_TIM_CHANNEL_CH2
2415 * @arg @ref LL_TIM_CHANNEL_CH3
2416 * @arg @ref LL_TIM_CHANNEL_CH4
2417 * @arg @ref LL_TIM_CHANNEL_CH5
2418 * @arg @ref LL_TIM_CHANNEL_CH6
2419 * @retval None
2420 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2421 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2422 {
2423 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2425 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2426 }
2427
2428 /**
2429 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2430 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2431 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2432 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2433 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2434 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2435 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2436 * @param TIMx Timer instance
2437 * @param Channel This parameter can be one of the following values:
2438 * @arg @ref LL_TIM_CHANNEL_CH1
2439 * @arg @ref LL_TIM_CHANNEL_CH2
2440 * @arg @ref LL_TIM_CHANNEL_CH3
2441 * @arg @ref LL_TIM_CHANNEL_CH4
2442 * @arg @ref LL_TIM_CHANNEL_CH5
2443 * @arg @ref LL_TIM_CHANNEL_CH6
2444 * @retval None
2445 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2446 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2447 {
2448 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2449 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2450 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2451 }
2452
2453 /**
2454 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2455 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2456 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2457 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2458 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2459 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2460 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2461 * @param TIMx Timer instance
2462 * @param Channel This parameter can be one of the following values:
2463 * @arg @ref LL_TIM_CHANNEL_CH1
2464 * @arg @ref LL_TIM_CHANNEL_CH2
2465 * @arg @ref LL_TIM_CHANNEL_CH3
2466 * @arg @ref LL_TIM_CHANNEL_CH4
2467 * @arg @ref LL_TIM_CHANNEL_CH5
2468 * @arg @ref LL_TIM_CHANNEL_CH6
2469 * @retval State of bit (1 or 0).
2470 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2471 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2472 {
2473 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2474 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2475 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2476 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2477 }
2478
2479 /**
2480 * @brief Enable clearing the output channel on an external event.
2481 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2482 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2483 * or not a timer instance can clear the OCxREF signal on an external event.
2484 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2485 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2486 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2487 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2488 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2489 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2490 * @param TIMx Timer instance
2491 * @param Channel This parameter can be one of the following values:
2492 * @arg @ref LL_TIM_CHANNEL_CH1
2493 * @arg @ref LL_TIM_CHANNEL_CH2
2494 * @arg @ref LL_TIM_CHANNEL_CH3
2495 * @arg @ref LL_TIM_CHANNEL_CH4
2496 * @arg @ref LL_TIM_CHANNEL_CH5
2497 * @arg @ref LL_TIM_CHANNEL_CH6
2498 * @retval None
2499 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2500 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2501 {
2502 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2503 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2504 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2505 }
2506
2507 /**
2508 * @brief Disable clearing the output channel on an external event.
2509 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2510 * or not a timer instance can clear the OCxREF signal on an external event.
2511 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2512 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2513 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2514 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2515 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2516 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2517 * @param TIMx Timer instance
2518 * @param Channel This parameter can be one of the following values:
2519 * @arg @ref LL_TIM_CHANNEL_CH1
2520 * @arg @ref LL_TIM_CHANNEL_CH2
2521 * @arg @ref LL_TIM_CHANNEL_CH3
2522 * @arg @ref LL_TIM_CHANNEL_CH4
2523 * @arg @ref LL_TIM_CHANNEL_CH5
2524 * @arg @ref LL_TIM_CHANNEL_CH6
2525 * @retval None
2526 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2527 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2528 {
2529 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2530 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2531 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2532 }
2533
2534 /**
2535 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2536 * @note This function enables clearing the output channel on an external event.
2537 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2538 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2539 * or not a timer instance can clear the OCxREF signal on an external event.
2540 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2541 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2542 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2543 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2544 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2545 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2546 * @param TIMx Timer instance
2547 * @param Channel This parameter can be one of the following values:
2548 * @arg @ref LL_TIM_CHANNEL_CH1
2549 * @arg @ref LL_TIM_CHANNEL_CH2
2550 * @arg @ref LL_TIM_CHANNEL_CH3
2551 * @arg @ref LL_TIM_CHANNEL_CH4
2552 * @arg @ref LL_TIM_CHANNEL_CH5
2553 * @arg @ref LL_TIM_CHANNEL_CH6
2554 * @retval State of bit (1 or 0).
2555 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2556 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2557 {
2558 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2559 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2560 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2561 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2562 }
2563
2564 /**
2565 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2566 * the Ocx and OCxN signals).
2567 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2568 * dead-time insertion feature is supported by a timer instance.
2569 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2570 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2571 * @param TIMx Timer instance
2572 * @param DeadTime between Min_Data=0 and Max_Data=255
2573 * @retval None
2574 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2575 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2576 {
2577 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2578 }
2579
2580 /**
2581 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2582 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2583 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2584 * whether or not a timer instance supports a 32 bits counter.
2585 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2586 * output channel 1 is supported by a timer instance.
2587 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2588 * @param TIMx Timer instance
2589 * @param CompareValue between Min_Data=0 and Max_Data=65535
2590 * @retval None
2591 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2592 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2593 {
2594 WRITE_REG(TIMx->CCR1, CompareValue);
2595 }
2596
2597 /**
2598 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2599 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2600 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2601 * whether or not a timer instance supports a 32 bits counter.
2602 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2603 * output channel 2 is supported by a timer instance.
2604 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2605 * @param TIMx Timer instance
2606 * @param CompareValue between Min_Data=0 and Max_Data=65535
2607 * @retval None
2608 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2609 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2610 {
2611 WRITE_REG(TIMx->CCR2, CompareValue);
2612 }
2613
2614 /**
2615 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2616 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2617 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2618 * whether or not a timer instance supports a 32 bits counter.
2619 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2620 * output channel is supported by a timer instance.
2621 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2622 * @param TIMx Timer instance
2623 * @param CompareValue between Min_Data=0 and Max_Data=65535
2624 * @retval None
2625 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2626 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2627 {
2628 WRITE_REG(TIMx->CCR3, CompareValue);
2629 }
2630
2631 /**
2632 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2633 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2634 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2635 * whether or not a timer instance supports a 32 bits counter.
2636 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2637 * output channel 4 is supported by a timer instance.
2638 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2639 * @param TIMx Timer instance
2640 * @param CompareValue between Min_Data=0 and Max_Data=65535
2641 * @retval None
2642 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2643 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2644 {
2645 WRITE_REG(TIMx->CCR4, CompareValue);
2646 }
2647
2648 /**
2649 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2650 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2651 * output channel 5 is supported by a timer instance.
2652 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2653 * @param TIMx Timer instance
2654 * @param CompareValue between Min_Data=0 and Max_Data=65535
2655 * @retval None
2656 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2657 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2658 {
2659 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2660 }
2661
2662 /**
2663 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2664 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2665 * output channel 6 is supported by a timer instance.
2666 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2667 * @param TIMx Timer instance
2668 * @param CompareValue between Min_Data=0 and Max_Data=65535
2669 * @retval None
2670 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2671 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2672 {
2673 WRITE_REG(TIMx->CCR6, CompareValue);
2674 }
2675
2676 /**
2677 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2678 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2679 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2680 * whether or not a timer instance supports a 32 bits counter.
2681 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2682 * output channel 1 is supported by a timer instance.
2683 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2684 * @param TIMx Timer instance
2685 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2686 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2687 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2688 {
2689 return (uint32_t)(READ_REG(TIMx->CCR1));
2690 }
2691
2692 /**
2693 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2694 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2695 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2696 * whether or not a timer instance supports a 32 bits counter.
2697 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2698 * output channel 2 is supported by a timer instance.
2699 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2700 * @param TIMx Timer instance
2701 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2702 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2703 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2704 {
2705 return (uint32_t)(READ_REG(TIMx->CCR2));
2706 }
2707
2708 /**
2709 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2710 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2711 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2712 * whether or not a timer instance supports a 32 bits counter.
2713 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2714 * output channel 3 is supported by a timer instance.
2715 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2716 * @param TIMx Timer instance
2717 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2718 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2719 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2720 {
2721 return (uint32_t)(READ_REG(TIMx->CCR3));
2722 }
2723
2724 /**
2725 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2726 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2727 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2728 * whether or not a timer instance supports a 32 bits counter.
2729 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2730 * output channel 4 is supported by a timer instance.
2731 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2732 * @param TIMx Timer instance
2733 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2734 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2735 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2736 {
2737 return (uint32_t)(READ_REG(TIMx->CCR4));
2738 }
2739
2740 /**
2741 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2742 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2743 * output channel 5 is supported by a timer instance.
2744 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2745 * @param TIMx Timer instance
2746 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2747 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2748 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2749 {
2750 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2751 }
2752
2753 /**
2754 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2755 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2756 * output channel 6 is supported by a timer instance.
2757 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2758 * @param TIMx Timer instance
2759 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2760 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2761 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2762 {
2763 return (uint32_t)(READ_REG(TIMx->CCR6));
2764 }
2765
2766 /**
2767 * @brief Select on which reference signal the OC5REF is combined to.
2768 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2769 * whether or not a timer instance supports the combined 3-phase PWM mode.
2770 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2771 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2772 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2773 * @param TIMx Timer instance
2774 * @param GroupCH5 This parameter can be a combination of the following values:
2775 * @arg @ref LL_TIM_GROUPCH5_NONE
2776 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2777 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2778 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2779 * @retval None
2780 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2781 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2782 {
2783 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2784 }
2785
2786 /**
2787 * @}
2788 */
2789
2790 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2791 * @{
2792 */
2793 /**
2794 * @brief Configure input channel.
2795 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2796 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2797 * CCMR1 IC1F LL_TIM_IC_Config\n
2798 * CCMR1 CC2S LL_TIM_IC_Config\n
2799 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2800 * CCMR1 IC2F LL_TIM_IC_Config\n
2801 * CCMR2 CC3S LL_TIM_IC_Config\n
2802 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2803 * CCMR2 IC3F LL_TIM_IC_Config\n
2804 * CCMR2 CC4S LL_TIM_IC_Config\n
2805 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2806 * CCMR2 IC4F LL_TIM_IC_Config\n
2807 * CCER CC1P LL_TIM_IC_Config\n
2808 * CCER CC1NP LL_TIM_IC_Config\n
2809 * CCER CC2P LL_TIM_IC_Config\n
2810 * CCER CC2NP LL_TIM_IC_Config\n
2811 * CCER CC3P LL_TIM_IC_Config\n
2812 * CCER CC3NP LL_TIM_IC_Config\n
2813 * CCER CC4P LL_TIM_IC_Config\n
2814 * CCER CC4NP LL_TIM_IC_Config
2815 * @param TIMx Timer instance
2816 * @param Channel This parameter can be one of the following values:
2817 * @arg @ref LL_TIM_CHANNEL_CH1
2818 * @arg @ref LL_TIM_CHANNEL_CH2
2819 * @arg @ref LL_TIM_CHANNEL_CH3
2820 * @arg @ref LL_TIM_CHANNEL_CH4
2821 * @param Configuration This parameter must be a combination of all the following values:
2822 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2823 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2824 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2825 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2826 * @retval None
2827 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2828 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2829 {
2830 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2831 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2832 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2833 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2834 << SHIFT_TAB_ICxx[iChannel]);
2835 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2836 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2837 }
2838
2839 /**
2840 * @brief Set the active input.
2841 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2842 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2843 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2844 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2845 * @param TIMx Timer instance
2846 * @param Channel This parameter can be one of the following values:
2847 * @arg @ref LL_TIM_CHANNEL_CH1
2848 * @arg @ref LL_TIM_CHANNEL_CH2
2849 * @arg @ref LL_TIM_CHANNEL_CH3
2850 * @arg @ref LL_TIM_CHANNEL_CH4
2851 * @param ICActiveInput This parameter can be one of the following values:
2852 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2853 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2854 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2855 * @retval None
2856 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2857 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2858 {
2859 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2860 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2861 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2862 }
2863
2864 /**
2865 * @brief Get the current active input.
2866 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2867 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2868 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2869 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2870 * @param TIMx Timer instance
2871 * @param Channel This parameter can be one of the following values:
2872 * @arg @ref LL_TIM_CHANNEL_CH1
2873 * @arg @ref LL_TIM_CHANNEL_CH2
2874 * @arg @ref LL_TIM_CHANNEL_CH3
2875 * @arg @ref LL_TIM_CHANNEL_CH4
2876 * @retval Returned value can be one of the following values:
2877 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2878 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2879 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2880 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2881 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2882 {
2883 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2884 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2885 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2886 }
2887
2888 /**
2889 * @brief Set the prescaler of input channel.
2890 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2891 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2892 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2893 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2894 * @param TIMx Timer instance
2895 * @param Channel This parameter can be one of the following values:
2896 * @arg @ref LL_TIM_CHANNEL_CH1
2897 * @arg @ref LL_TIM_CHANNEL_CH2
2898 * @arg @ref LL_TIM_CHANNEL_CH3
2899 * @arg @ref LL_TIM_CHANNEL_CH4
2900 * @param ICPrescaler This parameter can be one of the following values:
2901 * @arg @ref LL_TIM_ICPSC_DIV1
2902 * @arg @ref LL_TIM_ICPSC_DIV2
2903 * @arg @ref LL_TIM_ICPSC_DIV4
2904 * @arg @ref LL_TIM_ICPSC_DIV8
2905 * @retval None
2906 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2907 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2908 {
2909 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2910 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2911 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2912 }
2913
2914 /**
2915 * @brief Get the current prescaler value acting on an input channel.
2916 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2917 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2918 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2919 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2920 * @param TIMx Timer instance
2921 * @param Channel This parameter can be one of the following values:
2922 * @arg @ref LL_TIM_CHANNEL_CH1
2923 * @arg @ref LL_TIM_CHANNEL_CH2
2924 * @arg @ref LL_TIM_CHANNEL_CH3
2925 * @arg @ref LL_TIM_CHANNEL_CH4
2926 * @retval Returned value can be one of the following values:
2927 * @arg @ref LL_TIM_ICPSC_DIV1
2928 * @arg @ref LL_TIM_ICPSC_DIV2
2929 * @arg @ref LL_TIM_ICPSC_DIV4
2930 * @arg @ref LL_TIM_ICPSC_DIV8
2931 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2932 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2933 {
2934 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2935 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2936 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2937 }
2938
2939 /**
2940 * @brief Set the input filter duration.
2941 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2942 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2943 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2944 * CCMR2 IC4F LL_TIM_IC_SetFilter
2945 * @param TIMx Timer instance
2946 * @param Channel This parameter can be one of the following values:
2947 * @arg @ref LL_TIM_CHANNEL_CH1
2948 * @arg @ref LL_TIM_CHANNEL_CH2
2949 * @arg @ref LL_TIM_CHANNEL_CH3
2950 * @arg @ref LL_TIM_CHANNEL_CH4
2951 * @param ICFilter This parameter can be one of the following values:
2952 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2953 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2954 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2955 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2956 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2957 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2958 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2959 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2960 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2961 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2962 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2963 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2964 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2965 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2966 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2967 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2968 * @retval None
2969 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2970 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2971 {
2972 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2973 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2974 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2975 }
2976
2977 /**
2978 * @brief Get the input filter duration.
2979 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2980 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2981 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2982 * CCMR2 IC4F LL_TIM_IC_GetFilter
2983 * @param TIMx Timer instance
2984 * @param Channel This parameter can be one of the following values:
2985 * @arg @ref LL_TIM_CHANNEL_CH1
2986 * @arg @ref LL_TIM_CHANNEL_CH2
2987 * @arg @ref LL_TIM_CHANNEL_CH3
2988 * @arg @ref LL_TIM_CHANNEL_CH4
2989 * @retval Returned value can be one of the following values:
2990 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2991 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2992 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2993 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2994 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2995 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2996 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2997 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2998 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2999 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3000 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3001 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3002 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3003 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3004 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3005 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3006 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3007 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3008 {
3009 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3010 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3011 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3012 }
3013
3014 /**
3015 * @brief Set the input channel polarity.
3016 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3017 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3018 * CCER CC2P LL_TIM_IC_SetPolarity\n
3019 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3020 * CCER CC3P LL_TIM_IC_SetPolarity\n
3021 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3022 * CCER CC4P LL_TIM_IC_SetPolarity\n
3023 * CCER CC4NP LL_TIM_IC_SetPolarity
3024 * @param TIMx Timer instance
3025 * @param Channel This parameter can be one of the following values:
3026 * @arg @ref LL_TIM_CHANNEL_CH1
3027 * @arg @ref LL_TIM_CHANNEL_CH2
3028 * @arg @ref LL_TIM_CHANNEL_CH3
3029 * @arg @ref LL_TIM_CHANNEL_CH4
3030 * @param ICPolarity This parameter can be one of the following values:
3031 * @arg @ref LL_TIM_IC_POLARITY_RISING
3032 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3033 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3034 * @retval None
3035 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3036 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3037 {
3038 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3039 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3040 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3041 }
3042
3043 /**
3044 * @brief Get the current input channel polarity.
3045 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3046 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3047 * CCER CC2P LL_TIM_IC_GetPolarity\n
3048 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3049 * CCER CC3P LL_TIM_IC_GetPolarity\n
3050 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3051 * CCER CC4P LL_TIM_IC_GetPolarity\n
3052 * CCER CC4NP LL_TIM_IC_GetPolarity
3053 * @param TIMx Timer instance
3054 * @param Channel This parameter can be one of the following values:
3055 * @arg @ref LL_TIM_CHANNEL_CH1
3056 * @arg @ref LL_TIM_CHANNEL_CH2
3057 * @arg @ref LL_TIM_CHANNEL_CH3
3058 * @arg @ref LL_TIM_CHANNEL_CH4
3059 * @retval Returned value can be one of the following values:
3060 * @arg @ref LL_TIM_IC_POLARITY_RISING
3061 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3062 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3063 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3064 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3065 {
3066 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3067 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3068 SHIFT_TAB_CCxP[iChannel]);
3069 }
3070
3071 /**
3072 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3073 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3074 * a timer instance provides an XOR input.
3075 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3076 * @param TIMx Timer instance
3077 * @retval None
3078 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3079 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3080 {
3081 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3082 }
3083
3084 /**
3085 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3086 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3087 * a timer instance provides an XOR input.
3088 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3089 * @param TIMx Timer instance
3090 * @retval None
3091 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3092 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3093 {
3094 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3095 }
3096
3097 /**
3098 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3099 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3100 * a timer instance provides an XOR input.
3101 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3102 * @param TIMx Timer instance
3103 * @retval State of bit (1 or 0).
3104 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3105 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3106 {
3107 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3108 }
3109
3110 /**
3111 * @brief Get captured value for input channel 1.
3112 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3113 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3114 * whether or not a timer instance supports a 32 bits counter.
3115 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3116 * input channel 1 is supported by a timer instance.
3117 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3118 * @param TIMx Timer instance
3119 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3120 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3121 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3122 {
3123 return (uint32_t)(READ_REG(TIMx->CCR1));
3124 }
3125
3126 /**
3127 * @brief Get captured value for input channel 2.
3128 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3129 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3130 * whether or not a timer instance supports a 32 bits counter.
3131 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3132 * input channel 2 is supported by a timer instance.
3133 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3134 * @param TIMx Timer instance
3135 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3136 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3137 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3138 {
3139 return (uint32_t)(READ_REG(TIMx->CCR2));
3140 }
3141
3142 /**
3143 * @brief Get captured value for input channel 3.
3144 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3145 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3146 * whether or not a timer instance supports a 32 bits counter.
3147 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3148 * input channel 3 is supported by a timer instance.
3149 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3150 * @param TIMx Timer instance
3151 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3152 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3153 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3154 {
3155 return (uint32_t)(READ_REG(TIMx->CCR3));
3156 }
3157
3158 /**
3159 * @brief Get captured value for input channel 4.
3160 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3161 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3162 * whether or not a timer instance supports a 32 bits counter.
3163 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3164 * input channel 4 is supported by a timer instance.
3165 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3166 * @param TIMx Timer instance
3167 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3168 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3169 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3170 {
3171 return (uint32_t)(READ_REG(TIMx->CCR4));
3172 }
3173
3174 /**
3175 * @}
3176 */
3177
3178 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3179 * @{
3180 */
3181 /**
3182 * @brief Enable external clock mode 2.
3183 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3184 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3185 * whether or not a timer instance supports external clock mode2.
3186 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3187 * @param TIMx Timer instance
3188 * @retval None
3189 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3190 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3191 {
3192 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3193 }
3194
3195 /**
3196 * @brief Disable external clock mode 2.
3197 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3198 * whether or not a timer instance supports external clock mode2.
3199 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3200 * @param TIMx Timer instance
3201 * @retval None
3202 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3203 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3204 {
3205 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3206 }
3207
3208 /**
3209 * @brief Indicate whether external clock mode 2 is enabled.
3210 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3211 * whether or not a timer instance supports external clock mode2.
3212 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3213 * @param TIMx Timer instance
3214 * @retval State of bit (1 or 0).
3215 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3216 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3217 {
3218 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3219 }
3220
3221 /**
3222 * @brief Set the clock source of the counter clock.
3223 * @note when selected clock source is external clock mode 1, the timer input
3224 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3225 * function. This timer input must be configured by calling
3226 * the @ref LL_TIM_IC_Config() function.
3227 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3228 * whether or not a timer instance supports external clock mode1.
3229 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3230 * whether or not a timer instance supports external clock mode2.
3231 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3232 * SMCR ECE LL_TIM_SetClockSource
3233 * @param TIMx Timer instance
3234 * @param ClockSource This parameter can be one of the following values:
3235 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3236 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3237 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3238 * @retval None
3239 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3240 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3241 {
3242 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3243 }
3244
3245 /**
3246 * @brief Set the encoder interface mode.
3247 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3248 * whether or not a timer instance supports the encoder mode.
3249 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3250 * @param TIMx Timer instance
3251 * @param EncoderMode This parameter can be one of the following values:
3252 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3253 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3254 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3255 * @retval None
3256 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3257 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3258 {
3259 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3260 }
3261
3262 /**
3263 * @}
3264 */
3265
3266 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3267 * @{
3268 */
3269 /**
3270 * @brief Set the trigger output (TRGO) used for timer synchronization .
3271 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3272 * whether or not a timer instance can operate as a master timer.
3273 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3274 * @param TIMx Timer instance
3275 * @param TimerSynchronization This parameter can be one of the following values:
3276 * @arg @ref LL_TIM_TRGO_RESET
3277 * @arg @ref LL_TIM_TRGO_ENABLE
3278 * @arg @ref LL_TIM_TRGO_UPDATE
3279 * @arg @ref LL_TIM_TRGO_CC1IF
3280 * @arg @ref LL_TIM_TRGO_OC1REF
3281 * @arg @ref LL_TIM_TRGO_OC2REF
3282 * @arg @ref LL_TIM_TRGO_OC3REF
3283 * @arg @ref LL_TIM_TRGO_OC4REF
3284 * @retval None
3285 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3286 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3287 {
3288 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3289 }
3290
3291 /**
3292 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3293 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3294 * whether or not a timer instance can be used for ADC synchronization.
3295 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3296 * @param TIMx Timer Instance
3297 * @param ADCSynchronization This parameter can be one of the following values:
3298 * @arg @ref LL_TIM_TRGO2_RESET
3299 * @arg @ref LL_TIM_TRGO2_ENABLE
3300 * @arg @ref LL_TIM_TRGO2_UPDATE
3301 * @arg @ref LL_TIM_TRGO2_CC1F
3302 * @arg @ref LL_TIM_TRGO2_OC1
3303 * @arg @ref LL_TIM_TRGO2_OC2
3304 * @arg @ref LL_TIM_TRGO2_OC3
3305 * @arg @ref LL_TIM_TRGO2_OC4
3306 * @arg @ref LL_TIM_TRGO2_OC5
3307 * @arg @ref LL_TIM_TRGO2_OC6
3308 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3309 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3310 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3311 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3312 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3313 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3314 * @retval None
3315 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3316 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3317 {
3318 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3319 }
3320
3321 /**
3322 * @brief Set the synchronization mode of a slave timer.
3323 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3324 * a timer instance can operate as a slave timer.
3325 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3326 * @param TIMx Timer instance
3327 * @param SlaveMode This parameter can be one of the following values:
3328 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3329 * @arg @ref LL_TIM_SLAVEMODE_RESET
3330 * @arg @ref LL_TIM_SLAVEMODE_GATED
3331 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3332 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3333 * @retval None
3334 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3335 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3336 {
3337 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3338 }
3339
3340 /**
3341 * @brief Set the selects the trigger input to be used to synchronize the counter.
3342 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3343 * a timer instance can operate as a slave timer.
3344 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3345 * @param TIMx Timer instance
3346 * @param TriggerInput This parameter can be one of the following values:
3347 * @arg @ref LL_TIM_TS_ITR0
3348 * @arg @ref LL_TIM_TS_ITR1
3349 * @arg @ref LL_TIM_TS_ITR2
3350 * @arg @ref LL_TIM_TS_ITR3
3351 * @arg @ref LL_TIM_TS_TI1F_ED
3352 * @arg @ref LL_TIM_TS_TI1FP1
3353 * @arg @ref LL_TIM_TS_TI2FP2
3354 * @arg @ref LL_TIM_TS_ETRF
3355 * @retval None
3356 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3357 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3358 {
3359 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3360 }
3361
3362 /**
3363 * @brief Enable the Master/Slave mode.
3364 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3365 * a timer instance can operate as a slave timer.
3366 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3367 * @param TIMx Timer instance
3368 * @retval None
3369 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3370 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3371 {
3372 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3373 }
3374
3375 /**
3376 * @brief Disable the Master/Slave mode.
3377 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3378 * a timer instance can operate as a slave timer.
3379 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3380 * @param TIMx Timer instance
3381 * @retval None
3382 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3383 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3384 {
3385 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3386 }
3387
3388 /**
3389 * @brief Indicates whether the Master/Slave mode is enabled.
3390 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3391 * a timer instance can operate as a slave timer.
3392 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3393 * @param TIMx Timer instance
3394 * @retval State of bit (1 or 0).
3395 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3396 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3397 {
3398 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3399 }
3400
3401 /**
3402 * @brief Configure the external trigger (ETR) input.
3403 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3404 * a timer instance provides an external trigger input.
3405 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3406 * SMCR ETPS LL_TIM_ConfigETR\n
3407 * SMCR ETF LL_TIM_ConfigETR
3408 * @param TIMx Timer instance
3409 * @param ETRPolarity This parameter can be one of the following values:
3410 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3411 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3412 * @param ETRPrescaler This parameter can be one of the following values:
3413 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3414 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3415 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3416 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3417 * @param ETRFilter This parameter can be one of the following values:
3418 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3419 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3420 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3421 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3422 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3423 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3424 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3425 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3426 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3427 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3428 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3429 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3430 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3431 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3432 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3433 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3434 * @retval None
3435 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3436 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3437 uint32_t ETRFilter)
3438 {
3439 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3440 }
3441
3442 /**
3443 * @brief Select the external trigger (ETR) input source.
3444 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3445 * not a timer instance supports ETR source selection.
3446 * @note When this function is called with LL_TIM_ETRSOURCE_GPIO,
3447 * LL_TIM_ETRSOURCE_ADC1_AWD1, LL_TIM_ETRSOURCE_ADC1_AWD2 or
3448 * LL_TIM_ETRSOURCE_ADC1_AWD3, ETR source relies on TIMx ETR remapping
3449 * capability configured through the function @ref LL_TIM_SetRemap().
3450 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3451 * @param TIMx Timer instance
3452 * @param ETRSource This parameter can be one of the following values:
3453 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3454 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3455 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2 (*)
3456 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3 (*)
3457 * @arg @ref LL_TIM_ETRSOURCE_COMP1 (*)
3458 * @arg @ref LL_TIM_ETRSOURCE_COMP2 (*)
3459 *
3460 * (*) Value not defined in all devices. \n
3461 * @retval None
3462 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3463 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3464 {
3465 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3466 }
3467
3468 /**
3469 * @}
3470 */
3471
3472 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3473 * @{
3474 */
3475 /**
3476 * @brief Enable the break function.
3477 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3478 * a timer instance provides a break input.
3479 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3480 * @param TIMx Timer instance
3481 * @retval None
3482 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3483 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3484 {
3485 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3486 }
3487
3488 /**
3489 * @brief Disable the break function.
3490 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3491 * @param TIMx Timer instance
3492 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3493 * a timer instance provides a break input.
3494 * @retval None
3495 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3496 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3497 {
3498 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3499 }
3500
3501 /**
3502 * @brief Configure the break input.
3503 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3504 * a timer instance provides a break input.
3505 * @note Bidirectional mode is only supported by advanced timer instances.
3506 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3507 * a timer instance is an advanced-control timer.
3508 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3509 * in input mode and in open drain output mode. Any active Break event will
3510 * assert a low logic level on the Break input to indicate an internal break
3511 * event to external devices.
3512 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3513 * LL_TIM_BREAK_AFMODE_INPUT.
3514 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3515 * BDTR BKF LL_TIM_ConfigBRK\n
3516 * BDTR BKBID LL_TIM_ConfigBRK
3517 * @param TIMx Timer instance
3518 * @param BreakPolarity This parameter can be one of the following values:
3519 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3520 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3521 * @param BreakFilter This parameter can be one of the following values:
3522 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3523 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3524 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3525 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3526 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3527 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3528 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3529 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3530 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3531 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3532 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3533 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3534 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3535 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3536 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3537 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3538 * @param BreakAFMode This parameter can be one of the following values:
3539 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3540 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3541 * @retval None
3542 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3543 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3544 uint32_t BreakAFMode)
3545 {
3546 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3547 }
3548
3549 /**
3550 * @brief Disarm the break input (when it operates in bidirectional mode).
3551 * @note The break input can be disarmed only when it is configured in
3552 * bidirectional mode and when when MOE is reset.
3553 * @note Purpose is to be able to have the input voltage back to high-state,
3554 * whatever the time constant on the output .
3555 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3556 * @param TIMx Timer instance
3557 * @retval None
3558 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3559 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3560 {
3561 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3562 }
3563
3564 /**
3565 * @brief Enable the break 2 function.
3566 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3567 * a timer instance provides a second break input.
3568 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3569 * @param TIMx Timer instance
3570 * @retval None
3571 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3572 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3573 {
3574 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3575 }
3576
3577 /**
3578 * @brief Disable the break 2 function.
3579 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3580 * a timer instance provides a second break input.
3581 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3582 * @param TIMx Timer instance
3583 * @retval None
3584 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3585 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3586 {
3587 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3588 }
3589
3590 /**
3591 * @brief Configure the break 2 input.
3592 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3593 * a timer instance provides a second break input.
3594 * @note Bidirectional mode is only supported by advanced timer instances.
3595 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3596 * a timer instance is an advanced-control timer.
3597 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3598 * in input mode and in open drain output mode. Any active Break event will
3599 * assert a low logic level on the Break 2 input to indicate an internal break
3600 * event to external devices.
3601 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3602 * LL_TIM_BREAK2_AFMODE_INPUT.
3603 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3604 * BDTR BK2F LL_TIM_ConfigBRK2\n
3605 * BDTR BK2BID LL_TIM_ConfigBRK2
3606 * @param TIMx Timer instance
3607 * @param Break2Polarity This parameter can be one of the following values:
3608 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3609 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3610 * @param Break2Filter This parameter can be one of the following values:
3611 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3612 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3613 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3614 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3615 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3616 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3617 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3618 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3619 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3620 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3621 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3622 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3623 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3624 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3625 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3626 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3627 * @param Break2AFMode This parameter can be one of the following values:
3628 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3629 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3630 * @retval None
3631 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3632 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3633 uint32_t Break2AFMode)
3634 {
3635 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3636 }
3637
3638 /**
3639 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3640 * @note The break 2 input can be disarmed only when it is configured in
3641 * bidirectional mode and when when MOE is reset.
3642 * @note Purpose is to be able to have the input voltage back to high-state,
3643 * whatever the time constant on the output.
3644 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3645 * @param TIMx Timer instance
3646 * @retval None
3647 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3648 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3649 {
3650 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3651 }
3652
3653 /**
3654 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3655 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3656 * a timer instance provides a break input.
3657 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3658 * BDTR OSSR LL_TIM_SetOffStates
3659 * @param TIMx Timer instance
3660 * @param OffStateIdle This parameter can be one of the following values:
3661 * @arg @ref LL_TIM_OSSI_DISABLE
3662 * @arg @ref LL_TIM_OSSI_ENABLE
3663 * @param OffStateRun This parameter can be one of the following values:
3664 * @arg @ref LL_TIM_OSSR_DISABLE
3665 * @arg @ref LL_TIM_OSSR_ENABLE
3666 * @retval None
3667 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3668 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3669 {
3670 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3671 }
3672
3673 /**
3674 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3675 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3676 * a timer instance provides a break input.
3677 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3678 * @param TIMx Timer instance
3679 * @retval None
3680 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3681 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3682 {
3683 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3684 }
3685
3686 /**
3687 * @brief Disable automatic output (MOE can be set only by software).
3688 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3689 * a timer instance provides a break input.
3690 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3691 * @param TIMx Timer instance
3692 * @retval None
3693 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3694 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3695 {
3696 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3697 }
3698
3699 /**
3700 * @brief Indicate whether automatic output is enabled.
3701 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3702 * a timer instance provides a break input.
3703 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3704 * @param TIMx Timer instance
3705 * @retval State of bit (1 or 0).
3706 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3707 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3708 {
3709 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3710 }
3711
3712 /**
3713 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3714 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3715 * software and is reset in case of break or break2 event
3716 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3717 * a timer instance provides a break input.
3718 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3719 * @param TIMx Timer instance
3720 * @retval None
3721 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3722 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3723 {
3724 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3725 }
3726
3727 /**
3728 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3729 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3730 * software and is reset in case of break or break2 event.
3731 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3732 * a timer instance provides a break input.
3733 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3734 * @param TIMx Timer instance
3735 * @retval None
3736 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3737 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3738 {
3739 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3740 }
3741
3742 /**
3743 * @brief Indicates whether outputs are enabled.
3744 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3745 * a timer instance provides a break input.
3746 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3747 * @param TIMx Timer instance
3748 * @retval State of bit (1 or 0).
3749 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3750 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3751 {
3752 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3753 }
3754
3755 /**
3756 * @brief Enable the signals connected to the designated timer break input.
3757 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3758 * or not a timer instance allows for break input selection.
3759 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3760 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
3761 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
3762 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3763 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3764 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource
3765 * @param TIMx Timer instance
3766 * @param BreakInput This parameter can be one of the following values:
3767 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3768 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3769 * @param Source This parameter can be one of the following values:
3770 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3771 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
3772 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3773 *
3774 * (*) Value not defined in all devices.
3775 * @retval None
3776 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3777 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3778 {
3779 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3780 SET_BIT(*pReg, Source);
3781 }
3782
3783 /**
3784 * @brief Disable the signals connected to the designated timer break input.
3785 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3786 * or not a timer instance allows for break input selection.
3787 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3788 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
3789 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
3790 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3791 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3792 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource
3793 * @param TIMx Timer instance
3794 * @param BreakInput This parameter can be one of the following values:
3795 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3796 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3797 * @param Source This parameter can be one of the following values:
3798 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3799 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
3800 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3801 *
3802 * (*) Value not defined in all devices.
3803 * @retval None
3804 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3805 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3806 {
3807 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3808 CLEAR_BIT(*pReg, Source);
3809 }
3810
3811 /**
3812 * @brief Set the polarity of the break signal for the timer break input.
3813 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3814 * or not a timer instance allows for break input selection.
3815 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3816 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3817 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3818 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3819 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3820 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3821 * @param TIMx Timer instance
3822 * @param BreakInput This parameter can be one of the following values:
3823 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3824 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3825 * @param Source This parameter can be one of the following values:
3826 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3827 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
3828 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
3829 * @param Polarity This parameter can be one of the following values:
3830 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3831 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3832 *
3833 * (*) Value not defined in all devices.
3834 * @retval None
3835 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3836 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3837 uint32_t Polarity)
3838 {
3839 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3840 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3841 }
3842 /**
3843 * @}
3844 */
3845
3846 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3847 * @{
3848 */
3849 /**
3850 * @brief Configures the timer DMA burst feature.
3851 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3852 * not a timer instance supports the DMA burst mode.
3853 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3854 * DCR DBA LL_TIM_ConfigDMABurst
3855 * @param TIMx Timer instance
3856 * @param DMABurstBaseAddress This parameter can be one of the following values:
3857 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3858 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3859 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3860 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3861 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3862 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3863 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3864 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3865 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3866 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3867 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3868 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3869 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3870 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3871 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3872 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3873 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3874 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3875 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3876 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3877 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3878 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3879 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3880 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3881 * @param DMABurstLength This parameter can be one of the following values:
3882 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3883 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3884 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3885 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3886 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3887 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3888 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3889 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3890 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3891 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3892 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3893 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3894 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3895 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3896 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3897 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3898 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3899 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3900 * @retval None
3901 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3902 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3903 {
3904 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3905 }
3906
3907 /**
3908 * @}
3909 */
3910
3911 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3912 * @{
3913 */
3914 /**
3915 * @brief Remap TIM inputs (input channel, internal/external triggers).
3916 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3917 * a some timer inputs can be remapped.
3918 * @rmtoll TIM1_OR ETR_ADC1_RMP LL_TIM_SetRemap\n
3919 * TIM1_OR TI1_RMP LL_TIM_SetRemap\n
3920 * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3921 * TIM2_OR TI4_RMP LL_TIM_SetRemap\n
3922 * TIM2_OR TI1_RMP LL_TIM_SetRemap\n
3923 * TIM16_OR TI1_RMP LL_TIM_SetRemap (***)\n
3924 * TIM17_OR TI1_RMP LL_TIM_SetRemap (***)
3925 * @param TIMx Timer instance
3926 * @param Remap Remap param depends on the TIMx. Description available only
3927 * in CHM version of the User Manual (not in .pdf).
3928 * Otherwise see Reference Manual description of OR registers.
3929 *
3930 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3931 *
3932 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
3933 *
3934 * . . ADC1_RMP can be one of the following values
3935 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3936 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3937 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (**)
3938 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (**)
3939 *
3940 * . . TI1_RMP can be one of the following values
3941 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3942 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 (**)
3943 *
3944 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3945 *
3946 * ITR1_RMP can be one of the following values
3947 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
3948 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF (**)
3949 *
3950 * . . ETR1_RMP can be one of the following values
3951 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3952 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3953 *
3954 * . . TI4_RMP can be one of the following values
3955 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3956 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 (**)
3957 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 (**)
3958 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (**)
3959 *
3960 * TIM16: one of the following values (*)
3961 *
3962 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3963 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3964 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3965 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3966 *
3967 * TIM17: one of the following values (*)
3968 *
3969 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3970 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3971 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3972 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3973 *
3974 * (*) Timer instance not available on all devices \n
3975 * (**) Value not defined in all devices.
3976 * (***) Register not available in all devices.
3977 * @retval None
3978 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3979 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3980 {
3981 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3982 }
3983
3984 /**
3985 * @}
3986 */
3987
3988 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3989 * @{
3990 */
3991 /**
3992 * @brief Set the OCREF clear input source
3993 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3994 * @note This function can only be used in Output compare and PWM modes.
3995 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3996 * @param TIMx Timer instance
3997 * @param OCRefClearInputSource This parameter can be one of the following values:
3998 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3999 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4000 * @retval None
4001 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4002 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4003 {
4004 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4005 }
4006 /**
4007 * @}
4008 */
4009
4010 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4011 * @{
4012 */
4013 /**
4014 * @brief Clear the update interrupt flag (UIF).
4015 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4016 * @param TIMx Timer instance
4017 * @retval None
4018 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4019 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4020 {
4021 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4022 }
4023
4024 /**
4025 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4026 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4027 * @param TIMx Timer instance
4028 * @retval State of bit (1 or 0).
4029 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4030 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4031 {
4032 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4033 }
4034
4035 /**
4036 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4037 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4038 * @param TIMx Timer instance
4039 * @retval None
4040 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4041 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4042 {
4043 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4044 }
4045
4046 /**
4047 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4048 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4049 * @param TIMx Timer instance
4050 * @retval State of bit (1 or 0).
4051 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4052 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4053 {
4054 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4055 }
4056
4057 /**
4058 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4059 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4060 * @param TIMx Timer instance
4061 * @retval None
4062 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4063 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4064 {
4065 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4066 }
4067
4068 /**
4069 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4070 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4071 * @param TIMx Timer instance
4072 * @retval State of bit (1 or 0).
4073 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4074 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4075 {
4076 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4077 }
4078
4079 /**
4080 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4081 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4082 * @param TIMx Timer instance
4083 * @retval None
4084 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4085 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4086 {
4087 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4088 }
4089
4090 /**
4091 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4092 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4093 * @param TIMx Timer instance
4094 * @retval State of bit (1 or 0).
4095 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4096 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4097 {
4098 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4099 }
4100
4101 /**
4102 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4103 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4104 * @param TIMx Timer instance
4105 * @retval None
4106 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4107 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4108 {
4109 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4110 }
4111
4112 /**
4113 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4114 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4115 * @param TIMx Timer instance
4116 * @retval State of bit (1 or 0).
4117 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4118 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4119 {
4120 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4121 }
4122
4123 /**
4124 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4125 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4126 * @param TIMx Timer instance
4127 * @retval None
4128 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4129 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4130 {
4131 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4132 }
4133
4134 /**
4135 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4136 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4137 * @param TIMx Timer instance
4138 * @retval State of bit (1 or 0).
4139 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4140 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4141 {
4142 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4143 }
4144
4145 /**
4146 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4147 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4148 * @param TIMx Timer instance
4149 * @retval None
4150 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4151 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4152 {
4153 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4154 }
4155
4156 /**
4157 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4158 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4159 * @param TIMx Timer instance
4160 * @retval State of bit (1 or 0).
4161 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4162 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4163 {
4164 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4165 }
4166
4167 /**
4168 * @brief Clear the commutation interrupt flag (COMIF).
4169 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4170 * @param TIMx Timer instance
4171 * @retval None
4172 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4173 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4174 {
4175 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4176 }
4177
4178 /**
4179 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4180 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4181 * @param TIMx Timer instance
4182 * @retval State of bit (1 or 0).
4183 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4184 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4185 {
4186 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4187 }
4188
4189 /**
4190 * @brief Clear the trigger interrupt flag (TIF).
4191 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4192 * @param TIMx Timer instance
4193 * @retval None
4194 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4195 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4196 {
4197 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4198 }
4199
4200 /**
4201 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4202 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4203 * @param TIMx Timer instance
4204 * @retval State of bit (1 or 0).
4205 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4206 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4207 {
4208 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4209 }
4210
4211 /**
4212 * @brief Clear the break interrupt flag (BIF).
4213 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4214 * @param TIMx Timer instance
4215 * @retval None
4216 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4217 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4218 {
4219 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4220 }
4221
4222 /**
4223 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4224 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4225 * @param TIMx Timer instance
4226 * @retval State of bit (1 or 0).
4227 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4228 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4229 {
4230 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4231 }
4232
4233 /**
4234 * @brief Clear the break 2 interrupt flag (B2IF).
4235 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4236 * @param TIMx Timer instance
4237 * @retval None
4238 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4239 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4240 {
4241 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4242 }
4243
4244 /**
4245 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4246 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4247 * @param TIMx Timer instance
4248 * @retval State of bit (1 or 0).
4249 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4250 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4251 {
4252 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4253 }
4254
4255 /**
4256 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4257 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4258 * @param TIMx Timer instance
4259 * @retval None
4260 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4261 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4262 {
4263 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4264 }
4265
4266 /**
4267 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4268 * (Capture/Compare 1 interrupt is pending).
4269 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4270 * @param TIMx Timer instance
4271 * @retval State of bit (1 or 0).
4272 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4273 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4274 {
4275 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4276 }
4277
4278 /**
4279 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4280 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4281 * @param TIMx Timer instance
4282 * @retval None
4283 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4284 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4285 {
4286 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4287 }
4288
4289 /**
4290 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4291 * (Capture/Compare 2 over-capture interrupt is pending).
4292 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4293 * @param TIMx Timer instance
4294 * @retval State of bit (1 or 0).
4295 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4296 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4297 {
4298 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4299 }
4300
4301 /**
4302 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4303 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4304 * @param TIMx Timer instance
4305 * @retval None
4306 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4307 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4308 {
4309 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4310 }
4311
4312 /**
4313 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4314 * (Capture/Compare 3 over-capture interrupt is pending).
4315 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4316 * @param TIMx Timer instance
4317 * @retval State of bit (1 or 0).
4318 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4319 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4320 {
4321 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4322 }
4323
4324 /**
4325 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4326 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4327 * @param TIMx Timer instance
4328 * @retval None
4329 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4330 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4331 {
4332 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4333 }
4334
4335 /**
4336 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4337 * (Capture/Compare 4 over-capture interrupt is pending).
4338 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4339 * @param TIMx Timer instance
4340 * @retval State of bit (1 or 0).
4341 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4342 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4343 {
4344 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4345 }
4346
4347 /**
4348 * @brief Clear the system break interrupt flag (SBIF).
4349 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4350 * @param TIMx Timer instance
4351 * @retval None
4352 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4353 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4354 {
4355 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4356 }
4357
4358 /**
4359 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4360 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4361 * @param TIMx Timer instance
4362 * @retval State of bit (1 or 0).
4363 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4364 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4365 {
4366 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4367 }
4368
4369 /**
4370 * @}
4371 */
4372
4373 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4374 * @{
4375 */
4376 /**
4377 * @brief Enable update interrupt (UIE).
4378 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4379 * @param TIMx Timer instance
4380 * @retval None
4381 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4382 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4383 {
4384 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4385 }
4386
4387 /**
4388 * @brief Disable update interrupt (UIE).
4389 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4390 * @param TIMx Timer instance
4391 * @retval None
4392 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4393 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4394 {
4395 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4396 }
4397
4398 /**
4399 * @brief Indicates whether the update interrupt (UIE) is enabled.
4400 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4401 * @param TIMx Timer instance
4402 * @retval State of bit (1 or 0).
4403 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4404 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4405 {
4406 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4407 }
4408
4409 /**
4410 * @brief Enable capture/compare 1 interrupt (CC1IE).
4411 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4412 * @param TIMx Timer instance
4413 * @retval None
4414 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4415 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4416 {
4417 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4418 }
4419
4420 /**
4421 * @brief Disable capture/compare 1 interrupt (CC1IE).
4422 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4423 * @param TIMx Timer instance
4424 * @retval None
4425 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4426 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4427 {
4428 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4429 }
4430
4431 /**
4432 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4433 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4434 * @param TIMx Timer instance
4435 * @retval State of bit (1 or 0).
4436 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4437 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4438 {
4439 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4440 }
4441
4442 /**
4443 * @brief Enable capture/compare 2 interrupt (CC2IE).
4444 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4445 * @param TIMx Timer instance
4446 * @retval None
4447 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4448 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4449 {
4450 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4451 }
4452
4453 /**
4454 * @brief Disable capture/compare 2 interrupt (CC2IE).
4455 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4456 * @param TIMx Timer instance
4457 * @retval None
4458 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4459 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4460 {
4461 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4462 }
4463
4464 /**
4465 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4466 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4467 * @param TIMx Timer instance
4468 * @retval State of bit (1 or 0).
4469 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4470 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4471 {
4472 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4473 }
4474
4475 /**
4476 * @brief Enable capture/compare 3 interrupt (CC3IE).
4477 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4478 * @param TIMx Timer instance
4479 * @retval None
4480 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4481 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4482 {
4483 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4484 }
4485
4486 /**
4487 * @brief Disable capture/compare 3 interrupt (CC3IE).
4488 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4489 * @param TIMx Timer instance
4490 * @retval None
4491 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4492 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4493 {
4494 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4495 }
4496
4497 /**
4498 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4499 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4500 * @param TIMx Timer instance
4501 * @retval State of bit (1 or 0).
4502 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4503 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4504 {
4505 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4506 }
4507
4508 /**
4509 * @brief Enable capture/compare 4 interrupt (CC4IE).
4510 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4511 * @param TIMx Timer instance
4512 * @retval None
4513 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4514 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4515 {
4516 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4517 }
4518
4519 /**
4520 * @brief Disable capture/compare 4 interrupt (CC4IE).
4521 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4522 * @param TIMx Timer instance
4523 * @retval None
4524 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4525 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4526 {
4527 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4528 }
4529
4530 /**
4531 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4532 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4533 * @param TIMx Timer instance
4534 * @retval State of bit (1 or 0).
4535 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4536 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4537 {
4538 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4539 }
4540
4541 /**
4542 * @brief Enable commutation interrupt (COMIE).
4543 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4544 * @param TIMx Timer instance
4545 * @retval None
4546 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4547 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4548 {
4549 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4550 }
4551
4552 /**
4553 * @brief Disable commutation interrupt (COMIE).
4554 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4555 * @param TIMx Timer instance
4556 * @retval None
4557 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4558 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4559 {
4560 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4561 }
4562
4563 /**
4564 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4565 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4566 * @param TIMx Timer instance
4567 * @retval State of bit (1 or 0).
4568 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4569 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4570 {
4571 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4572 }
4573
4574 /**
4575 * @brief Enable trigger interrupt (TIE).
4576 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4577 * @param TIMx Timer instance
4578 * @retval None
4579 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4580 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4581 {
4582 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4583 }
4584
4585 /**
4586 * @brief Disable trigger interrupt (TIE).
4587 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4588 * @param TIMx Timer instance
4589 * @retval None
4590 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4591 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4592 {
4593 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4594 }
4595
4596 /**
4597 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4598 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4599 * @param TIMx Timer instance
4600 * @retval State of bit (1 or 0).
4601 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4602 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4603 {
4604 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4605 }
4606
4607 /**
4608 * @brief Enable break interrupt (BIE).
4609 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4610 * @param TIMx Timer instance
4611 * @retval None
4612 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4613 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4614 {
4615 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4616 }
4617
4618 /**
4619 * @brief Disable break interrupt (BIE).
4620 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4621 * @param TIMx Timer instance
4622 * @retval None
4623 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4624 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4625 {
4626 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4627 }
4628
4629 /**
4630 * @brief Indicates whether the break interrupt (BIE) is enabled.
4631 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4632 * @param TIMx Timer instance
4633 * @retval State of bit (1 or 0).
4634 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4635 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4636 {
4637 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4638 }
4639
4640 /**
4641 * @}
4642 */
4643
4644 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4645 * @{
4646 */
4647 /**
4648 * @brief Enable update DMA request (UDE).
4649 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4650 * @param TIMx Timer instance
4651 * @retval None
4652 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4653 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4654 {
4655 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4656 }
4657
4658 /**
4659 * @brief Disable update DMA request (UDE).
4660 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4661 * @param TIMx Timer instance
4662 * @retval None
4663 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4664 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4665 {
4666 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4667 }
4668
4669 /**
4670 * @brief Indicates whether the update DMA request (UDE) is enabled.
4671 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4672 * @param TIMx Timer instance
4673 * @retval State of bit (1 or 0).
4674 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4675 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4676 {
4677 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4678 }
4679
4680 /**
4681 * @brief Enable capture/compare 1 DMA request (CC1DE).
4682 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4683 * @param TIMx Timer instance
4684 * @retval None
4685 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4686 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4687 {
4688 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4689 }
4690
4691 /**
4692 * @brief Disable capture/compare 1 DMA request (CC1DE).
4693 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4694 * @param TIMx Timer instance
4695 * @retval None
4696 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4697 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4698 {
4699 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4700 }
4701
4702 /**
4703 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4704 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4705 * @param TIMx Timer instance
4706 * @retval State of bit (1 or 0).
4707 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4708 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4709 {
4710 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4711 }
4712
4713 /**
4714 * @brief Enable capture/compare 2 DMA request (CC2DE).
4715 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4716 * @param TIMx Timer instance
4717 * @retval None
4718 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4719 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4720 {
4721 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4722 }
4723
4724 /**
4725 * @brief Disable capture/compare 2 DMA request (CC2DE).
4726 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4727 * @param TIMx Timer instance
4728 * @retval None
4729 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4730 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4731 {
4732 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4733 }
4734
4735 /**
4736 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4737 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4738 * @param TIMx Timer instance
4739 * @retval State of bit (1 or 0).
4740 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4741 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4742 {
4743 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4744 }
4745
4746 /**
4747 * @brief Enable capture/compare 3 DMA request (CC3DE).
4748 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4749 * @param TIMx Timer instance
4750 * @retval None
4751 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4752 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4753 {
4754 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4755 }
4756
4757 /**
4758 * @brief Disable capture/compare 3 DMA request (CC3DE).
4759 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4760 * @param TIMx Timer instance
4761 * @retval None
4762 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4763 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4764 {
4765 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4766 }
4767
4768 /**
4769 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4770 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4771 * @param TIMx Timer instance
4772 * @retval State of bit (1 or 0).
4773 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4774 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4775 {
4776 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4777 }
4778
4779 /**
4780 * @brief Enable capture/compare 4 DMA request (CC4DE).
4781 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4782 * @param TIMx Timer instance
4783 * @retval None
4784 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4785 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4786 {
4787 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4788 }
4789
4790 /**
4791 * @brief Disable capture/compare 4 DMA request (CC4DE).
4792 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4793 * @param TIMx Timer instance
4794 * @retval None
4795 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4796 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4797 {
4798 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4799 }
4800
4801 /**
4802 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4803 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4804 * @param TIMx Timer instance
4805 * @retval State of bit (1 or 0).
4806 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4807 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4808 {
4809 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4810 }
4811
4812 /**
4813 * @brief Enable commutation DMA request (COMDE).
4814 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4815 * @param TIMx Timer instance
4816 * @retval None
4817 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4818 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4819 {
4820 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4821 }
4822
4823 /**
4824 * @brief Disable commutation DMA request (COMDE).
4825 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4826 * @param TIMx Timer instance
4827 * @retval None
4828 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4829 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4830 {
4831 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4832 }
4833
4834 /**
4835 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4836 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4837 * @param TIMx Timer instance
4838 * @retval State of bit (1 or 0).
4839 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4840 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4841 {
4842 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4843 }
4844
4845 /**
4846 * @brief Enable trigger interrupt (TDE).
4847 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4848 * @param TIMx Timer instance
4849 * @retval None
4850 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4851 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4852 {
4853 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4854 }
4855
4856 /**
4857 * @brief Disable trigger interrupt (TDE).
4858 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4859 * @param TIMx Timer instance
4860 * @retval None
4861 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4862 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4863 {
4864 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4865 }
4866
4867 /**
4868 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4869 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4870 * @param TIMx Timer instance
4871 * @retval State of bit (1 or 0).
4872 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4873 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4874 {
4875 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4876 }
4877
4878 /**
4879 * @}
4880 */
4881
4882 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4883 * @{
4884 */
4885 /**
4886 * @brief Generate an update event.
4887 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4888 * @param TIMx Timer instance
4889 * @retval None
4890 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4891 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4892 {
4893 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4894 }
4895
4896 /**
4897 * @brief Generate Capture/Compare 1 event.
4898 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4899 * @param TIMx Timer instance
4900 * @retval None
4901 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4902 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4903 {
4904 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4905 }
4906
4907 /**
4908 * @brief Generate Capture/Compare 2 event.
4909 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4910 * @param TIMx Timer instance
4911 * @retval None
4912 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4913 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4914 {
4915 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4916 }
4917
4918 /**
4919 * @brief Generate Capture/Compare 3 event.
4920 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4921 * @param TIMx Timer instance
4922 * @retval None
4923 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4924 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4925 {
4926 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4927 }
4928
4929 /**
4930 * @brief Generate Capture/Compare 4 event.
4931 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4932 * @param TIMx Timer instance
4933 * @retval None
4934 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4935 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4936 {
4937 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4938 }
4939
4940 /**
4941 * @brief Generate commutation event.
4942 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4943 * @param TIMx Timer instance
4944 * @retval None
4945 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4946 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4947 {
4948 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4949 }
4950
4951 /**
4952 * @brief Generate trigger event.
4953 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4954 * @param TIMx Timer instance
4955 * @retval None
4956 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4957 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4958 {
4959 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4960 }
4961
4962 /**
4963 * @brief Generate break event.
4964 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4965 * @param TIMx Timer instance
4966 * @retval None
4967 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4968 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4969 {
4970 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4971 }
4972
4973 /**
4974 * @brief Generate break 2 event.
4975 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4976 * @param TIMx Timer instance
4977 * @retval None
4978 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4979 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4980 {
4981 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4982 }
4983
4984 /**
4985 * @}
4986 */
4987
4988 #if defined(USE_FULL_LL_DRIVER)
4989 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4990 * @{
4991 */
4992
4993 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4994 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4995 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4996 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4997 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4998 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4999 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
5000 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5001 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
5002 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5003 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5004 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5005 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5006 /**
5007 * @}
5008 */
5009 #endif /* USE_FULL_LL_DRIVER */
5010
5011 /**
5012 * @}
5013 */
5014
5015 /**
5016 * @}
5017 */
5018
5019 #endif /* TIM1 || TIM2 || TIM16 || TIM17 */
5020
5021 /**
5022 * @}
5023 */
5024
5025 #ifdef __cplusplus
5026 }
5027 #endif
5028
5029 #endif /* __STM32WBxx_LL_TIM_H */
5030
