1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32u5xx_ll_spi.h"
22 #include "stm32u5xx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32U5xx_LL_Driver
30 * @{
31 */
32
33 #if defined(SPI1) || defined(SPI2) || defined(SPI3)
34
35 /** @addtogroup SPI_LL
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup SPI_LL_Private_Macros
44 * @{
45 */
46
47 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \
48 ((__VALUE__) == LL_SPI_MODE_SLAVE))
49
50 #define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
51 ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
52 ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
53 ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
54 ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
55 ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
56 ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
57 ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
58 ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
59 ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
60 ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
61 ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
62 ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
63 ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
64 ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
65 ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
66
67 #define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
68 ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
69 ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
70 ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
71 ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
72 ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
73 ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
74 ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
75 ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
76 ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
77 ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
78 ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
79 ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
80 ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
81 ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
82 ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
83
84 #define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
85 ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
86
87 #define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
88 ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
89
90 #define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
91 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \
92 ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
93
94 #define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
95 ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \
96 ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
97
98 #define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \
99 ((__VALUE__) == LL_SPI_PROTOCOL_TI))
100
101 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \
102 ((__VALUE__) == LL_SPI_PHASE_2EDGE))
103
104 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \
105 ((__VALUE__) == LL_SPI_POLARITY_HIGH))
106
107 #define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_BYPASS) || \
108 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \
109 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \
110 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \
111 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \
112 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \
113 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \
114 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \
115 ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
116
117 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \
118 ((__VALUE__) == LL_SPI_MSB_FIRST))
119
120 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \
121 ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \
122 ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \
123 ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \
124 ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
125
126 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \
127 ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \
128 ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \
129 ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \
130 ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \
131 ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \
132 ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \
133 ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \
134 ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \
135 ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \
136 ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \
137 ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \
138 ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \
139 ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \
140 ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \
141 ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \
142 ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \
143 ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \
144 ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \
145 ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \
146 ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \
147 ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \
148 ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \
149 ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \
150 ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \
151 ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \
152 ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \
153 ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \
154 ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
155
156 #define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \
157 ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \
158 ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \
159 ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \
160 ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \
161 ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \
162 ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \
163 ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \
164 ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \
165 ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \
166 ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \
167 ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \
168 ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \
169 ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \
170 ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \
171 ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
172
173 #define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \
174 ((__VALUE__) == LL_SPI_CRC_5BIT) || \
175 ((__VALUE__) == LL_SPI_CRC_6BIT) || \
176 ((__VALUE__) == LL_SPI_CRC_7BIT) || \
177 ((__VALUE__) == LL_SPI_CRC_8BIT) || \
178 ((__VALUE__) == LL_SPI_CRC_9BIT) || \
179 ((__VALUE__) == LL_SPI_CRC_10BIT) || \
180 ((__VALUE__) == LL_SPI_CRC_11BIT) || \
181 ((__VALUE__) == LL_SPI_CRC_12BIT) || \
182 ((__VALUE__) == LL_SPI_CRC_13BIT) || \
183 ((__VALUE__) == LL_SPI_CRC_14BIT) || \
184 ((__VALUE__) == LL_SPI_CRC_15BIT) || \
185 ((__VALUE__) == LL_SPI_CRC_16BIT) || \
186 ((__VALUE__) == LL_SPI_CRC_17BIT) || \
187 ((__VALUE__) == LL_SPI_CRC_18BIT) || \
188 ((__VALUE__) == LL_SPI_CRC_19BIT) || \
189 ((__VALUE__) == LL_SPI_CRC_20BIT) || \
190 ((__VALUE__) == LL_SPI_CRC_21BIT) || \
191 ((__VALUE__) == LL_SPI_CRC_22BIT) || \
192 ((__VALUE__) == LL_SPI_CRC_23BIT) || \
193 ((__VALUE__) == LL_SPI_CRC_24BIT) || \
194 ((__VALUE__) == LL_SPI_CRC_25BIT) || \
195 ((__VALUE__) == LL_SPI_CRC_26BIT) || \
196 ((__VALUE__) == LL_SPI_CRC_27BIT) || \
197 ((__VALUE__) == LL_SPI_CRC_28BIT) || \
198 ((__VALUE__) == LL_SPI_CRC_29BIT) || \
199 ((__VALUE__) == LL_SPI_CRC_30BIT) || \
200 ((__VALUE__) == LL_SPI_CRC_31BIT) || \
201 ((__VALUE__) == LL_SPI_CRC_32BIT))
202
203 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \
204 ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \
205 ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
206
207 #define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \
208 ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \
209 ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \
210 ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
211
212 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \
213 ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
214
215 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL)
216
217 /**
218 * @}
219 */
220
221 /* Private function prototypes -----------------------------------------------*/
222
223 /* Exported functions --------------------------------------------------------*/
224 /** @addtogroup SPI_LL_Exported_Functions
225 * @{
226 */
227
228 /** @addtogroup SPI_LL_EF_Init
229 * @{
230 */
231
232 /**
233 * @brief De-initialize the SPI registers to their default reset values.
234 * @param SPIx SPI Instance
235 * @retval An ErrorStatus enumeration value:
236 * - SUCCESS: SPI registers are de-initialized
237 * - ERROR: SPI registers are not de-initialized
238 */
LL_SPI_DeInit(const SPI_TypeDef * SPIx)239 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
240 {
241 ErrorStatus status = ERROR;
242
243 /* Check the parameters */
244 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
245
246 #if defined(SPI1)
247 if (SPIx == SPI1)
248 {
249 /* Force reset of SPI clock */
250 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
251
252 /* Release reset of SPI clock */
253 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
254
255 /* Update the return status */
256 status = SUCCESS;
257 }
258 #endif /* SPI1 */
259 #if defined(SPI2)
260 if (SPIx == SPI2)
261 {
262 /* Force reset of SPI clock */
263 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
264
265 /* Release reset of SPI clock */
266 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
267
268 /* Update the return status */
269 status = SUCCESS;
270 }
271 #endif /* SPI2 */
272 #if defined(SPI3)
273 if (SPIx == SPI3)
274 {
275 /* Force reset of SPI clock */
276 LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SPI3);
277
278 /* Release reset of SPI clock */
279 LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SPI3);
280
281 /* Update the return status */
282 status = SUCCESS;
283 }
284 #endif /* SPI3 */
285 #if defined(SPI4)
286 if (SPIx == SPI4)
287 {
288 /* Force reset of SPI clock */
289 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
290
291 /* Release reset of SPI clock */
292 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
293
294 /* Update the return status */
295 status = SUCCESS;
296 }
297 #endif /* SPI4 */
298 #if defined(SPI5)
299 if (SPIx == SPI5)
300 {
301 /* Force reset of SPI clock */
302 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
303
304 /* Release reset of SPI clock */
305 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
306
307 /* Update the return status */
308 status = SUCCESS;
309 }
310 #endif /* SPI5 */
311 #if defined(SPI6)
312 if (SPIx == SPI6)
313 {
314 /* Force reset of SPI clock */
315 LL_APB5_GRP1_ForceReset(LL_APB5_GRP1_PERIPH_SPI6);
316
317 /* Release reset of SPI clock */
318 LL_APB5_GRP1_ReleaseReset(LL_APB5_GRP1_PERIPH_SPI6);
319
320 /* Update the return status */
321 status = SUCCESS;
322 }
323 #endif /* SPI6 */
324
325 return status;
326 }
327
328 /**
329 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
330 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled
331 * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
332 * Otherwise, ERROR result will be returned.
333 * @param SPIx SPI Instance
334 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
335 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
336 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)337 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
338 {
339 ErrorStatus status = ERROR;
340 uint32_t tmp_nss;
341 uint32_t tmp_mode;
342 uint32_t tmp_nss_polarity;
343
344 /* Check the SPI Instance SPIx*/
345 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
346
347 /* Check the SPI parameters from SPI_InitStruct*/
348 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
349 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
350 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
351 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
352 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
353 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
354 assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate));
355 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
356 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
357
358 /* Check the SPI instance is not enabled */
359 if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
360 {
361 /*---------------------------- SPIx CFG1 Configuration ------------------------
362 * Configure SPIx CFG1 with parameters:
363 * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits & SPI_CFG1_BPASS bit
364 * - CRC Computation Enable : SPI_CFG1_CRCEN bit
365 * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits
366 */
367 MODIFY_REG(SPIx->CFG1, SPI_CFG1_BPASS | SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
368 SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
369
370 tmp_nss = SPI_InitStruct->NSS;
371 tmp_mode = SPI_InitStruct->Mode;
372 tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
373
374 /* Checks to setup Internal SS signal level and avoid a MODF Error */
375 if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \
376 (tmp_mode == LL_SPI_MODE_MASTER)) || \
377 ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
378 (tmp_mode == LL_SPI_MODE_SLAVE))))
379 {
380 LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
381 }
382
383 /*---------------------------- SPIx CFG2 Configuration ------------------------
384 * Configure SPIx CFG2 with parameters:
385 * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits
386 * - ClockPolarity : SPI_CFG2_CPOL bit
387 * - ClockPhase : SPI_CFG2_CPHA bit
388 * - BitOrder : SPI_CFG2_LSBFRST bit
389 * - Master/Slave Mode : SPI_CFG2_MASTER bit
390 * - SPI Mode : SPI_CFG2_COMM[1:0] bits
391 */
392 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE |
393 SPI_CFG2_CPOL | SPI_CFG2_CPHA |
394 SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM,
395 SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity |
396 SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder |
397 SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
398
399 /*---------------------------- SPIx CR1 Configuration ------------------------
400 * Configure SPIx CR1 with parameter:
401 * - Half Duplex Direction : SPI_CR1_HDDIR bit
402 */
403 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR);
404
405 /*---------------------------- SPIx CRCPOLY Configuration ----------------------
406 * Configure SPIx CRCPOLY with parameter:
407 * - CRCPoly : CRCPOLY[31:0] bits
408 */
409 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
410 {
411 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
412 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
413 }
414
415
416 status = SUCCESS;
417 }
418
419 return status;
420 }
421
422 /**
423 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
424 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
425 * whose fields will be set to default values.
426 * @retval None
427 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)428 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
429 {
430 /* Set SPI_InitStruct fields to default values */
431 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
432 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
433 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
434 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
435 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
436 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
437 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
438 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
439 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
440 SPI_InitStruct->CRCPoly = 7UL;
441 }
442
443 /**
444 * @}
445 */
446
447 /**
448 * @}
449 */
450
451 /**
452 * @}
453 */
454
455 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */
456
457 /**
458 * @}
459 */
460 #endif /* USE_FULL_LL_DRIVER */
461
