1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_TIM_H 21 #define STM32MP1xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 50 51 uint32_t CounterMode; /*!< Specifies the counter mode. 52 This parameter can be a value of @ref TIM_Counter_Mode */ 53 54 uint32_t Period; /*!< Specifies the period value to be loaded into the active 55 Auto-Reload Register at the next update event. 56 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 57 58 uint32_t ClockDivision; /*!< Specifies the clock division. 59 This parameter can be a value of @ref TIM_ClockDivision */ 60 61 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 62 reaches zero, an update event is generated and counting restarts 63 from the RCR value (N). 64 This means in PWM mode that (N+1) corresponds to: 65 - the number of PWM periods in edge-aligned mode 66 - the number of half PWM period in center-aligned mode 67 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 68 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 69 70 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 71 This parameter can be a value of @ref TIM_AutoReloadPreload */ 72 } TIM_Base_InitTypeDef; 73 74 /** 75 * @brief TIM Output Compare Configuration Structure definition 76 */ 77 typedef struct 78 { 79 uint32_t OCMode; /*!< Specifies the TIM mode. 80 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 81 82 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 83 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 84 85 uint32_t OCPolarity; /*!< Specifies the output polarity. 86 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 87 88 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 89 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 90 @note This parameter is valid only for timer instances supporting break feature. */ 91 92 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 93 This parameter can be a value of @ref TIM_Output_Fast_State 94 @note This parameter is valid only in PWM1 and PWM2 mode. */ 95 96 97 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 98 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 99 @note This parameter is valid only for timer instances supporting break feature. */ 100 101 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 102 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 103 @note This parameter is valid only for timer instances supporting break feature. */ 104 } TIM_OC_InitTypeDef; 105 106 /** 107 * @brief TIM One Pulse Mode Configuration Structure definition 108 */ 109 typedef struct 110 { 111 uint32_t OCMode; /*!< Specifies the TIM mode. 112 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 113 114 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 115 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 116 117 uint32_t OCPolarity; /*!< Specifies the output polarity. 118 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 119 120 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 121 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 122 @note This parameter is valid only for timer instances supporting break feature. */ 123 124 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 125 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 126 @note This parameter is valid only for timer instances supporting break feature. */ 127 128 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 129 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 130 @note This parameter is valid only for timer instances supporting break feature. */ 131 132 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 133 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 134 135 uint32_t ICSelection; /*!< Specifies the input. 136 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 137 138 uint32_t ICFilter; /*!< Specifies the input capture filter. 139 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 140 } TIM_OnePulse_InitTypeDef; 141 142 /** 143 * @brief TIM Input Capture Configuration Structure definition 144 */ 145 typedef struct 146 { 147 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 148 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 149 150 uint32_t ICSelection; /*!< Specifies the input. 151 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 152 153 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 154 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 155 156 uint32_t ICFilter; /*!< Specifies the input capture filter. 157 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 158 } TIM_IC_InitTypeDef; 159 160 /** 161 * @brief TIM Encoder Configuration Structure definition 162 */ 163 typedef struct 164 { 165 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 166 This parameter can be a value of @ref TIM_Encoder_Mode */ 167 168 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 169 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 170 171 uint32_t IC1Selection; /*!< Specifies the input. 172 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 173 174 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 175 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 176 177 uint32_t IC1Filter; /*!< Specifies the input capture filter. 178 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 179 180 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 181 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 182 183 uint32_t IC2Selection; /*!< Specifies the input. 184 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 185 186 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 187 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 188 189 uint32_t IC2Filter; /*!< Specifies the input capture filter. 190 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 191 } TIM_Encoder_InitTypeDef; 192 193 /** 194 * @brief Clock Configuration Handle Structure definition 195 */ 196 typedef struct 197 { 198 uint32_t ClockSource; /*!< TIM clock sources 199 This parameter can be a value of @ref TIM_Clock_Source */ 200 uint32_t ClockPolarity; /*!< TIM clock polarity 201 This parameter can be a value of @ref TIM_Clock_Polarity */ 202 uint32_t ClockPrescaler; /*!< TIM clock prescaler 203 This parameter can be a value of @ref TIM_Clock_Prescaler */ 204 uint32_t ClockFilter; /*!< TIM clock filter 205 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 206 } TIM_ClockConfigTypeDef; 207 208 /** 209 * @brief TIM Clear Input Configuration Handle Structure definition 210 */ 211 typedef struct 212 { 213 uint32_t ClearInputState; /*!< TIM clear Input state 214 This parameter can be ENABLE or DISABLE */ 215 uint32_t ClearInputSource; /*!< TIM clear Input sources 216 This parameter can be a value of @ref TIM_ClearInput_Source */ 217 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 218 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 219 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 220 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 221 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 223 } TIM_ClearInputConfigTypeDef; 224 225 /** 226 * @brief TIM Master configuration Structure definition 227 * @note Advanced timers provide TRGO2 internal line which is redirected 228 * to the ADC 229 */ 230 typedef struct 231 { 232 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 233 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 234 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 235 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 236 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 237 This parameter can be a value of @ref TIM_Master_Slave_Mode 238 @note When the Master/slave mode is enabled, the effect of 239 an event on the trigger input (TRGI) is delayed to allow a 240 perfect synchronization between the current timer and its 241 slaves (through TRGO). It is not mandatory in case of timer 242 synchronization mode. */ 243 } TIM_MasterConfigTypeDef; 244 245 /** 246 * @brief TIM Slave configuration Structure definition 247 */ 248 typedef struct 249 { 250 uint32_t SlaveMode; /*!< Slave mode selection 251 This parameter can be a value of @ref TIM_Slave_Mode */ 252 uint32_t InputTrigger; /*!< Input Trigger source 253 This parameter can be a value of @ref TIM_Trigger_Selection */ 254 uint32_t TriggerPolarity; /*!< Input Trigger polarity 255 This parameter can be a value of @ref TIM_Trigger_Polarity */ 256 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 257 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 258 uint32_t TriggerFilter; /*!< Input trigger filter 259 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 260 261 } TIM_SlaveConfigTypeDef; 262 263 /** 264 * @brief TIM Break input(s) and Dead time configuration Structure definition 265 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 266 * filter and polarity. 267 */ 268 typedef struct 269 { 270 uint32_t OffStateRunMode; /*!< TIM off state in run mode 271 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 272 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 273 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 274 uint32_t LockLevel; /*!< TIM Lock level 275 This parameter can be a value of @ref TIM_Lock_level */ 276 uint32_t DeadTime; /*!< TIM dead Time 277 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 278 uint32_t BreakState; /*!< TIM Break State 279 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 280 uint32_t BreakPolarity; /*!< TIM Break input polarity 281 This parameter can be a value of @ref TIM_Break_Polarity */ 282 uint32_t BreakFilter; /*!< Specifies the break input filter. 283 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 284 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. 285 This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 286 uint32_t Break2State; /*!< TIM Break2 State 287 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 288 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 289 This parameter can be a value of @ref TIM_Break2_Polarity */ 290 uint32_t Break2Filter; /*!< TIM break2 input filter. 291 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 292 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. 293 This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ 294 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 295 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 296 } TIM_BreakDeadTimeConfigTypeDef; 297 298 /** 299 * @brief HAL State structures definition 300 */ 301 typedef enum 302 { 303 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 304 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 305 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 306 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 307 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 308 } HAL_TIM_StateTypeDef; 309 310 /** 311 * @brief HAL Active channel structures definition 312 */ 313 typedef enum 314 { 315 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 316 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 317 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 318 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 319 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 320 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 321 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 322 } HAL_TIM_ActiveChannel; 323 324 /** 325 * @brief TIM Time Base Handle Structure definition 326 */ 327 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 328 typedef struct __TIM_HandleTypeDef 329 #else 330 typedef struct 331 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 332 { 333 TIM_TypeDef *Instance; /*!< Register base address */ 334 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 335 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 336 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 337 This array is accessed by a @ref DMA_Handle_index */ 338 HAL_LockTypeDef Lock; /*!< Locking object */ 339 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 340 341 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 342 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 343 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 344 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 345 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 346 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 347 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 348 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 349 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 350 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 351 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 352 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 353 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 354 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 355 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 356 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 357 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 358 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 359 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 360 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 361 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 362 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 363 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 364 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 365 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 366 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 367 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 368 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 369 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 370 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 371 } TIM_HandleTypeDef; 372 373 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 374 /** 375 * @brief HAL TIM Callback ID enumeration definition 376 */ 377 typedef enum 378 { 379 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 380 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 381 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 382 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 383 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 384 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 385 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 386 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 387 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 388 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 389 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 390 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 391 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 392 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 393 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 394 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 395 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 396 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 397 398 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 399 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 400 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 401 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 402 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 403 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 404 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 405 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 406 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 407 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 408 } HAL_TIM_CallbackIDTypeDef; 409 410 /** 411 * @brief HAL TIM Callback pointer definition 412 */ 413 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 414 415 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 416 417 /** 418 * @} 419 */ 420 /* End of exported types -----------------------------------------------------*/ 421 422 /* Exported constants --------------------------------------------------------*/ 423 /** @defgroup TIM_Exported_Constants TIM Exported Constants 424 * @{ 425 */ 426 427 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 428 * @{ 429 */ 430 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ 431 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 432 /** 433 * @} 434 */ 435 436 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 437 * @{ 438 */ 439 #define TIM_DMABASE_CR1 0x00000000U 440 #define TIM_DMABASE_CR2 0x00000001U 441 #define TIM_DMABASE_SMCR 0x00000002U 442 #define TIM_DMABASE_DIER 0x00000003U 443 #define TIM_DMABASE_SR 0x00000004U 444 #define TIM_DMABASE_EGR 0x00000005U 445 #define TIM_DMABASE_CCMR1 0x00000006U 446 #define TIM_DMABASE_CCMR2 0x00000007U 447 #define TIM_DMABASE_CCER 0x00000008U 448 #define TIM_DMABASE_CNT 0x00000009U 449 #define TIM_DMABASE_PSC 0x0000000AU 450 #define TIM_DMABASE_ARR 0x0000000BU 451 #define TIM_DMABASE_RCR 0x0000000CU 452 #define TIM_DMABASE_CCR1 0x0000000DU 453 #define TIM_DMABASE_CCR2 0x0000000EU 454 #define TIM_DMABASE_CCR3 0x0000000FU 455 #define TIM_DMABASE_CCR4 0x00000010U 456 #define TIM_DMABASE_BDTR 0x00000011U 457 #define TIM_DMABASE_DCR 0x00000012U 458 #define TIM_DMABASE_DMAR 0x00000013U 459 #define TIM_DMABASE_CCMR3 0x00000015U 460 #define TIM_DMABASE_CCR5 0x00000016U 461 #define TIM_DMABASE_CCR6 0x00000017U 462 #define TIM_DMABASE_AF1 0x00000018U 463 #define TIM_DMABASE_AF2 0x00000019U 464 #define TIM_DMABASE_TISEL 0x00000020U 465 /** 466 * @} 467 */ 468 469 /** @defgroup TIM_Event_Source TIM Event Source 470 * @{ 471 */ 472 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 473 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 474 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 475 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 476 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 477 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 478 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 479 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 480 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 486 * @{ 487 */ 488 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 489 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 490 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 491 /** 492 * @} 493 */ 494 495 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 496 * @{ 497 */ 498 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 499 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 505 * @{ 506 */ 507 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 508 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 509 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 510 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 511 /** 512 * @} 513 */ 514 515 /** @defgroup TIM_Counter_Mode TIM Counter Mode 516 * @{ 517 */ 518 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 519 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 520 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 521 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 522 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 523 /** 524 * @} 525 */ 526 527 /** @defgroup TIM_ClockDivision TIM Clock Division 528 * @{ 529 */ 530 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 531 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 532 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 533 /** 534 * @} 535 */ 536 537 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 538 * @{ 539 */ 540 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 541 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 542 /** 543 * @} 544 */ 545 546 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 547 * @{ 548 */ 549 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 550 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 551 552 /** 553 * @} 554 */ 555 556 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 557 * @{ 558 */ 559 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 560 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 561 /** 562 * @} 563 */ 564 565 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 566 * @{ 567 */ 568 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 569 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 570 /** 571 * @} 572 */ 573 574 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 575 * @{ 576 */ 577 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 578 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 579 /** 580 * @} 581 */ 582 583 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 584 * @{ 585 */ 586 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 587 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 588 /** 589 * @} 590 */ 591 592 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 593 * @{ 594 */ 595 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 596 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 597 /** 598 * @} 599 */ 600 601 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 602 * @{ 603 */ 604 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 605 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 611 * @{ 612 */ 613 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 614 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 615 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 616 /** 617 * @} 618 */ 619 620 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 621 * @{ 622 */ 623 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 624 connected to IC1, IC2, IC3 or IC4, respectively */ 625 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 626 connected to IC2, IC1, IC4 or IC3, respectively */ 627 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 633 * @{ 634 */ 635 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 636 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 637 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 638 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 639 /** 640 * @} 641 */ 642 643 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 644 * @{ 645 */ 646 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 647 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 648 /** 649 * @} 650 */ 651 652 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 653 * @{ 654 */ 655 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 656 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 657 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 658 /** 659 * @} 660 */ 661 662 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 663 * @{ 664 */ 665 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 666 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 667 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 668 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 669 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 670 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 671 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 672 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 673 /** 674 * @} 675 */ 676 677 /** @defgroup TIM_Commutation_Source TIM Commutation Source 678 * @{ 679 */ 680 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 681 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 682 /** 683 * @} 684 */ 685 686 /** @defgroup TIM_DMA_sources TIM DMA Sources 687 * @{ 688 */ 689 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 690 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 691 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 692 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 693 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 694 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 695 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup TIM_Flag_definition TIM Flag Definition 701 * @{ 702 */ 703 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 704 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 705 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 706 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 707 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 708 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 709 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 710 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 711 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 712 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 713 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 714 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 715 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 716 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 717 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 718 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup TIM_Channel TIM Channel 724 * @{ 725 */ 726 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 727 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 728 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 729 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 730 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 731 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 732 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 733 /** 734 * @} 735 */ 736 737 /** @defgroup TIM_Clock_Source TIM Clock Source 738 * @{ 739 */ 740 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 741 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 742 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 743 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 744 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 745 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 746 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 747 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 748 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 749 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 750 /** 751 * @} 752 */ 753 754 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 755 * @{ 756 */ 757 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 758 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 759 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 760 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 761 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 762 /** 763 * @} 764 */ 765 766 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 767 * @{ 768 */ 769 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 770 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 771 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 772 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 778 * @{ 779 */ 780 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 781 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 782 /** 783 * @} 784 */ 785 786 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 787 * @{ 788 */ 789 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 790 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 791 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 792 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 793 /** 794 * @} 795 */ 796 797 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 798 * @{ 799 */ 800 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 801 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 802 /** 803 * @} 804 */ 805 806 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 807 * @{ 808 */ 809 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 810 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 811 /** 812 * @} 813 */ 814 /** @defgroup TIM_Lock_level TIM Lock level 815 * @{ 816 */ 817 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 818 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 819 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 820 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 826 * @{ 827 */ 828 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 829 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 830 /** 831 * @} 832 */ 833 834 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 835 * @{ 836 */ 837 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 838 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 839 /** 840 * @} 841 */ 842 843 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 844 * @{ 845 */ 846 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 847 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 848 /** 849 * @} 850 */ 851 852 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 853 * @{ 854 */ 855 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 856 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 857 /** 858 * @} 859 */ 860 861 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 862 * @{ 863 */ 864 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 865 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 866 /** 867 * @} 868 */ 869 870 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode 871 * @{ 872 */ 873 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 874 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 875 /** 876 * @} 877 */ 878 879 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 880 * @{ 881 */ 882 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 883 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 884 (if none of the break inputs BRK and BRK2 is active) */ 885 /** 886 * @} 887 */ 888 889 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 890 * @{ 891 */ 892 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 893 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 894 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 895 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 896 /** 897 * @} 898 */ 899 900 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 901 * @{ 902 */ 903 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 904 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 905 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 906 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 907 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 908 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 909 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 910 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 911 /** 912 * @} 913 */ 914 915 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 916 * @{ 917 */ 918 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 919 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 920 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 921 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 922 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 923 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 924 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 925 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 926 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 927 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 928 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 929 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 930 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 931 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 932 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 933 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 934 /** 935 * @} 936 */ 937 938 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 939 * @{ 940 */ 941 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 942 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 943 /** 944 * @} 945 */ 946 947 /** @defgroup TIM_Slave_Mode TIM Slave mode 948 * @{ 949 */ 950 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 951 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 952 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 953 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 954 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 955 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 956 /** 957 * @} 958 */ 959 960 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 961 * @{ 962 */ 963 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 964 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 965 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 966 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 967 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 968 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 969 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 970 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 971 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 972 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 973 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 974 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 975 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 976 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 977 /** 978 * @} 979 */ 980 981 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 982 * @{ 983 */ 984 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 985 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 986 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 987 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 988 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 989 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 990 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 991 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 992 #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ 993 /** 994 * @} 995 */ 996 997 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 998 * @{ 999 */ 1000 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1001 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1002 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1003 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1004 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1005 /** 1006 * @} 1007 */ 1008 1009 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1010 * @{ 1011 */ 1012 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1013 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1014 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1015 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1016 /** 1017 * @} 1018 */ 1019 1020 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1021 * @{ 1022 */ 1023 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1024 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1025 /** 1026 * @} 1027 */ 1028 1029 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1030 * @{ 1031 */ 1032 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1033 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1034 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1035 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1036 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1037 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1038 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1039 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1040 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1041 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1042 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1043 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1044 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1045 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1046 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1047 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1048 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1049 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1055 * @{ 1056 */ 1057 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1058 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1059 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1060 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1061 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1062 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1063 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1064 /** 1065 * @} 1066 */ 1067 1068 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1069 * @{ 1070 */ 1071 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1072 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1073 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1074 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1075 /** 1076 * @} 1077 */ 1078 1079 /** @defgroup TIM_Break_System TIM Break System 1080 * @{ 1081 */ 1082 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1083 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ 1084 /** 1085 * @} 1086 */ 1087 1088 /** 1089 * @} 1090 */ 1091 /* End of exported constants -------------------------------------------------*/ 1092 1093 /* Exported macros -----------------------------------------------------------*/ 1094 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1095 * @{ 1096 */ 1097 1098 /** @brief Reset TIM handle state. 1099 * @param __HANDLE__ TIM handle. 1100 * @retval None 1101 */ 1102 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1103 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1104 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1105 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1106 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1107 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1108 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1109 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1110 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1111 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1112 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1113 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1114 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1115 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1116 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1117 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1118 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1119 } while(0) 1120 #else 1121 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) 1122 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1123 1124 /** 1125 * @brief Enable the TIM peripheral. 1126 * @param __HANDLE__ TIM handle 1127 * @retval None 1128 */ 1129 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1130 1131 /** 1132 * @brief Enable the TIM main Output. 1133 * @param __HANDLE__ TIM handle 1134 * @retval None 1135 */ 1136 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1137 1138 /** 1139 * @brief Disable the TIM peripheral. 1140 * @param __HANDLE__ TIM handle 1141 * @retval None 1142 */ 1143 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1144 do { \ 1145 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1146 { \ 1147 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1148 { \ 1149 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1150 } \ 1151 } \ 1152 } while(0) 1153 1154 /** 1155 * @brief Disable the TIM main Output. 1156 * @param __HANDLE__ TIM handle 1157 * @retval None 1158 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1159 */ 1160 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1161 do { \ 1162 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1163 { \ 1164 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1165 { \ 1166 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1167 } \ 1168 } \ 1169 } while(0) 1170 1171 /** 1172 * @brief Disable the TIM main Output. 1173 * @param __HANDLE__ TIM handle 1174 * @retval None 1175 * @note The Main Output Enable of a timer instance is disabled unconditionally 1176 */ 1177 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1178 1179 /** @brief Enable the specified TIM interrupt. 1180 * @param __HANDLE__ specifies the TIM Handle. 1181 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1182 * This parameter can be one of the following values: 1183 * @arg TIM_IT_UPDATE: Update interrupt 1184 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1185 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1186 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1187 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1188 * @arg TIM_IT_COM: Commutation interrupt 1189 * @arg TIM_IT_TRIGGER: Trigger interrupt 1190 * @arg TIM_IT_BREAK: Break interrupt 1191 * @retval None 1192 */ 1193 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1194 1195 /** @brief Disable the specified TIM interrupt. 1196 * @param __HANDLE__ specifies the TIM Handle. 1197 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1198 * This parameter can be one of the following values: 1199 * @arg TIM_IT_UPDATE: Update interrupt 1200 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1201 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1202 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1203 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1204 * @arg TIM_IT_COM: Commutation interrupt 1205 * @arg TIM_IT_TRIGGER: Trigger interrupt 1206 * @arg TIM_IT_BREAK: Break interrupt 1207 * @retval None 1208 */ 1209 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1210 1211 /** @brief Enable the specified DMA request. 1212 * @param __HANDLE__ specifies the TIM Handle. 1213 * @param __DMA__ specifies the TIM DMA request to enable. 1214 * This parameter can be one of the following values: 1215 * @arg TIM_DMA_UPDATE: Update DMA request 1216 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1217 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1218 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1219 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1220 * @arg TIM_DMA_COM: Commutation DMA request 1221 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1222 * @retval None 1223 */ 1224 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1225 1226 /** @brief Disable the specified DMA request. 1227 * @param __HANDLE__ specifies the TIM Handle. 1228 * @param __DMA__ specifies the TIM DMA request to disable. 1229 * This parameter can be one of the following values: 1230 * @arg TIM_DMA_UPDATE: Update DMA request 1231 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1232 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1233 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1234 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1235 * @arg TIM_DMA_COM: Commutation DMA request 1236 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1237 * @retval None 1238 */ 1239 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1240 1241 /** @brief Check whether the specified TIM interrupt flag is set or not. 1242 * @param __HANDLE__ specifies the TIM Handle. 1243 * @param __FLAG__ specifies the TIM interrupt flag to check. 1244 * This parameter can be one of the following values: 1245 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1246 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1247 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1248 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1249 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1250 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1251 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1252 * @arg TIM_FLAG_COM: Commutation interrupt flag 1253 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1254 * @arg TIM_FLAG_BREAK: Break interrupt flag 1255 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1256 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1257 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1258 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1259 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1260 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1261 * @retval The new state of __FLAG__ (TRUE or FALSE). 1262 */ 1263 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1264 1265 /** @brief Clear the specified TIM interrupt flag. 1266 * @param __HANDLE__ specifies the TIM Handle. 1267 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1268 * This parameter can be one of the following values: 1269 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1270 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1271 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1272 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1273 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1274 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1275 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1276 * @arg TIM_FLAG_COM: Commutation interrupt flag 1277 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1278 * @arg TIM_FLAG_BREAK: Break interrupt flag 1279 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1280 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1281 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1282 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1283 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1284 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1285 * @retval The new state of __FLAG__ (TRUE or FALSE). 1286 */ 1287 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1288 1289 /** 1290 * @brief Check whether the specified TIM interrupt source is enabled or not. 1291 * @param __HANDLE__ TIM handle 1292 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1293 * This parameter can be one of the following values: 1294 * @arg TIM_IT_UPDATE: Update interrupt 1295 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1296 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1297 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1298 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1299 * @arg TIM_IT_COM: Commutation interrupt 1300 * @arg TIM_IT_TRIGGER: Trigger interrupt 1301 * @arg TIM_IT_BREAK: Break interrupt 1302 * @retval The state of TIM_IT (SET or RESET). 1303 */ 1304 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1305 == (__INTERRUPT__)) ? SET : RESET) 1306 1307 /** @brief Clear the TIM interrupt pending bits. 1308 * @param __HANDLE__ TIM handle 1309 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1310 * This parameter can be one of the following values: 1311 * @arg TIM_IT_UPDATE: Update interrupt 1312 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1313 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1314 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1315 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1316 * @arg TIM_IT_COM: Commutation interrupt 1317 * @arg TIM_IT_TRIGGER: Trigger interrupt 1318 * @arg TIM_IT_BREAK: Break interrupt 1319 * @retval None 1320 */ 1321 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1322 1323 /** 1324 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1325 * @param __HANDLE__ TIM handle. 1326 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1327 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1328 mode. 1329 */ 1330 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1331 1332 /** 1333 * @brief Set the TIM Prescaler on runtime. 1334 * @param __HANDLE__ TIM handle. 1335 * @param __PRESC__ specifies the Prescaler new value. 1336 * @retval None 1337 */ 1338 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1339 1340 /** 1341 * @brief Set the TIM Counter Register value on runtime. 1342 * @param __HANDLE__ TIM handle. 1343 * @param __COUNTER__ specifies the Counter register new value. 1344 * @retval None 1345 */ 1346 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1347 1348 /** 1349 * @brief Get the TIM Counter Register value on runtime. 1350 * @param __HANDLE__ TIM handle. 1351 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1352 */ 1353 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1354 1355 /** 1356 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1357 * @param __HANDLE__ TIM handle. 1358 * @param __AUTORELOAD__ specifies the Counter register new value. 1359 * @retval None 1360 */ 1361 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1362 do{ \ 1363 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1364 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1365 } while(0) 1366 1367 /** 1368 * @brief Get the TIM Autoreload Register value on runtime. 1369 * @param __HANDLE__ TIM handle. 1370 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1371 */ 1372 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1373 1374 /** 1375 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1376 * @param __HANDLE__ TIM handle. 1377 * @param __CKD__ specifies the clock division value. 1378 * This parameter can be one of the following value: 1379 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1380 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1381 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1382 * @retval None 1383 */ 1384 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1385 do{ \ 1386 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1387 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1388 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1389 } while(0) 1390 1391 /** 1392 * @brief Get the TIM Clock Division value on runtime. 1393 * @param __HANDLE__ TIM handle. 1394 * @retval The clock division can be one of the following values: 1395 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1396 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1397 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1398 */ 1399 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1400 1401 /** 1402 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1403 * @param __HANDLE__ TIM handle. 1404 * @param __CHANNEL__ TIM Channels to be configured. 1405 * This parameter can be one of the following values: 1406 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1407 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1408 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1409 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1410 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1411 * This parameter can be one of the following values: 1412 * @arg TIM_ICPSC_DIV1: no prescaler 1413 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1414 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1415 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1416 * @retval None 1417 */ 1418 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1419 do{ \ 1420 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1421 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1422 } while(0) 1423 1424 /** 1425 * @brief Get the TIM Input Capture prescaler on runtime. 1426 * @param __HANDLE__ TIM handle. 1427 * @param __CHANNEL__ TIM Channels to be configured. 1428 * This parameter can be one of the following values: 1429 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1430 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1431 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1432 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1433 * @retval The input capture prescaler can be one of the following values: 1434 * @arg TIM_ICPSC_DIV1: no prescaler 1435 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1436 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1437 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1438 */ 1439 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1440 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1441 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1442 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1443 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1444 1445 /** 1446 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1447 * @param __HANDLE__ TIM handle. 1448 * @param __CHANNEL__ TIM Channels to be configured. 1449 * This parameter can be one of the following values: 1450 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1451 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1452 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1453 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1454 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1455 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1456 * @param __COMPARE__ specifies the Capture Compare register new value. 1457 * @retval None 1458 */ 1459 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1460 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1461 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1462 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1463 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1464 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1465 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1466 1467 /** 1468 * @brief Get the TIM Capture Compare Register value on runtime. 1469 * @param __HANDLE__ TIM handle. 1470 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1471 * This parameter can be one of the following values: 1472 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1473 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1474 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1475 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1476 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1477 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1478 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1479 */ 1480 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1481 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1482 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1483 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1484 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1485 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1486 ((__HANDLE__)->Instance->CCR6)) 1487 1488 /** 1489 * @brief Set the TIM Output compare preload. 1490 * @param __HANDLE__ TIM handle. 1491 * @param __CHANNEL__ TIM Channels to be configured. 1492 * This parameter can be one of the following values: 1493 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1494 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1495 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1496 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1497 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1498 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1499 * @retval None 1500 */ 1501 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1502 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1503 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1504 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1505 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1506 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1507 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1508 1509 /** 1510 * @brief Reset the TIM Output compare preload. 1511 * @param __HANDLE__ TIM handle. 1512 * @param __CHANNEL__ TIM Channels to be configured. 1513 * This parameter can be one of the following values: 1514 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1515 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1516 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1517 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1518 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1519 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1520 * @retval None 1521 */ 1522 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1523 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1524 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1525 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1526 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1527 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1528 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1529 1530 /** 1531 * @brief Enable fast mode for a given channel. 1532 * @param __HANDLE__ TIM handle. 1533 * @param __CHANNEL__ TIM Channels to be configured. 1534 * This parameter can be one of the following values: 1535 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1536 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1537 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1538 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1539 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1540 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1541 * @note When fast mode is enabled an active edge on the trigger input acts 1542 * like a compare match on CCx output. Delay to sample the trigger 1543 * input and to activate CCx output is reduced to 3 clock cycles. 1544 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1545 * @retval None 1546 */ 1547 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1548 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1549 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1550 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1551 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1552 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1553 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1554 1555 /** 1556 * @brief Disable fast mode for a given channel. 1557 * @param __HANDLE__ TIM handle. 1558 * @param __CHANNEL__ TIM Channels to be configured. 1559 * This parameter can be one of the following values: 1560 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1561 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1562 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1563 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1564 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1565 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1566 * @note When fast mode is disabled CCx output behaves normally depending 1567 * on counter and CCRx values even when the trigger is ON. The minimum 1568 * delay to activate CCx output when an active edge occurs on the 1569 * trigger input is 5 clock cycles. 1570 * @retval None 1571 */ 1572 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1573 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1574 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1575 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1576 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1577 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1578 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1579 1580 /** 1581 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1582 * @param __HANDLE__ TIM handle. 1583 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1584 * overflow/underflow generates an update interrupt or DMA request (if 1585 * enabled) 1586 * @retval None 1587 */ 1588 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1589 1590 /** 1591 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1592 * @param __HANDLE__ TIM handle. 1593 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1594 * following events generate an update interrupt or DMA request (if 1595 * enabled): 1596 * _ Counter overflow underflow 1597 * _ Setting the UG bit 1598 * _ Update generation through the slave mode controller 1599 * @retval None 1600 */ 1601 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1602 1603 /** 1604 * @brief Set the TIM Capture x input polarity on runtime. 1605 * @param __HANDLE__ TIM handle. 1606 * @param __CHANNEL__ TIM Channels to be configured. 1607 * This parameter can be one of the following values: 1608 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1609 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1610 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1611 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1612 * @param __POLARITY__ Polarity for TIx source 1613 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1614 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1615 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1616 * @retval None 1617 */ 1618 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1619 do{ \ 1620 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1621 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1622 }while(0) 1623 1624 /** 1625 * @} 1626 */ 1627 /* End of exported macros ----------------------------------------------------*/ 1628 1629 /* Private constants ---------------------------------------------------------*/ 1630 /** @defgroup TIM_Private_Constants TIM Private Constants 1631 * @{ 1632 */ 1633 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1634 channels have been disabled */ 1635 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1636 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) 1637 /** 1638 * @} 1639 */ 1640 /* End of private constants --------------------------------------------------*/ 1641 1642 /* Private macros ------------------------------------------------------------*/ 1643 /** @defgroup TIM_Private_Macros TIM Private Macros 1644 * @{ 1645 */ 1646 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ 1647 ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) 1648 1649 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1650 ((__BASE__) == TIM_DMABASE_CR2) || \ 1651 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1652 ((__BASE__) == TIM_DMABASE_DIER) || \ 1653 ((__BASE__) == TIM_DMABASE_SR) || \ 1654 ((__BASE__) == TIM_DMABASE_EGR) || \ 1655 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1656 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1657 ((__BASE__) == TIM_DMABASE_CCER) || \ 1658 ((__BASE__) == TIM_DMABASE_CNT) || \ 1659 ((__BASE__) == TIM_DMABASE_PSC) || \ 1660 ((__BASE__) == TIM_DMABASE_ARR) || \ 1661 ((__BASE__) == TIM_DMABASE_RCR) || \ 1662 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1663 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1664 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1665 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1666 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1667 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1668 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1669 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1670 ((__BASE__) == TIM_DMABASE_TISEL)) 1671 1672 1673 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1674 1675 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1676 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1677 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1678 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1679 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1680 1681 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1682 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1683 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1684 1685 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1686 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1687 1688 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1689 ((__STATE__) == TIM_OCFAST_ENABLE)) 1690 1691 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1692 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1693 1694 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1695 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1696 1697 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1698 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1699 1700 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1701 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1702 1703 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1704 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1705 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1706 1707 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1708 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1709 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1710 1711 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1712 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1713 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1714 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1715 1716 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1717 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1718 1719 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1720 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1721 ((__MODE__) == TIM_ENCODERMODE_TI12)) 1722 1723 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1724 1725 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1726 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1727 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1728 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1729 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1730 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1731 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1732 1733 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1734 ((__CHANNEL__) == TIM_CHANNEL_2)) 1735 1736 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1737 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1738 ((__CHANNEL__) == TIM_CHANNEL_3)) 1739 1740 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1741 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1742 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1743 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1744 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1745 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1746 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1747 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1748 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1749 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) 1750 1751 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 1752 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 1753 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 1754 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 1755 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 1756 1757 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 1758 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 1759 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 1760 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 1761 1762 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1763 1764 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 1765 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 1766 1767 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 1768 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 1769 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 1770 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 1771 1772 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1773 1774 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 1775 ((__STATE__) == TIM_OSSR_DISABLE)) 1776 1777 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 1778 ((__STATE__) == TIM_OSSI_DISABLE)) 1779 1780 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 1781 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 1782 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 1783 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 1784 1785 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 1786 1787 1788 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 1789 ((__STATE__) == TIM_BREAK_DISABLE)) 1790 1791 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 1792 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 1793 1794 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 1795 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 1796 1797 1798 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 1799 ((__STATE__) == TIM_BREAK2_DISABLE)) 1800 1801 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 1802 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 1803 1804 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ 1805 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) 1806 1807 1808 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 1809 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 1810 1811 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 1812 1813 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 1814 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 1815 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 1816 ((__SOURCE__) == TIM_TRGO_OC1) || \ 1817 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 1818 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 1819 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 1820 ((__SOURCE__) == TIM_TRGO_OC4REF)) 1821 1822 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 1823 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 1824 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 1825 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 1826 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 1827 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 1828 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1829 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 1830 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 1831 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 1832 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 1833 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 1834 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 1835 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 1836 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 1837 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 1838 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 1839 1840 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 1841 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 1842 1843 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 1844 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 1845 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 1846 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 1847 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 1848 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1849 1850 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 1851 ((__MODE__) == TIM_OCMODE_PWM2) || \ 1852 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 1853 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 1854 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 1855 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 1856 1857 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 1858 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 1859 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 1860 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 1861 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 1862 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 1863 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 1864 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) 1865 1866 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1867 ((__SELECTION__) == TIM_TS_ITR1) || \ 1868 ((__SELECTION__) == TIM_TS_ITR2) || \ 1869 ((__SELECTION__) == TIM_TS_ITR3) || \ 1870 ((__SELECTION__) == TIM_TS_TI1F_ED) || \ 1871 ((__SELECTION__) == TIM_TS_TI1FP1) || \ 1872 ((__SELECTION__) == TIM_TS_TI2FP2) || \ 1873 ((__SELECTION__) == TIM_TS_ETRF)) 1874 1875 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 1876 ((__SELECTION__) == TIM_TS_ITR1) || \ 1877 ((__SELECTION__) == TIM_TS_ITR2) || \ 1878 ((__SELECTION__) == TIM_TS_ITR3) || \ 1879 ((__SELECTION__) == TIM_TS_NONE)) 1880 1881 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 1882 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 1883 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 1884 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 1885 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 1886 1887 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 1888 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 1889 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 1890 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 1891 1892 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1893 1894 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 1895 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 1896 1897 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 1898 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 1899 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 1900 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 1901 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 1902 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 1903 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 1904 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 1905 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 1906 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 1907 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 1908 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 1909 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 1910 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 1911 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 1912 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 1913 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 1914 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) 1915 1916 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 1917 1918 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 1919 1920 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 1921 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 1922 1923 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 1924 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 1925 1926 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1927 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 1928 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 1929 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 1930 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 1931 1932 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 1933 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 1934 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 1935 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 1936 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 1937 1938 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1939 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 1940 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 1941 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 1942 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 1943 1944 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 1945 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 1946 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 1947 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 1948 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 1949 1950 /** 1951 * @} 1952 */ 1953 /* End of private macros -----------------------------------------------------*/ 1954 1955 /* Include TIM HAL Extended module */ 1956 #include "stm32mp1xx_hal_tim_ex.h" 1957 1958 /* Exported functions --------------------------------------------------------*/ 1959 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 1960 * @{ 1961 */ 1962 1963 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 1964 * @brief Time Base functions 1965 * @{ 1966 */ 1967 /* Time Base functions ********************************************************/ 1968 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 1969 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 1970 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 1971 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 1972 /* Blocking mode: Polling */ 1973 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 1974 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 1975 /* Non-Blocking mode: Interrupt */ 1976 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 1977 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 1978 /* Non-Blocking mode: DMA */ 1979 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 1980 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 1981 /** 1982 * @} 1983 */ 1984 1985 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 1986 * @brief TIM Output Compare functions 1987 * @{ 1988 */ 1989 /* Timer Output Compare functions *********************************************/ 1990 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 1991 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 1992 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 1993 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 1994 /* Blocking mode: Polling */ 1995 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 1996 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 1997 /* Non-Blocking mode: Interrupt */ 1998 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 1999 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2000 /* Non-Blocking mode: DMA */ 2001 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2002 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2003 /** 2004 * @} 2005 */ 2006 2007 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2008 * @brief TIM PWM functions 2009 * @{ 2010 */ 2011 /* Timer PWM functions ********************************************************/ 2012 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2013 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2014 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2015 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2016 /* Blocking mode: Polling */ 2017 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2018 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2019 /* Non-Blocking mode: Interrupt */ 2020 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2021 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2022 /* Non-Blocking mode: DMA */ 2023 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2024 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2025 /** 2026 * @} 2027 */ 2028 2029 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2030 * @brief TIM Input Capture functions 2031 * @{ 2032 */ 2033 /* Timer Input Capture functions **********************************************/ 2034 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2035 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2036 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2037 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2038 /* Blocking mode: Polling */ 2039 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2040 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2041 /* Non-Blocking mode: Interrupt */ 2042 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2043 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2044 /* Non-Blocking mode: DMA */ 2045 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2046 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2047 /** 2048 * @} 2049 */ 2050 2051 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2052 * @brief TIM One Pulse functions 2053 * @{ 2054 */ 2055 /* Timer One Pulse functions **************************************************/ 2056 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2057 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2058 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2059 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2060 /* Blocking mode: Polling */ 2061 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2062 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2063 /* Non-Blocking mode: Interrupt */ 2064 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2065 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2066 /** 2067 * @} 2068 */ 2069 2070 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2071 * @brief TIM Encoder functions 2072 * @{ 2073 */ 2074 /* Timer Encoder functions ****************************************************/ 2075 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2076 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2077 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2078 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2079 /* Blocking mode: Polling */ 2080 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2081 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2082 /* Non-Blocking mode: Interrupt */ 2083 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2084 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2085 /* Non-Blocking mode: DMA */ 2086 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2087 uint32_t *pData2, uint16_t Length); 2088 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2089 /** 2090 * @} 2091 */ 2092 2093 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2094 * @brief IRQ handler management 2095 * @{ 2096 */ 2097 /* Interrupt Handler functions ***********************************************/ 2098 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2099 /** 2100 * @} 2101 */ 2102 2103 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2104 * @brief Peripheral Control functions 2105 * @{ 2106 */ 2107 /* Control functions *********************************************************/ 2108 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2109 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2110 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2111 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2112 uint32_t OutputChannel, uint32_t InputChannel); 2113 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2114 uint32_t Channel); 2115 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2116 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2117 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2118 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2119 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2120 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2121 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2122 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2123 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2124 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2125 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2126 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2127 /** 2128 * @} 2129 */ 2130 2131 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2132 * @brief TIM Callbacks functions 2133 * @{ 2134 */ 2135 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2136 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2137 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2138 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2139 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2140 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2141 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2142 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2143 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2144 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2145 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2146 2147 /* Callbacks Register/UnRegister functions ***********************************/ 2148 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2149 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2150 pTIM_CallbackTypeDef pCallback); 2151 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2152 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2153 2154 /** 2155 * @} 2156 */ 2157 2158 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2159 * @brief Peripheral State functions 2160 * @{ 2161 */ 2162 /* Peripheral State functions ************************************************/ 2163 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2164 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2165 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2166 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2167 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2168 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2169 /** 2170 * @} 2171 */ 2172 2173 /** 2174 * @} 2175 */ 2176 /* End of exported functions -------------------------------------------------*/ 2177 2178 /* Private functions----------------------------------------------------------*/ 2179 /** @defgroup TIM_Private_Functions TIM Private Functions 2180 * @{ 2181 */ 2182 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2183 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2184 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2185 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2186 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2187 2188 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); 2189 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2190 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2191 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2192 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2193 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2194 2195 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2196 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2197 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2198 2199 /** 2200 * @} 2201 */ 2202 /* End of private functions --------------------------------------------------*/ 2203 2204 /** 2205 * @} 2206 */ 2207 2208 /** 2209 * @} 2210 */ 2211 2212 #ifdef __cplusplus 2213 } 2214 #endif 2215 2216 #endif /* STM32MP1xx_HAL_TIM_H */ 2217
