1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32MP1xx_HAL_CORTEX_H 21 #define __STM32MP1xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup CORTEX 35 * @{ 36 */ 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup CORTEX_Exported_Types Cortex Exported Types 39 * @{ 40 */ 41 42 #if (__MPU_PRESENT == 1) 43 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 44 * @brief MPU Region initialization structure 45 * @{ 46 */ 47 typedef struct 48 { 49 uint8_t Enable; /*!< Specifies the status of the region. 50 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 51 uint8_t Number; /*!< Specifies the number of the region to protect. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 53 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 54 uint8_t Size; /*!< Specifies the size of the region to protect. 55 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 56 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 57 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 58 uint8_t TypeExtField; /*!< Specifies the TEX field level. 59 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 60 uint8_t AccessPermission; /*!< Specifies the region access permission type. 61 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 62 uint8_t DisableExec; /*!< Specifies the instruction access status. 63 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 64 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 65 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 66 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 67 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 68 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 70 } MPU_Region_InitTypeDef; 71 /** 72 * @} 73 */ 74 #endif /* __MPU_PRESENT */ 75 76 /** 77 * @} 78 */ 79 80 /* Exported constants --------------------------------------------------------*/ 81 82 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 83 * @{ 84 */ 85 86 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 87 * @{ 88 */ 89 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority 90 4 bits for subpriority */ 91 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority 92 3 bits for subpriority */ 93 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority 94 2 bits for subpriority */ 95 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority 96 1 bits for subpriority */ 97 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority 98 0 bits for subpriority */ 99 /** 100 * @} 101 */ 102 103 #if (__MPU_PRESENT == 1) 104 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 105 * @{ 106 */ 107 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) 108 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) 109 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) 110 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) 111 /** 112 * @} 113 */ 114 115 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 116 * @{ 117 */ 118 #define MPU_REGION_ENABLE ((uint8_t)0x01) 119 #define MPU_REGION_DISABLE ((uint8_t)0x00) 120 /** 121 * @} 122 */ 123 124 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 125 * @{ 126 */ 127 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 128 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 129 /** 130 * @} 131 */ 132 133 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 134 * @{ 135 */ 136 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 137 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 138 /** 139 * @} 140 */ 141 142 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 143 * @{ 144 */ 145 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 146 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 147 /** 148 * @} 149 */ 150 151 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 152 * @{ 153 */ 154 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 155 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 156 /** 157 * @} 158 */ 159 160 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 161 * @{ 162 */ 163 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 164 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 165 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 166 /** 167 * @} 168 */ 169 170 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 171 * @{ 172 */ 173 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 174 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 175 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 176 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 177 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 178 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 179 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 180 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 181 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 182 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 183 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 184 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 185 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 186 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 187 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 188 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 189 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 190 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 191 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 192 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 193 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 194 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 195 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 196 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 197 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 198 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 199 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 200 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 201 /** 202 * @} 203 */ 204 205 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 206 * @{ 207 */ 208 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 209 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 210 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 211 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 212 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 213 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 214 /** 215 * @} 216 */ 217 218 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 219 * @{ 220 */ 221 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 222 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 223 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 224 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 225 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 226 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 227 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 228 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 229 /** 230 * @} 231 */ 232 #endif /* __MPU_PRESENT */ 233 234 /** 235 * @} 236 */ 237 238 239 /* Exported Macros -----------------------------------------------------------*/ 240 241 /* Exported functions --------------------------------------------------------*/ 242 /** @addtogroup CORTEX_Exported_Functions 243 * @{ 244 */ 245 246 /** @addtogroup CORTEX_Exported_Functions_Group1 247 * @{ 248 */ 249 /* Initialization and de-initialization functions *****************************/ 250 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 251 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 252 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 253 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 254 void HAL_NVIC_SystemReset(void); 255 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 256 /** 257 * @} 258 */ 259 260 /** @addtogroup CORTEX_Exported_Functions_Group2 261 * @{ 262 */ 263 /* Peripheral Control functions ***********************************************/ 264 #if (__MPU_PRESENT == 1) 265 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 266 #endif /* __MPU_PRESENT */ 267 uint32_t HAL_NVIC_GetPriorityGrouping(void); 268 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); 269 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 270 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 271 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 272 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 273 void HAL_SYSTICK_IRQHandler(void); 274 void HAL_SYSTICK_Callback(void); 275 276 277 278 /** 279 * @} 280 */ 281 282 /** 283 * @} 284 */ 285 286 /* Private types -------------------------------------------------------------*/ 287 /* Private variables ---------------------------------------------------------*/ 288 /* Private constants ---------------------------------------------------------*/ 289 /* Private macros ------------------------------------------------------------*/ 290 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 291 * @{ 292 */ 293 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 294 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 295 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 296 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 297 ((GROUP) == NVIC_PRIORITYGROUP_4)) 298 299 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 300 301 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 302 303 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 304 305 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 306 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 307 308 #if (__MPU_PRESENT == 1) 309 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 310 ((STATE) == MPU_REGION_DISABLE)) 311 312 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 313 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 314 315 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 316 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 317 318 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 319 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 320 321 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 322 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 323 324 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 325 ((TYPE) == MPU_TEX_LEVEL1) || \ 326 ((TYPE) == MPU_TEX_LEVEL2)) 327 328 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 329 ((TYPE) == MPU_REGION_PRIV_RW) || \ 330 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 331 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 332 ((TYPE) == MPU_REGION_PRIV_RO) || \ 333 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 334 335 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 336 ((NUMBER) == MPU_REGION_NUMBER1) || \ 337 ((NUMBER) == MPU_REGION_NUMBER2) || \ 338 ((NUMBER) == MPU_REGION_NUMBER3) || \ 339 ((NUMBER) == MPU_REGION_NUMBER4) || \ 340 ((NUMBER) == MPU_REGION_NUMBER5) || \ 341 ((NUMBER) == MPU_REGION_NUMBER6) || \ 342 ((NUMBER) == MPU_REGION_NUMBER7)) 343 344 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 345 ((SIZE) == MPU_REGION_SIZE_64B) || \ 346 ((SIZE) == MPU_REGION_SIZE_128B) || \ 347 ((SIZE) == MPU_REGION_SIZE_256B) || \ 348 ((SIZE) == MPU_REGION_SIZE_512B) || \ 349 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 350 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 351 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 352 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 353 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 354 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 355 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 356 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 357 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 358 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 359 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 360 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 361 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 362 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 363 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 364 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 365 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 366 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 367 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 368 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 369 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 370 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 371 ((SIZE) == MPU_REGION_SIZE_4GB)) 372 373 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 374 #endif /* __MPU_PRESENT */ 375 376 /** 377 * @} 378 */ 379 380 /* Private functions ---------------------------------------------------------*/ 381 /** @defgroup CORTEX_Private_Functions CORTEX Private Functions 382 * @brief CORTEX private functions 383 * @{ 384 */ 385 386 #if (__MPU_PRESENT == 1) 387 /** 388 * @brief Disables the MPU 389 * @retval None 390 */ HAL_MPU_Disable(void)391__STATIC_INLINE void HAL_MPU_Disable(void) 392 { 393 /* Disable fault exceptions */ 394 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 395 396 /* Disable the MPU */ 397 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 398 } 399 400 /** 401 * @brief Enables the MPU 402 * @param MPU_Control: Specifies the control mode of the MPU during hard fault, 403 * NMI, FAULTMASK and privileged access to the default memory 404 * This parameter can be one of the following values: 405 * @arg MPU_HFNMI_PRIVDEF_NONE 406 * @arg MPU_HARDFAULT_NMI 407 * @arg MPU_PRIVILEGED_DEFAULT 408 * @arg MPU_HFNMI_PRIVDEF 409 * @retval None 410 */ HAL_MPU_Enable(uint32_t MPU_Control)411__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) 412 { 413 /* Enable the MPU */ 414 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 415 416 /* Enable fault exceptions */ 417 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 418 } 419 #endif /* __MPU_PRESENT */ 420 421 /** 422 * @} 423 */ 424 425 /** 426 * @} 427 */ 428 429 /** 430 * @} 431 */ 432 433 #ifdef __cplusplus 434 } 435 #endif 436 437 #endif /* __STM32MP1xx_HAL_CORTEX_H */ 438
