1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #if defined(STM32U5) 46 #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF 47 #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF 48 #endif /* STM32U5 */ 49 #endif /* STM32U5 || STM32H7 || STM32MP1 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 55 * @{ 56 */ 57 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 58 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 59 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 60 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 61 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 62 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 63 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 64 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 65 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 66 #define REGULAR_GROUP ADC_REGULAR_GROUP 67 #define INJECTED_GROUP ADC_INJECTED_GROUP 68 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 69 #define AWD_EVENT ADC_AWD_EVENT 70 #define AWD1_EVENT ADC_AWD1_EVENT 71 #define AWD2_EVENT ADC_AWD2_EVENT 72 #define AWD3_EVENT ADC_AWD3_EVENT 73 #define OVR_EVENT ADC_OVR_EVENT 74 #define JQOVF_EVENT ADC_JQOVF_EVENT 75 #define ALL_CHANNELS ADC_ALL_CHANNELS 76 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 77 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 78 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 79 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 80 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 81 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 82 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 83 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 84 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 85 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 86 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 87 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 88 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 89 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 90 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 91 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 92 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 93 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 94 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 95 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 96 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 97 98 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 99 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 100 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 101 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 102 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 103 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 104 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 105 106 #if defined(STM32H7) 107 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 108 #endif /* STM32H7 */ 109 110 #if defined(STM32U5) 111 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 112 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 113 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 114 #endif /* STM32U5 */ 115 /** 116 * @} 117 */ 118 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 120 * @{ 121 */ 122 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 130 * @{ 131 */ 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 141 #if defined(STM32L0) 142 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 143 #endif 144 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 145 #if defined(STM32F373xC) || defined(STM32F378xx) 146 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 147 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 148 #endif /* STM32F373xC || STM32F378xx */ 149 150 #if defined(STM32L0) || defined(STM32L4) 151 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 152 153 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 154 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 155 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 156 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 157 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 158 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 159 160 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 161 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 162 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 163 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 164 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 165 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 166 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 167 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 168 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 169 #if defined(STM32L0) 170 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 171 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 172 /* to the second dedicated IO (only for COMP2). */ 173 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 174 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 175 #else 176 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 177 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 178 #endif 179 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 180 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 181 182 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 183 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 184 185 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 186 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 187 #if defined(COMP_CSR_LOCK) 188 #define COMP_FLAG_LOCK COMP_CSR_LOCK 189 #elif defined(COMP_CSR_COMP1LOCK) 190 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 191 #elif defined(COMP_CSR_COMPxLOCK) 192 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 193 #endif 194 195 #if defined(STM32L4) 196 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 197 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 198 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 199 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 200 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 201 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 202 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 203 #endif 204 205 #if defined(STM32L0) 206 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 207 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 208 #else 209 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 210 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 211 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 212 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 213 #endif 214 215 #endif 216 /** 217 * @} 218 */ 219 220 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 221 * @{ 222 */ 223 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 224 #if defined(STM32U5) 225 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 226 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 227 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 228 #endif /* STM32U5 */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup CRC_Aliases CRC API aliases 234 * @{ 235 */ 236 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ 237 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ 238 239 /** 240 * @} 241 */ 242 243 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 244 * @{ 245 */ 246 247 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 248 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 249 250 /** 251 * @} 252 */ 253 254 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 255 * @{ 256 */ 257 258 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 259 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 260 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 261 #define DAC_WAVE_NONE 0x00000000U 262 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 263 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 264 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 265 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 266 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 267 268 #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) 269 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 270 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 271 #endif 272 273 #if defined(STM32U5) 274 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 275 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 276 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 277 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 278 #endif 279 280 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 281 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 282 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 283 #endif 284 285 /** 286 * @} 287 */ 288 289 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 290 * @{ 291 */ 292 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 293 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 294 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 295 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 296 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 297 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 298 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 299 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 300 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 301 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 302 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 303 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 304 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 305 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 306 307 #define IS_HAL_REMAPDMA IS_DMA_REMAP 308 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 309 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 310 311 #if defined(STM32L4) 312 313 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 314 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 315 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 316 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 317 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 318 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 319 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 320 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 321 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 322 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 323 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 324 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 325 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 326 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 327 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 328 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 329 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 330 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 331 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 332 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 333 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 334 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 335 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 336 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 337 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 338 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 339 340 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 341 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 342 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 343 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 344 345 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 346 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 347 #endif 348 349 #endif /* STM32L4 */ 350 351 #if defined(STM32G0) 352 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 353 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 354 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 355 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 356 357 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 358 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 359 #endif 360 361 #if defined(STM32H7) 362 363 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 364 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 365 366 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 367 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 368 369 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 370 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 371 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 372 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 373 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 374 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 375 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 376 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 377 378 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 379 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 380 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 381 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 382 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 383 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 384 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 385 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 386 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 387 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 388 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 389 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 390 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 391 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 392 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 393 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 394 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 395 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 396 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 397 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 398 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 399 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 400 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 401 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 402 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 403 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 404 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 405 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 406 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 407 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 408 409 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 410 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 411 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 412 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 413 414 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 415 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 416 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 417 418 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 419 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 420 421 #endif /* STM32H7 */ 422 423 #if defined(STM32U5) 424 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 425 #endif /* STM32U5 */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 431 * @{ 432 */ 433 434 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 435 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 436 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 437 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 438 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 439 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 440 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 441 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 442 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 443 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 444 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 445 #define OBEX_PCROP OPTIONBYTE_PCROP 446 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 447 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 448 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 449 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 450 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 451 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 452 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 453 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 454 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 455 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 456 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 457 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 458 /* #define PAGESIZE FLASH_PAGE_SIZE */ 459 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 460 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 461 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 462 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 463 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 464 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 465 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 466 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 467 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 468 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 469 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 470 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 471 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 472 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 473 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 474 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 475 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 476 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 477 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 478 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 479 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 480 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 481 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 482 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 483 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 484 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 485 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 486 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 487 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 488 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 489 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 490 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 491 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 492 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 493 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 494 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 495 #define OB_WDG_SW OB_IWDG_SW 496 #define OB_WDG_HW OB_IWDG_HW 497 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 498 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 499 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 500 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 501 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 502 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 503 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 504 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 505 #if defined(STM32G0) 506 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 507 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 508 #else 509 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 510 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 511 #endif 512 #if defined(STM32H7) 513 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 514 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 515 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 516 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 517 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 518 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 519 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 520 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 521 #endif /* STM32H7 */ 522 #if defined(STM32U5) 523 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 524 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 525 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 526 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 527 #define OB_USER_nBOOT0 OB_USER_NBOOT0 528 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 529 #define OB_nBOOT0_SET OB_NBOOT0_SET 530 #endif /* STM32U5 */ 531 532 /** 533 * @} 534 */ 535 536 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 537 * @{ 538 */ 539 540 #if defined(STM32H7) 541 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 542 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 543 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 544 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 545 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 546 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 547 #endif /* STM32H7 */ 548 549 /** 550 * @} 551 */ 552 553 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 554 * @{ 555 */ 556 557 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 558 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 559 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 560 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 561 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 562 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 563 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 564 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 565 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 566 #if defined(STM32G4) 567 568 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 569 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 570 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 571 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 572 #endif /* STM32G4 */ 573 574 /** 575 * @} 576 */ 577 578 579 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 580 * @{ 581 */ 582 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 583 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 584 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 585 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 586 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 587 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 588 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 589 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 590 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 591 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 592 #endif 593 /** 594 * @} 595 */ 596 597 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 598 * @{ 599 */ 600 601 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 602 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 603 /** 604 * @} 605 */ 606 607 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 608 * @{ 609 */ 610 #define GET_GPIO_SOURCE GPIO_GET_INDEX 611 #define GET_GPIO_INDEX GPIO_GET_INDEX 612 613 #if defined(STM32F4) 614 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 615 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 616 #endif 617 618 #if defined(STM32F7) 619 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 620 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 621 #endif 622 623 #if defined(STM32L4) 624 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 625 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 626 #endif 627 628 #if defined(STM32H7) 629 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 630 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 631 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 632 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 633 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 634 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 635 636 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 637 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 638 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 639 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 640 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 641 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 642 #endif /* STM32H7 */ 643 644 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 645 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 646 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 647 648 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 649 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 650 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 651 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 652 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 653 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 654 655 #if defined(STM32L1) 656 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 657 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 658 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 659 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 660 #endif /* STM32L1 */ 661 662 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 663 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 664 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 665 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 666 #endif /* STM32F0 || STM32F3 || STM32F1 */ 667 668 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 669 670 #if defined(STM32U5) 671 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 672 #endif /* STM32U5 */ 673 #if defined(STM32U5) 674 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 675 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 676 #endif /* STM32U5 */ 677 /** 678 * @} 679 */ 680 681 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 682 * @{ 683 */ 684 #if defined(STM32U5) 685 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 686 #endif /* STM32U5 */ 687 /** 688 * @} 689 */ 690 691 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 692 * @{ 693 */ 694 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 695 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 696 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 697 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 698 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 699 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 700 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 701 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 702 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 703 704 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 705 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 706 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 707 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 708 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 709 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 710 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 711 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 712 713 #if defined(STM32G4) 714 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 715 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 716 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 717 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 718 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 719 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 720 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 721 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 722 #endif /* STM32G4 */ 723 724 #if defined(STM32H7) 725 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 726 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 727 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 728 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 729 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 730 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 731 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 732 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 733 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 734 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 735 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 736 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 737 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 738 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 739 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 740 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 741 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 742 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 743 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 744 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 745 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 746 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 747 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 748 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 749 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 750 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 751 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 752 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 753 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 754 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 755 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 756 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 757 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 758 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 759 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 760 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 761 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 762 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 763 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 764 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 765 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 766 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 767 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 768 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 769 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 770 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 771 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 772 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 773 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 774 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 775 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 776 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 777 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 778 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 779 780 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 781 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 782 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 783 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 784 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 785 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 786 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 787 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 788 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 789 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 790 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 791 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 792 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 793 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 794 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 795 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 796 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 797 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 798 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 799 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 800 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 801 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 802 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 803 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 804 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 805 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 806 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 807 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 808 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 809 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 810 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 811 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 812 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 813 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 814 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 815 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 816 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 817 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 818 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 819 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 820 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 821 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 822 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 823 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 824 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 825 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 826 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 827 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 828 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 829 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 830 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 831 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 832 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 833 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 834 #endif /* STM32H7 */ 835 836 #if defined(STM32F3) 837 /** @brief Constants defining available sources associated to external events. 838 */ 839 #define HRTIM_EVENTSRC_1 (0x00000000U) 840 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 841 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 842 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 843 844 /** @brief Constants defining the DLL calibration periods (in micro seconds) 845 */ 846 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 847 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 848 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 849 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 850 851 #endif /* STM32F3 */ 852 /** 853 * @} 854 */ 855 856 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 857 * @{ 858 */ 859 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 860 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 861 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 862 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 863 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 864 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 865 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 866 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 867 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 868 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 869 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 870 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 871 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 872 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 873 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 874 #endif 875 /** 876 * @} 877 */ 878 879 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 880 * @{ 881 */ 882 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 883 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 884 885 /** 886 * @} 887 */ 888 889 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 890 * @{ 891 */ 892 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 893 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 894 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 895 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 896 /** 897 * @} 898 */ 899 900 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 901 * @{ 902 */ 903 904 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 905 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 906 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 907 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 908 909 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 910 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 911 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 912 913 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 914 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 915 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 916 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 917 918 /* The following 3 definition have also been present in a temporary version of lptim.h */ 919 /* They need to be renamed also to the right name, just in case */ 920 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 921 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 922 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 923 924 925 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 926 * @{ 927 */ 928 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 929 /** 930 * @} 931 */ 932 933 #if defined(STM32U5) 934 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 935 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 936 #define LPTIM_CHANNEL_ALL 0x00000000U 937 #endif /* STM32U5 */ 938 /** 939 * @} 940 */ 941 942 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 943 * @{ 944 */ 945 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 946 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 947 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 948 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 949 950 #define NAND_AddressTypedef NAND_AddressTypeDef 951 952 #define __ARRAY_ADDRESS ARRAY_ADDRESS 953 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 954 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 955 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 956 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 957 /** 958 * @} 959 */ 960 961 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 962 * @{ 963 */ 964 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 965 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 966 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 967 #define NOR_ERROR HAL_NOR_STATUS_ERROR 968 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 969 970 #define __NOR_WRITE NOR_WRITE 971 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 972 /** 973 * @} 974 */ 975 976 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 977 * @{ 978 */ 979 980 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 981 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 982 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 983 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 984 985 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 986 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 987 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 988 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 989 990 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 991 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 992 993 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 994 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 995 996 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 997 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 998 999 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1000 1001 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1002 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1003 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1004 1005 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) 1006 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1007 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1008 #endif 1009 1010 #if defined(STM32L4) || defined(STM32L5) 1011 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1012 #elif defined(STM32G4) 1013 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1014 #endif 1015 1016 /** 1017 * @} 1018 */ 1019 1020 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1021 * @{ 1022 */ 1023 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1024 1025 #if defined(STM32H7) 1026 #define I2S_IT_TXE I2S_IT_TXP 1027 #define I2S_IT_RXNE I2S_IT_RXP 1028 1029 #define I2S_FLAG_TXE I2S_FLAG_TXP 1030 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1031 #endif 1032 1033 #if defined(STM32F7) 1034 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1035 #endif 1036 /** 1037 * @} 1038 */ 1039 1040 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1041 * @{ 1042 */ 1043 1044 /* Compact Flash-ATA registers description */ 1045 #define CF_DATA ATA_DATA 1046 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1047 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1048 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1049 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1050 #define CF_CARD_HEAD ATA_CARD_HEAD 1051 #define CF_STATUS_CMD ATA_STATUS_CMD 1052 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1053 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1054 1055 /* Compact Flash-ATA commands */ 1056 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1057 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1058 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1059 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1060 1061 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1062 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1063 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1064 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1065 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1066 /** 1067 * @} 1068 */ 1069 1070 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1071 * @{ 1072 */ 1073 1074 #define FORMAT_BIN RTC_FORMAT_BIN 1075 #define FORMAT_BCD RTC_FORMAT_BCD 1076 1077 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1078 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1079 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1080 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1081 1082 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1083 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1084 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1085 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1086 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1087 1088 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1089 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1090 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1091 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1092 1093 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1094 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1095 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1096 1097 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1098 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1099 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1100 1101 #if defined(STM32F7) 1102 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1103 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1104 #endif /* STM32F7 */ 1105 1106 #if defined(STM32H7) 1107 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1108 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1109 #endif /* STM32H7 */ 1110 1111 #if defined(STM32F7) || defined(STM32H7) 1112 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1113 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1114 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1115 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1116 #endif /* STM32F7 || STM32H7 */ 1117 1118 /** 1119 * @} 1120 */ 1121 1122 1123 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1124 * @{ 1125 */ 1126 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1127 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1128 1129 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1130 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1131 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1132 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1133 1134 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1135 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1136 1137 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1138 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1139 /** 1140 * @} 1141 */ 1142 1143 1144 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1145 * @{ 1146 */ 1147 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1148 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1149 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1150 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1151 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1152 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1153 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1154 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1155 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1156 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1157 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1158 /** 1159 * @} 1160 */ 1161 1162 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1163 * @{ 1164 */ 1165 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1166 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1167 1168 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1169 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1170 1171 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1172 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1173 1174 #if defined(STM32H7) 1175 1176 #define SPI_FLAG_TXE SPI_FLAG_TXP 1177 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1178 1179 #define SPI_IT_TXE SPI_IT_TXP 1180 #define SPI_IT_RXNE SPI_IT_RXP 1181 1182 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1183 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1184 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1185 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1186 1187 #endif /* STM32H7 */ 1188 1189 /** 1190 * @} 1191 */ 1192 1193 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1194 * @{ 1195 */ 1196 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1197 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1198 1199 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1200 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1201 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1202 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1203 #define TIM_DMABase_SR TIM_DMABASE_SR 1204 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1205 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1206 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1207 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1208 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1209 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1210 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1211 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1212 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1213 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1214 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1215 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1216 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1217 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1218 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1219 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1220 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1221 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1222 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1223 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1224 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1225 #define TIM_DMABase_OR TIM_DMABASE_OR 1226 1227 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1228 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1229 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1230 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1231 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1232 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1233 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1234 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1235 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1236 1237 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1238 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1239 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1240 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1241 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1242 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1243 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1244 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1245 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1246 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1247 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1248 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1249 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1250 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1251 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1252 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1253 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1254 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1255 1256 #if defined(STM32L0) 1257 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1258 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1259 #endif 1260 1261 #if defined(STM32F3) 1262 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1263 #endif 1264 1265 #if defined(STM32H7) 1266 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1267 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1268 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1269 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1270 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1271 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1272 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1273 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1274 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1275 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1276 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1277 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1278 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1279 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1280 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1281 #endif 1282 1283 #if defined(STM32U5) || defined(STM32MP2) 1284 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1285 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1286 #endif 1287 /** 1288 * @} 1289 */ 1290 1291 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1292 * @{ 1293 */ 1294 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1295 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1296 /** 1297 * @} 1298 */ 1299 1300 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1301 * @{ 1302 */ 1303 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1304 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1305 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1306 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1307 1308 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1309 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1310 1311 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1312 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1313 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1314 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1315 1316 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1317 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1318 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1319 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1320 1321 #define __DIV_LPUART UART_DIV_LPUART 1322 1323 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1324 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1325 1326 /** 1327 * @} 1328 */ 1329 1330 1331 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1332 * @{ 1333 */ 1334 1335 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1336 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1337 1338 #define USARTNACK_ENABLED USART_NACK_ENABLE 1339 #define USARTNACK_DISABLED USART_NACK_DISABLE 1340 /** 1341 * @} 1342 */ 1343 1344 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1345 * @{ 1346 */ 1347 #define CFR_BASE WWDG_CFR_BASE 1348 1349 /** 1350 * @} 1351 */ 1352 1353 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1354 * @{ 1355 */ 1356 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1357 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1358 #define CAN_IT_RQCP0 CAN_IT_TME 1359 #define CAN_IT_RQCP1 CAN_IT_TME 1360 #define CAN_IT_RQCP2 CAN_IT_TME 1361 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1362 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1363 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1364 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1365 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1366 1367 /** 1368 * @} 1369 */ 1370 1371 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1372 * @{ 1373 */ 1374 1375 #define VLAN_TAG ETH_VLAN_TAG 1376 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1377 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1378 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1379 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1380 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1381 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1382 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1383 1384 #define ETH_MMCCR 0x00000100U 1385 #define ETH_MMCRIR 0x00000104U 1386 #define ETH_MMCTIR 0x00000108U 1387 #define ETH_MMCRIMR 0x0000010CU 1388 #define ETH_MMCTIMR 0x00000110U 1389 #define ETH_MMCTGFSCCR 0x0000014CU 1390 #define ETH_MMCTGFMSCCR 0x00000150U 1391 #define ETH_MMCTGFCR 0x00000168U 1392 #define ETH_MMCRFCECR 0x00000194U 1393 #define ETH_MMCRFAECR 0x00000198U 1394 #define ETH_MMCRGUFCR 0x000001C4U 1395 1396 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1397 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1398 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1399 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1400 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1401 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1402 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1403 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1404 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1405 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1406 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1407 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1408 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1409 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1410 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1411 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1412 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1413 #if defined(STM32F1) 1414 #else 1415 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1416 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1417 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1418 #endif 1419 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1420 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1421 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1422 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1423 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1424 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1425 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1426 1427 /** 1428 * @} 1429 */ 1430 1431 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1432 * @{ 1433 */ 1434 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1435 #define DCMI_IT_OVF DCMI_IT_OVR 1436 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1437 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1438 1439 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1440 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1441 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1442 1443 /** 1444 * @} 1445 */ 1446 1447 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1448 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1449 || defined(STM32H7) 1450 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1451 * @{ 1452 */ 1453 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1454 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1455 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1456 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1457 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1458 1459 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1460 #define CM_RGB888 DMA2D_INPUT_RGB888 1461 #define CM_RGB565 DMA2D_INPUT_RGB565 1462 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1463 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1464 #define CM_L8 DMA2D_INPUT_L8 1465 #define CM_AL44 DMA2D_INPUT_AL44 1466 #define CM_AL88 DMA2D_INPUT_AL88 1467 #define CM_L4 DMA2D_INPUT_L4 1468 #define CM_A8 DMA2D_INPUT_A8 1469 #define CM_A4 DMA2D_INPUT_A4 1470 /** 1471 * @} 1472 */ 1473 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1474 1475 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1476 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1477 || defined(STM32H7) || defined(STM32U5) 1478 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1479 * @{ 1480 */ 1481 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1482 for compatibility with legacy code */ 1483 /** 1484 * @} 1485 */ 1486 1487 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1488 1489 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1490 * @{ 1491 */ 1492 1493 /** 1494 * @} 1495 */ 1496 1497 /* Exported functions --------------------------------------------------------*/ 1498 1499 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1500 * @{ 1501 */ 1502 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1503 /** 1504 * @} 1505 */ 1506 1507 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1508 * @{ 1509 */ 1510 1511 #if defined(STM32U5) 1512 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1513 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1514 #endif /* STM32U5 */ 1515 1516 /** 1517 * @} 1518 */ 1519 1520 #if !defined(STM32F2) 1521 /** @defgroup HASH_alias HASH API alias 1522 * @{ 1523 */ 1524 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1525 /** 1526 * 1527 * @} 1528 */ 1529 #endif /* STM32F2 */ 1530 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1531 * @{ 1532 */ 1533 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1534 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1535 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1536 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1537 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1538 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1539 1540 /*HASH Algorithm Selection*/ 1541 1542 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1543 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1544 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1545 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1546 1547 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1548 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1549 1550 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1551 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1552 1553 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1554 1555 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1556 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1557 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1558 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1559 1560 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1561 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1562 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1563 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1564 1565 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1566 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1567 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1568 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1569 1570 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1571 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1572 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1573 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1574 1575 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1576 /** 1577 * @} 1578 */ 1579 1580 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1581 * @{ 1582 */ 1583 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1584 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1585 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1586 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1587 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1588 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1589 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1590 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1591 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1592 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1593 #if defined(STM32L0) 1594 #else 1595 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1596 #endif 1597 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1598 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1599 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1600 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1601 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1602 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1603 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1604 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1605 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1606 1607 /** 1608 * @} 1609 */ 1610 1611 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1612 * @{ 1613 */ 1614 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1615 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1616 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1617 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1618 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1619 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1620 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1621 1622 /** 1623 * @} 1624 */ 1625 1626 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1627 * @{ 1628 */ 1629 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1630 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1631 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1632 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1633 1634 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1635 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1636 1637 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1638 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1639 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1640 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1641 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1642 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1643 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1644 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1645 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1646 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1647 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1648 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1649 1650 #if defined(STM32F4) 1651 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1652 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1653 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1654 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1655 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1656 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1657 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1658 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1659 #endif /* STM32F4 */ 1660 /** 1661 * @} 1662 */ 1663 1664 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1665 * @{ 1666 */ 1667 1668 #if defined(STM32G0) 1669 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1670 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1671 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1672 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1673 #endif 1674 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1675 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1676 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1677 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1678 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1679 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1680 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1681 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1682 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1683 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1684 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1685 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1686 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1687 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1688 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1689 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1690 1691 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1692 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1693 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1694 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1695 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1696 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1697 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1698 1699 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1700 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1701 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1702 #define CR_PMODE_BB CR_VOS_BB 1703 1704 #define DBP_BitNumber DBP_BIT_NUMBER 1705 #define PVDE_BitNumber PVDE_BIT_NUMBER 1706 #define PMODE_BitNumber PMODE_BIT_NUMBER 1707 #define EWUP_BitNumber EWUP_BIT_NUMBER 1708 #define FPDS_BitNumber FPDS_BIT_NUMBER 1709 #define ODEN_BitNumber ODEN_BIT_NUMBER 1710 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1711 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1712 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1713 #define BRE_BitNumber BRE_BIT_NUMBER 1714 1715 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1716 1717 #if defined (STM32U5) 1718 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1719 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1720 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1721 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1722 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1723 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1724 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1725 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1726 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1727 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1728 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1729 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1730 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1731 1732 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1733 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1734 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1735 1736 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1737 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1738 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1739 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1740 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1741 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1742 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1743 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1744 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1745 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1746 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1747 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1748 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1749 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1750 1751 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1752 1753 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1754 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1755 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1756 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1757 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1758 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1759 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1760 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1761 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1762 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1763 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1764 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1765 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1766 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1767 1768 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 1769 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 1770 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 1771 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 1772 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 1773 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 1774 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 1775 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 1776 1777 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 1778 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 1779 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 1780 1781 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 1782 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 1783 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 1784 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 1785 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 1786 1787 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 1788 #endif 1789 1790 /** 1791 * @} 1792 */ 1793 1794 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1795 * @{ 1796 */ 1797 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1798 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1799 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1800 /** 1801 * @} 1802 */ 1803 1804 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1805 * @{ 1806 */ 1807 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1808 /** 1809 * @} 1810 */ 1811 1812 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1813 * @{ 1814 */ 1815 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1816 #define HAL_TIM_DMAError TIM_DMAError 1817 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1818 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1819 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1820 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1821 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1822 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1823 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1824 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1825 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1826 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1827 /** 1828 * @} 1829 */ 1830 1831 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1832 * @{ 1833 */ 1834 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1835 /** 1836 * @} 1837 */ 1838 1839 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1840 * @{ 1841 */ 1842 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1843 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1844 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1845 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1846 /** 1847 * @} 1848 */ 1849 1850 1851 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1852 * @{ 1853 */ 1854 1855 /** 1856 * @} 1857 */ 1858 1859 /* Exported macros ------------------------------------------------------------*/ 1860 1861 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1862 * @{ 1863 */ 1864 #define AES_IT_CC CRYP_IT_CC 1865 #define AES_IT_ERR CRYP_IT_ERR 1866 #define AES_FLAG_CCF CRYP_FLAG_CCF 1867 /** 1868 * @} 1869 */ 1870 1871 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1872 * @{ 1873 */ 1874 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1875 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1876 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1877 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1878 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1879 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1880 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1881 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1882 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1883 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1884 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1885 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1886 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1887 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1888 1889 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1890 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1891 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1892 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1893 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1894 1895 /** 1896 * @} 1897 */ 1898 1899 1900 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1901 * @{ 1902 */ 1903 #define __ADC_ENABLE __HAL_ADC_ENABLE 1904 #define __ADC_DISABLE __HAL_ADC_DISABLE 1905 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1906 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1907 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1908 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1909 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1910 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1911 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1912 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1913 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1914 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1915 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1916 1917 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1918 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1919 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1920 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1921 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1922 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1923 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1924 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1925 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1926 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1927 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1928 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1929 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1930 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1931 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1932 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1933 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1934 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1935 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1936 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1937 1938 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1939 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1940 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1941 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1942 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1943 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1944 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1945 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1946 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1947 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1948 1949 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1950 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1951 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1952 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1953 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1954 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1955 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1956 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1957 1958 #define __HAL_ADC_SQR1 ADC_SQR1 1959 #define __HAL_ADC_SMPR1 ADC_SMPR1 1960 #define __HAL_ADC_SMPR2 ADC_SMPR2 1961 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1962 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1963 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1964 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1965 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1966 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1967 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1968 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1969 #define __HAL_ADC_JSQR ADC_JSQR 1970 1971 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1972 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1973 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1974 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1975 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1976 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1977 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1978 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1979 1980 /** 1981 * @} 1982 */ 1983 1984 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1985 * @{ 1986 */ 1987 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1988 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 1989 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 1990 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 1991 1992 /** 1993 * @} 1994 */ 1995 1996 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 1997 * @{ 1998 */ 1999 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2000 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2001 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2002 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2003 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2004 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2005 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2006 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2007 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2008 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2009 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2010 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2011 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2012 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2013 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2014 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2015 2016 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2017 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2018 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2019 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2020 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2021 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2022 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2023 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2024 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2025 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2026 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2027 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2028 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2029 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2030 2031 2032 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2033 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2034 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2035 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2036 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2037 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2038 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2039 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2040 #if defined(STM32H7) 2041 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2042 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2043 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2044 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2045 #else 2046 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2047 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2048 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2049 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2050 #endif /* STM32H7 */ 2051 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2052 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2053 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2054 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2055 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2056 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2057 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2058 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2059 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2060 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2061 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2062 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2063 2064 /** 2065 * @} 2066 */ 2067 2068 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2069 * @{ 2070 */ 2071 #if defined(STM32F3) 2072 #define COMP_START __HAL_COMP_ENABLE 2073 #define COMP_STOP __HAL_COMP_DISABLE 2074 #define COMP_LOCK __HAL_COMP_LOCK 2075 2076 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2077 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2078 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2079 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2080 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2081 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2082 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2083 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2084 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2085 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2086 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2087 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2088 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2089 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2090 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2091 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2092 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2093 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2094 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2095 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2096 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2097 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2098 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2099 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2100 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2101 # endif 2102 # if defined(STM32F302xE) || defined(STM32F302xC) 2103 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2104 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2105 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2106 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2107 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2108 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2109 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2110 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2111 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2112 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2113 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2114 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2115 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2116 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2117 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2118 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2119 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2120 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2121 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2122 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2123 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2124 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2125 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2126 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2127 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2128 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2129 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2130 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2131 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2132 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2133 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2134 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2135 # endif 2136 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2137 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2138 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2139 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2140 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2141 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2142 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2143 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2144 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2145 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2146 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2147 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2148 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2149 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2150 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2151 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2152 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2153 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2154 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2155 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2156 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2157 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2158 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2159 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2160 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2161 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2162 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2163 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2164 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2165 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2166 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2167 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2168 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2169 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2170 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2171 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2172 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2173 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2174 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2175 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2176 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2177 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2178 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2179 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2180 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2181 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2182 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2183 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2184 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2185 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2186 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2187 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2188 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2189 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2190 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2191 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2192 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2193 # endif 2194 # if defined(STM32F373xC) ||defined(STM32F378xx) 2195 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2196 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2197 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2198 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2199 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2200 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2201 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2202 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2203 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2204 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2205 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2206 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2207 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2208 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2209 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2210 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2211 # endif 2212 #else 2213 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2214 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2215 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2216 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2217 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2218 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2219 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2220 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2221 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2222 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2223 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2224 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2225 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2226 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2227 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2228 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2229 #endif 2230 2231 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2232 2233 #if defined(STM32L0) || defined(STM32L4) 2234 /* Note: On these STM32 families, the only argument of this macro */ 2235 /* is COMP_FLAG_LOCK. */ 2236 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2237 /* argument. */ 2238 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2239 #endif 2240 /** 2241 * @} 2242 */ 2243 2244 #if defined(STM32L0) || defined(STM32L4) 2245 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2246 * @{ 2247 */ 2248 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2249 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2250 /** 2251 * @} 2252 */ 2253 #endif 2254 2255 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2256 * @{ 2257 */ 2258 2259 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2260 ((WAVE) == DAC_WAVE_NOISE)|| \ 2261 ((WAVE) == DAC_WAVE_TRIANGLE)) 2262 2263 /** 2264 * @} 2265 */ 2266 2267 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2268 * @{ 2269 */ 2270 2271 #define IS_WRPAREA IS_OB_WRPAREA 2272 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2273 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2274 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2275 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2276 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2277 2278 /** 2279 * @} 2280 */ 2281 2282 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2283 * @{ 2284 */ 2285 2286 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2287 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2288 #if defined(STM32F1) 2289 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2290 #else 2291 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2292 #endif /* STM32F1 */ 2293 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2294 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2295 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2296 #define __HAL_I2C_SPEED I2C_SPEED 2297 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2298 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2299 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2300 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2301 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2302 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2303 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2304 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2305 /** 2306 * @} 2307 */ 2308 2309 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2310 * @{ 2311 */ 2312 2313 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2314 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2315 2316 #if defined(STM32H7) 2317 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2318 #endif 2319 2320 /** 2321 * @} 2322 */ 2323 2324 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2325 * @{ 2326 */ 2327 2328 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2329 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2330 2331 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2332 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2333 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2334 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2335 2336 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2337 2338 2339 /** 2340 * @} 2341 */ 2342 2343 2344 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2345 * @{ 2346 */ 2347 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2348 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2349 /** 2350 * @} 2351 */ 2352 2353 2354 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2355 * @{ 2356 */ 2357 2358 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2359 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2360 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2361 2362 /** 2363 * @} 2364 */ 2365 2366 2367 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2368 * @{ 2369 */ 2370 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2371 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2372 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2373 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2374 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2375 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2376 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2377 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2378 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2379 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2380 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2381 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2382 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2383 2384 /** 2385 * @} 2386 */ 2387 2388 2389 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2390 * @{ 2391 */ 2392 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2393 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2394 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2395 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2396 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2397 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2398 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2399 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2400 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2401 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2402 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2403 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2404 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2405 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2406 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2407 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2408 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2409 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2410 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2411 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2412 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2413 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2414 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2415 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2416 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2417 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2418 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2419 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2420 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2421 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2422 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2423 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2424 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2425 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2426 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2427 2428 #if defined (STM32F4) 2429 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2430 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2431 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2432 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2433 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2434 #else 2435 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2436 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2437 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2438 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2439 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2440 #endif /* STM32F4 */ 2441 /** 2442 * @} 2443 */ 2444 2445 2446 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2447 * @{ 2448 */ 2449 2450 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2451 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2452 2453 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2454 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2455 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2456 2457 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2458 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2459 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2460 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2461 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2462 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2463 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2464 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2465 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2466 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2467 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2468 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2469 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2470 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2471 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2472 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2473 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2474 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2475 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2476 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2477 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2478 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2479 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2480 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2481 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2482 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2483 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2484 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2485 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2486 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2487 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2488 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2489 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2490 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2491 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2492 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2493 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2494 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2495 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2496 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2497 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2498 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2499 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2500 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2501 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2502 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2503 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2504 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2505 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2506 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2507 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2508 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2509 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2510 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2511 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2512 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2513 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2514 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2515 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2516 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2517 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2518 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2519 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2520 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2521 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2522 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2523 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2524 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2525 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2526 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2527 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2528 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2529 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2530 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2531 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2532 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2533 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2534 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2535 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2536 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2537 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2538 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2539 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2540 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2541 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2542 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2543 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2544 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2545 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2546 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2547 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2548 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2549 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2550 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2551 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2552 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2553 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2554 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2555 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2556 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2557 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2558 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2559 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2560 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2561 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2562 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2563 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2564 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2565 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2566 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2567 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2568 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2569 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2570 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2571 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2572 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2573 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2574 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2575 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2576 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2577 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2578 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2579 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2580 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2581 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2582 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2583 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2584 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2585 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2586 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2587 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2588 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2589 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2590 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2591 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2592 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2593 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2594 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2595 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2596 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2597 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2598 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2599 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2600 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2601 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2602 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2603 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2604 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2605 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2606 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2607 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2608 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2609 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2610 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2611 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2612 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2613 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2614 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2615 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2616 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2617 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2618 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2619 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2620 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2621 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2622 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2623 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2624 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2625 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2626 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2627 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2628 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2629 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2630 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2631 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2632 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2633 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2634 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2635 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2636 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2637 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2638 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2639 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2640 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2641 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2642 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2643 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2644 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2645 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2646 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2647 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2648 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2649 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2650 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2651 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2652 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2653 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2654 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2655 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2656 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2657 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2658 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2659 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2660 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2661 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2662 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2663 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2664 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2665 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2666 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2667 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2668 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2669 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2670 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2671 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2672 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2673 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2674 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2675 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2676 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2677 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2678 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2679 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2680 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2681 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2682 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2683 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2684 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2685 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2686 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2687 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2688 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2689 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2690 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2691 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2692 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2693 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2694 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2695 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2696 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2697 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2698 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2699 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2700 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2701 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2702 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2703 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2704 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2705 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2706 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2707 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2708 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2709 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2710 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2711 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2712 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2713 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2714 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2715 2716 #if defined(STM32WB) 2717 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2718 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2719 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2720 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2721 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2722 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2723 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2724 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2725 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2726 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2727 #define QSPI_IRQHandler QUADSPI_IRQHandler 2728 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2729 2730 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2731 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2732 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2733 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2734 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2735 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2736 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2737 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2738 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2739 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2740 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2741 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2742 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2743 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2744 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2745 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2746 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2747 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2748 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2749 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2750 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2751 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2752 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2753 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2754 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2755 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2756 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2757 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2758 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2759 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2760 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2761 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2762 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2763 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2764 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2765 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2766 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2767 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2768 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2769 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2770 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2771 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2772 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2773 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2774 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2775 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2776 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2777 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2778 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2779 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2780 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2781 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2782 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2783 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2784 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2785 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2786 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2787 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2788 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2789 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2790 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2791 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2792 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2793 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2794 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2795 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2796 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2797 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2798 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2799 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2800 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2801 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2802 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2803 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2804 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2805 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2806 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2807 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2808 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2809 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2810 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2811 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2812 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2813 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2814 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2815 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2816 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2817 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2818 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2819 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2820 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2821 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2822 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2823 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2824 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2825 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2826 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2827 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2828 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2829 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2830 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2831 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2832 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2833 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2834 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2835 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2836 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2837 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2838 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2839 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2840 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2841 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2842 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2843 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2844 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2845 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2846 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2847 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2848 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2849 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2850 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2851 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2852 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2853 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2854 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2855 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2856 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2857 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2858 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2859 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2860 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2861 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2862 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2863 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2864 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2865 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2866 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2867 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2868 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2869 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2870 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2871 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2872 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2873 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2874 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2875 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2876 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2877 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2878 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2879 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2880 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2881 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2882 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2883 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2884 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2885 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2886 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2887 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2888 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2889 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2890 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2891 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2892 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2893 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2894 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2895 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2896 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2897 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2898 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2899 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2900 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2901 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2902 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2903 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2904 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2905 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2906 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2907 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2908 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2909 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2910 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2911 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2912 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2913 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2914 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2915 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2916 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2917 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2918 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2919 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2920 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2921 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2922 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2923 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2924 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2925 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2926 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2927 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2928 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2929 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2930 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2931 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2932 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2933 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2934 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2935 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2936 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2937 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2938 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2939 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2940 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2941 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2942 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2943 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2944 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2945 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2946 2947 #if defined(STM32H7) 2948 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2949 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2950 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2951 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2952 2953 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2954 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2955 2956 2957 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2958 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2959 #endif 2960 2961 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2962 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2963 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2964 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2965 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2966 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2967 2968 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2969 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2970 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2971 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2972 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2973 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2974 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2975 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2976 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2977 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2978 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2979 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2980 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2981 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2982 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2983 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 2984 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 2985 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 2986 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 2987 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 2988 2989 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 2990 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 2991 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 2992 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 2993 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 2994 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 2995 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 2996 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 2997 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 2998 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 2999 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3000 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3001 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3002 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3003 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3004 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3005 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3006 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3007 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3008 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3009 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3010 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3011 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3012 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3013 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3014 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3015 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3016 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3017 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3018 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3019 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3020 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3021 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3022 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3023 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3024 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3025 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3026 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3027 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3028 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3029 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3030 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3031 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3032 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3033 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3034 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3035 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3036 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3037 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3038 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3039 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3040 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3041 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3042 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3043 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3044 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3045 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3046 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3047 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3048 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3049 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3050 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3051 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3052 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3053 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3054 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3055 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3056 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3057 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3058 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3059 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3060 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3061 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3062 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3063 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3064 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3065 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3066 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3067 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3068 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3069 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3070 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3071 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3072 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3073 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3074 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3075 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3076 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3077 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3078 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3079 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3080 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3081 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3082 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3083 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3084 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3085 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3086 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3087 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3088 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3089 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3090 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3091 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3092 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3093 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3094 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3095 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3096 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3097 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3098 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3099 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3100 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3101 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3102 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3103 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3104 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3105 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3106 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3107 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3108 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3109 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3110 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3111 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3112 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3113 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3114 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3115 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3116 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3117 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3118 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3119 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3120 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3121 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3122 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3123 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3124 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3125 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3126 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3127 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3128 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3129 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3130 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3131 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3132 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3133 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3134 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3135 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3136 3137 /* alias define maintained for legacy */ 3138 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3139 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3140 3141 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3142 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3143 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3144 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3145 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3146 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3147 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3148 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3149 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3150 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3151 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3152 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3153 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3154 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3155 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3156 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3157 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3158 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3159 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3160 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3161 3162 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3163 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3164 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3165 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3166 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3167 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3168 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3169 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3170 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3171 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3172 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3173 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3174 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3175 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3176 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3177 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3178 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3179 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3180 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3181 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3182 3183 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3184 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3185 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3186 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3187 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3188 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3189 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3190 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3191 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3192 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3193 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3194 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3195 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3196 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3197 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3198 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3199 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3200 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3201 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3202 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3203 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3204 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3205 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3206 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3207 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3208 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3209 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3210 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3211 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3212 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3213 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3214 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3215 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3216 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3217 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3218 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3219 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3220 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3221 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3222 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3223 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3224 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3225 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3226 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3227 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3228 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3229 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3230 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3231 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3232 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3233 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3234 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3235 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3236 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3237 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3238 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3239 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3240 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3241 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3242 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3243 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3244 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3245 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3246 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3247 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3248 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3249 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3250 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3251 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3252 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3253 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3254 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3255 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3256 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3257 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3258 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3259 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3260 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3261 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3262 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3263 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3264 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3265 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3266 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3267 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3268 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3269 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3270 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3271 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3272 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3273 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3274 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3275 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3276 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3277 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3278 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3279 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3280 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3281 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3282 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3283 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3284 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3285 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3286 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3287 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3288 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3289 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3290 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3291 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3292 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3293 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3294 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3295 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3296 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3297 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3298 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3299 3300 #if defined(STM32L1) 3301 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3302 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3303 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3304 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3305 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3306 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3307 #endif /* STM32L1 */ 3308 3309 #if defined(STM32F4) 3310 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3311 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3312 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3313 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3314 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3315 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3316 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3317 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3318 #define Sdmmc1ClockSelection SdioClockSelection 3319 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3320 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3321 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3322 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3323 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3324 #endif 3325 3326 #if defined(STM32F7) || defined(STM32L4) 3327 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3328 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3329 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3330 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3331 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3332 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3333 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3334 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3335 #define SdioClockSelection Sdmmc1ClockSelection 3336 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3337 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3338 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3339 #endif 3340 3341 #if defined(STM32F7) 3342 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3343 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3344 #endif 3345 3346 #if defined(STM32H7) 3347 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3348 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3349 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3350 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3351 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3352 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3353 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3354 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3355 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3356 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3357 3358 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3359 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3360 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3361 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3362 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3363 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3364 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3365 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3366 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3367 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3368 #endif 3369 3370 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3371 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3372 3373 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3374 3375 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3376 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3377 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3378 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3379 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3380 3381 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3382 3383 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3384 #define RCC_IT_CSSHSE RCC_IT_CSS 3385 3386 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3387 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3388 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3389 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3390 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3391 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3392 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3393 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3394 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3395 3396 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3397 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3398 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3399 3400 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3401 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3402 #define RCC_MCO_NODIV RCC_MCODIV_1 3403 #define RCC_MCO_DIV1 RCC_MCODIV_1 3404 #define RCC_MCO_DIV2 RCC_MCODIV_2 3405 #define RCC_MCO_DIV4 RCC_MCODIV_4 3406 #define RCC_MCO_DIV8 RCC_MCODIV_8 3407 #define RCC_MCO_DIV16 RCC_MCODIV_16 3408 #define RCC_MCO_DIV32 RCC_MCODIV_32 3409 #define RCC_MCO_DIV64 RCC_MCODIV_64 3410 #define RCC_MCO_DIV128 RCC_MCODIV_128 3411 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3412 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3413 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3414 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3415 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3416 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3417 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3418 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3419 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3420 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3421 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3422 3423 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) 3424 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3425 #else 3426 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3427 #endif 3428 3429 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3430 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3431 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3432 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3433 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3434 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3435 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3436 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3437 3438 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3439 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3440 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3441 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3442 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3443 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3444 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3445 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3446 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3447 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3448 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3449 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3450 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3451 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3452 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3453 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3454 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3455 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3456 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3457 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3458 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3459 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3460 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3461 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3462 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3463 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3464 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3465 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3466 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3467 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3468 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3469 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3470 3471 #define CR_HSION_BB RCC_CR_HSION_BB 3472 #define CR_CSSON_BB RCC_CR_CSSON_BB 3473 #define CR_PLLON_BB RCC_CR_PLLON_BB 3474 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3475 #define CR_MSION_BB RCC_CR_MSION_BB 3476 #define CSR_LSION_BB RCC_CSR_LSION_BB 3477 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3478 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3479 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3480 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3481 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3482 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3483 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3484 #define CR_HSEON_BB RCC_CR_HSEON_BB 3485 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3486 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3487 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3488 3489 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3490 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3491 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3492 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3493 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3494 3495 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3496 3497 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3498 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3499 3500 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3501 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3502 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3503 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3504 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3505 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3506 3507 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3508 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3509 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3510 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3511 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3512 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3513 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3514 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3515 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3516 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3517 #define DfsdmClockSelection Dfsdm1ClockSelection 3518 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3519 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3520 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3521 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3522 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3523 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3524 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3525 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3526 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3527 3528 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3529 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3530 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3531 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3532 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3533 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3534 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3535 #if defined(STM32U5) 3536 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3537 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3538 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3539 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3540 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3541 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3542 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3543 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3544 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3545 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3546 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3547 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3548 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3549 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3550 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3551 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3552 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3553 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3554 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3555 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3556 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3557 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3558 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3559 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3560 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3561 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3562 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3563 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3564 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3565 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3566 #endif /* STM32U5 */ 3567 3568 /** 3569 * @} 3570 */ 3571 3572 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3573 * @{ 3574 */ 3575 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3576 3577 /** 3578 * @} 3579 */ 3580 3581 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3582 * @{ 3583 */ 3584 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ 3585 defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) 3586 #else 3587 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3588 #endif 3589 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3590 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3591 3592 #if defined (STM32F1) 3593 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3594 3595 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3596 3597 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3598 3599 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3600 3601 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3602 #else 3603 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3604 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3605 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3606 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3607 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3608 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3609 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3610 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3611 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3612 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3613 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3614 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3615 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3616 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3617 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3618 #endif /* STM32F1 */ 3619 3620 #define IS_ALARM IS_RTC_ALARM 3621 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3622 #define IS_TAMPER IS_RTC_TAMPER 3623 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3624 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3625 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3626 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3627 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3628 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3629 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3630 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3631 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3632 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3633 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3634 3635 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3636 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3637 3638 /** 3639 * @} 3640 */ 3641 3642 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3643 * @{ 3644 */ 3645 3646 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3647 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3648 3649 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3650 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3651 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3652 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3653 3654 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3655 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3656 #endif 3657 3658 #if defined(STM32F4) || defined(STM32F2) 3659 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3660 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3661 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3662 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3663 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3664 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3665 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3666 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3667 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3668 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3669 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3670 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3671 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3672 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3673 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3674 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3675 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3676 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3677 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3678 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3679 /* alias CMSIS */ 3680 #define SDMMC1_IRQn SDIO_IRQn 3681 #define SDMMC1_IRQHandler SDIO_IRQHandler 3682 #endif 3683 3684 #if defined(STM32F7) || defined(STM32L4) 3685 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3686 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3687 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3688 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3689 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3690 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3691 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3692 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3693 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3694 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3695 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3696 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3697 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3698 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3699 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3700 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3701 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3702 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3703 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3704 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3705 /* alias CMSIS for compatibilities */ 3706 #define SDIO_IRQn SDMMC1_IRQn 3707 #define SDIO_IRQHandler SDMMC1_IRQHandler 3708 #endif 3709 3710 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3711 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3712 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3713 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3714 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3715 #endif 3716 3717 #if defined(STM32H7) || defined(STM32L5) 3718 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3719 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3720 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3721 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3722 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3723 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3724 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3725 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3726 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3727 #endif 3728 /** 3729 * @} 3730 */ 3731 3732 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3733 * @{ 3734 */ 3735 3736 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3737 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3738 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3739 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3740 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3741 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3742 3743 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3744 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3745 3746 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3747 3748 /** 3749 * @} 3750 */ 3751 3752 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3753 * @{ 3754 */ 3755 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3756 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3757 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3758 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3759 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3760 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3761 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3762 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3763 /** 3764 * @} 3765 */ 3766 3767 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3768 * @{ 3769 */ 3770 3771 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3772 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3773 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3774 3775 /** 3776 * @} 3777 */ 3778 3779 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3780 * @{ 3781 */ 3782 3783 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3784 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3785 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3786 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3787 3788 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3789 3790 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3791 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3792 3793 /** 3794 * @} 3795 */ 3796 3797 3798 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3799 * @{ 3800 */ 3801 3802 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3803 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3804 #define __USART_ENABLE __HAL_USART_ENABLE 3805 #define __USART_DISABLE __HAL_USART_DISABLE 3806 3807 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3808 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3809 3810 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 3811 #define USART_OVERSAMPLING_16 0x00000000U 3812 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 3813 3814 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 3815 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 3816 #endif /* STM32F0 || STM32F3 || STM32F7 */ 3817 /** 3818 * @} 3819 */ 3820 3821 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3822 * @{ 3823 */ 3824 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3825 3826 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3827 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3828 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3829 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3830 3831 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3832 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3833 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3834 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3835 3836 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3837 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3838 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3839 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3840 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3841 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3842 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3843 3844 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3845 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3846 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3847 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3848 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3849 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3850 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3851 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3852 3853 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3854 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3855 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3856 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3857 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3858 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3859 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3860 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3861 3862 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3863 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3864 3865 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3866 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3867 /** 3868 * @} 3869 */ 3870 3871 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3872 * @{ 3873 */ 3874 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3875 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3876 3877 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3878 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3879 3880 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3881 3882 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3883 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3884 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3885 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3886 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3887 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3888 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3889 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3890 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3891 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3892 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3893 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3894 3895 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3896 /** 3897 * @} 3898 */ 3899 3900 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3901 * @{ 3902 */ 3903 3904 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3905 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3906 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3907 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3908 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3909 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3910 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3911 3912 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3913 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3914 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3915 /** 3916 * @} 3917 */ 3918 3919 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3920 * @{ 3921 */ 3922 #define __HAL_LTDC_LAYER LTDC_LAYER 3923 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3924 /** 3925 * @} 3926 */ 3927 3928 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3929 * @{ 3930 */ 3931 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3932 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3933 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3934 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3935 #define SAI_STREOMODE SAI_STEREOMODE 3936 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3937 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3938 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3939 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3940 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3941 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3942 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3943 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3944 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3945 /** 3946 * @} 3947 */ 3948 3949 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3950 * @{ 3951 */ 3952 #if defined(STM32H7) 3953 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3954 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3955 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3956 #endif 3957 /** 3958 * @} 3959 */ 3960 3961 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3962 * @{ 3963 */ 3964 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3965 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3966 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3967 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3968 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3969 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3970 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3971 #endif 3972 /** 3973 * @} 3974 */ 3975 3976 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3977 * @{ 3978 */ 3979 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3980 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3981 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3982 /** 3983 * @} 3984 */ 3985 3986 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 3987 * @{ 3988 */ 3989 #if defined (STM32F7) 3990 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 3991 #endif /* STM32F7 */ 3992 /** 3993 * @} 3994 */ 3995 3996 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 3997 * @{ 3998 */ 3999 4000 /** 4001 * @} 4002 */ 4003 4004 #ifdef __cplusplus 4005 } 4006 #endif 4007 4008 #endif /* STM32_HAL_LEGACY */ 4009 4010
