1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32l5xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif /* USE_FULL_ASSERT */
26
27 /** @addtogroup STM32L5xx_LL_Driver
28 * @{
29 */
30
31 #if defined(RCC)
32
33 /** @addtogroup RCC_LL
34 * @{
35 */
36
37 /* Private types -------------------------------------------------------------*/
38 /* Private variables ---------------------------------------------------------*/
39 /* Private constants ---------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
42 * @{
43 */
44 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
45 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
47
48 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
50
51 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
52
53 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
55 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
57
58 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
59 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
60 || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE))
61
62 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
63 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
64
65 #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
66
67 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
68
69 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
70
71 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
72
73 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
74
75 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
76
77 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
78
79 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
80
81 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
82
83 /**
84 * @}
85 */
86
87 /* Private function prototypes -----------------------------------------------*/
88 /** @defgroup RCC_LL_Private_Functions RCC Private Functions
89 * @{
90 */
91 static uint32_t RCC_GetSystemClockFreq(void);
92 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
93 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
94 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
95 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
96 static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
97 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
98 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
99 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
100 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
101 static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
102 /**
103 * @}
104 */
105
106
107 /* Exported functions --------------------------------------------------------*/
108 /** @addtogroup RCC_LL_Exported_Functions
109 * @{
110 */
111
112 /** @addtogroup RCC_LL_EF_Init
113 * @{
114 */
115
116 /**
117 * @brief Reset the RCC clock configuration to the default reset state.
118 * @note The default reset state of the clock configuration is given below:
119 * - MSI ON and used as system clock source
120 * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF
121 * - AHB, APB1 and APB2 prescaler set to 1.
122 * - CSS, MCO OFF
123 * - All interrupts disabled
124 * @note This function doesn't modify the configuration of the
125 * - Peripheral clocks
126 * - LSI, LSE and RTC clocks
127 * @retval An ErrorStatus enumeration value:
128 * - SUCCESS: RCC registers are de-initialized
129 * - ERROR: not applicable
130 */
LL_RCC_DeInit(void)131 ErrorStatus LL_RCC_DeInit(void)
132 {
133 __IO uint32_t vl_mask;
134
135 /* Set MSION bit */
136 LL_RCC_MSI_Enable();
137
138 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
139 while (LL_RCC_MSI_IsReady() == 0U)
140 {
141 }
142
143 /* Set MSIRANGE default value */
144 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
145
146 /* Set MSITRIM bits to the reset value*/
147 LL_RCC_MSI_SetCalibTrimming(0);
148
149 /* Set HSITRIM bits to the reset value*/
150 LL_RCC_HSI_SetCalibTrimming(0x40U);
151
152 /* Reset CFGR register */
153 LL_RCC_WriteReg(CFGR, 0x00000000U);
154
155 /* Read CR register */
156 vl_mask = LL_RCC_ReadReg(CR);
157
158 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, PLLSAI1ON and PLLSAI2ON bits */
159 CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON |
160 RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON));
161
162 /* Write new mask in CR register */
163 LL_RCC_WriteReg(CR, vl_mask);
164
165 /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */
166 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
167 {
168 }
169
170 /* Reset PLLCFGR register */
171 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
172
173 /* Reset PLLSAI1CFGR register */
174 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
175
176 /* Reset PLLSAI2CFGR register */
177 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
178
179 /* Reset HSEBYP bit */
180 LL_RCC_HSE_DisableBypass();
181
182 /* Disable all interrupts */
183 LL_RCC_WriteReg(CIER, 0x00000000U);
184
185 /* Clear all interrupt flags */
186 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
187 RCC_CICR_HSI48RDYC | RCC_CICR_PLLSAI1RDYC | RCC_CICR_PLLSAI2RDYC | RCC_CICR_CSSC;
188 LL_RCC_WriteReg(CICR, vl_mask);
189
190 /* Clear reset flags */
191 LL_RCC_ClearResetFlags();
192
193 /* Reset privilege mode */
194 LL_RCC_DisablePrivilege();
195
196 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
197 /* Reset secure configuration */
198 LL_RCC_ConfigSecure(LL_RCC_ALL_NSEC);
199 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
200
201 return SUCCESS;
202 }
203
204 /**
205 * @}
206 */
207
208 /** @addtogroup RCC_LL_EF_Get_Freq
209 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
210 * and different peripheral clocks available on the device.
211 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
212 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
213 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
214 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
215 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
216 * @note (*) MSI_VALUE is a constant defined in this file (default value
217 * 4 MHz) but the real value may vary depending on the variations
218 * in voltage and temperature.
219 * @note (**) HSI_VALUE is a constant defined in this file (default value
220 * 16 MHz) but the real value may vary depending on the variations
221 * in voltage and temperature.
222 * @note (***) HSE_VALUE is a constant defined in this file (default value
223 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
224 * frequency of the crystal used. Otherwise, this function may
225 * have wrong result.
226 * @note The result of this function could be incorrect when using fractional
227 * value for HSE crystal.
228 * @note This function can be used by the user application to compute the
229 * baud-rate for the communication peripherals or configure other parameters.
230 * @{
231 */
232
233 /**
234 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
235 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
236 * must be called to update structure fields. Otherwise, any
237 * configuration based on this function will be incorrect.
238 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
239 * @retval None
240 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)241 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
242 {
243 /* Get SYSCLK frequency */
244 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
245
246 /* HCLK clock frequency */
247 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
248
249 /* PCLK1 clock frequency */
250 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
251
252 /* PCLK2 clock frequency */
253 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
254 }
255
256 /**
257 * @brief Return USARTx clock frequency
258 * @param USARTxSource This parameter can be one of the following values:
259 * @arg @ref LL_RCC_USART1_CLKSOURCE
260 * @arg @ref LL_RCC_USART2_CLKSOURCE
261 * @arg @ref LL_RCC_USART3_CLKSOURCE
262 * @retval USART clock frequency (in Hz)
263 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
264 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)265 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
266 {
267 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
268
269 /* Check parameter */
270 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
271
272 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
273 {
274 /* USART1CLK clock frequency */
275 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
276 {
277 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
278 usart_frequency = RCC_GetSystemClockFreq();
279 break;
280
281 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
282 if (LL_RCC_HSI_IsReady() == 1U)
283 {
284 usart_frequency = HSI_VALUE;
285 }
286 break;
287
288 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
289 if (LL_RCC_LSE_IsReady() == 1U)
290 {
291 usart_frequency = LSE_VALUE;
292 }
293 break;
294
295 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
296 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
297 break;
298
299 default:
300 /* unreachable code */
301 break;
302 }
303 }
304 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
305 {
306 /* USART2CLK clock frequency */
307 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
308 {
309 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
310 usart_frequency = RCC_GetSystemClockFreq();
311 break;
312
313 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
314 if (LL_RCC_HSI_IsReady() == 1U)
315 {
316 usart_frequency = HSI_VALUE;
317 }
318 break;
319
320 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
321 if (LL_RCC_LSE_IsReady() == 1U)
322 {
323 usart_frequency = LSE_VALUE;
324 }
325 break;
326
327 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
328 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
329 break;
330
331 default:
332 /* unreachable code */
333 break;
334 }
335 }
336 else if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
337 {
338 /* USART3CLK clock frequency */
339 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
340 {
341 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
342 usart_frequency = RCC_GetSystemClockFreq();
343 break;
344
345 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
346 if (LL_RCC_HSI_IsReady() == 1U)
347 {
348 usart_frequency = HSI_VALUE;
349 }
350 break;
351
352 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
353 if (LL_RCC_LSE_IsReady() == 1U)
354 {
355 usart_frequency = LSE_VALUE;
356 }
357 break;
358
359 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
360 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
361 break;
362
363 default:
364 /* unreachable code */
365 break;
366 }
367 }
368 else
369 {
370 /* nothing to do */
371 }
372
373 return usart_frequency;
374 }
375
376 /**
377 * @brief Return UARTx clock frequency
378 * @param UARTxSource This parameter can be one of the following values:
379 * @arg @ref LL_RCC_UART4_CLKSOURCE
380 * @arg @ref LL_RCC_UART5_CLKSOURCE
381 * @retval UART clock frequency (in Hz)
382 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
383 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)384 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
385 {
386 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
387
388 /* Check parameter */
389 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
390
391 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
392 {
393 /* UART4CLK clock frequency */
394 switch (LL_RCC_GetUARTClockSource(UARTxSource))
395 {
396 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
397 uart_frequency = RCC_GetSystemClockFreq();
398 break;
399
400 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
401 if (LL_RCC_HSI_IsReady() == 1U)
402 {
403 uart_frequency = HSI_VALUE;
404 }
405 break;
406
407 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
408 if (LL_RCC_LSE_IsReady() == 1U)
409 {
410 uart_frequency = LSE_VALUE;
411 }
412 break;
413
414 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
415 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
416 break;
417
418 default:
419 /* unreachable code */
420 break;
421 }
422 }
423 else if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
424 {
425 /* UART5CLK clock frequency */
426 switch (LL_RCC_GetUARTClockSource(UARTxSource))
427 {
428 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
429 uart_frequency = RCC_GetSystemClockFreq();
430 break;
431
432 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
433 if (LL_RCC_HSI_IsReady() == 1U)
434 {
435 uart_frequency = HSI_VALUE;
436 }
437 break;
438
439 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
440 if (LL_RCC_LSE_IsReady() == 1U)
441 {
442 uart_frequency = LSE_VALUE;
443 }
444 break;
445
446 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
447 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
448 break;
449
450 default:
451 /* unreachable code */
452 break;
453 }
454 }
455 else
456 {
457 /* nothing to do */
458 }
459
460 return uart_frequency;
461 }
462
463 /**
464 * @brief Return I2Cx clock frequency
465 * @param I2CxSource This parameter can be one of the following values:
466 * @arg @ref LL_RCC_I2C1_CLKSOURCE
467 * @arg @ref LL_RCC_I2C2_CLKSOURCE
468 * @arg @ref LL_RCC_I2C3_CLKSOURCE
469 * @arg @ref LL_RCC_I2C4_CLKSOURCE
470 * @retval I2C clock frequency (in Hz)
471 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
472 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)473 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
474 {
475 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
476
477 /* Check parameter */
478 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
479
480 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
481 {
482 /* I2C1 CLK clock frequency */
483 switch (LL_RCC_GetI2CClockSource(I2CxSource))
484 {
485 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
486 i2c_frequency = RCC_GetSystemClockFreq();
487 break;
488
489 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
490 if (LL_RCC_HSI_IsReady() == 1U)
491 {
492 i2c_frequency = HSI_VALUE;
493 }
494 break;
495
496 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
497 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
498 break;
499
500 default:
501 /* unreachable code */
502 break;
503 }
504 }
505 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
506 {
507 /* I2C2 CLK clock frequency */
508 switch (LL_RCC_GetI2CClockSource(I2CxSource))
509 {
510 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
511 i2c_frequency = RCC_GetSystemClockFreq();
512 break;
513
514 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
515 if (LL_RCC_HSI_IsReady() == 1U)
516 {
517 i2c_frequency = HSI_VALUE;
518 }
519 break;
520
521 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
522 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
523 break;
524
525 default:
526 /* unreachable code */
527 break;
528 }
529 }
530 else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
531 {
532 /* I2C3 CLK clock frequency */
533 switch (LL_RCC_GetI2CClockSource(I2CxSource))
534 {
535 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
536 i2c_frequency = RCC_GetSystemClockFreq();
537 break;
538
539 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
540 if (LL_RCC_HSI_IsReady() == 1U)
541 {
542 i2c_frequency = HSI_VALUE;
543 }
544 break;
545
546 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
547 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
548 break;
549
550 default:
551 /* unreachable code */
552 break;
553 }
554 }
555 else if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
556 {
557 /* I2C4 CLK clock frequency */
558 switch (LL_RCC_GetI2CClockSource(I2CxSource))
559 {
560 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
561 i2c_frequency = RCC_GetSystemClockFreq();
562 break;
563
564 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
565 if (LL_RCC_HSI_IsReady() == 1U)
566 {
567 i2c_frequency = HSI_VALUE;
568 }
569 break;
570
571 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
572 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
573 break;
574
575 default:
576 /* unreachable code */
577 break;
578 }
579 }
580 else
581 {
582 /* nothing to do */
583 }
584
585 return i2c_frequency;
586 }
587
588
589 /**
590 * @brief Return LPUARTx clock frequency
591 * @param LPUARTxSource This parameter can be one of the following values:
592 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
593 * @retval LPUART clock frequency (in Hz)
594 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
595 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)596 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
597 {
598 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
599
600 /* Check parameter */
601 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
602
603 /* LPUART1CLK clock frequency */
604 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
605 {
606 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
607 lpuart_frequency = RCC_GetSystemClockFreq();
608 break;
609
610 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
611 if (LL_RCC_HSI_IsReady() == 1U)
612 {
613 lpuart_frequency = HSI_VALUE;
614 }
615 break;
616
617 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
618 if (LL_RCC_LSE_IsReady() == 1U)
619 {
620 lpuart_frequency = LSE_VALUE;
621 }
622 break;
623
624 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
625 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
626 break;
627
628 default:
629 /* unreachable code */
630 break;
631 }
632
633 return lpuart_frequency;
634 }
635
636 /**
637 * @brief Return LPTIMx clock frequency
638 * @param LPTIMxSource This parameter can be one of the following values:
639 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
640 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
641 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE
642 * @retval LPTIM clock frequency (in Hz)
643 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
644 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)645 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
646 {
647 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
648
649 /* Check parameter */
650 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
651
652 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
653 {
654 /* LPTIM1CLK clock frequency */
655 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
656 {
657 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
658 if (LL_RCC_LSI_IsReady() == 1U)
659 {
660 lptim_frequency = LSI_VALUE;
661 }
662 break;
663
664 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
665 if (LL_RCC_HSI_IsReady() == 1U)
666 {
667 lptim_frequency = HSI_VALUE;
668 }
669 break;
670
671 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
672 if (LL_RCC_LSE_IsReady() == 1U)
673 {
674 lptim_frequency = LSE_VALUE;
675 }
676 break;
677
678 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
679 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
680 break;
681
682 default:
683 /* unreachable code */
684 break;
685 }
686 }
687 else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
688 {
689 /* LPTIM2CLK clock frequency */
690 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
691 {
692 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
693 if (LL_RCC_LSI_IsReady() == 1U)
694 {
695 lptim_frequency = LSI_VALUE;
696 }
697 break;
698
699 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
700 if (LL_RCC_HSI_IsReady() == 1U)
701 {
702 lptim_frequency = HSI_VALUE;
703 }
704 break;
705
706 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
707 if (LL_RCC_LSE_IsReady() == 1U)
708 {
709 lptim_frequency = LSE_VALUE;
710 }
711 break;
712
713 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
714 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
715 break;
716
717 default:
718 /* unreachable code */
719 break;
720 }
721 }
722 else if (LPTIMxSource == LL_RCC_LPTIM3_CLKSOURCE)
723 {
724 /* LPTIM3CLK clock frequency */
725 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
726 {
727 case LL_RCC_LPTIM3_CLKSOURCE_LSI: /* LPTIM3 Clock is LSI Osc. */
728 if (LL_RCC_LSI_IsReady() == 1U)
729 {
730 lptim_frequency = LSI_VALUE;
731 }
732 break;
733
734 case LL_RCC_LPTIM3_CLKSOURCE_HSI: /* LPTIM3 Clock is HSI Osc. */
735 if (LL_RCC_HSI_IsReady() == 1U)
736 {
737 lptim_frequency = HSI_VALUE;
738 }
739 break;
740
741 case LL_RCC_LPTIM3_CLKSOURCE_LSE: /* LPTIM3 Clock is LSE Osc. */
742 if (LL_RCC_LSE_IsReady() == 1U)
743 {
744 lptim_frequency = LSE_VALUE;
745 }
746 break;
747
748 case LL_RCC_LPTIM3_CLKSOURCE_PCLK1: /* LPTIM3 Clock is PCLK1 */
749 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
750 break;
751
752 default:
753 /* unreachable code */
754 break;
755 }
756 }
757 else
758 {
759 /* nothing to do */
760 }
761
762 return lptim_frequency;
763 }
764
765 /**
766 * @brief Return SAIx clock frequency
767 * @param SAIxSource This parameter can be one of the following values:
768 * @arg @ref LL_RCC_SAI1_CLKSOURCE
769 * @arg @ref LL_RCC_SAI2_CLKSOURCE
770 * @retval SAI clock frequency (in Hz)
771 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
772 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)773 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
774 {
775 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
776
777 /* Check parameter */
778 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
779
780 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
781 {
782 /* SAI1CLK clock frequency */
783 switch (LL_RCC_GetSAIClockSource(SAIxSource))
784 {
785 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
786 if (LL_RCC_PLLSAI1_IsReady() == 1U)
787 {
788 if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() == 1U)
789 {
790 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
791 }
792 }
793 break;
794
795 case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
796 if (LL_RCC_PLLSAI2_IsReady() == 1U)
797 {
798 if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() == 1U)
799 {
800 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
801 }
802 }
803 break;
804
805 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
806 if (LL_RCC_PLL_IsReady() == 1U)
807 {
808 if (LL_RCC_PLL_IsEnabledDomain_SAI() == 1U)
809 {
810 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
811 }
812 }
813 break;
814
815 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
816 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
817 break;
818
819 default:
820 /* unreachable code */
821 break;
822 }
823 }
824 else if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
825 {
826 /* SAI2CLK clock frequency */
827 switch (LL_RCC_GetSAIClockSource(SAIxSource))
828 {
829 case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
830 if (LL_RCC_PLLSAI1_IsReady() == 1U)
831 {
832 if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() == 1U)
833 {
834 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
835 }
836 }
837 break;
838
839 case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
840 if (LL_RCC_PLLSAI2_IsReady() == 1U)
841 {
842 if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() == 1U)
843 {
844 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
845 }
846 }
847 break;
848
849 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
850 if (LL_RCC_PLL_IsReady() == 1U)
851 {
852 if (LL_RCC_PLL_IsEnabledDomain_SAI() == 1U)
853 {
854 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
855 }
856 }
857 break;
858
859 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
860 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
861 break;
862
863 default:
864 /* unreachable code */
865 break;
866 }
867 }
868 else
869 {
870 /* nothing to do */
871 }
872
873 return sai_frequency;
874 }
875
876 /**
877 * @brief Return SDMMCx kernel clock frequency
878 * @param SDMMCxSource This parameter can be one of the following values:
879 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
880 * @retval SDMMC clock frequency (in Hz)
881 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
882 */
LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)883 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
884 {
885 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
886
887 /* Check parameter */
888 assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
889
890 /* SDMMC1CLK kernel clock frequency */
891 switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
892 {
893 case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */
894 sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);
895 break;
896
897 case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
898 if (LL_RCC_PLL_IsReady() == 1U)
899 {
900 if (LL_RCC_PLL_IsEnabledDomain_SAI() == 1U)
901 {
902 sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
903 }
904 }
905 break;
906
907 default:
908 /* unreachable code */
909 break;
910 }
911
912 return sdmmc_frequency;
913 }
914
915 /**
916 * @brief Return SDMMCx clock frequency
917 * @param SDMMCxSource This parameter can be one of the following values:
918 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
919 * @retval SDMMC clock frequency (in Hz)
920 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLL is not ready
921 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)922 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
923 {
924 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
925
926 /* Check parameter */
927 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
928
929 /* SDMMC1CLK clock frequency */
930 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
931 {
932 case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
933 if (LL_RCC_PLLSAI1_IsReady() == 1U)
934 {
935 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() == 1U)
936 {
937 sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
938 }
939 }
940 break;
941
942 case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
943 if (LL_RCC_PLL_IsReady() == 1U)
944 {
945 if (LL_RCC_PLL_IsEnabledDomain_48M() == 1U)
946 {
947 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
948 }
949 }
950 break;
951
952 case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
953 if (LL_RCC_MSI_IsReady() == 1U)
954 {
955 sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
956 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
957 LL_RCC_MSI_GetRange() :
958 LL_RCC_MSI_GetRangeAfterStandby()));
959 }
960 break;
961
962 case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
963 if (LL_RCC_HSI48_IsReady() == 1U)
964 {
965 sdmmc_frequency = HSI48_VALUE;
966 }
967 break;
968
969
970 default:
971 /* unreachable code */
972 break;
973 }
974
975 return sdmmc_frequency;
976 }
977
978 /**
979 * @brief Return RNGx clock frequency
980 * @param RNGxSource This parameter can be one of the following values:
981 * @arg @ref LL_RCC_RNG_CLKSOURCE
982 * @retval RNG clock frequency (in Hz)
983 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLL is not ready
984 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)985 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
986 {
987 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
988
989 /* Check parameter */
990 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
991
992 /* RNGCLK clock frequency */
993 switch (LL_RCC_GetRNGClockSource(RNGxSource))
994 {
995 case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
996 if (LL_RCC_PLLSAI1_IsReady() == 1U)
997 {
998 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() == 1U)
999 {
1000 rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1001 }
1002 }
1003 break;
1004
1005 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
1006 if (LL_RCC_PLL_IsReady() == 1U)
1007 {
1008 if (LL_RCC_PLL_IsEnabledDomain_48M() == 1U)
1009 {
1010 rng_frequency = RCC_PLL_GetFreqDomain_48M();
1011 }
1012 }
1013 break;
1014
1015 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
1016 if (LL_RCC_MSI_IsReady() == 1U)
1017 {
1018 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1019 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1020 LL_RCC_MSI_GetRange() :
1021 LL_RCC_MSI_GetRangeAfterStandby()));
1022 }
1023 break;
1024
1025 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 clock used as RNG clock source */
1026 if (LL_RCC_HSI48_IsReady() == 1U)
1027 {
1028 rng_frequency = HSI48_VALUE;
1029 }
1030 break;
1031
1032 default:
1033 /* unreachable code */
1034 break;
1035 }
1036
1037 return rng_frequency;
1038 }
1039
1040 /**
1041 * @brief Return USBx clock frequency
1042 * @param USBxSource This parameter can be one of the following values:
1043 * @arg @ref LL_RCC_USB_CLKSOURCE
1044 * @retval USB clock frequency (in Hz)
1045 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLL is not ready
1046 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1047 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1048 {
1049 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1050
1051 /* Check parameter */
1052 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1053
1054 /* USBCLK clock frequency */
1055 switch (LL_RCC_GetUSBClockSource(USBxSource))
1056 {
1057 case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
1058 if (LL_RCC_PLLSAI1_IsReady() == 1U)
1059 {
1060 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() == 1U)
1061 {
1062 usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1063 }
1064 }
1065 break;
1066
1067 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1068 if (LL_RCC_PLL_IsReady() == 1U)
1069 {
1070 if (LL_RCC_PLL_IsEnabledDomain_48M() == 1U)
1071 {
1072 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1073 }
1074 }
1075 break;
1076
1077 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
1078 if (LL_RCC_MSI_IsReady() == 1U)
1079 {
1080 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1081 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1082 LL_RCC_MSI_GetRange() :
1083 LL_RCC_MSI_GetRangeAfterStandby()));
1084 }
1085 break;
1086
1087 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
1088 if (LL_RCC_HSI48_IsReady() == 1U)
1089 {
1090 usb_frequency = HSI48_VALUE;
1091 }
1092 break;
1093
1094 default:
1095 /* unreachable code */
1096 break;
1097 }
1098
1099 return usb_frequency;
1100 }
1101
1102 /**
1103 * @brief Return ADCx clock frequency
1104 * @param ADCxSource This parameter can be one of the following values:
1105 * @arg @ref LL_RCC_ADC_CLKSOURCE
1106 * @retval ADC clock frequency (in Hz)
1107 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator or PLL is not ready
1108 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1109 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)1110 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
1111 {
1112 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1113
1114 /* Check parameter */
1115 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
1116
1117 /* ADCCLK clock frequency */
1118 switch (LL_RCC_GetADCClockSource(ADCxSource))
1119 {
1120 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
1121 if (LL_RCC_PLLSAI1_IsReady() == 1U)
1122 {
1123 if (LL_RCC_PLLSAI1_IsEnabledDomain_ADC() == 1U)
1124 {
1125 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
1126 }
1127 }
1128 break;
1129
1130 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
1131 adc_frequency = RCC_GetSystemClockFreq();
1132 break;
1133
1134 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
1135 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1136 break;
1137
1138 default:
1139 /* unreachable code */
1140 break;
1141 }
1142
1143 return adc_frequency;
1144 }
1145
1146 /**
1147 * @brief Return DFSDMx clock frequency
1148 * @param DFSDMxSource This parameter can be one of the following values:
1149 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1150 * @retval DFSDM clock frequency (in Hz)
1151 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1152 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1153 {
1154 uint32_t dfsdm_frequency;
1155
1156 /* Check parameter */
1157 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1158
1159 /* DFSDM1CLK clock frequency */
1160 if (LL_RCC_GetDFSDMClockSource(DFSDMxSource) == LL_RCC_DFSDM1_CLKSOURCE_PCLK2)
1161 {
1162 /* DFSDM1 Clock is PCLK2 */
1163 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1164 }
1165 else
1166 {
1167 /* DFSDM1 Clock is SYSCLK */
1168 dfsdm_frequency = RCC_GetSystemClockFreq();
1169 }
1170
1171 return dfsdm_frequency;
1172 }
1173
1174 /**
1175 * @brief Return DFSDMx Audio clock frequency
1176 * @param DFSDMxSource This parameter can be one of the following values:
1177 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1178 * @retval DFSDM clock frequency (in Hz)
1179 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI) is not ready
1180 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)1181 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1182 {
1183 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1184
1185 /* Check parameter */
1186 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1187
1188 /* DFSDM1CLK clock frequency */
1189 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1190 {
1191 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1192 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1193 break;
1194
1195 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */
1196 if (LL_RCC_MSI_IsReady() == 1U)
1197 {
1198 dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1199 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1200 LL_RCC_MSI_GetRange() :
1201 LL_RCC_MSI_GetRangeAfterStandby()));
1202 }
1203 break;
1204
1205 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */
1206 if (LL_RCC_HSI_IsReady() == 1U)
1207 {
1208 dfsdm_frequency = HSI_VALUE;
1209 }
1210 break;
1211
1212 default:
1213 /* unreachable code */
1214 break;
1215 }
1216
1217 return dfsdm_frequency;
1218 }
1219
1220 /**
1221 * @brief Return OCTOSPI clock frequency
1222 * @param OCTOSPIxSource This parameter can be one of the following values:
1223 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
1224 * @retval OCTOSPI clock frequency (in Hz)
1225 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1226 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)1227 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
1228 {
1229 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1230
1231 /* Check parameter */
1232 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
1233
1234 /* OCTOSPI clock frequency */
1235 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
1236 {
1237 case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
1238 octospi_frequency = RCC_GetSystemClockFreq();
1239 break;
1240
1241 case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */
1242 if (LL_RCC_MSI_IsReady() == 1U)
1243 {
1244 octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1245 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1246 LL_RCC_MSI_GetRange() :
1247 LL_RCC_MSI_GetRangeAfterStandby()));
1248 }
1249 break;
1250
1251 case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */
1252 if (LL_RCC_PLL_IsReady() == 1U)
1253 {
1254 if (LL_RCC_PLL_IsEnabledDomain_48M() == 1U)
1255 {
1256 octospi_frequency = RCC_PLL_GetFreqDomain_48M();
1257 }
1258 }
1259 break;
1260
1261 default:
1262 /* unreachable code */
1263 break;
1264 }
1265
1266 return octospi_frequency;
1267 }
1268
1269 /**
1270 * @brief Return FDCAN kernel clock frequency
1271 * @param FDCANxSource This parameter can be one of the following values:
1272 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1273 * @retval FDCAN kernel clock frequency (in Hz)
1274 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSE) or PLL is not ready
1275 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)1276 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1277 {
1278 uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1279
1280 /* Check parameter */
1281 assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
1282
1283 /* FDCAN kernel clock frequency */
1284 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1285 {
1286 case LL_RCC_FDCAN_CLKSOURCE_HSE: /* HSE clock used as FDCAN kernel clock */
1287 if (LL_RCC_HSE_IsReady() == 1U)
1288 {
1289 fdcan_frequency = HSE_VALUE;
1290 }
1291 break;
1292
1293 case LL_RCC_FDCAN_CLKSOURCE_PLL: /* PLL clock used as FDCAN kernel clock */
1294 if (LL_RCC_PLL_IsReady() == 1U)
1295 {
1296 if (LL_RCC_PLL_IsEnabledDomain_48M() == 1U)
1297 {
1298 fdcan_frequency = RCC_PLL_GetFreqDomain_48M();
1299 }
1300 }
1301 break;
1302
1303 case LL_RCC_FDCAN_CLKSOURCE_PLLSAI1: /* MSI clock used as FDCAN kernel clock */
1304 if (LL_RCC_PLLSAI1_IsReady() == 1U)
1305 {
1306 if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() == 1U)
1307 {
1308 fdcan_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
1309 }
1310 }
1311 break;
1312
1313 default:
1314 /* unreachable code */
1315 break;
1316 }
1317
1318 return fdcan_frequency;
1319 }
1320
1321 /**
1322 * @}
1323 */
1324
1325 /**
1326 * @}
1327 */
1328
1329 /** @addtogroup RCC_LL_Private_Functions
1330 * @{
1331 */
1332
1333 /**
1334 * @brief Return SYSTEM clock frequency
1335 * @retval SYSTEM clock frequency (in Hz)
1336 */
RCC_GetSystemClockFreq(void)1337 static uint32_t RCC_GetSystemClockFreq(void)
1338 {
1339 uint32_t frequency;
1340
1341 /* Get SYSCLK source -------------------------------------------------------*/
1342 switch (LL_RCC_GetSysClkSource())
1343 {
1344 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
1345 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1346 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1347 LL_RCC_MSI_GetRange() :
1348 LL_RCC_MSI_GetRangeAfterStandby()));
1349 break;
1350
1351 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1352 frequency = HSI_VALUE;
1353 break;
1354
1355 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1356 frequency = HSE_VALUE;
1357 break;
1358
1359 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1360 frequency = RCC_PLL_GetFreqDomain_SYS();
1361 break;
1362
1363 default:
1364 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1365 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1366 LL_RCC_MSI_GetRange() :
1367 LL_RCC_MSI_GetRangeAfterStandby()));
1368 break;
1369 }
1370
1371 return frequency;
1372 }
1373
1374 /**
1375 * @brief Return HCLK clock frequency
1376 * @param SYSCLK_Frequency SYSCLK clock frequency
1377 * @retval HCLK clock frequency (in Hz)
1378 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1379 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1380 {
1381 /* HCLK clock frequency */
1382 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1383 }
1384
1385 /**
1386 * @brief Return PCLK1 clock frequency
1387 * @param HCLK_Frequency HCLK clock frequency
1388 * @retval PCLK1 clock frequency (in Hz)
1389 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1390 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1391 {
1392 /* PCLK1 clock frequency */
1393 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1394 }
1395
1396 /**
1397 * @brief Return PCLK2 clock frequency
1398 * @param HCLK_Frequency HCLK clock frequency
1399 * @retval PCLK2 clock frequency (in Hz)
1400 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1401 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1402 {
1403 /* PCLK2 clock frequency */
1404 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1405 }
1406
1407 /**
1408 * @brief Return PLL clock frequency used for system domain
1409 * @retval PLL clock frequency (in Hz)
1410 */
RCC_PLL_GetFreqDomain_SYS(void)1411 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1412 {
1413 uint32_t pllinputfreq, pllsource;
1414
1415 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1416 SYSCLK = PLL_VCO / PLLR
1417 */
1418 pllsource = LL_RCC_PLL_GetMainSource();
1419
1420 switch (pllsource)
1421 {
1422 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1423 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1424 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1425 LL_RCC_MSI_GetRange() :
1426 LL_RCC_MSI_GetRangeAfterStandby()));
1427 break;
1428
1429 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1430 pllinputfreq = HSI_VALUE;
1431 break;
1432
1433 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1434 pllinputfreq = HSE_VALUE;
1435 break;
1436
1437 default:
1438 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1439 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1440 LL_RCC_MSI_GetRange() :
1441 LL_RCC_MSI_GetRangeAfterStandby()));
1442 break;
1443 }
1444 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1445 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1446 }
1447 /**
1448 * @brief Return PLL clock frequency used for SAI domain
1449 * @retval PLL clock frequency (in Hz)
1450 */
RCC_PLL_GetFreqDomain_SAI(void)1451 static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1452 {
1453 uint32_t pllinputfreq, plloutputfreq, pllsource;
1454 uint32_t plln, pllpdiv;
1455
1456 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
1457 SAI Domain clock = PLL_VCO / PLLP
1458 */
1459 pllsource = LL_RCC_PLL_GetMainSource();
1460
1461 switch (pllsource)
1462 {
1463 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1464 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1465 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1466 LL_RCC_MSI_GetRange() :
1467 LL_RCC_MSI_GetRangeAfterStandby()));
1468 break;
1469
1470 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1471 pllinputfreq = HSI_VALUE;
1472 break;
1473
1474 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1475 pllinputfreq = HSE_VALUE;
1476 break;
1477
1478 default:
1479 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1480 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1481 LL_RCC_MSI_GetRange() :
1482 LL_RCC_MSI_GetRangeAfterStandby()));
1483 break;
1484 }
1485
1486 plln = LL_RCC_PLL_GetN();
1487 pllpdiv = LL_RCC_PLL_GetP();
1488 if ((plln >= 8U) && (pllpdiv >= LL_RCC_PLLP_DIV_2))
1489 {
1490 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1491 plln, pllpdiv);
1492 }
1493 else
1494 {
1495 plloutputfreq = 0; /* Invalid PLLN or PLLPDIV value */
1496 }
1497 return plloutputfreq;
1498 }
1499
1500 /**
1501 * @brief Return PLL clock frequency used for 48 MHz domain
1502 * @retval PLL clock frequency (in Hz)
1503 */
RCC_PLL_GetFreqDomain_48M(void)1504 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
1505 {
1506 uint32_t pllinputfreq, pllsource;
1507
1508 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1509 48M Domain clock = PLL_VCO / PLLQ
1510 */
1511 pllsource = LL_RCC_PLL_GetMainSource();
1512
1513 switch (pllsource)
1514 {
1515 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1516 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1517 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1518 LL_RCC_MSI_GetRange() :
1519 LL_RCC_MSI_GetRangeAfterStandby()));
1520 break;
1521
1522 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1523 pllinputfreq = HSI_VALUE;
1524 break;
1525
1526 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1527 pllinputfreq = HSE_VALUE;
1528 break;
1529
1530 default:
1531 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1532 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1533 LL_RCC_MSI_GetRange() :
1534 LL_RCC_MSI_GetRangeAfterStandby()));
1535 break;
1536 }
1537 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1538 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1539 }
1540
1541 /**
1542 * @brief Return PLLSAI1 clock frequency used for SAI domain
1543 * @retval PLLSAI1 clock frequency (in Hz)
1544 */
RCC_PLLSAI1_GetFreqDomain_SAI(void)1545 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
1546 {
1547 uint32_t pllinputfreq, plloutputfreq, pllsource;
1548 uint32_t plln, pllpdiv;
1549
1550 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1551 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
1552 pllsource = LL_RCC_PLLSAI1_GetSource();
1553
1554 switch (pllsource)
1555 {
1556 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1557 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1558 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1559 LL_RCC_MSI_GetRange() :
1560 LL_RCC_MSI_GetRangeAfterStandby()));
1561 break;
1562
1563 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1564 pllinputfreq = HSI_VALUE;
1565 break;
1566
1567 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1568 pllinputfreq = HSE_VALUE;
1569 break;
1570
1571 default:
1572 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1573 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1574 LL_RCC_MSI_GetRange() :
1575 LL_RCC_MSI_GetRangeAfterStandby()));
1576 break;
1577 }
1578
1579 plln = LL_RCC_PLLSAI1_GetN();
1580 pllpdiv = LL_RCC_PLLSAI1_GetP();
1581 if ((plln >= 8U) && (pllpdiv >= LL_RCC_PLLSAI1P_DIV_2))
1582 {
1583 plloutputfreq = __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI1_GetDivider(),
1584 plln, pllpdiv);
1585 }
1586 else
1587 {
1588 plloutputfreq = 0; /* Invalid PLLSAI1N or PLLSAI1PDIV value */
1589 }
1590 return plloutputfreq;
1591 }
1592
1593 /**
1594 * @brief Return PLLSAI1 clock frequency used for 48Mhz domain
1595 * @retval PLLSAI1 clock frequency (in Hz)
1596 */
RCC_PLLSAI1_GetFreqDomain_48M(void)1597 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
1598 {
1599 uint32_t pllinputfreq, pllsource;
1600
1601 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1602 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
1603 pllsource = LL_RCC_PLLSAI1_GetSource();
1604
1605 switch (pllsource)
1606 {
1607 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1608 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1609 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1610 LL_RCC_MSI_GetRange() :
1611 LL_RCC_MSI_GetRangeAfterStandby()));
1612 break;
1613
1614 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1615 pllinputfreq = HSI_VALUE;
1616 break;
1617
1618 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1619 pllinputfreq = HSE_VALUE;
1620 break;
1621
1622 default:
1623 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1624 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1625 LL_RCC_MSI_GetRange() :
1626 LL_RCC_MSI_GetRangeAfterStandby()));
1627 break;
1628 }
1629 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI1_GetDivider(),
1630 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
1631 }
1632
1633 /**
1634 * @brief Return PLLSAI1 clock frequency used for ADC domain
1635 * @retval PLLSAI1 clock frequency (in Hz)
1636 */
RCC_PLLSAI1_GetFreqDomain_ADC(void)1637 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
1638 {
1639 uint32_t pllinputfreq, pllsource;
1640
1641 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1642 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
1643 pllsource = LL_RCC_PLLSAI1_GetSource();
1644
1645 switch (pllsource)
1646 {
1647 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1648 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1649 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1650 LL_RCC_MSI_GetRange() :
1651 LL_RCC_MSI_GetRangeAfterStandby()));
1652 break;
1653
1654 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1655 pllinputfreq = HSI_VALUE;
1656 break;
1657
1658 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1659 pllinputfreq = HSE_VALUE;
1660 break;
1661
1662 default:
1663 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1664 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1665 LL_RCC_MSI_GetRange() :
1666 LL_RCC_MSI_GetRangeAfterStandby()));
1667 break;
1668 }
1669 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLLSAI1_GetDivider(),
1670 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
1671 }
1672
1673 /**
1674 * @brief Return PLLSAI2 clock frequency used for SAI domain
1675 * @retval PLLSAI2 clock frequency (in Hz)
1676 */
RCC_PLLSAI2_GetFreqDomain_SAI(void)1677 static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
1678 {
1679 uint32_t pllinputfreq, plloutputfreq, pllsource;
1680 uint32_t plln, pllpdiv;
1681
1682 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1683 /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */
1684 pllsource = LL_RCC_PLLSAI2_GetSource();
1685
1686 switch (pllsource)
1687 {
1688 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1689 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1690 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1691 LL_RCC_MSI_GetRange() :
1692 LL_RCC_MSI_GetRangeAfterStandby()));
1693 break;
1694
1695 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1696 pllinputfreq = HSI_VALUE;
1697 break;
1698
1699 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1700 pllinputfreq = HSE_VALUE;
1701 break;
1702
1703 default:
1704 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1705 ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ?
1706 LL_RCC_MSI_GetRange() :
1707 LL_RCC_MSI_GetRangeAfterStandby()));
1708 break;
1709 }
1710
1711 plln = LL_RCC_PLLSAI2_GetN();
1712 pllpdiv = LL_RCC_PLLSAI2_GetP();
1713 if ((plln >= 8U) && (pllpdiv >= LL_RCC_PLLSAI2P_DIV_2))
1714 {
1715 plloutputfreq = __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1716 plln, pllpdiv);
1717 }
1718 else
1719 {
1720 plloutputfreq = 0; /* Invalid PLLSAI2N or PLLSAI2PDIV value */
1721 }
1722 return plloutputfreq;
1723 }
1724
1725 /**
1726 * @}
1727 */
1728
1729 /**
1730 * @}
1731 */
1732
1733 #endif /* defined(RCC) */
1734
1735 /**
1736 * @}
1737 */
1738
1739 #endif /* USE_FULL_LL_DRIVER */
1740
1741
