1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2019 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file in
14 * the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL CORTEX driver contains a set of generic APIs that can be
24 used by user:
25 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
26 functions
27 (+) Low power mode configuration (SCB register of Cortex-MCU)
28 (+) API to access to MCU info (CPUID register)
29 (+) API to enable fault handler (SHCSR accesses)
30 (+) API to enable and disable the MPU secure and non-secure
31 (+) API to configure the region of MPU secure and non-secure
32 (+) API to configure the attributes region of MPU secure and non-secure
33
34 @endverbatim
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef STM32L5xx_LL_CORTEX_H
40 #define STM32L5xx_LL_CORTEX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l5xx.h"
48
49 /** @addtogroup STM32L5xx_LL_Driver
50 * @{
51 */
52
53 /** @defgroup CORTEX_LL CORTEX
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes
62 * @{
63 */
64 /* Register MPU_RBAR (Cortex-M33) : bits [4:0] */
65 #define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk)
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
75 * @{
76 */
77
78 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
79 * @{
80 */
81 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick
82 clock source */
83 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick
84 clock source */
85 /**
86 * @}
87 */
88
89 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
90 * @{
91 */
92 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
93 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
94 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
95 #define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */
96 /**
97 * @}
98 */
99
100 #if (__MPU_PRESENT == 1)
101 /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
102 * @{
103 */
104 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U
105 #define LL_MPU_CTRL_HARDFAULT_NMI 2U
106 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U
107 #define LL_MPU_CTRL_HFNMI_PRIVDEF 6U
108 /**
109 * @}
110 */
111
112 /** @defgroup CORTEX_LL_MPU_Attributes MPU Attributes
113 * @{
114 */
115 #define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */
116 #define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */
117 #define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */
118 #define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */
119
120 #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */
121 #define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */
122 #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */
123
124 #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */
125 #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */
126
127 #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */
128 #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */
129 #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */
130 #define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */
131 /**
132 * @}
133 */
134
135 /** @defgroup CORTEX_LL_MPU_Region_Enable MPU Region Enable
136 * @{
137 */
138 #define LL_MPU_REGION_ENABLE 1U
139 #define LL_MPU_REGION_DISABLE 0U
140 /**
141 * @}
142 */
143
144 /** @defgroup CORTEX_LL_MPU_Instruction_Access MPU Instruction Access
145 * @{
146 */
147 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos)
148 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos)
149 /**
150 * @}
151 */
152
153 /** @defgroup CORTEX_LL_MPU_Access_Shareable MPU Instruction Access Shareable
154 * @{
155 */
156 #define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos)
157 #define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos)
158 #define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos)
159 /**
160 * @}
161 */
162
163 /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes MPU Region Permission Attributes
164 * @{
165 */
166 #define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos)
167 #define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos)
168 #define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos)
169 #define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos)
170 /**
171 * @}
172 */
173
174 /** @defgroup CORTEX_LL_MPU_Region_Number MPU Region Number
175 * @{
176 */
177 #define LL_MPU_REGION_NUMBER0 0U
178 #define LL_MPU_REGION_NUMBER1 1U
179 #define LL_MPU_REGION_NUMBER2 2U
180 #define LL_MPU_REGION_NUMBER3 3U
181 #define LL_MPU_REGION_NUMBER4 4U
182 #define LL_MPU_REGION_NUMBER5 5U
183 #define LL_MPU_REGION_NUMBER6 6U
184 #define LL_MPU_REGION_NUMBER7 7U
185 /**
186 * @}
187 */
188
189 /** @defgroup CORTEX_LL_MPU_Attributes_Number MPU Memory Attributes Number
190 * @{
191 */
192 #define LL_MPU_ATTRIBUTES_NUMBER0 0U
193 #define LL_MPU_ATTRIBUTES_NUMBER1 1U
194 #define LL_MPU_ATTRIBUTES_NUMBER2 2U
195 #define LL_MPU_ATTRIBUTES_NUMBER3 3U
196 #define LL_MPU_ATTRIBUTES_NUMBER4 4U
197 #define LL_MPU_ATTRIBUTES_NUMBER5 5U
198 #define LL_MPU_ATTRIBUTES_NUMBER6 6U
199 #define LL_MPU_ATTRIBUTES_NUMBER7 7U
200 /**
201 * @}
202 */
203
204 #endif /* __MPU_PRESENT */
205
206 /**
207 * @}
208 */
209
210 /* Exported macro ------------------------------------------------------------*/
211
212 /* Exported functions --------------------------------------------------------*/
213 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
214 * @{
215 */
216
217 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
218 * @brief CORTEX SYSTICK LL module driver
219 * @{
220 */
221
222 /**
223 * @brief This function checks if the Systick counter flag is active or not.
224 * @note It can be used in timeout function on application side.
225 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
226 * @retval State of bit (1 or 0).
227 */
LL_SYSTICK_IsActiveCounterFlag(void)228 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
229 {
230 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
231 }
232
233 /**
234 * @brief Configures the SysTick clock source
235 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
236 * @param Source This parameter can be one of the following values:
237 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
238 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
239 * @retval None
240 */
LL_SYSTICK_SetClkSource(uint32_t Source)241 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
242 {
243 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
244 {
245 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
246 }
247 else
248 {
249 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
250 }
251 }
252
253 /**
254 * @brief Get the SysTick clock source
255 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
256 * @retval Returned value can be one of the following values:
257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
259 */
LL_SYSTICK_GetClkSource(void)260 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
261 {
262 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
263 }
264
265 /**
266 * @brief Enable SysTick exception request
267 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
268 * @retval None
269 */
LL_SYSTICK_EnableIT(void)270 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
271 {
272 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
273 }
274
275 /**
276 * @brief Disable SysTick exception request
277 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
278 * @retval None
279 */
LL_SYSTICK_DisableIT(void)280 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
281 {
282 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
283 }
284
285 /**
286 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
287 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
288 * @retval State of bit (1 or 0).
289 */
LL_SYSTICK_IsEnabledIT(void)290 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
291 {
292 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
293 }
294
295 /**
296 * @}
297 */
298
299 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
300 * @{
301 */
302
303 /**
304 * @brief Processor uses sleep as its low power mode
305 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
306 * @retval None
307 */
LL_LPM_EnableSleep(void)308 __STATIC_INLINE void LL_LPM_EnableSleep(void)
309 {
310 /* Clear SLEEPDEEP bit of Cortex System Control Register */
311 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
312 }
313
314 /**
315 * @brief Processor uses deep sleep as its low power mode
316 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
317 * @retval None
318 */
LL_LPM_EnableDeepSleep(void)319 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
320 {
321 /* Set SLEEPDEEP bit of Cortex System Control Register */
322 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
323 }
324
325 /**
326 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
327 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
328 * empty main application.
329 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
330 * @retval None
331 */
LL_LPM_EnableSleepOnExit(void)332 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
333 {
334 /* Set SLEEPONEXIT bit of Cortex System Control Register */
335 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
336 }
337
338 /**
339 * @brief Do not sleep when returning to Thread mode.
340 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
341 * @retval None
342 */
LL_LPM_DisableSleepOnExit(void)343 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
344 {
345 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
346 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
347 }
348
349 /**
350 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
351 * processor.
352 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
353 * @retval None
354 */
LL_LPM_EnableEventOnPend(void)355 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
356 {
357 /* Set SEVEONPEND bit of Cortex System Control Register */
358 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
359 }
360
361 /**
362 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
363 * excluded
364 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
365 * @retval None
366 */
LL_LPM_DisableEventOnPend(void)367 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
368 {
369 /* Clear SEVEONPEND bit of Cortex System Control Register */
370 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
371 }
372
373 /**
374 * @}
375 */
376
377 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
378 * @{
379 */
380
381 /**
382 * @brief Enable a fault in System handler control register (SHCSR)
383 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n
384 * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n
385 * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n
386 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault
387 * @param Fault This parameter can be a combination of the following values:
388 * @arg @ref LL_HANDLER_FAULT_USG
389 * @arg @ref LL_HANDLER_FAULT_BUS
390 * @arg @ref LL_HANDLER_FAULT_MEM
391 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
392 *
393 * (*) value applicable in secure when the system implements the security.
394 * @retval None
395 */
LL_HANDLER_EnableFault(uint32_t Fault)396 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
397 {
398 /* Enable the system handler fault */
399 SET_BIT(SCB->SHCSR, Fault);
400 }
401
402 /**
403 * @brief Disable a fault in System handler control register (SHCSR)
404 * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n
405 * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n
406 * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n
407 * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault
408 * @param Fault This parameter can be a combination of the following values:
409 * @arg @ref LL_HANDLER_FAULT_USG
410 * @arg @ref LL_HANDLER_FAULT_BUS
411 * @arg @ref LL_HANDLER_FAULT_MEM
412 * @arg @ref LL_HANDLER_FAULT_SECURE (*)
413 *
414 * (*) value applicable in secure when the system implements the security.
415 * @retval None
416 */
LL_HANDLER_DisableFault(uint32_t Fault)417 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
418 {
419 /* Disable the system handler fault */
420 CLEAR_BIT(SCB->SHCSR, Fault);
421 }
422
423 /**
424 * @}
425 */
426
427 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
428 * @{
429 */
430
431 /**
432 * @brief Get Implementer code
433 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
434 * @retval Value should be equal to 0x41 for ARM
435 */
LL_CPUID_GetImplementer(void)436 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
437 {
438 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
439 }
440
441 /**
442 * @brief Get Variant number (The r value in the rnpn product revision identifier)
443 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
444 * @retval Value between 0 and 255 (0x0: revision 0)
445 */
LL_CPUID_GetVariant(void)446 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
447 {
448 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
449 }
450
451 /**
452 * @brief Get Constant number
453 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
454 * @retval Value should be equal to 0xF for Cortex-M33 devices
455 */
LL_CPUID_GetConstant(void)456 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
457 {
458 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
459 }
460
461 /**
462 * @brief Get Part number
463 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
464 * @retval Value should be equal to 0xD21 for Cortex-M33
465 */
LL_CPUID_GetParNo(void)466 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
467 {
468 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
469 }
470
471 /**
472 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
473 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
474 * @retval Value between 0 and 255 (0x1: patch 1)
475 */
LL_CPUID_GetRevision(void)476 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
477 {
478 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
479 }
480
481 /**
482 * @}
483 */
484
485 #if __MPU_PRESENT
486 /** @defgroup CORTEX_LL_EF_MPU MPU
487 * @{
488 */
489
490 /**
491 * @brief Enable MPU with input options
492 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable\n
493 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable\n
494 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable
495 * @param MPU_Control This parameter can be one of the following values:
496 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
497 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
498 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
499 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
500 * @retval None
501 */
LL_MPU_Enable(uint32_t MPU_Control)502 __STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control)
503 {
504 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
505
506 /* Enable the MPU*/
507 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
508
509 /* Follow ARM recommendation with */
510 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
511 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
512 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
513 }
514
515 /**
516 * @brief Disable MPU
517 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable\n
518 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable\n
519 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable
520 * @retval None
521 */
LL_MPU_Disable(void)522 __STATIC_INLINE void LL_MPU_Disable(void)
523 {
524 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
525
526 /* Disable MPU */
527 WRITE_REG(MPU->CTRL, 0U);
528
529 /* Follow ARM recommendation with */
530 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
531 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
532 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
533 }
534
535 /**
536 * @brief Check if MPU is enabled or not
537 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
538 * @retval State of bit (1 or 0).
539 */
LL_MPU_IsEnabled(void)540 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
541 {
542 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
543 }
544
545 /**
546 * @brief Enable a MPU region
547 * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion\n
548 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion
549 * @param Region This parameter can be one of the following values:
550 * @arg @ref LL_MPU_REGION_NUMBER0
551 * @arg @ref LL_MPU_REGION_NUMBER1
552 * @arg @ref LL_MPU_REGION_NUMBER2
553 * @arg @ref LL_MPU_REGION_NUMBER3
554 * @arg @ref LL_MPU_REGION_NUMBER4
555 * @arg @ref LL_MPU_REGION_NUMBER5
556 * @arg @ref LL_MPU_REGION_NUMBER6
557 * @arg @ref LL_MPU_REGION_NUMBER7
558 * @note cortex-M33 supports 8 secure and 8 non secure regions.
559 * @retval None
560 */
LL_MPU_EnableRegion(uint32_t Region)561 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
562 {
563 /* Set Region number */
564 WRITE_REG(MPU->RNR, Region);
565
566 /* Enable the MPU region */
567 SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
568 }
569
570 /**
571 * @brief Check if MPU region is enabled or not
572 * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion\n
573 * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion
574 * @param Region This parameter can be one of the following values:
575 * @arg @ref LL_MPU_REGION_NUMBER0
576 * @arg @ref LL_MPU_REGION_NUMBER1
577 * @arg @ref LL_MPU_REGION_NUMBER2
578 * @arg @ref LL_MPU_REGION_NUMBER3
579 * @arg @ref LL_MPU_REGION_NUMBER4
580 * @arg @ref LL_MPU_REGION_NUMBER5
581 * @arg @ref LL_MPU_REGION_NUMBER6
582 * @arg @ref LL_MPU_REGION_NUMBER7
583 * @note cortex-M33 supports 8 secure and 8 non secure regions.
584 * @retval State of bit (1 or 0).
585 */
LL_MPU_IsEnabledRegion(uint32_t Region)586 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region)
587 {
588 return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL);
589 }
590
591 /**
592 * @brief Disable a MPU region
593 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
594 * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion
595 * @param Region This parameter can be one of the following values:
596 * @arg @ref LL_MPU_REGION_NUMBER0
597 * @arg @ref LL_MPU_REGION_NUMBER1
598 * @arg @ref LL_MPU_REGION_NUMBER2
599 * @arg @ref LL_MPU_REGION_NUMBER3
600 * @arg @ref LL_MPU_REGION_NUMBER4
601 * @arg @ref LL_MPU_REGION_NUMBER5
602 * @arg @ref LL_MPU_REGION_NUMBER6
603 * @arg @ref LL_MPU_REGION_NUMBER7
604 * @note cortex-M33 supports 8 secure and 8 non secure regions.
605 * @retval None
606 */
LL_MPU_DisableRegion(uint32_t Region)607 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
608 {
609 /* Set Region number */
610 WRITE_REG(MPU->RNR, Region);
611
612 /* Disable the MPU region */
613 CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk);
614 }
615
616 /**
617 * @brief Configure and enable a MPU region
618 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
619 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
620 * MPU_RLAR ADDR LL_MPU_ConfigRegion\n
621 * MPU_RBAR XN LL_MPU_ConfigRegion\n
622 * MPU_RBAR AP LL_MPU_ConfigRegion\n
623 * MPU_RBAR SH LL_MPU_ConfigRegion\n
624 * MPU_RLAR EN LL_MPU_ConfigRegion\n
625 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion
626 * @param Region This parameter can be one of the following values:
627 * @arg @ref LL_MPU_REGION_NUMBER0
628 * @arg @ref LL_MPU_REGION_NUMBER1
629 * @arg @ref LL_MPU_REGION_NUMBER2
630 * @arg @ref LL_MPU_REGION_NUMBER3
631 * @arg @ref LL_MPU_REGION_NUMBER4
632 * @arg @ref LL_MPU_REGION_NUMBER5
633 * @arg @ref LL_MPU_REGION_NUMBER6
634 * @arg @ref LL_MPU_REGION_NUMBER7
635 * @param Attributes This parameter can be a combination of the following values:
636 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
637 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
638 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
639 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
640 * or @ref LL_MPU_REGION_ALL_RO
641 * @param AttrIndx This parameter can be one of the following values:
642 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
643 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
644 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
645 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
646 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
647 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
648 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
649 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
650 * @param BaseAddress Value of region base address
651 * @param LimitAddress Value of region limit address
652 * @note cortex-M33 supports 8 secure and 8 non secure regions.
653 * @retval None
654 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)655 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress,
656 uint32_t LimitAddress)
657 {
658 /* Set Region number */
659 WRITE_REG(MPU->RNR, Region);
660
661 /* Set region base address and region access attributes */
662 WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
663
664 /* Set region limit address, memory attributes index and enable region */
665 WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
666 }
667
668 /**
669 * @brief Configure a MPU region address range
670 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n
671 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n
672 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n
673 * @param Region This parameter can be one of the following values:
674 * @arg @ref LL_MPU_REGION_NUMBER0
675 * @arg @ref LL_MPU_REGION_NUMBER1
676 * @arg @ref LL_MPU_REGION_NUMBER2
677 * @arg @ref LL_MPU_REGION_NUMBER3
678 * @arg @ref LL_MPU_REGION_NUMBER4
679 * @arg @ref LL_MPU_REGION_NUMBER5
680 * @arg @ref LL_MPU_REGION_NUMBER6
681 * @arg @ref LL_MPU_REGION_NUMBER7
682 * @param BaseAddress Value of region base address
683 * @param LimitAddress Value of region limit address
684 * @note cortex-M33 supports 8 secure and 8 non secure regions.
685 * @retval None
686 */
LL_MPU_ConfigRegionAddress(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)687 __STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
688 {
689 /* Set Region number */
690 WRITE_REG(MPU->RNR, Region);
691
692 /* Modify region base address */
693 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
694
695 /* Modify region limit address */
696 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
697 }
698
699 /**
700 * @brief Configure a MPU attributes index
701 * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes\n
702 * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes\n
703 * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes\n
704 * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes\n
705 * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes\n
706 * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes\n
707 * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes\n
708 * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes
709 * @param AttIndex This parameter can be one of the following values:
710 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
711 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
712 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
713 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
714 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
715 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
716 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
717 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
718 * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
719 * @retval None
720 */
LL_MPU_ConfigAttributes(uint32_t AttIndex,uint32_t Attributes)721 __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes)
722 {
723 /* When selected index is in range [0;3] */
724 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
725 {
726 /* Modify Attr<i> field of MPU_MAIR0 accordingly */
727 MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
728 }
729 /* When selected index is in range [4;7] */
730 else
731 {
732 /* Modify Attr<i> field of MPU_MAIR1 accordingly */
733 MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
734 }
735 }
736
737 /**
738 * @brief Configure a MPU region base address
739 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n
740 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress
741 * @param Region This parameter can be one of the following values:
742 * @arg @ref LL_MPU_REGION_NUMBER0
743 * @arg @ref LL_MPU_REGION_NUMBER1
744 * @arg @ref LL_MPU_REGION_NUMBER2
745 * @arg @ref LL_MPU_REGION_NUMBER3
746 * @arg @ref LL_MPU_REGION_NUMBER4
747 * @arg @ref LL_MPU_REGION_NUMBER5
748 * @arg @ref LL_MPU_REGION_NUMBER6
749 * @arg @ref LL_MPU_REGION_NUMBER7
750 * @param BaseAddress Value of region base address
751 * @note cortex-M33 supports 8 secure and 8 non secure regions.
752 * @retval None
753 */
LL_MPU_SetRegionBaseAddress(uint32_t Region,uint32_t BaseAddress)754 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress)
755 {
756 /* Set Region number */
757 WRITE_REG(MPU->RNR, Region);
758
759 /* Set base address */
760 MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
761 }
762
763 /**
764 * @brief Get a MPU region base address
765 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n
766 * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress
767 * @param Region This parameter can be one of the following values:
768 * @arg @ref LL_MPU_REGION_NUMBER0
769 * @arg @ref LL_MPU_REGION_NUMBER1
770 * @arg @ref LL_MPU_REGION_NUMBER2
771 * @arg @ref LL_MPU_REGION_NUMBER3
772 * @arg @ref LL_MPU_REGION_NUMBER4
773 * @arg @ref LL_MPU_REGION_NUMBER5
774 * @arg @ref LL_MPU_REGION_NUMBER6
775 * @arg @ref LL_MPU_REGION_NUMBER7
776 * @retval None
777 */
LL_MPU_GetRegionBaseAddress(uint32_t Region)778 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region)
779 {
780 /* Set Region number */
781 WRITE_REG(MPU->RNR, Region);
782
783 return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk));
784 }
785
786 /**
787 * @brief Configure a MPU region limit address
788 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n
789 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress
790 * @param Region This parameter can be one of the following values:
791 * @arg @ref LL_MPU_REGION_NUMBER0
792 * @arg @ref LL_MPU_REGION_NUMBER1
793 * @arg @ref LL_MPU_REGION_NUMBER2
794 * @arg @ref LL_MPU_REGION_NUMBER3
795 * @arg @ref LL_MPU_REGION_NUMBER4
796 * @arg @ref LL_MPU_REGION_NUMBER5
797 * @arg @ref LL_MPU_REGION_NUMBER6
798 * @arg @ref LL_MPU_REGION_NUMBER7
799 * @param LimitAddress Value of region limit address
800 * @note cortex-M33 supports 8 secure and 8 non secure regions.
801 * @retval None
802 */
LL_MPU_SetRegionLimitAddress(uint32_t Region,uint32_t LimitAddress)803 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress)
804 {
805 /* Set Region number */
806 WRITE_REG(MPU->RNR, Region);
807
808 /* Set limit address */
809 MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
810 }
811
812 /**
813 * @brief Get a MPU region limit address
814 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n
815 * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress
816 * @param Region This parameter can be one of the following values:
817 * @arg @ref LL_MPU_REGION_NUMBER0
818 * @arg @ref LL_MPU_REGION_NUMBER1
819 * @arg @ref LL_MPU_REGION_NUMBER2
820 * @arg @ref LL_MPU_REGION_NUMBER3
821 * @arg @ref LL_MPU_REGION_NUMBER4
822 * @arg @ref LL_MPU_REGION_NUMBER5
823 * @arg @ref LL_MPU_REGION_NUMBER6
824 * @arg @ref LL_MPU_REGION_NUMBER7
825 * @retval None
826 */
LL_MPU_GetRegionLimitAddress(uint32_t Region)827 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region)
828 {
829 /* Set Region number */
830 WRITE_REG(MPU->RNR, Region);
831
832 return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk));
833 }
834
835 /**
836 * @brief Configure a MPU region access attributes and enable a region
837 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n
838 * MPU_RBAR XN LL_MPU_SetRegionAccess\n
839 * MPU_RBAR AP LL_MPU_SetRegionAccess\n
840 * MPU_RBAR SH LL_MPU_SetRegionAccess
841 * @param Region This parameter can be one of the following values:
842 * @arg @ref LL_MPU_REGION_NUMBER0
843 * @arg @ref LL_MPU_REGION_NUMBER1
844 * @arg @ref LL_MPU_REGION_NUMBER2
845 * @arg @ref LL_MPU_REGION_NUMBER3
846 * @arg @ref LL_MPU_REGION_NUMBER4
847 * @arg @ref LL_MPU_REGION_NUMBER5
848 * @arg @ref LL_MPU_REGION_NUMBER6
849 * @arg @ref LL_MPU_REGION_NUMBER7
850 * @param Attributes This parameter can be a combination of the following values:
851 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
852 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
853 or @ref LL_MPU_ACCESS_INNER_SHAREABLE
854 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
855 or @ref LL_MPU_REGION_ALL_RO
856 * @note cortex-M33 supports 8 secure and 8 non secure regions.
857 * @retval None
858 */
LL_MPU_SetRegionAccess(uint32_t Region,uint32_t Attributes)859 __STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes)
860 {
861 /* Set Region number */
862 WRITE_REG(MPU->RNR, Region);
863
864 /* Set base address */
865 MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
866 }
867
868 /**
869 * @brief Get a MPU region access attributes
870 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n
871 * MPU_RBAR XN LL_MPU_GetRegionAccess\n
872 * MPU_RBAR AP LL_MPU_GetRegionAccess\n
873 * MPU_RBAR SH LL_MPU_GetRegionAccess
874 * @param Region This parameter can be one of the following values:
875 * @arg @ref LL_MPU_REGION_NUMBER0
876 * @arg @ref LL_MPU_REGION_NUMBER1
877 * @arg @ref LL_MPU_REGION_NUMBER2
878 * @arg @ref LL_MPU_REGION_NUMBER3
879 * @arg @ref LL_MPU_REGION_NUMBER4
880 * @arg @ref LL_MPU_REGION_NUMBER5
881 * @arg @ref LL_MPU_REGION_NUMBER6
882 * @arg @ref LL_MPU_REGION_NUMBER7
883 * @retval None
884 */
LL_MPU_GetRegionAccess(uint32_t Region)885 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region)
886 {
887 /* Set Region number */
888 WRITE_REG(MPU->RNR, Region);
889
890 return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
891 }
892
893 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
894 /**
895 * @brief Enable non-secure MPU with input options
896 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable_NS\n
897 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable_NS\n
898 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable_NS
899 * @param MPU_Control This parameter can be one of the following values:
900 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
901 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
902 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
903 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
904 * @retval None
905 */
LL_MPU_Enable_NS(uint32_t MPU_Control)906 __STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control)
907 {
908 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */
909
910 /* Enable the MPU*/
911 MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control;
912
913 /* Follow ARM recommendation with */
914 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
915 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
916 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
917 }
918
919 /**
920 * @brief Disable non-secure MPU
921 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS\n
922 * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable_NS\n
923 * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable_NS
924 * @retval None
925 */
LL_MPU_Disable_NS(void)926 __STATIC_INLINE void LL_MPU_Disable_NS(void)
927 {
928 __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */
929
930 /* Disable MPU*/
931 WRITE_REG(MPU_NS->CTRL, 0U);
932
933 /* Follow ARM recommendation with */
934 /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */
935 __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */
936 __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */
937 }
938
939 /**
940 * @brief Check if non-secure MPU is enabled or not
941 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS
942 * @retval State of bit (1 or 0).
943 */
LL_MPU_IsEnabled_NS(void)944 __STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void)
945 {
946 return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
947 }
948
949 /**
950 * @brief Enable a non-secure MPU region
951 * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion_NS\n
952 * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS
953 * @param Region This parameter can be one of the following values:
954 * @arg @ref LL_MPU_REGION_NUMBER0
955 * @arg @ref LL_MPU_REGION_NUMBER1
956 * @arg @ref LL_MPU_REGION_NUMBER2
957 * @arg @ref LL_MPU_REGION_NUMBER3
958 * @arg @ref LL_MPU_REGION_NUMBER4
959 * @arg @ref LL_MPU_REGION_NUMBER5
960 * @arg @ref LL_MPU_REGION_NUMBER6
961 * @arg @ref LL_MPU_REGION_NUMBER7
962 * @note cortex-M33 supports 8 secure and 8 non secure regions.
963 * @retval None
964 */
LL_MPU_EnableRegion_NS(uint32_t Region)965 __STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region)
966 {
967 /* Set Region number */
968 WRITE_REG(MPU_NS->RNR, Region);
969
970 /* Enable the MPU region */
971 SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
972 }
973
974 /**
975 * @brief Disable a non-secure MPU region
976 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n
977 * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion_NS
978 * @param Region This parameter can be one of the following values:
979 * @arg @ref LL_MPU_REGION_NUMBER0
980 * @arg @ref LL_MPU_REGION_NUMBER1
981 * @arg @ref LL_MPU_REGION_NUMBER2
982 * @arg @ref LL_MPU_REGION_NUMBER3
983 * @arg @ref LL_MPU_REGION_NUMBER4
984 * @arg @ref LL_MPU_REGION_NUMBER5
985 * @arg @ref LL_MPU_REGION_NUMBER6
986 * @arg @ref LL_MPU_REGION_NUMBER7
987 * @note cortex-M33 supports 8 secure and 8 non secure regions.
988 * @retval None
989 */
LL_MPU_DisableRegion_NS(uint32_t Region)990 __STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region)
991 {
992 /* Set Region number */
993 WRITE_REG(MPU_NS->RNR, Region);
994
995 /* Disable the MPU region */
996 CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk);
997 }
998
999 /**
1000 * @brief Check if non-secure MPU region is enabled or not
1001 * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion_NS\n
1002 * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion_NS
1003 * @param Region This parameter can be one of the following values:
1004 * @arg @ref LL_MPU_REGION_NUMBER0
1005 * @arg @ref LL_MPU_REGION_NUMBER1
1006 * @arg @ref LL_MPU_REGION_NUMBER2
1007 * @arg @ref LL_MPU_REGION_NUMBER3
1008 * @arg @ref LL_MPU_REGION_NUMBER4
1009 * @arg @ref LL_MPU_REGION_NUMBER5
1010 * @arg @ref LL_MPU_REGION_NUMBER6
1011 * @arg @ref LL_MPU_REGION_NUMBER7
1012 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1013 * @retval State of bit (1 or 0).
1014 */
LL_MPU_IsEnabledRegion_NS(uint32_t Region)1015 __STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region)
1016 {
1017 return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL);
1018 }
1019
1020 /**
1021 * @brief Configure and enable a non-secure MPU region
1022 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n
1023 * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n
1024 * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n
1025 * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n
1026 * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n
1027 * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n
1028 * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n
1029 * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS
1030 * @param Region This parameter can be one of the following values:
1031 * @arg @ref LL_MPU_REGION_NUMBER0
1032 * @arg @ref LL_MPU_REGION_NUMBER1
1033 * @arg @ref LL_MPU_REGION_NUMBER2
1034 * @arg @ref LL_MPU_REGION_NUMBER3
1035 * @arg @ref LL_MPU_REGION_NUMBER4
1036 * @arg @ref LL_MPU_REGION_NUMBER5
1037 * @arg @ref LL_MPU_REGION_NUMBER6
1038 * @arg @ref LL_MPU_REGION_NUMBER7
1039 * @param Attributes This parameter can be a combination of the following values:
1040 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1041 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1042 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1043 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1044 * or @ref LL_MPU_REGION_ALL_RO
1045 * @param AttrIndx This parameter can be one of the following values:
1046 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1047 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1048 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1049 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1050 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1051 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1052 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1053 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1054 * @param BaseAddress Value of region base address
1055 * @param LimitAddress Value of region limit address
1056 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1057 * @retval None
1058 */
LL_MPU_ConfigRegion_NS(uint32_t Region,uint32_t Attributes,uint32_t AttrIndx,uint32_t BaseAddress,uint32_t LimitAddress)1059 __STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx,
1060 uint32_t BaseAddress, uint32_t LimitAddress)
1061 {
1062 /* Set Region number */
1063 WRITE_REG(MPU_NS->RNR, Region);
1064
1065 /* Set region base address and region access attributes */
1066 WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes));
1067
1068 /* Set region limit address, memory attributes index and enable region */
1069 WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk));
1070 }
1071
1072 /**
1073 * @brief Configure a non-secure MPU region address range
1074 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n
1075 * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n
1076 * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n
1077 * @param Region This parameter can be one of the following values:
1078 * @arg @ref LL_MPU_REGION_NUMBER0
1079 * @arg @ref LL_MPU_REGION_NUMBER1
1080 * @arg @ref LL_MPU_REGION_NUMBER2
1081 * @arg @ref LL_MPU_REGION_NUMBER3
1082 * @arg @ref LL_MPU_REGION_NUMBER4
1083 * @arg @ref LL_MPU_REGION_NUMBER5
1084 * @arg @ref LL_MPU_REGION_NUMBER6
1085 * @arg @ref LL_MPU_REGION_NUMBER7
1086 * @param BaseAddress Value of region base address
1087 * @param LimitAddress Value of region limit address
1088 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1089 * @retval None
1090 */
LL_MPU_ConfigRegionAddress_NS(uint32_t Region,uint32_t BaseAddress,uint32_t LimitAddress)1091 __STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress)
1092 {
1093 /* Set Region number */
1094 WRITE_REG(MPU_NS->RNR, Region);
1095
1096 /* Set base address */
1097 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1098
1099 /* Set limit address */
1100 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1101 }
1102
1103 /**
1104 * @brief Configure a non-secure MPU attributes index
1105 * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes_NS\n
1106 * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes_NS\n
1107 * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes_NS\n
1108 * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes_NS\n
1109 * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes_NS\n
1110 * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes_NS\n
1111 * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes_NS\n
1112 * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes_NS
1113 * @param AttIndex This parameter can be one of the following values:
1114 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0
1115 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1
1116 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2
1117 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3
1118 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4
1119 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5
1120 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6
1121 * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7
1122 * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF
1123 * @retval None
1124 */
LL_MPU_ConfigAttributes_NS(uint32_t AttIndex,uint32_t Attributes)1125 __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes)
1126 {
1127 /* When selected index is in range [0;3] */
1128 if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4)
1129 {
1130 /* Modify Attr<i> field of MPU_MAIR0_NS accordingly */
1131 MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U)));
1132 }
1133 /* When selected index is in range [4;7] */
1134 else
1135 {
1136 /* Modify Attr<i> field of MPU_MAIR1_NS accordingly */
1137 MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U)));
1138 }
1139 }
1140
1141 /**
1142 * @brief Configure a non-secure MPU region base address
1143 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n
1144 * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS
1145 * @param Region This parameter can be one of the following values:
1146 * @arg @ref LL_MPU_REGION_NUMBER0
1147 * @arg @ref LL_MPU_REGION_NUMBER1
1148 * @arg @ref LL_MPU_REGION_NUMBER2
1149 * @arg @ref LL_MPU_REGION_NUMBER3
1150 * @arg @ref LL_MPU_REGION_NUMBER4
1151 * @arg @ref LL_MPU_REGION_NUMBER5
1152 * @arg @ref LL_MPU_REGION_NUMBER6
1153 * @arg @ref LL_MPU_REGION_NUMBER7
1154 * @param BaseAddress Value of region base address
1155 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1156 * @retval None
1157 */
LL_MPU_SetRegionBaseAddress_NS(uint32_t Region,uint32_t BaseAddress)1158 __STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress)
1159 {
1160 /* Set Region number */
1161 WRITE_REG(MPU_NS->RNR, Region);
1162
1163 /* Set base address */
1164 MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk));
1165 }
1166
1167 /**
1168 * @brief Get a non-secure MPU region base address
1169 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n
1170 * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS
1171 * @param Region This parameter can be one of the following values:
1172 * @arg @ref LL_MPU_REGION_NUMBER0
1173 * @arg @ref LL_MPU_REGION_NUMBER1
1174 * @arg @ref LL_MPU_REGION_NUMBER2
1175 * @arg @ref LL_MPU_REGION_NUMBER3
1176 * @arg @ref LL_MPU_REGION_NUMBER4
1177 * @arg @ref LL_MPU_REGION_NUMBER5
1178 * @arg @ref LL_MPU_REGION_NUMBER6
1179 * @arg @ref LL_MPU_REGION_NUMBER7
1180 * @retval None
1181 */
LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)1182 __STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region)
1183 {
1184 /* Set Region number */
1185 WRITE_REG(MPU_NS->RNR, Region);
1186
1187 return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk));
1188 }
1189
1190 /**
1191 * @brief Configure a non-secure MPU region limit address
1192 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n
1193 * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS
1194 * @param Region This parameter can be one of the following values:
1195 * @arg @ref LL_MPU_REGION_NUMBER0
1196 * @arg @ref LL_MPU_REGION_NUMBER1
1197 * @arg @ref LL_MPU_REGION_NUMBER2
1198 * @arg @ref LL_MPU_REGION_NUMBER3
1199 * @arg @ref LL_MPU_REGION_NUMBER4
1200 * @arg @ref LL_MPU_REGION_NUMBER5
1201 * @arg @ref LL_MPU_REGION_NUMBER6
1202 * @arg @ref LL_MPU_REGION_NUMBER7
1203 * @param LimitAddress Value of region limit address
1204 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1205 * @retval None
1206 */
LL_MPU_SetRegionLimitAddress_NS(uint32_t Region,uint32_t LimitAddress)1207 __STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress)
1208 {
1209 /* Set Region number */
1210 WRITE_REG(MPU_NS->RNR, Region);
1211
1212 /* Set limit address */
1213 MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk));
1214 }
1215
1216 /**
1217 * @brief Get a non-secure MPU region limit address
1218 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n
1219 * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS
1220 * @param Region This parameter can be one of the following values:
1221 * @arg @ref LL_MPU_REGION_NUMBER0
1222 * @arg @ref LL_MPU_REGION_NUMBER1
1223 * @arg @ref LL_MPU_REGION_NUMBER2
1224 * @arg @ref LL_MPU_REGION_NUMBER3
1225 * @arg @ref LL_MPU_REGION_NUMBER4
1226 * @arg @ref LL_MPU_REGION_NUMBER5
1227 * @arg @ref LL_MPU_REGION_NUMBER6
1228 * @arg @ref LL_MPU_REGION_NUMBER7
1229 * @retval None
1230 */
LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)1231 __STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region)
1232 {
1233 /* Set Region number */
1234 WRITE_REG(MPU_NS->RNR, Region);
1235
1236 return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk));
1237 }
1238
1239 /**
1240 * @brief Configure a non-secure MPU region access attributes and enable a region
1241 * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n
1242 * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n
1243 * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n
1244 * MPU_RBAR SH LL_MPU_SetRegionAccess_NS
1245 * @param Region This parameter can be one of the following values:
1246 * @arg @ref LL_MPU_REGION_NUMBER0
1247 * @arg @ref LL_MPU_REGION_NUMBER1
1248 * @arg @ref LL_MPU_REGION_NUMBER2
1249 * @arg @ref LL_MPU_REGION_NUMBER3
1250 * @arg @ref LL_MPU_REGION_NUMBER4
1251 * @arg @ref LL_MPU_REGION_NUMBER5
1252 * @arg @ref LL_MPU_REGION_NUMBER6
1253 * @arg @ref LL_MPU_REGION_NUMBER7
1254 * @param Attributes This parameter can be a combination of the following values:
1255 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
1256 * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE
1257 * or @ref LL_MPU_ACCESS_INNER_SHAREABLE
1258 * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO
1259 * or @ref LL_MPU_REGION_ALL_RO
1260 * @note cortex-M33 supports 8 secure and 8 non secure regions.
1261 * @retval None
1262 */
LL_MPU_SetRegionAccess_NS(uint32_t Region,uint32_t Attributes)1263 __STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes)
1264 {
1265 /* Set Region number */
1266 WRITE_REG(MPU_NS->RNR, Region);
1267
1268 /* Set base address Attributes */
1269 MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK));
1270 }
1271
1272 /**
1273 * @brief Get a non-secure MPU region access attributes
1274 * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n
1275 * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n
1276 * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n
1277 * MPU_RBAR SH LL_MPU_GetRegionAccess_NS
1278 * @param Region This parameter can be one of the following values:
1279 * @arg @ref LL_MPU_REGION_NUMBER0
1280 * @arg @ref LL_MPU_REGION_NUMBER1
1281 * @arg @ref LL_MPU_REGION_NUMBER2
1282 * @arg @ref LL_MPU_REGION_NUMBER3
1283 * @arg @ref LL_MPU_REGION_NUMBER4
1284 * @arg @ref LL_MPU_REGION_NUMBER5
1285 * @arg @ref LL_MPU_REGION_NUMBER6
1286 * @arg @ref LL_MPU_REGION_NUMBER7
1287 * @retval None
1288 */
LL_MPU_GetRegionAccess_NS(uint32_t Region)1289 __STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region)
1290 {
1291 /* Set Region number */
1292 WRITE_REG(MPU_NS->RNR, Region);
1293
1294 return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk)));
1295 }
1296 #endif /* __ARM_FEATURE_CMSE */
1297
1298 /**
1299 * @}
1300 */
1301
1302 #endif /* __MPU_PRESENT */
1303 /**
1304 * @}
1305 */
1306
1307 /**
1308 * @}
1309 */
1310
1311 /**
1312 * @}
1313 */
1314
1315 #ifdef __cplusplus
1316 }
1317 #endif
1318
1319 #endif /* STM32L5xx_LL_CORTEX_H */
1320
1321
