1 /**
2   ******************************************************************************
3   * @file    stm32l422xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32L422xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32l422xx
30   * @{
31   */
32 
33 #ifndef __STM32L422xx_H
34 #define __STM32L422xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32L4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32L4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts         */
80   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
95   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
96   ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
97   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
98   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
99   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
100   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
101   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
102   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
103   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
104   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
105   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
106   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
107   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
108   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
109   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
110   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
111   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
112   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
113   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
114   TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */
115   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
116   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
117   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
118   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
119   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
120   COMP_IRQn                   = 64,     /*!< COMP1 Interrupt                                                   */
121   LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
122   LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
123   USB_IRQn                    = 67,     /*!< USB event Interrupt                                               */
124   DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
125   DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
126   LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
127   QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
128   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
129   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
130   TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
131   AES_IRQn                    = 79,     /*!< AES global interrupt                                              */
132   RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
133   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
134   CRS_IRQn                    = 82      /*!< CRS global interrupt                                              */
135 } IRQn_Type;
136 
137 /**
138   * @}
139   */
140 
141 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
142 #include "system_stm32l4xx.h"
143 #include <stdint.h>
144 
145 /** @addtogroup Peripheral_registers_structures
146   * @{
147   */
148 
149 /**
150   * @brief Analog to Digital Converter
151   */
152 
153 typedef struct
154 {
155   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
156   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
157   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
158   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
159   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
160   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
161   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
162        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
163   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
164   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
165   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
166        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
167   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
168   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
169   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
170   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
171   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
172        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
173        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
174   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
175        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
176   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
177   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
178   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
179   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
180        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
181   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
182   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
183   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
184   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
185        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
186   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
187   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
188        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
189        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
190   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
191   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
192 
193 } ADC_TypeDef;
194 
195 typedef struct
196 {
197   __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
198   uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
199   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
200   __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
201 } ADC_Common_TypeDef;
202 
203 
204 
205 
206 /**
207   * @brief Comparator
208   */
209 
210 typedef struct
211 {
212   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
213 } COMP_TypeDef;
214 
215 typedef struct
216 {
217   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
218 } COMP_Common_TypeDef;
219 
220 /**
221   * @brief CRC calculation unit
222   */
223 
224 typedef struct
225 {
226   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
227   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
228   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
229   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
230   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
231   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
232   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
233   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
234 } CRC_TypeDef;
235 
236 /**
237   * @brief Clock Recovery System
238   */
239 typedef struct
240 {
241 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
242 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
243 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
244 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
245 } CRS_TypeDef;
246 
247 
248 
249 /**
250   * @brief Debug MCU
251   */
252 
253 typedef struct
254 {
255   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
256   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
257   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
258   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
259   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
260 } DBGMCU_TypeDef;
261 
262 
263 /**
264   * @brief DMA Controller
265   */
266 
267 typedef struct
268 {
269   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
270   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
271   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
272   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
273 } DMA_Channel_TypeDef;
274 
275 typedef struct
276 {
277   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
278   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
279 } DMA_TypeDef;
280 
281 typedef struct
282 {
283   __IO uint32_t CSELR;       /*!< DMA channel selection register              */
284 } DMA_Request_TypeDef;
285 
286 /* Legacy define */
287 #define DMA_request_TypeDef  DMA_Request_TypeDef
288 
289 
290 /**
291   * @brief External Interrupt/Event Controller
292   */
293 
294 typedef struct
295 {
296   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
297   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
298   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
299   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
300   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
301   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
302   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
303   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
304   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
305   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
306   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
307   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
308   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
309   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
310 } EXTI_TypeDef;
311 
312 
313 /**
314   * @brief Firewall
315   */
316 
317 typedef struct
318 {
319   __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
320   __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
321   __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
322   __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
323   __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
324   __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
325   uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
326   uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
327   __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
328 } FIREWALL_TypeDef;
329 
330 
331 /**
332   * @brief FLASH Registers
333   */
334 
335 typedef struct
336 {
337   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
338   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
339   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
340   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
341   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
342   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
343   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
344   __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
345   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
346   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
347   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
348   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
349   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
350 } FLASH_TypeDef;
351 
352 
353 
354 /**
355   * @brief General Purpose I/O
356   */
357 
358 typedef struct
359 {
360   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
361   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
362   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
363   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
364   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
365   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
366   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
367   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
368   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
369   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
370 
371 } GPIO_TypeDef;
372 
373 
374 /**
375   * @brief Inter-integrated Circuit Interface
376   */
377 
378 typedef struct
379 {
380   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
381   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
382   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
383   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
384   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
385   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
386   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
387   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
388   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
389   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
390   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
391 } I2C_TypeDef;
392 
393 /**
394   * @brief Independent WATCHDOG
395   */
396 
397 typedef struct
398 {
399   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
400   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
401   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
402   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
403   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
404 } IWDG_TypeDef;
405 
406 /**
407   * @brief LPTIMER
408   */
409 typedef struct
410 {
411   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
412   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
413   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
414   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
415   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
416   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
417   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
418   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
419   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
420   __IO uint32_t RESERVED;    /*!< Reserved,                                           Address offset: 0x24 */
421   __IO uint32_t RCR;         /*!< LPTIM repetition counter register,                  Address offset: 0x28 */
422 } LPTIM_TypeDef;
423 
424 /**
425   * @brief Operational Amplifier (OPAMP)
426   */
427 
428 typedef struct
429 {
430   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
431   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
432   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
433 } OPAMP_TypeDef;
434 
435 typedef struct
436 {
437   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
438 } OPAMP_Common_TypeDef;
439 
440 /**
441   * @brief Power Control
442   */
443 
444 typedef struct
445 {
446   __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
447   __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
448   __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
449   __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
450   __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
451   __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
452   __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
453   uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
454   __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
455   __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
456   __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
457   __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
458   __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
459   __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
460   __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
461   __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
462   __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
463   __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
464   uint32_t RESERVED1;  /*!< Reserved,                            Address offset: 0x48 */
465   uint32_t RESERVED2;  /*!< Reserved,                            Address offset: 0x4C */
466   uint32_t RESERVED3;  /*!< Reserved,                            Address offset: 0x50 */
467   uint32_t RESERVED4;  /*!< Reserved,                            Address offset: 0x54 */
468   __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
469   __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
470 } PWR_TypeDef;
471 
472 
473 /**
474   * @brief QUAD Serial Peripheral Interface
475   */
476 
477 typedef struct
478 {
479   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
480   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
481   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
482   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
483   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
484   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
485   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
486   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
487   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
488   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
489   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
490   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
491   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
492 } QUADSPI_TypeDef;
493 
494 
495 /**
496   * @brief Reset and Clock Control
497   */
498 
499 typedef struct
500 {
501   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
502   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
503   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
504   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
505   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x10 */
506   uint32_t      RESERVED;    /*!< Reserved,                                                                Address offset: 0x14 */
507   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
508   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
509   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
510   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
511   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
512   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
513   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
514   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
515   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
516   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
517   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
518   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
519   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
520   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
521   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
522   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
523   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
524   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
525   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
526   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
527   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
528   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
529   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
530   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
531   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
532   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
533   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
534   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
535   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
536   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
537   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
538   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
539   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
540 } RCC_TypeDef;
541 
542 /**
543   * @brief Real-Time Clock
544   */
545 
546 typedef struct
547 {
548   __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
549   __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
550   __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
551   __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
552   __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
553   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
554   __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
555        uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x1C */
556        uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x20 */
557   __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
558   __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
559   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
560   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
561   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
562   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
563        uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
564   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
565   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
566   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
567   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
568   __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
569   __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
570        uint32_t RESERVED3;   /*!< Reserved,                                       Address offset: 0x58 */
571   __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
572 } RTC_TypeDef;
573 
574 /**
575   * @brief Tamper and backup registers
576   */
577 typedef struct
578 {
579   __IO uint32_t CR1;         /*!< TAMP configuration register 1,            Address offset: 0x00 */
580   __IO uint32_t CR2;         /*!< TAMP configuration register 2,            Address offset: 0x04 */
581        uint32_t RESERVED0;   /*!< Reserved,                                 Address offset: 0x08 */
582   __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
583        uint32_t RESERVED1[7];/*!< Reserved,                                 Address offset: 0x10 -- 0x28 */
584   __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
585   __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
586   __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
587        uint32_t RESERVED2;   /*!< Reserved,                                 Address offset: 0x38 */
588   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
589        uint32_t RESERVED3[48];/*!< Reserved,                                Address offset: 0x40 -- 0xFC */
590   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
591   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
592   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
593   __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
594   __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
595   __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
596   __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
597   __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
598   __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
599   __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
600   __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
601   __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
602   __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
603   __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
604   __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
605   __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
606   __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
607   __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
608   __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
609   __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
610   __IO uint32_t BKP20R;      /*!< TAMP backup register 20,                  Address offset: 0x150 */
611   __IO uint32_t BKP21R;      /*!< TAMP backup register 21,                  Address offset: 0x154 */
612   __IO uint32_t BKP22R;      /*!< TAMP backup register 22,                  Address offset: 0x158 */
613   __IO uint32_t BKP23R;      /*!< TAMP backup register 23,                  Address offset: 0x15C */
614   __IO uint32_t BKP24R;      /*!< TAMP backup register 24,                  Address offset: 0x160 */
615   __IO uint32_t BKP25R;      /*!< TAMP backup register 25,                  Address offset: 0x164 */
616   __IO uint32_t BKP26R;      /*!< TAMP backup register 26,                  Address offset: 0x168 */
617   __IO uint32_t BKP27R;      /*!< TAMP backup register 27,                  Address offset: 0x16C */
618   __IO uint32_t BKP28R;      /*!< TAMP backup register 28,                  Address offset: 0x170 */
619   __IO uint32_t BKP29R;      /*!< TAMP backup register 29,                  Address offset: 0x174 */
620   __IO uint32_t BKP30R;      /*!< TAMP backup register 30,                  Address offset: 0x178 */
621   __IO uint32_t BKP31R;      /*!< TAMP backup register 31,                  Address offset: 0x17C */
622 } TAMP_TypeDef;
623 
624 
625 
626 /**
627   * @brief Serial Peripheral Interface
628   */
629 
630 typedef struct
631 {
632   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
633   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
634   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
635   __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */
636   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
637   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
638   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
639 } SPI_TypeDef;
640 
641 
642 /**
643   * @brief System configuration controller
644   */
645 
646 typedef struct
647 {
648   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
649   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
650   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
651   __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
652   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
653   __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
654   __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
655 } SYSCFG_TypeDef;
656 
657 
658 /**
659   * @brief TIM
660   */
661 
662 typedef struct
663 {
664   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
665   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
666   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
667   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
668   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
669   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
670   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
671   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
672   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
673   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
674   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
675   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
676   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
677   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
678   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
679   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
680   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
681   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
682   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
683   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
684   __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
685   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
686   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
687   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
688   __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
689   __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
690 } TIM_TypeDef;
691 
692 
693 /**
694   * @brief Touch Sensing Controller (TSC)
695   */
696 
697 typedef struct
698 {
699   __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
700   __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
701   __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
702   __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
703   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
704   uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
705   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
706   uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
707   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
708   uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
709   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
710   uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
711   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
712   __IO uint32_t IOGXCR[7];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-4C */
713 } TSC_TypeDef;
714 
715 /**
716   * @brief Universal Synchronous Asynchronous Receiver Transmitter
717   */
718 
719 typedef struct
720 {
721   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
722   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
723   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
724   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
725   __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
726   uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
727   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
728   __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
729   uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
730   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
731   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
732   __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
733   uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
734   __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
735   uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
736 } USART_TypeDef;
737 
738 /**
739   * @brief Universal Serial Bus Full Speed Device
740   */
741 
742 typedef struct
743 {
744   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
745   __IO uint16_t RESERVED0;       /*!< Reserved */
746   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
747   __IO uint16_t RESERVED1;       /*!< Reserved */
748   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
749   __IO uint16_t RESERVED2;       /*!< Reserved */
750   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
751   __IO uint16_t RESERVED3;       /*!< Reserved */
752   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
753   __IO uint16_t RESERVED4;       /*!< Reserved */
754   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
755   __IO uint16_t RESERVED5;       /*!< Reserved */
756   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
757   __IO uint16_t RESERVED6;       /*!< Reserved */
758   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
759   __IO uint16_t RESERVED7[17];   /*!< Reserved */
760   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
761   __IO uint16_t RESERVED8;       /*!< Reserved */
762   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
763   __IO uint16_t RESERVED9;       /*!< Reserved */
764   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
765   __IO uint16_t RESERVEDA;       /*!< Reserved */
766   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
767   __IO uint16_t RESERVEDB;       /*!< Reserved */
768   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
769   __IO uint16_t RESERVEDC;       /*!< Reserved */
770   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
771   __IO uint16_t RESERVEDD;       /*!< Reserved */
772   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
773   __IO uint16_t RESERVEDE;       /*!< Reserved */
774 } USB_TypeDef;
775 
776 
777 /**
778   * @brief Window WATCHDOG
779   */
780 
781 typedef struct
782 {
783   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
784   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
785   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
786 } WWDG_TypeDef;
787 
788 /**
789   * @brief AES hardware accelerator
790   */
791 
792 typedef struct
793 {
794   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
795   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
796   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
797   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
798   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
799   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
800   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
801   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
802   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
803   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
804   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
805   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
806   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
807   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
808   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
809   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
810   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
811   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
812   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
813   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
814   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
815   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
816   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
817   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
818 } AES_TypeDef;
819 
820 /**
821   * @brief RNG
822   */
823 
824 typedef struct
825 {
826   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
827   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
828   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
829 } RNG_TypeDef;
830 
831 /**
832   * @}
833   */
834 
835 /** @addtogroup Peripheral_memory_map
836   * @{
837   */
838 #define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 128 KB) base address */
839 #define FLASH_END             (0x0801FFFFUL) /*!< FLASH END address                */
840 #define FLASH_BANK1_END       (0x0801FFFFUL) /*!< FLASH END address of bank1       */
841 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 32 KB) base address  */
842 #define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(8 KB) base address */
843 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
844 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
845 
846 #define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */
847 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */
848 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
849 
850 /* Legacy defines */
851 #define SRAM_BASE             SRAM1_BASE
852 #define SRAM_BB_BASE          SRAM1_BB_BASE
853 
854 #define SRAM1_SIZE_MAX        (0x00008000UL) /*!< maximum SRAM1 size (up to 32 KBytes) */
855 #define SRAM2_SIZE            (0x00002000UL) /*!< SRAM2 size (8 KBytes) */
856 
857 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
858 
859 #define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) :  \
860                                   (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
861 
862 /*!< Peripheral memory map */
863 #define APB1PERIPH_BASE        PERIPH_BASE
864 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
865 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
866 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
867 
868 
869 /*!< APB1 peripherals */
870 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
871 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
872 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
873 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
874 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
875 #define TAMP_BASE             (APB1PERIPH_BASE + 0x3400U)
876 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
877 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
878 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
879 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
880 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
881 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
882 #define CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
883 #define USB_BASE              (APB1PERIPH_BASE + 0x6800UL)  /*!< USB_IP Peripheral Registers base address */
884 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x6C00UL)  /*!< USB_IP Packet Memory Area base address */
885 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
886 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
887 #define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)
888 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
889 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
890 #define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
891 
892 
893 /*!< APB2 peripherals */
894 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
895 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
896 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
897 #define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)
898 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
899 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
900 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
901 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
902 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
903 
904 /*!< AHB1 peripherals */
905 #define DMA1_BASE             (AHB1PERIPH_BASE)
906 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
907 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
908 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
909 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
910 #define TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)
911 
912 
913 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
914 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
915 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
916 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
917 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
918 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
919 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
920 #define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
921 
922 
923 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
924 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
925 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
926 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
927 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
928 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
929 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
930 #define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
931 
932 
933 /*!< AHB2 peripherals */
934 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
935 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
936 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
937 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
938 #define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)
939 
940 
941 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)
942 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100UL)
943 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08040300UL)
944 
945 
946 #define AES_BASE              (AHB2PERIPH_BASE + 0x08060000UL)
947 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
948 
949 
950 
951 /* Debug MCU registers base address */
952 #define DBGMCU_BASE           (0xE0042000UL)
953 
954 
955 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
956 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
957 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
958 /**
959   * @}
960   */
961 
962 /** @addtogroup Peripheral_declaration
963   * @{
964   */
965 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
966 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
967 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
968 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
969 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
970 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
971 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
972 #define USART2              ((USART_TypeDef *) USART2_BASE)
973 #define USART3              ((USART_TypeDef *) USART3_BASE)
974 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
975 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
976 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
977 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
978 #define USB                 ((USB_TypeDef *) USB_BASE)
979 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
980 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
981 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
982 #define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
983 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
984 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
985 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
986 
987 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
988 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
989 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
990 #define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
991 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
992 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
993 #define USART1              ((USART_TypeDef *) USART1_BASE)
994 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
995 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
996 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
997 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
998 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
999 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1000 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1001 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
1002 
1003 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1004 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1005 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1006 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1007 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1008 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1009 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1010 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1011 #define AES                 ((AES_TypeDef *) AES_BASE)
1012 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1013 
1014 
1015 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1016 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1017 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1018 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1019 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1020 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1021 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1022 #define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1023 
1024 
1025 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1026 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1027 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1028 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1029 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1030 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1031 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1032 #define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1033 
1034 
1035 
1036 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1037 
1038 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1039 
1040 /**
1041   * @}
1042   */
1043 
1044 /** @addtogroup Exported_constants
1045   * @{
1046   */
1047 
1048 /** @addtogroup Hardware_Constant_Definition
1049   * @{
1050   */
1051 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1052 
1053 /**
1054   * @}
1055   */
1056 
1057 /** @addtogroup Peripheral_Registers_Bits_Definition
1058   * @{
1059   */
1060 
1061 /******************************************************************************/
1062 /*                         Peripheral Registers_Bits_Definition               */
1063 /******************************************************************************/
1064 
1065 /******************************************************************************/
1066 /*                                                                            */
1067 /*                        Analog to Digital Converter                         */
1068 /*                                                                            */
1069 /******************************************************************************/
1070 
1071 /*
1072  * @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
1073  */
1074 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1075 
1076 /********************  Bit definition for ADC_ISR register  *******************/
1077 #define ADC_ISR_ADRDY_Pos              (0U)
1078 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1079 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1080 #define ADC_ISR_EOSMP_Pos              (1U)
1081 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1082 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1083 #define ADC_ISR_EOC_Pos                (2U)
1084 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1085 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1086 #define ADC_ISR_EOS_Pos                (3U)
1087 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1088 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1089 #define ADC_ISR_OVR_Pos                (4U)
1090 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1091 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1092 #define ADC_ISR_JEOC_Pos               (5U)
1093 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1094 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1095 #define ADC_ISR_JEOS_Pos               (6U)
1096 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1097 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1098 #define ADC_ISR_AWD1_Pos               (7U)
1099 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1100 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1101 #define ADC_ISR_AWD2_Pos               (8U)
1102 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1103 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1104 #define ADC_ISR_AWD3_Pos               (9U)
1105 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1106 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1107 #define ADC_ISR_JQOVF_Pos              (10U)
1108 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1109 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1110 
1111 /********************  Bit definition for ADC_IER register  *******************/
1112 #define ADC_IER_ADRDYIE_Pos            (0U)
1113 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1114 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1115 #define ADC_IER_EOSMPIE_Pos            (1U)
1116 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1117 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1118 #define ADC_IER_EOCIE_Pos              (2U)
1119 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1120 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1121 #define ADC_IER_EOSIE_Pos              (3U)
1122 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1123 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1124 #define ADC_IER_OVRIE_Pos              (4U)
1125 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1126 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1127 #define ADC_IER_JEOCIE_Pos             (5U)
1128 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1129 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1130 #define ADC_IER_JEOSIE_Pos             (6U)
1131 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1132 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1133 #define ADC_IER_AWD1IE_Pos             (7U)
1134 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1135 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1136 #define ADC_IER_AWD2IE_Pos             (8U)
1137 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1138 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1139 #define ADC_IER_AWD3IE_Pos             (9U)
1140 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1141 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1142 #define ADC_IER_JQOVFIE_Pos            (10U)
1143 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1144 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1145 
1146 /* Legacy defines */
1147 #define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
1148 #define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
1149 #define ADC_IER_EOC             (ADC_IER_EOCIE)
1150 #define ADC_IER_EOS             (ADC_IER_EOSIE)
1151 #define ADC_IER_OVR             (ADC_IER_OVRIE)
1152 #define ADC_IER_JEOC            (ADC_IER_JEOCIE)
1153 #define ADC_IER_JEOS            (ADC_IER_JEOSIE)
1154 #define ADC_IER_AWD1            (ADC_IER_AWD1IE)
1155 #define ADC_IER_AWD2            (ADC_IER_AWD2IE)
1156 #define ADC_IER_AWD3            (ADC_IER_AWD3IE)
1157 #define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
1158 
1159 /********************  Bit definition for ADC_CR register  ********************/
1160 #define ADC_CR_ADEN_Pos                (0U)
1161 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1162 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1163 #define ADC_CR_ADDIS_Pos               (1U)
1164 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1165 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1166 #define ADC_CR_ADSTART_Pos             (2U)
1167 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1168 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1169 #define ADC_CR_JADSTART_Pos            (3U)
1170 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1171 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1172 #define ADC_CR_ADSTP_Pos               (4U)
1173 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1174 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1175 #define ADC_CR_JADSTP_Pos              (5U)
1176 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1177 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1178 #define ADC_CR_ADVREGEN_Pos            (28U)
1179 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1180 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1181 #define ADC_CR_DEEPPWD_Pos             (29U)
1182 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1183 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1184 #define ADC_CR_ADCALDIF_Pos            (30U)
1185 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1186 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1187 #define ADC_CR_ADCAL_Pos               (31U)
1188 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1189 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1190 
1191 /********************  Bit definition for ADC_CFGR register  ******************/
1192 #define ADC_CFGR_DMAEN_Pos             (0U)
1193 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1194 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1195 #define ADC_CFGR_DMACFG_Pos            (1U)
1196 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1197 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1198 
1199 #define ADC_CFGR_RES_Pos               (3U)
1200 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1201 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1202 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1203 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1204 
1205 #define ADC_CFGR_ALIGN_Pos             (5U)
1206 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */
1207 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1208 
1209 #define ADC_CFGR_EXTSEL_Pos            (6U)
1210 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */
1211 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1212 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1213 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1214 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1215 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000200 */
1216 
1217 #define ADC_CFGR_EXTEN_Pos             (10U)
1218 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1219 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1220 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1221 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1222 
1223 #define ADC_CFGR_OVRMOD_Pos            (12U)
1224 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1225 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1226 #define ADC_CFGR_CONT_Pos              (13U)
1227 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1228 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1229 #define ADC_CFGR_AUTDLY_Pos            (14U)
1230 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1231 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1232 
1233 #define ADC_CFGR_DISCEN_Pos            (16U)
1234 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1235 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1236 
1237 #define ADC_CFGR_DISCNUM_Pos           (17U)
1238 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1239 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1240 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1241 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1242 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1243 
1244 #define ADC_CFGR_JDISCEN_Pos           (20U)
1245 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1246 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1247 #define ADC_CFGR_JQM_Pos               (21U)
1248 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1249 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1250 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1251 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1252 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1253 #define ADC_CFGR_AWD1EN_Pos            (23U)
1254 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1255 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1256 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1257 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1258 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1259 #define ADC_CFGR_JAUTO_Pos             (25U)
1260 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1261 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1262 
1263 #define ADC_CFGR_AWD1CH_Pos            (26U)
1264 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1265 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1266 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1267 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1268 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1269 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1270 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1271 
1272 #define ADC_CFGR_JQDIS_Pos             (31U)
1273 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1274 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1275 
1276 /********************  Bit definition for ADC_CFGR2 register  *****************/
1277 #define ADC_CFGR2_ROVSE_Pos            (0U)
1278 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1279 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1280 #define ADC_CFGR2_JOVSE_Pos            (1U)
1281 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1282 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1283 
1284 #define ADC_CFGR2_OVSR_Pos             (2U)
1285 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1286 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1287 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1288 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1289 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1290 
1291 #define ADC_CFGR2_OVSS_Pos             (5U)
1292 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1293 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1294 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1295 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1296 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1297 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1298 
1299 #define ADC_CFGR2_TROVS_Pos            (9U)
1300 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1301 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1302 #define ADC_CFGR2_ROVSM_Pos            (10U)
1303 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1304 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1305 
1306 /********************  Bit definition for ADC_SMPR1 register  *****************/
1307 #define ADC_SMPR1_SMP0_Pos             (0U)
1308 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1309 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1310 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1311 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1312 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1313 
1314 #define ADC_SMPR1_SMP1_Pos             (3U)
1315 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1316 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1317 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1318 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1319 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1320 
1321 #define ADC_SMPR1_SMP2_Pos             (6U)
1322 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1323 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1324 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1325 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1326 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1327 
1328 #define ADC_SMPR1_SMP3_Pos             (9U)
1329 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1330 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1331 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1332 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1333 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1334 
1335 #define ADC_SMPR1_SMP4_Pos             (12U)
1336 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1337 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1338 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1339 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1340 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1341 
1342 #define ADC_SMPR1_SMP5_Pos             (15U)
1343 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1344 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1345 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1346 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1347 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1348 
1349 #define ADC_SMPR1_SMP6_Pos             (18U)
1350 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1351 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1352 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1353 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1354 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1355 
1356 #define ADC_SMPR1_SMP7_Pos             (21U)
1357 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1358 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1359 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1360 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1361 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1362 
1363 #define ADC_SMPR1_SMP8_Pos             (24U)
1364 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1365 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1366 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1367 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1368 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1369 
1370 #define ADC_SMPR1_SMP9_Pos             (27U)
1371 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1372 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1373 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1374 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1375 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1376 
1377 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1378 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1379 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1380 
1381 /********************  Bit definition for ADC_SMPR2 register  *****************/
1382 #define ADC_SMPR2_SMP10_Pos            (0U)
1383 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1384 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1385 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1386 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1387 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1388 
1389 #define ADC_SMPR2_SMP11_Pos            (3U)
1390 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1391 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1392 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1393 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1394 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1395 
1396 #define ADC_SMPR2_SMP12_Pos            (6U)
1397 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1398 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1399 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1400 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1401 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1402 
1403 #define ADC_SMPR2_SMP13_Pos            (9U)
1404 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1405 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1406 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1407 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1408 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1409 
1410 #define ADC_SMPR2_SMP14_Pos            (12U)
1411 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1412 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1413 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1414 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1415 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1416 
1417 #define ADC_SMPR2_SMP15_Pos            (15U)
1418 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1419 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1420 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1421 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1422 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1423 
1424 #define ADC_SMPR2_SMP16_Pos            (18U)
1425 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1426 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1427 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1428 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1429 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1430 
1431 #define ADC_SMPR2_SMP17_Pos            (21U)
1432 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1433 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1434 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1435 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1436 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1437 
1438 #define ADC_SMPR2_SMP18_Pos            (24U)
1439 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1440 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1441 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1442 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1443 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1444 
1445 /********************  Bit definition for ADC_TR1 register  *******************/
1446 #define ADC_TR1_LT1_Pos                (0U)
1447 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1448 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1449 #define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
1450 #define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
1451 #define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
1452 #define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
1453 #define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
1454 #define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
1455 #define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
1456 #define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
1457 #define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
1458 #define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
1459 #define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
1460 #define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
1461 
1462 #define ADC_TR1_HT1_Pos                (16U)
1463 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1464 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
1465 #define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
1466 #define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
1467 #define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
1468 #define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
1469 #define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
1470 #define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
1471 #define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
1472 #define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
1473 #define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
1474 #define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
1475 #define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
1476 #define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
1477 
1478 /********************  Bit definition for ADC_TR2 register  *******************/
1479 #define ADC_TR2_LT2_Pos                (0U)
1480 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1481 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1482 #define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)             /*!< 0x00000001 */
1483 #define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)             /*!< 0x00000002 */
1484 #define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)             /*!< 0x00000004 */
1485 #define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)             /*!< 0x00000008 */
1486 #define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)             /*!< 0x00000010 */
1487 #define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)             /*!< 0x00000020 */
1488 #define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)             /*!< 0x00000040 */
1489 #define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)             /*!< 0x00000080 */
1490 
1491 #define ADC_TR2_HT2_Pos                (16U)
1492 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1493 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1494 #define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)             /*!< 0x00010000 */
1495 #define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)             /*!< 0x00020000 */
1496 #define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)             /*!< 0x00040000 */
1497 #define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)             /*!< 0x00080000 */
1498 #define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)             /*!< 0x00100000 */
1499 #define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)             /*!< 0x00200000 */
1500 #define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)             /*!< 0x00400000 */
1501 #define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)             /*!< 0x00800000 */
1502 
1503 /********************  Bit definition for ADC_TR3 register  *******************/
1504 #define ADC_TR3_LT3_Pos                (0U)
1505 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1506 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1507 #define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)             /*!< 0x00000001 */
1508 #define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)             /*!< 0x00000002 */
1509 #define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)             /*!< 0x00000004 */
1510 #define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)             /*!< 0x00000008 */
1511 #define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)             /*!< 0x00000010 */
1512 #define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)             /*!< 0x00000020 */
1513 #define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)             /*!< 0x00000040 */
1514 #define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)             /*!< 0x00000080 */
1515 
1516 #define ADC_TR3_HT3_Pos                (16U)
1517 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1518 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1519 #define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)             /*!< 0x00010000 */
1520 #define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)             /*!< 0x00020000 */
1521 #define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)             /*!< 0x00040000 */
1522 #define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)             /*!< 0x00080000 */
1523 #define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)             /*!< 0x00100000 */
1524 #define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)             /*!< 0x00200000 */
1525 #define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)             /*!< 0x00400000 */
1526 #define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)             /*!< 0x00800000 */
1527 
1528 /********************  Bit definition for ADC_SQR1 register  ******************/
1529 #define ADC_SQR1_L_Pos                 (0U)
1530 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1531 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1532 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1533 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1534 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1535 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1536 
1537 #define ADC_SQR1_SQ1_Pos               (6U)
1538 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1539 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1540 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1541 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1542 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1543 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1544 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1545 
1546 #define ADC_SQR1_SQ2_Pos               (12U)
1547 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1548 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1549 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1550 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1551 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1552 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1553 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1554 
1555 #define ADC_SQR1_SQ3_Pos               (18U)
1556 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1557 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1558 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1559 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1560 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1561 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1562 #define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
1563 
1564 #define ADC_SQR1_SQ4_Pos               (24U)
1565 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1566 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1567 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1568 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1569 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1570 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1571 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1572 
1573 /********************  Bit definition for ADC_SQR2 register  ******************/
1574 #define ADC_SQR2_SQ5_Pos               (0U)
1575 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1576 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1577 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1578 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1579 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1580 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1581 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1582 
1583 #define ADC_SQR2_SQ6_Pos               (6U)
1584 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1585 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1586 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1587 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1588 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1589 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1590 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1591 
1592 #define ADC_SQR2_SQ7_Pos               (12U)
1593 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1594 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1595 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1596 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1597 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1598 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1599 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1600 
1601 #define ADC_SQR2_SQ8_Pos               (18U)
1602 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1603 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1604 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1605 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1606 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1607 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1608 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1609 
1610 #define ADC_SQR2_SQ9_Pos               (24U)
1611 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1612 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1613 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1614 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1615 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1616 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1617 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1618 
1619 /********************  Bit definition for ADC_SQR3 register  ******************/
1620 #define ADC_SQR3_SQ10_Pos              (0U)
1621 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1622 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1623 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1624 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1625 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1626 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1627 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1628 
1629 #define ADC_SQR3_SQ11_Pos              (6U)
1630 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1631 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1632 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1633 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1634 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1635 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1636 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1637 
1638 #define ADC_SQR3_SQ12_Pos              (12U)
1639 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1640 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1641 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1642 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1643 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1644 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1645 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1646 
1647 #define ADC_SQR3_SQ13_Pos              (18U)
1648 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1649 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1650 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1651 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1652 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1653 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1654 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1655 
1656 #define ADC_SQR3_SQ14_Pos              (24U)
1657 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1658 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1659 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1660 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1661 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1662 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1663 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1664 
1665 /********************  Bit definition for ADC_SQR4 register  ******************/
1666 #define ADC_SQR4_SQ15_Pos              (0U)
1667 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1668 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1669 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1670 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1671 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1672 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1673 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1674 
1675 #define ADC_SQR4_SQ16_Pos              (6U)
1676 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1677 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1678 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1679 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1680 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1681 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1682 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1683 
1684 /********************  Bit definition for ADC_DR register  ********************/
1685 #define ADC_DR_RDATA_Pos               (0U)
1686 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1687 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1688 #define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)          /*!< 0x00000001 */
1689 #define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)          /*!< 0x00000002 */
1690 #define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)          /*!< 0x00000004 */
1691 #define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)          /*!< 0x00000008 */
1692 #define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)          /*!< 0x00000010 */
1693 #define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)          /*!< 0x00000020 */
1694 #define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)          /*!< 0x00000040 */
1695 #define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)          /*!< 0x00000080 */
1696 #define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)          /*!< 0x00000100 */
1697 #define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)          /*!< 0x00000200 */
1698 #define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)          /*!< 0x00000400 */
1699 #define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)          /*!< 0x00000800 */
1700 #define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)          /*!< 0x00001000 */
1701 #define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)          /*!< 0x00002000 */
1702 #define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)          /*!< 0x00004000 */
1703 #define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)          /*!< 0x00008000 */
1704 
1705 /********************  Bit definition for ADC_JSQR register  ******************/
1706 #define ADC_JSQR_JL_Pos                (0U)
1707 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1708 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1709 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1710 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1711 
1712 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1713 #define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x0000003C */
1714 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1715 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1716 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1717 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1718 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1719 
1720 #define ADC_JSQR_JEXTEN_Pos            (6U)
1721 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x000000C0 */
1722 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1723 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000040 */
1724 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1725 
1726 #define ADC_JSQR_JSQ1_Pos              (8U)
1727 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001F00 */
1728 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1729 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000100 */
1730 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1731 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1732 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1733 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1734 
1735 #define ADC_JSQR_JSQ2_Pos              (14U)
1736 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1737 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1738 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1739 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1740 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1741 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1742 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1743 
1744 #define ADC_JSQR_JSQ3_Pos              (20U)
1745 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01F00000 */
1746 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1747 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00100000 */
1748 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
1749 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
1750 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
1751 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
1752 
1753 #define ADC_JSQR_JSQ4_Pos              (26U)
1754 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0x7C000000 */
1755 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1756 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x04000000 */
1757 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
1758 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
1759 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
1760 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
1761 
1762 /********************  Bit definition for ADC_OFR1 register  ******************/
1763 #define ADC_OFR1_OFFSET1_Pos           (0U)
1764 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
1765 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1766 #define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000001 */
1767 #define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000002 */
1768 #define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000004 */
1769 #define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000008 */
1770 #define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000010 */
1771 #define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000020 */
1772 #define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000040 */
1773 #define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000080 */
1774 #define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000100 */
1775 #define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000200 */
1776 #define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000400 */
1777 #define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000800 */
1778 
1779 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1780 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
1781 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1782 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
1783 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
1784 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
1785 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
1786 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
1787 
1788 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1789 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
1790 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1791 
1792 /********************  Bit definition for ADC_OFR2 register  ******************/
1793 #define ADC_OFR2_OFFSET2_Pos           (0U)
1794 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
1795 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1796 #define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000001 */
1797 #define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000002 */
1798 #define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000004 */
1799 #define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000008 */
1800 #define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000010 */
1801 #define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000020 */
1802 #define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000040 */
1803 #define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000080 */
1804 #define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000100 */
1805 #define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000200 */
1806 #define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000400 */
1807 #define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000800 */
1808 
1809 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1810 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
1811 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1812 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
1813 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
1814 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
1815 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
1816 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
1817 
1818 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1819 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
1820 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1821 
1822 /********************  Bit definition for ADC_OFR3 register  ******************/
1823 #define ADC_OFR3_OFFSET3_Pos           (0U)
1824 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
1825 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1826 #define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000001 */
1827 #define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000002 */
1828 #define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000004 */
1829 #define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000008 */
1830 #define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000010 */
1831 #define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000020 */
1832 #define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000040 */
1833 #define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000080 */
1834 #define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000100 */
1835 #define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000200 */
1836 #define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000400 */
1837 #define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000800 */
1838 
1839 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1840 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
1841 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1842 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
1843 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
1844 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
1845 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
1846 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
1847 
1848 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
1849 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
1850 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
1851 
1852 /********************  Bit definition for ADC_OFR4 register  ******************/
1853 #define ADC_OFR4_OFFSET4_Pos           (0U)
1854 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
1855 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
1856 #define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000001 */
1857 #define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000002 */
1858 #define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000004 */
1859 #define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000008 */
1860 #define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000010 */
1861 #define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000020 */
1862 #define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000040 */
1863 #define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000080 */
1864 #define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000100 */
1865 #define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000200 */
1866 #define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000400 */
1867 #define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000800 */
1868 
1869 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
1870 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
1871 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
1872 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
1873 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
1874 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
1875 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
1876 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
1877 
1878 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
1879 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
1880 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
1881 
1882 /********************  Bit definition for ADC_JDR1 register  ******************/
1883 #define ADC_JDR1_JDATA_Pos             (0U)
1884 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
1885 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
1886 #define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000001 */
1887 #define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000002 */
1888 #define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000004 */
1889 #define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000008 */
1890 #define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000010 */
1891 #define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000020 */
1892 #define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000040 */
1893 #define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000080 */
1894 #define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000100 */
1895 #define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000200 */
1896 #define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000400 */
1897 #define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000800 */
1898 #define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00001000 */
1899 #define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00002000 */
1900 #define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00004000 */
1901 #define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00008000 */
1902 
1903 /********************  Bit definition for ADC_JDR2 register  ******************/
1904 #define ADC_JDR2_JDATA_Pos             (0U)
1905 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
1906 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
1907 #define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000001 */
1908 #define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000002 */
1909 #define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000004 */
1910 #define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000008 */
1911 #define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000010 */
1912 #define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000020 */
1913 #define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000040 */
1914 #define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000080 */
1915 #define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000100 */
1916 #define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000200 */
1917 #define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000400 */
1918 #define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000800 */
1919 #define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00001000 */
1920 #define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00002000 */
1921 #define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00004000 */
1922 #define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00008000 */
1923 
1924 /********************  Bit definition for ADC_JDR3 register  ******************/
1925 #define ADC_JDR3_JDATA_Pos             (0U)
1926 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
1927 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
1928 #define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000001 */
1929 #define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000002 */
1930 #define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000004 */
1931 #define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000008 */
1932 #define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000010 */
1933 #define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000020 */
1934 #define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000040 */
1935 #define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000080 */
1936 #define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000100 */
1937 #define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000200 */
1938 #define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000400 */
1939 #define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000800 */
1940 #define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00001000 */
1941 #define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00002000 */
1942 #define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00004000 */
1943 #define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00008000 */
1944 
1945 /********************  Bit definition for ADC_JDR4 register  ******************/
1946 #define ADC_JDR4_JDATA_Pos             (0U)
1947 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
1948 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
1949 #define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000001 */
1950 #define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000002 */
1951 #define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000004 */
1952 #define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000008 */
1953 #define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000010 */
1954 #define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000020 */
1955 #define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000040 */
1956 #define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000080 */
1957 #define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000100 */
1958 #define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000200 */
1959 #define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000400 */
1960 #define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000800 */
1961 #define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00001000 */
1962 #define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00002000 */
1963 #define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00004000 */
1964 #define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00008000 */
1965 
1966 /********************  Bit definition for ADC_AWD2CR register  ****************/
1967 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1968 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1969 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1970 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1971 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1972 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1973 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1974 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1975 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1976 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1977 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1978 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1979 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1980 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1981 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1982 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1983 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1984 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1985 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1986 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1987 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1988 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1989 
1990 /********************  Bit definition for ADC_AWD3CR register  ****************/
1991 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1992 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1993 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1994 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1995 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1996 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1997 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1998 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1999 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2000 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2001 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2002 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2003 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2004 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2005 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2006 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2007 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2008 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2009 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2010 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2011 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2012 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2013 
2014 /********************  Bit definition for ADC_DIFSEL register  ****************/
2015 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2016 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2017 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2018 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2019 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2020 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2021 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2022 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2023 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2024 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2025 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2026 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2027 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2028 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2029 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2030 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2031 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2032 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2033 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2034 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2035 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2036 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2037 
2038 /********************  Bit definition for ADC_CALFACT register  ***************/
2039 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2040 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2041 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2042 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2043 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2044 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2045 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2046 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2047 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2048 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
2049 
2050 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2051 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2052 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2053 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2054 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2055 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2056 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2057 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2058 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2059 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
2060 
2061 /*************************  ADC Common registers  *****************************/
2062 /********************  Bit definition for ADC_CSR register  *******************/
2063 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2064 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2065 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2066 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2067 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2068 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2069 #define ADC_CSR_EOC_MST_Pos            (2U)
2070 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2071 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2072 #define ADC_CSR_EOS_MST_Pos            (3U)
2073 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2074 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2075 #define ADC_CSR_OVR_MST_Pos            (4U)
2076 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2077 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2078 #define ADC_CSR_JEOC_MST_Pos           (5U)
2079 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2080 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2081 #define ADC_CSR_JEOS_MST_Pos           (6U)
2082 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2083 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2084 #define ADC_CSR_AWD1_MST_Pos           (7U)
2085 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2086 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2087 #define ADC_CSR_AWD2_MST_Pos           (8U)
2088 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2089 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2090 #define ADC_CSR_AWD3_MST_Pos           (9U)
2091 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2092 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2093 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2094 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2095 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2096 
2097 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2098 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2099 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2100 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2101 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2102 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2103 #define ADC_CSR_EOC_SLV_Pos            (18U)
2104 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2105 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2106 #define ADC_CSR_EOS_SLV_Pos            (19U)
2107 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2108 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2109 #define ADC_CSR_OVR_SLV_Pos            (20U)
2110 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2111 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2112 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2113 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2114 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2115 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2116 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2117 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2118 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2119 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2120 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2121 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2122 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2123 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2124 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2125 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2126 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2127 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2128 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2129 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2130 
2131 /********************  Bit definition for ADC_CCR register  *******************/
2132 #define ADC_CCR_DUAL_Pos               (0U)
2133 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2134 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2135 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2136 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2137 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2138 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2139 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2140 
2141 #define ADC_CCR_DELAY_Pos              (8U)
2142 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2143 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2144 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2145 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2146 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2147 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2148 
2149 #define ADC_CCR_DMACFG_Pos             (13U)
2150 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2151 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2152 
2153 #define ADC_CCR_MDMA_Pos               (14U)
2154 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2155 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2156 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2157 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2158 
2159 #define ADC_CCR_CKMODE_Pos             (16U)
2160 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2161 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2162 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2163 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2164 
2165 #define ADC_CCR_PRESC_Pos              (18U)
2166 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2167 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2168 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2169 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2170 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2171 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2172 
2173 #define ADC_CCR_VREFEN_Pos             (22U)
2174 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2175 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2176 #define ADC_CCR_TSEN_Pos               (23U)
2177 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
2178 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2179 #define ADC_CCR_VBATEN_Pos             (24U)
2180 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
2181 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2182 
2183 /********************  Bit definition for ADC_CDR register  *******************/
2184 #define ADC_CDR_RDATA_MST_Pos          (0U)
2185 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2186 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2187 #define ADC_CDR_RDATA_MST_0            (0x0001UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000001 */
2188 #define ADC_CDR_RDATA_MST_1            (0x0002UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000002 */
2189 #define ADC_CDR_RDATA_MST_2            (0x0004UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000004 */
2190 #define ADC_CDR_RDATA_MST_3            (0x0008UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000008 */
2191 #define ADC_CDR_RDATA_MST_4            (0x0010UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000010 */
2192 #define ADC_CDR_RDATA_MST_5            (0x0020UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000020 */
2193 #define ADC_CDR_RDATA_MST_6            (0x0040UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000040 */
2194 #define ADC_CDR_RDATA_MST_7            (0x0080UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000080 */
2195 #define ADC_CDR_RDATA_MST_8            (0x0100UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000100 */
2196 #define ADC_CDR_RDATA_MST_9            (0x0200UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000200 */
2197 #define ADC_CDR_RDATA_MST_10           (0x0400UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000400 */
2198 #define ADC_CDR_RDATA_MST_11           (0x0800UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000800 */
2199 #define ADC_CDR_RDATA_MST_12           (0x1000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00001000 */
2200 #define ADC_CDR_RDATA_MST_13           (0x2000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00002000 */
2201 #define ADC_CDR_RDATA_MST_14           (0x4000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00004000 */
2202 #define ADC_CDR_RDATA_MST_15           (0x8000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00008000 */
2203 
2204 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2205 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2206 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2207 #define ADC_CDR_RDATA_SLV_0            (0x0001UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00010000 */
2208 #define ADC_CDR_RDATA_SLV_1            (0x0002UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00020000 */
2209 #define ADC_CDR_RDATA_SLV_2            (0x0004UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00040000 */
2210 #define ADC_CDR_RDATA_SLV_3            (0x0008UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00080000 */
2211 #define ADC_CDR_RDATA_SLV_4            (0x0010UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00100000 */
2212 #define ADC_CDR_RDATA_SLV_5            (0x0020UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00200000 */
2213 #define ADC_CDR_RDATA_SLV_6            (0x0040UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00400000 */
2214 #define ADC_CDR_RDATA_SLV_7            (0x0080UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00800000 */
2215 #define ADC_CDR_RDATA_SLV_8            (0x0100UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x01000000 */
2216 #define ADC_CDR_RDATA_SLV_9            (0x0200UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x02000000 */
2217 #define ADC_CDR_RDATA_SLV_10           (0x0400UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x04000000 */
2218 #define ADC_CDR_RDATA_SLV_11           (0x0800UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x08000000 */
2219 #define ADC_CDR_RDATA_SLV_12           (0x1000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x10000000 */
2220 #define ADC_CDR_RDATA_SLV_13           (0x2000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x20000000 */
2221 #define ADC_CDR_RDATA_SLV_14           (0x4000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x40000000 */
2222 #define ADC_CDR_RDATA_SLV_15           (0x8000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x80000000 */
2223 
2224 
2225 /******************************************************************************/
2226 /*                                                                            */
2227 /*                          CRC calculation unit                              */
2228 /*                                                                            */
2229 /******************************************************************************/
2230 /*******************  Bit definition for CRC_DR register  *********************/
2231 #define CRC_DR_DR_Pos            (0U)
2232 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2233 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2234 
2235 /*******************  Bit definition for CRC_IDR register  ********************/
2236 #define CRC_IDR_IDR_Pos          (0U)
2237 #define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
2238 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
2239 
2240 /********************  Bit definition for CRC_CR register  ********************/
2241 #define CRC_CR_RESET_Pos         (0U)
2242 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2243 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2244 #define CRC_CR_POLYSIZE_Pos      (3U)
2245 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2246 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2247 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2248 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2249 #define CRC_CR_REV_IN_Pos        (5U)
2250 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2251 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2252 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2253 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2254 #define CRC_CR_REV_OUT_Pos       (7U)
2255 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2256 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2257 
2258 /*******************  Bit definition for CRC_INIT register  *******************/
2259 #define CRC_INIT_INIT_Pos        (0U)
2260 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2261 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2262 
2263 /*******************  Bit definition for CRC_POL register  ********************/
2264 #define CRC_POL_POL_Pos          (0U)
2265 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2266 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2267 
2268 /******************************************************************************/
2269 /*                                                                            */
2270 /*                          CRS Clock Recovery System                         */
2271 /******************************************************************************/
2272 
2273 /*******************  Bit definition for CRS_CR register  *********************/
2274 #define CRS_CR_SYNCOKIE_Pos       (0U)
2275 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2276 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2277 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2278 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2279 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2280 #define CRS_CR_ERRIE_Pos          (2U)
2281 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2282 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2283 #define CRS_CR_ESYNCIE_Pos        (3U)
2284 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2285 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2286 #define CRS_CR_CEN_Pos            (5U)
2287 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2288 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2289 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2290 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2291 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2292 #define CRS_CR_SWSYNC_Pos         (7U)
2293 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2294 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2295 #define CRS_CR_TRIM_Pos           (8U)
2296 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2297 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< TRIM[6:0] HSI48 oscillator smooth trimming */
2298 #define CRS_CR_TRIM_0             (0x01UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000100 */
2299 #define CRS_CR_TRIM_1             (0x02UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000200 */
2300 #define CRS_CR_TRIM_2             (0x04UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000400 */
2301 #define CRS_CR_TRIM_3             (0x08UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000800 */
2302 #define CRS_CR_TRIM_4             (0x10UL << CRS_CR_TRIM_Pos)                  /*!< 0x00001000 */
2303 #define CRS_CR_TRIM_5             (0x20UL << CRS_CR_TRIM_Pos)                  /*!< 0x00002000 */
2304 #define CRS_CR_TRIM_6             (0x40UL << CRS_CR_TRIM_Pos)                  /*!< 0x00004000 */
2305 
2306 /*******************  Bit definition for CRS_CFGR register  *********************/
2307 #define CRS_CFGR_RELOAD_Pos       (0U)
2308 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2309 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2310 #define CRS_CFGR_FELIM_Pos        (16U)
2311 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2312 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2313 
2314 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2315 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2316 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2317 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2318 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2319 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2320 
2321 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2322 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2323 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2324 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2325 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2326 
2327 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2328 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2329 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2330 
2331 /*******************  Bit definition for CRS_ISR register  *********************/
2332 #define CRS_ISR_SYNCOKF_Pos       (0U)
2333 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2334 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2335 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2336 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2337 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2338 #define CRS_ISR_ERRF_Pos          (2U)
2339 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2340 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2341 #define CRS_ISR_ESYNCF_Pos        (3U)
2342 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2343 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2344 #define CRS_ISR_SYNCERR_Pos       (8U)
2345 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2346 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2347 #define CRS_ISR_SYNCMISS_Pos      (9U)
2348 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2349 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2350 #define CRS_ISR_TRIMOVF_Pos       (10U)
2351 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2352 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2353 #define CRS_ISR_FEDIR_Pos         (15U)
2354 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2355 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2356 #define CRS_ISR_FECAP_Pos         (16U)
2357 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2358 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2359 
2360 /*******************  Bit definition for CRS_ICR register  *********************/
2361 #define CRS_ICR_SYNCOKC_Pos       (0U)
2362 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2363 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2364 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2365 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2366 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2367 #define CRS_ICR_ERRC_Pos          (2U)
2368 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2369 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2370 #define CRS_ICR_ESYNCC_Pos        (3U)
2371 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2372 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2373 
2374 /******************************************************************************/
2375 /*                                                                            */
2376 /*                       Advanced Encryption Standard (AES)                   */
2377 /*                                                                            */
2378 /******************************************************************************/
2379 /*******************  Bit definition for AES_CR register  *********************/
2380 #define AES_CR_EN_Pos            (0U)
2381 #define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
2382 #define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
2383 #define AES_CR_DATATYPE_Pos      (1U)
2384 #define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
2385 #define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
2386 #define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000002 */
2387 #define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000004 */
2388 
2389 #define AES_CR_MODE_Pos          (3U)
2390 #define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
2391 #define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
2392 #define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                    /*!< 0x00000008 */
2393 #define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                    /*!< 0x00000010 */
2394 
2395 #define AES_CR_CHMOD_Pos         (5U)
2396 #define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
2397 #define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
2398 #define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000020 */
2399 #define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000040 */
2400 #define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010000 */
2401 
2402 #define AES_CR_CCFC_Pos          (7U)
2403 #define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
2404 #define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
2405 #define AES_CR_ERRC_Pos          (8U)
2406 #define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
2407 #define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
2408 #define AES_CR_CCFIE_Pos         (9U)
2409 #define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
2410 #define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
2411 #define AES_CR_ERRIE_Pos         (10U)
2412 #define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
2413 #define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
2414 #define AES_CR_DMAINEN_Pos       (11U)
2415 #define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
2416 #define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
2417 #define AES_CR_DMAOUTEN_Pos      (12U)
2418 #define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
2419 #define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
2420 
2421 #define AES_CR_GCMPH_Pos         (13U)
2422 #define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
2423 #define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
2424 #define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                   /*!< 0x00002000 */
2425 #define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                   /*!< 0x00004000 */
2426 
2427 #define AES_CR_KEYSIZE_Pos       (18U)
2428 #define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
2429 #define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
2430 
2431 /*******************  Bit definition for AES_SR register  *********************/
2432 #define AES_SR_CCF_Pos           (0U)
2433 #define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
2434 #define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
2435 #define AES_SR_RDERR_Pos         (1U)
2436 #define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
2437 #define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
2438 #define AES_SR_WRERR_Pos         (2U)
2439 #define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
2440 #define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
2441 #define AES_SR_BUSY_Pos          (3U)
2442 #define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
2443 #define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
2444 
2445 /*******************  Bit definition for AES_DINR register  *******************/
2446 #define AES_DINR_Pos             (0U)
2447 #define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
2448 #define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
2449 
2450 /*******************  Bit definition for AES_DOUTR register  ******************/
2451 #define AES_DOUTR_Pos            (0U)
2452 #define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
2453 #define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
2454 
2455 /*******************  Bit definition for AES_KEYR0 register  ******************/
2456 #define AES_KEYR0_Pos            (0U)
2457 #define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
2458 #define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
2459 
2460 /*******************  Bit definition for AES_KEYR1 register  ******************/
2461 #define AES_KEYR1_Pos            (0U)
2462 #define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
2463 #define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
2464 
2465 /*******************  Bit definition for AES_KEYR2 register  ******************/
2466 #define AES_KEYR2_Pos            (0U)
2467 #define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
2468 #define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
2469 
2470 /*******************  Bit definition for AES_KEYR3 register  ******************/
2471 #define AES_KEYR3_Pos            (0U)
2472 #define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
2473 #define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
2474 
2475 /*******************  Bit definition for AES_KEYR4 register  ******************/
2476 #define AES_KEYR4_Pos            (0U)
2477 #define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
2478 #define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
2479 
2480 /*******************  Bit definition for AES_KEYR5 register  ******************/
2481 #define AES_KEYR5_Pos            (0U)
2482 #define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
2483 #define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
2484 
2485 /*******************  Bit definition for AES_KEYR6 register  ******************/
2486 #define AES_KEYR6_Pos            (0U)
2487 #define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
2488 #define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
2489 
2490 /*******************  Bit definition for AES_KEYR7 register  ******************/
2491 #define AES_KEYR7_Pos            (0U)
2492 #define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
2493 #define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
2494 
2495 /*******************  Bit definition for AES_IVR0 register   ******************/
2496 #define AES_IVR0_Pos             (0U)
2497 #define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
2498 #define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
2499 
2500 /*******************  Bit definition for AES_IVR1 register   ******************/
2501 #define AES_IVR1_Pos             (0U)
2502 #define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
2503 #define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
2504 
2505 /*******************  Bit definition for AES_IVR2 register   ******************/
2506 #define AES_IVR2_Pos             (0U)
2507 #define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
2508 #define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
2509 
2510 /*******************  Bit definition for AES_IVR3 register   ******************/
2511 #define AES_IVR3_Pos             (0U)
2512 #define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
2513 #define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
2514 
2515 /*******************  Bit definition for AES_SUSP0R register  ******************/
2516 #define AES_SUSP0R_Pos           (0U)
2517 #define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
2518 #define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
2519 
2520 /*******************  Bit definition for AES_SUSP1R register  ******************/
2521 #define AES_SUSP1R_Pos           (0U)
2522 #define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
2523 #define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
2524 
2525 /*******************  Bit definition for AES_SUSP2R register  ******************/
2526 #define AES_SUSP2R_Pos           (0U)
2527 #define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
2528 #define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
2529 
2530 /*******************  Bit definition for AES_SUSP3R register  ******************/
2531 #define AES_SUSP3R_Pos           (0U)
2532 #define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
2533 #define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
2534 
2535 /*******************  Bit definition for AES_SUSP4R register  ******************/
2536 #define AES_SUSP4R_Pos           (0U)
2537 #define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
2538 #define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
2539 
2540 /*******************  Bit definition for AES_SUSP5R register  ******************/
2541 #define AES_SUSP5R_Pos           (0U)
2542 #define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
2543 #define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
2544 
2545 /*******************  Bit definition for AES_SUSP6R register  ******************/
2546 #define AES_SUSP6R_Pos           (0U)
2547 #define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
2548 #define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
2549 
2550 /*******************  Bit definition for AES_SUSP7R register  ******************/
2551 #define AES_SUSP7R_Pos           (0U)
2552 #define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
2553 #define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
2554 
2555 
2556 /******************************************************************************/
2557 /*                                                                            */
2558 /*                           DMA Controller (DMA)                             */
2559 /*                                                                            */
2560 /******************************************************************************/
2561 
2562 /*******************  Bit definition for DMA_ISR register  ********************/
2563 #define DMA_ISR_GIF1_Pos       (0U)
2564 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
2565 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
2566 #define DMA_ISR_TCIF1_Pos      (1U)
2567 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
2568 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
2569 #define DMA_ISR_HTIF1_Pos      (2U)
2570 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
2571 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
2572 #define DMA_ISR_TEIF1_Pos      (3U)
2573 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
2574 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
2575 #define DMA_ISR_GIF2_Pos       (4U)
2576 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
2577 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
2578 #define DMA_ISR_TCIF2_Pos      (5U)
2579 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
2580 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
2581 #define DMA_ISR_HTIF2_Pos      (6U)
2582 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
2583 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
2584 #define DMA_ISR_TEIF2_Pos      (7U)
2585 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
2586 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
2587 #define DMA_ISR_GIF3_Pos       (8U)
2588 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
2589 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
2590 #define DMA_ISR_TCIF3_Pos      (9U)
2591 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
2592 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
2593 #define DMA_ISR_HTIF3_Pos      (10U)
2594 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
2595 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
2596 #define DMA_ISR_TEIF3_Pos      (11U)
2597 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
2598 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
2599 #define DMA_ISR_GIF4_Pos       (12U)
2600 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
2601 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
2602 #define DMA_ISR_TCIF4_Pos      (13U)
2603 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
2604 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
2605 #define DMA_ISR_HTIF4_Pos      (14U)
2606 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
2607 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
2608 #define DMA_ISR_TEIF4_Pos      (15U)
2609 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
2610 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
2611 #define DMA_ISR_GIF5_Pos       (16U)
2612 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
2613 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
2614 #define DMA_ISR_TCIF5_Pos      (17U)
2615 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
2616 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
2617 #define DMA_ISR_HTIF5_Pos      (18U)
2618 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
2619 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
2620 #define DMA_ISR_TEIF5_Pos      (19U)
2621 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
2622 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
2623 #define DMA_ISR_GIF6_Pos       (20U)
2624 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
2625 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
2626 #define DMA_ISR_TCIF6_Pos      (21U)
2627 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
2628 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
2629 #define DMA_ISR_HTIF6_Pos      (22U)
2630 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
2631 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
2632 #define DMA_ISR_TEIF6_Pos      (23U)
2633 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
2634 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
2635 #define DMA_ISR_GIF7_Pos       (24U)
2636 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
2637 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
2638 #define DMA_ISR_TCIF7_Pos      (25U)
2639 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
2640 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
2641 #define DMA_ISR_HTIF7_Pos      (26U)
2642 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
2643 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
2644 #define DMA_ISR_TEIF7_Pos      (27U)
2645 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
2646 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
2647 
2648 /*******************  Bit definition for DMA_IFCR register  *******************/
2649 #define DMA_IFCR_CGIF1_Pos     (0U)
2650 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
2651 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
2652 #define DMA_IFCR_CTCIF1_Pos    (1U)
2653 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
2654 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
2655 #define DMA_IFCR_CHTIF1_Pos    (2U)
2656 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
2657 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
2658 #define DMA_IFCR_CTEIF1_Pos    (3U)
2659 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
2660 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
2661 #define DMA_IFCR_CGIF2_Pos     (4U)
2662 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
2663 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
2664 #define DMA_IFCR_CTCIF2_Pos    (5U)
2665 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
2666 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
2667 #define DMA_IFCR_CHTIF2_Pos    (6U)
2668 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
2669 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
2670 #define DMA_IFCR_CTEIF2_Pos    (7U)
2671 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
2672 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
2673 #define DMA_IFCR_CGIF3_Pos     (8U)
2674 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
2675 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
2676 #define DMA_IFCR_CTCIF3_Pos    (9U)
2677 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
2678 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
2679 #define DMA_IFCR_CHTIF3_Pos    (10U)
2680 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
2681 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
2682 #define DMA_IFCR_CTEIF3_Pos    (11U)
2683 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
2684 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
2685 #define DMA_IFCR_CGIF4_Pos     (12U)
2686 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
2687 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
2688 #define DMA_IFCR_CTCIF4_Pos    (13U)
2689 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
2690 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
2691 #define DMA_IFCR_CHTIF4_Pos    (14U)
2692 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
2693 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
2694 #define DMA_IFCR_CTEIF4_Pos    (15U)
2695 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
2696 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
2697 #define DMA_IFCR_CGIF5_Pos     (16U)
2698 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
2699 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
2700 #define DMA_IFCR_CTCIF5_Pos    (17U)
2701 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
2702 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
2703 #define DMA_IFCR_CHTIF5_Pos    (18U)
2704 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
2705 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
2706 #define DMA_IFCR_CTEIF5_Pos    (19U)
2707 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
2708 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
2709 #define DMA_IFCR_CGIF6_Pos     (20U)
2710 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
2711 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
2712 #define DMA_IFCR_CTCIF6_Pos    (21U)
2713 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
2714 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
2715 #define DMA_IFCR_CHTIF6_Pos    (22U)
2716 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
2717 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
2718 #define DMA_IFCR_CTEIF6_Pos    (23U)
2719 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
2720 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
2721 #define DMA_IFCR_CGIF7_Pos     (24U)
2722 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
2723 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
2724 #define DMA_IFCR_CTCIF7_Pos    (25U)
2725 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
2726 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
2727 #define DMA_IFCR_CHTIF7_Pos    (26U)
2728 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
2729 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
2730 #define DMA_IFCR_CTEIF7_Pos    (27U)
2731 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
2732 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
2733 
2734 /*******************  Bit definition for DMA_CCR register  ********************/
2735 #define DMA_CCR_EN_Pos         (0U)
2736 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2737 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2738 #define DMA_CCR_TCIE_Pos       (1U)
2739 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2740 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2741 #define DMA_CCR_HTIE_Pos       (2U)
2742 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2743 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2744 #define DMA_CCR_TEIE_Pos       (3U)
2745 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2746 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2747 #define DMA_CCR_DIR_Pos        (4U)
2748 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2749 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2750 #define DMA_CCR_CIRC_Pos       (5U)
2751 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2752 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2753 #define DMA_CCR_PINC_Pos       (6U)
2754 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2755 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2756 #define DMA_CCR_MINC_Pos       (7U)
2757 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2758 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2759 
2760 #define DMA_CCR_PSIZE_Pos      (8U)
2761 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2762 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2763 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
2764 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
2765 
2766 #define DMA_CCR_MSIZE_Pos      (10U)
2767 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2768 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2769 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
2770 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
2771 
2772 #define DMA_CCR_PL_Pos         (12U)
2773 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2774 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2775 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
2776 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
2777 
2778 #define DMA_CCR_MEM2MEM_Pos    (14U)
2779 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2780 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2781 
2782 /******************  Bit definition for DMA_CNDTR register  *******************/
2783 #define DMA_CNDTR_NDT_Pos      (0U)
2784 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2785 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2786 
2787 /******************  Bit definition for DMA_CPAR register  ********************/
2788 #define DMA_CPAR_PA_Pos        (0U)
2789 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2790 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2791 
2792 /******************  Bit definition for DMA_CMAR register  ********************/
2793 #define DMA_CMAR_MA_Pos        (0U)
2794 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2795 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2796 
2797 
2798 /*******************  Bit definition for DMA_CSELR register  *******************/
2799 #define DMA_CSELR_C1S_Pos      (0U)
2800 #define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                    /*!< 0x0000000F */
2801 #define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
2802 #define DMA_CSELR_C2S_Pos      (4U)
2803 #define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                    /*!< 0x000000F0 */
2804 #define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
2805 #define DMA_CSELR_C3S_Pos      (8U)
2806 #define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                    /*!< 0x00000F00 */
2807 #define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
2808 #define DMA_CSELR_C4S_Pos      (12U)
2809 #define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                    /*!< 0x0000F000 */
2810 #define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
2811 #define DMA_CSELR_C5S_Pos      (16U)
2812 #define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                    /*!< 0x000F0000 */
2813 #define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
2814 #define DMA_CSELR_C6S_Pos      (20U)
2815 #define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                    /*!< 0x00F00000 */
2816 #define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
2817 #define DMA_CSELR_C7S_Pos      (24U)
2818 #define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                    /*!< 0x0F000000 */
2819 #define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
2820 
2821 /******************************************************************************/
2822 /*                                                                            */
2823 /*                    External Interrupt/Event Controller                     */
2824 /*                                                                            */
2825 /******************************************************************************/
2826 /*******************  Bit definition for EXTI_IMR1 register  ******************/
2827 #define EXTI_IMR1_IM0_Pos        (0U)
2828 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
2829 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
2830 #define EXTI_IMR1_IM1_Pos        (1U)
2831 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
2832 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
2833 #define EXTI_IMR1_IM2_Pos        (2U)
2834 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
2835 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
2836 #define EXTI_IMR1_IM3_Pos        (3U)
2837 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
2838 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
2839 #define EXTI_IMR1_IM4_Pos        (4U)
2840 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
2841 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
2842 #define EXTI_IMR1_IM5_Pos        (5U)
2843 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
2844 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
2845 #define EXTI_IMR1_IM6_Pos        (6U)
2846 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
2847 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
2848 #define EXTI_IMR1_IM7_Pos        (7U)
2849 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
2850 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
2851 #define EXTI_IMR1_IM8_Pos        (8U)
2852 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
2853 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
2854 #define EXTI_IMR1_IM9_Pos        (9U)
2855 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
2856 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
2857 #define EXTI_IMR1_IM10_Pos       (10U)
2858 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
2859 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
2860 #define EXTI_IMR1_IM11_Pos       (11U)
2861 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
2862 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
2863 #define EXTI_IMR1_IM12_Pos       (12U)
2864 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
2865 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
2866 #define EXTI_IMR1_IM13_Pos       (13U)
2867 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
2868 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
2869 #define EXTI_IMR1_IM14_Pos       (14U)
2870 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
2871 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
2872 #define EXTI_IMR1_IM15_Pos       (15U)
2873 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
2874 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
2875 #define EXTI_IMR1_IM16_Pos       (16U)
2876 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
2877 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
2878 #define EXTI_IMR1_IM17_Pos       (17U)
2879 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
2880 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
2881 #define EXTI_IMR1_IM18_Pos       (18U)
2882 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
2883 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
2884 #define EXTI_IMR1_IM19_Pos       (19U)
2885 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
2886 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
2887 #define EXTI_IMR1_IM20_Pos       (20U)
2888 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
2889 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
2890 #define EXTI_IMR1_IM21_Pos       (21U)
2891 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
2892 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
2893 #define EXTI_IMR1_IM23_Pos       (23U)
2894 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
2895 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
2896 #define EXTI_IMR1_IM24_Pos       (24U)
2897 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
2898 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
2899 #define EXTI_IMR1_IM25_Pos       (25U)
2900 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
2901 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
2902 #define EXTI_IMR1_IM26_Pos       (26U)
2903 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
2904 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
2905 #define EXTI_IMR1_IM27_Pos       (27U)
2906 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
2907 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
2908 #define EXTI_IMR1_IM28_Pos       (28U)
2909 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
2910 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
2911 #define EXTI_IMR1_IM29_Pos       (29U)
2912 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
2913 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
2914 #define EXTI_IMR1_IM30_Pos       (30U)
2915 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
2916 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
2917 #define EXTI_IMR1_IM31_Pos       (31U)
2918 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
2919 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
2920 #define EXTI_IMR1_IM_Pos         (0U)
2921 #define EXTI_IMR1_IM_Msk         (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0x9FFFFFFF */
2922 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
2923 
2924 /*******************  Bit definition for EXTI_EMR1 register  ******************/
2925 #define EXTI_EMR1_EM0_Pos        (0U)
2926 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
2927 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
2928 #define EXTI_EMR1_EM1_Pos        (1U)
2929 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
2930 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
2931 #define EXTI_EMR1_EM2_Pos        (2U)
2932 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
2933 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
2934 #define EXTI_EMR1_EM3_Pos        (3U)
2935 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
2936 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
2937 #define EXTI_EMR1_EM4_Pos        (4U)
2938 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
2939 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
2940 #define EXTI_EMR1_EM5_Pos        (5U)
2941 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
2942 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
2943 #define EXTI_EMR1_EM6_Pos        (6U)
2944 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
2945 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
2946 #define EXTI_EMR1_EM7_Pos        (7U)
2947 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
2948 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
2949 #define EXTI_EMR1_EM8_Pos        (8U)
2950 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
2951 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
2952 #define EXTI_EMR1_EM9_Pos        (9U)
2953 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
2954 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
2955 #define EXTI_EMR1_EM10_Pos       (10U)
2956 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
2957 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
2958 #define EXTI_EMR1_EM11_Pos       (11U)
2959 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
2960 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
2961 #define EXTI_EMR1_EM12_Pos       (12U)
2962 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
2963 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
2964 #define EXTI_EMR1_EM13_Pos       (13U)
2965 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
2966 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
2967 #define EXTI_EMR1_EM14_Pos       (14U)
2968 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
2969 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
2970 #define EXTI_EMR1_EM15_Pos       (15U)
2971 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
2972 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
2973 #define EXTI_EMR1_EM16_Pos       (16U)
2974 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
2975 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
2976 #define EXTI_EMR1_EM17_Pos       (17U)
2977 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
2978 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
2979 #define EXTI_EMR1_EM18_Pos       (18U)
2980 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
2981 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
2982 #define EXTI_EMR1_EM19_Pos       (19U)
2983 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
2984 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
2985 #define EXTI_EMR1_EM20_Pos       (20U)
2986 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
2987 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
2988 #define EXTI_EMR1_EM21_Pos       (21U)
2989 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
2990 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
2991 #define EXTI_EMR1_EM23_Pos       (23U)
2992 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
2993 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
2994 #define EXTI_EMR1_EM24_Pos       (24U)
2995 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
2996 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
2997 #define EXTI_EMR1_EM25_Pos       (25U)
2998 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
2999 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
3000 #define EXTI_EMR1_EM26_Pos       (26U)
3001 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
3002 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
3003 #define EXTI_EMR1_EM27_Pos       (27U)
3004 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
3005 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
3006 #define EXTI_EMR1_EM28_Pos       (28U)
3007 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
3008 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
3009 #define EXTI_EMR1_EM31_Pos       (31U)
3010 #define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */
3011 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
3012 
3013 /******************  Bit definition for EXTI_RTSR1 register  ******************/
3014 #define EXTI_RTSR1_RT0_Pos       (0U)
3015 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
3016 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
3017 #define EXTI_RTSR1_RT1_Pos       (1U)
3018 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
3019 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
3020 #define EXTI_RTSR1_RT2_Pos       (2U)
3021 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
3022 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
3023 #define EXTI_RTSR1_RT3_Pos       (3U)
3024 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
3025 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
3026 #define EXTI_RTSR1_RT4_Pos       (4U)
3027 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
3028 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
3029 #define EXTI_RTSR1_RT5_Pos       (5U)
3030 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
3031 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
3032 #define EXTI_RTSR1_RT6_Pos       (6U)
3033 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
3034 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
3035 #define EXTI_RTSR1_RT7_Pos       (7U)
3036 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
3037 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
3038 #define EXTI_RTSR1_RT8_Pos       (8U)
3039 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
3040 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
3041 #define EXTI_RTSR1_RT9_Pos       (9U)
3042 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
3043 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
3044 #define EXTI_RTSR1_RT10_Pos      (10U)
3045 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
3046 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
3047 #define EXTI_RTSR1_RT11_Pos      (11U)
3048 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
3049 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
3050 #define EXTI_RTSR1_RT12_Pos      (12U)
3051 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
3052 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
3053 #define EXTI_RTSR1_RT13_Pos      (13U)
3054 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
3055 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
3056 #define EXTI_RTSR1_RT14_Pos      (14U)
3057 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
3058 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
3059 #define EXTI_RTSR1_RT15_Pos      (15U)
3060 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
3061 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
3062 #define EXTI_RTSR1_RT16_Pos      (16U)
3063 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
3064 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
3065 #define EXTI_RTSR1_RT18_Pos      (18U)
3066 #define EXTI_RTSR1_RT18_Msk      (0x1UL << EXTI_RTSR1_RT18_Pos)                /*!< 0x00040000 */
3067 #define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
3068 #define EXTI_RTSR1_RT19_Pos      (19U)
3069 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
3070 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
3071 #define EXTI_RTSR1_RT20_Pos      (20U)
3072 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
3073 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
3074 #define EXTI_RTSR1_RT21_Pos      (21U)
3075 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
3076 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
3077 
3078 /******************  Bit definition for EXTI_FTSR1 register  ******************/
3079 #define EXTI_FTSR1_FT0_Pos       (0U)
3080 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
3081 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
3082 #define EXTI_FTSR1_FT1_Pos       (1U)
3083 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
3084 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
3085 #define EXTI_FTSR1_FT2_Pos       (2U)
3086 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
3087 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
3088 #define EXTI_FTSR1_FT3_Pos       (3U)
3089 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
3090 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
3091 #define EXTI_FTSR1_FT4_Pos       (4U)
3092 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
3093 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
3094 #define EXTI_FTSR1_FT5_Pos       (5U)
3095 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
3096 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
3097 #define EXTI_FTSR1_FT6_Pos       (6U)
3098 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
3099 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
3100 #define EXTI_FTSR1_FT7_Pos       (7U)
3101 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
3102 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
3103 #define EXTI_FTSR1_FT8_Pos       (8U)
3104 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
3105 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
3106 #define EXTI_FTSR1_FT9_Pos       (9U)
3107 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
3108 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
3109 #define EXTI_FTSR1_FT10_Pos      (10U)
3110 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
3111 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
3112 #define EXTI_FTSR1_FT11_Pos      (11U)
3113 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
3114 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
3115 #define EXTI_FTSR1_FT12_Pos      (12U)
3116 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
3117 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
3118 #define EXTI_FTSR1_FT13_Pos      (13U)
3119 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
3120 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
3121 #define EXTI_FTSR1_FT14_Pos      (14U)
3122 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
3123 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
3124 #define EXTI_FTSR1_FT15_Pos      (15U)
3125 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
3126 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
3127 #define EXTI_FTSR1_FT16_Pos      (16U)
3128 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
3129 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
3130 #define EXTI_FTSR1_FT18_Pos      (18U)
3131 #define EXTI_FTSR1_FT18_Msk      (0x1UL << EXTI_FTSR1_FT18_Pos)                /*!< 0x00040000 */
3132 #define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
3133 #define EXTI_FTSR1_FT19_Pos      (19U)
3134 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
3135 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
3136 #define EXTI_FTSR1_FT20_Pos      (20U)
3137 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
3138 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
3139 #define EXTI_FTSR1_FT21_Pos      (21U)
3140 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
3141 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
3142 
3143 /******************  Bit definition for EXTI_SWIER1 register  *****************/
3144 #define EXTI_SWIER1_SWI0_Pos     (0U)
3145 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
3146 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
3147 #define EXTI_SWIER1_SWI1_Pos     (1U)
3148 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
3149 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
3150 #define EXTI_SWIER1_SWI2_Pos     (2U)
3151 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
3152 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
3153 #define EXTI_SWIER1_SWI3_Pos     (3U)
3154 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
3155 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
3156 #define EXTI_SWIER1_SWI4_Pos     (4U)
3157 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
3158 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
3159 #define EXTI_SWIER1_SWI5_Pos     (5U)
3160 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
3161 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
3162 #define EXTI_SWIER1_SWI6_Pos     (6U)
3163 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
3164 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
3165 #define EXTI_SWIER1_SWI7_Pos     (7U)
3166 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
3167 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
3168 #define EXTI_SWIER1_SWI8_Pos     (8U)
3169 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
3170 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
3171 #define EXTI_SWIER1_SWI9_Pos     (9U)
3172 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
3173 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
3174 #define EXTI_SWIER1_SWI10_Pos    (10U)
3175 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
3176 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
3177 #define EXTI_SWIER1_SWI11_Pos    (11U)
3178 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
3179 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
3180 #define EXTI_SWIER1_SWI12_Pos    (12U)
3181 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
3182 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
3183 #define EXTI_SWIER1_SWI13_Pos    (13U)
3184 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
3185 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
3186 #define EXTI_SWIER1_SWI14_Pos    (14U)
3187 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
3188 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
3189 #define EXTI_SWIER1_SWI15_Pos    (15U)
3190 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
3191 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
3192 #define EXTI_SWIER1_SWI16_Pos    (16U)
3193 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
3194 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
3195 #define EXTI_SWIER1_SWI18_Pos    (18U)
3196 #define EXTI_SWIER1_SWI18_Msk    (0x1UL << EXTI_SWIER1_SWI18_Pos)              /*!< 0x00040000 */
3197 #define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
3198 #define EXTI_SWIER1_SWI19_Pos    (19U)
3199 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
3200 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
3201 #define EXTI_SWIER1_SWI20_Pos    (20U)
3202 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
3203 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
3204 #define EXTI_SWIER1_SWI21_Pos    (21U)
3205 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
3206 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
3207 
3208 /*******************  Bit definition for EXTI_PR1 register  *******************/
3209 #define EXTI_PR1_PIF0_Pos        (0U)
3210 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
3211 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
3212 #define EXTI_PR1_PIF1_Pos        (1U)
3213 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
3214 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
3215 #define EXTI_PR1_PIF2_Pos        (2U)
3216 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
3217 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
3218 #define EXTI_PR1_PIF3_Pos        (3U)
3219 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
3220 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
3221 #define EXTI_PR1_PIF4_Pos        (4U)
3222 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
3223 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
3224 #define EXTI_PR1_PIF5_Pos        (5U)
3225 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
3226 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
3227 #define EXTI_PR1_PIF6_Pos        (6U)
3228 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
3229 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
3230 #define EXTI_PR1_PIF7_Pos        (7U)
3231 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
3232 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
3233 #define EXTI_PR1_PIF8_Pos        (8U)
3234 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
3235 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
3236 #define EXTI_PR1_PIF9_Pos        (9U)
3237 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
3238 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
3239 #define EXTI_PR1_PIF10_Pos       (10U)
3240 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
3241 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
3242 #define EXTI_PR1_PIF11_Pos       (11U)
3243 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
3244 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
3245 #define EXTI_PR1_PIF12_Pos       (12U)
3246 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
3247 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
3248 #define EXTI_PR1_PIF13_Pos       (13U)
3249 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
3250 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
3251 #define EXTI_PR1_PIF14_Pos       (14U)
3252 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
3253 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
3254 #define EXTI_PR1_PIF15_Pos       (15U)
3255 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
3256 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
3257 #define EXTI_PR1_PIF16_Pos       (16U)
3258 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
3259 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
3260 #define EXTI_PR1_PIF18_Pos       (18U)
3261 #define EXTI_PR1_PIF18_Msk       (0x1UL << EXTI_PR1_PIF18_Pos)                 /*!< 0x00040000 */
3262 #define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
3263 #define EXTI_PR1_PIF19_Pos       (19U)
3264 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
3265 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
3266 #define EXTI_PR1_PIF20_Pos       (20U)
3267 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
3268 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
3269 #define EXTI_PR1_PIF21_Pos       (21U)
3270 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
3271 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
3272 
3273 /*******************  Bit definition for EXTI_IMR2 register  ******************/
3274 #define EXTI_IMR2_IM32_Pos       (0U)
3275 #define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */
3276 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
3277 #define EXTI_IMR2_IM33_Pos       (1U)
3278 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
3279 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
3280 #define EXTI_IMR2_IM35_Pos       (3U)
3281 #define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */
3282 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
3283 #define EXTI_IMR2_IM37_Pos       (5U)
3284 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
3285 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
3286 #define EXTI_IMR2_IM38_Pos       (6U)
3287 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
3288 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
3289 #define EXTI_IMR2_IM_Pos         (0U)
3290 #define EXTI_IMR2_IM_Msk         (0x6BUL << EXTI_IMR2_IM_Pos)                   /*!< 0x0000006B */
3291 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
3292 
3293 /*******************  Bit definition for EXTI_EMR2 register  ******************/
3294 #define EXTI_EMR2_EM32_Pos       (0U)
3295 #define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */
3296 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
3297 #define EXTI_EMR2_EM33_Pos       (1U)
3298 #define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */
3299 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
3300 #define EXTI_EMR2_EM35_Pos       (3U)
3301 #define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */
3302 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
3303 #define EXTI_EMR2_EM37_Pos       (5U)
3304 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
3305 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
3306 #define EXTI_EMR2_EM38_Pos       (6U)
3307 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
3308 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
3309 #define EXTI_EMR2_EM_Pos         (0U)
3310 #define EXTI_EMR2_EM_Msk         (0x6BUL << EXTI_EMR2_EM_Pos)                   /*!< 0x0000006B */
3311 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
3312 
3313 /******************  Bit definition for EXTI_RTSR2 register  ******************/
3314 #define EXTI_RTSR2_RT35_Pos      (3U)
3315 #define EXTI_RTSR2_RT35_Msk      (0x1UL << EXTI_RTSR2_RT35_Pos)                /*!< 0x00000008 */
3316 #define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
3317 #define EXTI_RTSR2_RT37_Pos      (5U)
3318 #define EXTI_RTSR2_RT37_Msk      (0x1UL << EXTI_RTSR2_RT37_Pos)                /*!< 0x00000020 */
3319 #define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
3320 #define EXTI_RTSR2_RT38_Pos      (6U)
3321 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
3322 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
3323 
3324 /******************  Bit definition for EXTI_FTSR2 register  ******************/
3325 #define EXTI_FTSR2_FT35_Pos      (3U)
3326 #define EXTI_FTSR2_FT35_Msk      (0x1UL << EXTI_FTSR2_FT35_Pos)                /*!< 0x00000008 */
3327 #define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
3328 #define EXTI_FTSR2_FT37_Pos      (5U)
3329 #define EXTI_FTSR2_FT37_Msk      (0x1UL << EXTI_FTSR2_FT37_Pos)                /*!< 0x00000020 */
3330 #define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
3331 #define EXTI_FTSR2_FT38_Pos      (6U)
3332 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
3333 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
3334 
3335 /******************  Bit definition for EXTI_SWIER2 register  *****************/
3336 #define EXTI_SWIER2_SWI35_Pos    (3U)
3337 #define EXTI_SWIER2_SWI35_Msk    (0x1UL << EXTI_SWIER2_SWI35_Pos)              /*!< 0x00000008 */
3338 #define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
3339 #define EXTI_SWIER2_SWI37_Pos    (5U)
3340 #define EXTI_SWIER2_SWI37_Msk    (0x1UL << EXTI_SWIER2_SWI37_Pos)              /*!< 0x00000020 */
3341 #define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
3342 #define EXTI_SWIER2_SWI38_Pos    (6U)
3343 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
3344 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
3345 
3346 /*******************  Bit definition for EXTI_PR2 register  *******************/
3347 #define EXTI_PR2_PIF35_Pos       (3U)
3348 #define EXTI_PR2_PIF35_Msk       (0x1UL << EXTI_PR2_PIF35_Pos)                 /*!< 0x00000008 */
3349 #define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
3350 #define EXTI_PR2_PIF37_Pos       (5U)
3351 #define EXTI_PR2_PIF37_Msk       (0x1UL << EXTI_PR2_PIF37_Pos)                 /*!< 0x00000020 */
3352 #define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
3353 #define EXTI_PR2_PIF38_Pos       (6U)
3354 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
3355 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
3356 
3357 
3358 /******************************************************************************/
3359 /*                                                                            */
3360 /*                                    FLASH                                   */
3361 /*                                                                            */
3362 /******************************************************************************/
3363 /*******************  Bits definition for FLASH_ACR register  *****************/
3364 #define FLASH_ACR_LATENCY_Pos             (0U)
3365 #define FLASH_ACR_LATENCY_Msk             (0x7UL << FLASH_ACR_LATENCY_Pos)     /*!< 0x00000007 */
3366 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
3367 #define FLASH_ACR_LATENCY_0WS             (0x00000000UL)
3368 #define FLASH_ACR_LATENCY_1WS             (0x00000001UL)
3369 #define FLASH_ACR_LATENCY_2WS             (0x00000002UL)
3370 #define FLASH_ACR_LATENCY_3WS             (0x00000003UL)
3371 #define FLASH_ACR_LATENCY_4WS             (0x00000004UL)
3372 #define FLASH_ACR_PRFTEN_Pos              (8U)
3373 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
3374 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
3375 #define FLASH_ACR_ICEN_Pos                (9U)
3376 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
3377 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
3378 #define FLASH_ACR_DCEN_Pos                (10U)
3379 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
3380 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
3381 #define FLASH_ACR_ICRST_Pos               (11U)
3382 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
3383 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
3384 #define FLASH_ACR_DCRST_Pos               (12U)
3385 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
3386 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
3387 #define FLASH_ACR_RUN_PD_Pos              (13U)
3388 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
3389 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
3390 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
3391 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
3392 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
3393 
3394 /*******************  Bits definition for FLASH_SR register  ******************/
3395 #define FLASH_SR_EOP_Pos                  (0U)
3396 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
3397 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
3398 #define FLASH_SR_OPERR_Pos                (1U)
3399 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
3400 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
3401 #define FLASH_SR_PROGERR_Pos              (3U)
3402 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
3403 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
3404 #define FLASH_SR_WRPERR_Pos               (4U)
3405 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
3406 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
3407 #define FLASH_SR_PGAERR_Pos               (5U)
3408 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
3409 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
3410 #define FLASH_SR_SIZERR_Pos               (6U)
3411 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
3412 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
3413 #define FLASH_SR_PGSERR_Pos               (7U)
3414 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
3415 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
3416 #define FLASH_SR_MISERR_Pos               (8U)
3417 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
3418 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
3419 #define FLASH_SR_FASTERR_Pos              (9U)
3420 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
3421 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
3422 #define FLASH_SR_RDERR_Pos                (14U)
3423 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
3424 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
3425 #define FLASH_SR_OPTVERR_Pos              (15U)
3426 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
3427 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
3428 #define FLASH_SR_BSY_Pos                  (16U)
3429 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
3430 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
3431 #define FLASH_SR_PEMPTY_Pos               (17U)
3432 #define FLASH_SR_PEMPTY_Msk               (0x1UL << FLASH_SR_PEMPTY_Pos)       /*!< 0x00020000 */
3433 #define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk
3434 
3435 /*******************  Bits definition for FLASH_CR register  ******************/
3436 #define FLASH_CR_PG_Pos                   (0U)
3437 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
3438 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
3439 #define FLASH_CR_PER_Pos                  (1U)
3440 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
3441 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
3442 #define FLASH_CR_MER1_Pos                 (2U)
3443 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
3444 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
3445 #define FLASH_CR_PNB_Pos                  (3U)
3446 #define FLASH_CR_PNB_Msk                  (0x3FUL << FLASH_CR_PNB_Pos)         /*!< 0x000001F8 */
3447 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
3448 #define FLASH_CR_STRT_Pos                 (16U)
3449 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
3450 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
3451 #define FLASH_CR_OPTSTRT_Pos              (17U)
3452 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
3453 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
3454 #define FLASH_CR_FSTPG_Pos                (18U)
3455 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
3456 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
3457 #define FLASH_CR_EOPIE_Pos                (24U)
3458 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
3459 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
3460 #define FLASH_CR_ERRIE_Pos                (25U)
3461 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
3462 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
3463 #define FLASH_CR_RDERRIE_Pos              (26U)
3464 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
3465 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
3466 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
3467 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
3468 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
3469 #define FLASH_CR_OPTLOCK_Pos              (30U)
3470 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
3471 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
3472 #define FLASH_CR_LOCK_Pos                 (31U)
3473 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
3474 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
3475 
3476 /*******************  Bits definition for FLASH_ECCR register  ***************/
3477 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
3478 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
3479 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
3480 #define FLASH_ECCR_SYSF_ECC_Pos           (20U)
3481 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00100000 */
3482 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
3483 #define FLASH_ECCR_ECCIE_Pos              (24U)
3484 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
3485 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
3486 #define FLASH_ECCR_ECCC_Pos               (30U)
3487 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
3488 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
3489 #define FLASH_ECCR_ECCD_Pos               (31U)
3490 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
3491 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
3492 
3493 /*******************  Bits definition for FLASH_OPTR register  ***************/
3494 #define FLASH_OPTR_RDP_Pos                (0U)
3495 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
3496 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
3497 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
3498 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
3499 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
3500 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
3501 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
3502 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
3503 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
3504 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
3505 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
3506 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
3507 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
3508 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
3509 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
3510 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
3511 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
3512 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
3513 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
3514 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
3515 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
3516 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
3517 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
3518 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
3519 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
3520 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
3521 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
3522 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
3523 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
3524 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
3525 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
3526 #define FLASH_OPTR_nBOOT1_Pos             (23U)
3527 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
3528 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
3529 #define FLASH_OPTR_SRAM2_PE_Pos           (24U)
3530 #define FLASH_OPTR_SRAM2_PE_Msk           (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)   /*!< 0x01000000 */
3531 #define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk
3532 #define FLASH_OPTR_SRAM2_RST_Pos          (25U)
3533 #define FLASH_OPTR_SRAM2_RST_Msk          (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)  /*!< 0x02000000 */
3534 #define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk
3535 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
3536 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
3537 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
3538 #define FLASH_OPTR_nBOOT0_Pos             (27U)
3539 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
3540 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
3541 
3542 /******************  Bits definition for FLASH_PCROP1SR register  **********/
3543 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
3544 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00003FFF */
3545 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
3546 
3547 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
3548 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
3549 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00003FFF */
3550 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
3551 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
3552 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
3553 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
3554 
3555 /******************  Bits definition for FLASH_WRP1AR register  ***************/
3556 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
3557 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */
3558 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
3559 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
3560 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)  /*!< 0x003F0000 */
3561 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
3562 
3563 /******************  Bits definition for FLASH_WRPB1R register  ***************/
3564 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
3565 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */
3566 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
3567 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
3568 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)  /*!< 0x003F0000 */
3569 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
3570 
3571 
3572 
3573 
3574 /******************************************************************************/
3575 /*                                                                            */
3576 /*                       General Purpose IOs (GPIO)                           */
3577 /*                                                                            */
3578 /******************************************************************************/
3579 /******************  Bits definition for GPIO_MODER register  *****************/
3580 #define GPIO_MODER_MODE0_Pos           (0U)
3581 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
3582 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
3583 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
3584 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
3585 #define GPIO_MODER_MODE1_Pos           (2U)
3586 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
3587 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
3588 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
3589 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
3590 #define GPIO_MODER_MODE2_Pos           (4U)
3591 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
3592 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
3593 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
3594 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
3595 #define GPIO_MODER_MODE3_Pos           (6U)
3596 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
3597 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
3598 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
3599 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
3600 #define GPIO_MODER_MODE4_Pos           (8U)
3601 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
3602 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
3603 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
3604 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
3605 #define GPIO_MODER_MODE5_Pos           (10U)
3606 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
3607 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
3608 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
3609 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
3610 #define GPIO_MODER_MODE6_Pos           (12U)
3611 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
3612 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
3613 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
3614 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
3615 #define GPIO_MODER_MODE7_Pos           (14U)
3616 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
3617 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
3618 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
3619 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
3620 #define GPIO_MODER_MODE8_Pos           (16U)
3621 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
3622 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
3623 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
3624 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
3625 #define GPIO_MODER_MODE9_Pos           (18U)
3626 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
3627 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
3628 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
3629 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
3630 #define GPIO_MODER_MODE10_Pos          (20U)
3631 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
3632 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
3633 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
3634 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
3635 #define GPIO_MODER_MODE11_Pos          (22U)
3636 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
3637 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
3638 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
3639 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
3640 #define GPIO_MODER_MODE12_Pos          (24U)
3641 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
3642 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
3643 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
3644 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
3645 #define GPIO_MODER_MODE13_Pos          (26U)
3646 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
3647 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
3648 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
3649 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
3650 #define GPIO_MODER_MODE14_Pos          (28U)
3651 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
3652 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
3653 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
3654 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
3655 #define GPIO_MODER_MODE15_Pos          (30U)
3656 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
3657 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
3658 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
3659 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
3660 
3661 /* Legacy defines */
3662 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
3663 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
3664 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
3665 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
3666 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
3667 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
3668 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
3669 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
3670 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
3671 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
3672 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
3673 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
3674 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
3675 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
3676 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
3677 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
3678 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
3679 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
3680 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
3681 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
3682 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
3683 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
3684 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
3685 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
3686 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
3687 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
3688 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
3689 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
3690 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
3691 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
3692 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
3693 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
3694 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
3695 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
3696 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
3697 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
3698 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
3699 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
3700 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
3701 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
3702 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
3703 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
3704 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
3705 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
3706 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
3707 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
3708 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
3709 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
3710 
3711 /******************  Bits definition for GPIO_OTYPER register  ****************/
3712 #define GPIO_OTYPER_OT0_Pos            (0U)
3713 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
3714 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
3715 #define GPIO_OTYPER_OT1_Pos            (1U)
3716 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
3717 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
3718 #define GPIO_OTYPER_OT2_Pos            (2U)
3719 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
3720 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
3721 #define GPIO_OTYPER_OT3_Pos            (3U)
3722 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
3723 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
3724 #define GPIO_OTYPER_OT4_Pos            (4U)
3725 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
3726 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
3727 #define GPIO_OTYPER_OT5_Pos            (5U)
3728 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
3729 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
3730 #define GPIO_OTYPER_OT6_Pos            (6U)
3731 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
3732 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
3733 #define GPIO_OTYPER_OT7_Pos            (7U)
3734 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
3735 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
3736 #define GPIO_OTYPER_OT8_Pos            (8U)
3737 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
3738 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3739 #define GPIO_OTYPER_OT9_Pos            (9U)
3740 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
3741 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3742 #define GPIO_OTYPER_OT10_Pos           (10U)
3743 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
3744 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3745 #define GPIO_OTYPER_OT11_Pos           (11U)
3746 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
3747 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3748 #define GPIO_OTYPER_OT12_Pos           (12U)
3749 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
3750 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3751 #define GPIO_OTYPER_OT13_Pos           (13U)
3752 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
3753 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3754 #define GPIO_OTYPER_OT14_Pos           (14U)
3755 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
3756 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3757 #define GPIO_OTYPER_OT15_Pos           (15U)
3758 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
3759 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3760 
3761 /* Legacy defines */
3762 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
3763 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
3764 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
3765 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
3766 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
3767 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
3768 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
3769 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
3770 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
3771 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
3772 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
3773 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
3774 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
3775 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
3776 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
3777 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
3778 
3779 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3780 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3781 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
3782 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3783 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
3784 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
3785 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3786 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
3787 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3788 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
3789 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
3790 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3791 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
3792 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3793 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
3794 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
3795 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3796 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
3797 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3798 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
3799 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
3800 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3801 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
3802 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3803 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
3804 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
3805 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3806 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
3807 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3808 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
3809 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
3810 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3811 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
3812 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3813 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
3814 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
3815 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3816 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
3817 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3818 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
3819 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
3820 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3821 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
3822 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3823 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
3824 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
3825 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
3826 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
3827 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
3828 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
3829 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
3830 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
3831 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
3832 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
3833 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
3834 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
3835 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
3836 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
3837 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
3838 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
3839 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
3840 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
3841 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
3842 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
3843 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
3844 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
3845 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
3846 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
3847 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
3848 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
3849 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
3850 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
3851 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
3852 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
3853 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
3854 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
3855 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
3856 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
3857 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
3858 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
3859 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
3860 
3861 /* Legacy defines */
3862 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
3863 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
3864 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
3865 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
3866 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
3867 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
3868 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
3869 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
3870 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
3871 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
3872 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
3873 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
3874 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
3875 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
3876 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
3877 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
3878 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
3879 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
3880 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
3881 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
3882 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
3883 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
3884 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
3885 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
3886 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
3887 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
3888 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
3889 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
3890 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
3891 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
3892 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
3893 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
3894 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
3895 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
3896 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
3897 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
3898 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
3899 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
3900 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
3901 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
3902 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
3903 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
3904 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
3905 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
3906 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
3907 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
3908 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
3909 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
3910 
3911 /******************  Bits definition for GPIO_PUPDR register  *****************/
3912 #define GPIO_PUPDR_PUPD0_Pos           (0U)
3913 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
3914 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
3915 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
3916 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
3917 #define GPIO_PUPDR_PUPD1_Pos           (2U)
3918 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
3919 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
3920 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
3921 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
3922 #define GPIO_PUPDR_PUPD2_Pos           (4U)
3923 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
3924 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
3925 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
3926 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
3927 #define GPIO_PUPDR_PUPD3_Pos           (6U)
3928 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
3929 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
3930 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
3931 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
3932 #define GPIO_PUPDR_PUPD4_Pos           (8U)
3933 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
3934 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
3935 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
3936 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
3937 #define GPIO_PUPDR_PUPD5_Pos           (10U)
3938 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
3939 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
3940 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
3941 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
3942 #define GPIO_PUPDR_PUPD6_Pos           (12U)
3943 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
3944 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
3945 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
3946 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
3947 #define GPIO_PUPDR_PUPD7_Pos           (14U)
3948 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
3949 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
3950 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
3951 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
3952 #define GPIO_PUPDR_PUPD8_Pos           (16U)
3953 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
3954 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
3955 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
3956 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
3957 #define GPIO_PUPDR_PUPD9_Pos           (18U)
3958 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
3959 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
3960 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
3961 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
3962 #define GPIO_PUPDR_PUPD10_Pos          (20U)
3963 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
3964 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
3965 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
3966 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
3967 #define GPIO_PUPDR_PUPD11_Pos          (22U)
3968 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
3969 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
3970 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
3971 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
3972 #define GPIO_PUPDR_PUPD12_Pos          (24U)
3973 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
3974 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
3975 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
3976 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
3977 #define GPIO_PUPDR_PUPD13_Pos          (26U)
3978 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
3979 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
3980 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
3981 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
3982 #define GPIO_PUPDR_PUPD14_Pos          (28U)
3983 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
3984 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
3985 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
3986 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
3987 #define GPIO_PUPDR_PUPD15_Pos          (30U)
3988 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
3989 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
3990 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
3991 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
3992 
3993 /* Legacy defines */
3994 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
3995 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
3996 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
3997 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
3998 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
3999 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
4000 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
4001 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
4002 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
4003 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
4004 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
4005 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
4006 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
4007 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
4008 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
4009 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
4010 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
4011 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
4012 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
4013 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
4014 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
4015 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
4016 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
4017 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
4018 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
4019 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
4020 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
4021 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
4022 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
4023 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
4024 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
4025 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
4026 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
4027 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
4028 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
4029 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
4030 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
4031 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
4032 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
4033 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
4034 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
4035 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
4036 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
4037 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
4038 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
4039 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
4040 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
4041 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
4042 
4043 /******************  Bits definition for GPIO_IDR register  *******************/
4044 #define GPIO_IDR_ID0_Pos               (0U)
4045 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
4046 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
4047 #define GPIO_IDR_ID1_Pos               (1U)
4048 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
4049 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
4050 #define GPIO_IDR_ID2_Pos               (2U)
4051 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
4052 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
4053 #define GPIO_IDR_ID3_Pos               (3U)
4054 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
4055 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
4056 #define GPIO_IDR_ID4_Pos               (4U)
4057 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
4058 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
4059 #define GPIO_IDR_ID5_Pos               (5U)
4060 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
4061 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
4062 #define GPIO_IDR_ID6_Pos               (6U)
4063 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
4064 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
4065 #define GPIO_IDR_ID7_Pos               (7U)
4066 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
4067 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
4068 #define GPIO_IDR_ID8_Pos               (8U)
4069 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
4070 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
4071 #define GPIO_IDR_ID9_Pos               (9U)
4072 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
4073 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
4074 #define GPIO_IDR_ID10_Pos              (10U)
4075 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
4076 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
4077 #define GPIO_IDR_ID11_Pos              (11U)
4078 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
4079 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
4080 #define GPIO_IDR_ID12_Pos              (12U)
4081 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
4082 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
4083 #define GPIO_IDR_ID13_Pos              (13U)
4084 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
4085 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
4086 #define GPIO_IDR_ID14_Pos              (14U)
4087 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
4088 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
4089 #define GPIO_IDR_ID15_Pos              (15U)
4090 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
4091 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
4092 
4093 /* Legacy defines */
4094 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
4095 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
4096 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
4097 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
4098 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
4099 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
4100 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
4101 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
4102 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
4103 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
4104 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
4105 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
4106 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
4107 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
4108 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
4109 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
4110 
4111 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4112 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
4113 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
4114 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
4115 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
4116 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
4117 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
4118 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
4119 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
4120 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
4121 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
4122 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
4123 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
4124 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
4125 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
4126 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
4127 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
4128 
4129 /******************  Bits definition for GPIO_ODR register  *******************/
4130 #define GPIO_ODR_OD0_Pos               (0U)
4131 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
4132 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
4133 #define GPIO_ODR_OD1_Pos               (1U)
4134 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
4135 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
4136 #define GPIO_ODR_OD2_Pos               (2U)
4137 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
4138 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
4139 #define GPIO_ODR_OD3_Pos               (3U)
4140 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
4141 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
4142 #define GPIO_ODR_OD4_Pos               (4U)
4143 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
4144 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
4145 #define GPIO_ODR_OD5_Pos               (5U)
4146 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
4147 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
4148 #define GPIO_ODR_OD6_Pos               (6U)
4149 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
4150 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
4151 #define GPIO_ODR_OD7_Pos               (7U)
4152 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
4153 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
4154 #define GPIO_ODR_OD8_Pos               (8U)
4155 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
4156 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
4157 #define GPIO_ODR_OD9_Pos               (9U)
4158 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
4159 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
4160 #define GPIO_ODR_OD10_Pos              (10U)
4161 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
4162 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
4163 #define GPIO_ODR_OD11_Pos              (11U)
4164 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
4165 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
4166 #define GPIO_ODR_OD12_Pos              (12U)
4167 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
4168 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
4169 #define GPIO_ODR_OD13_Pos              (13U)
4170 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
4171 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
4172 #define GPIO_ODR_OD14_Pos              (14U)
4173 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
4174 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
4175 #define GPIO_ODR_OD15_Pos              (15U)
4176 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
4177 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
4178 
4179 /* Legacy defines */
4180 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
4181 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
4182 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
4183 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
4184 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
4185 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
4186 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
4187 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
4188 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
4189 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
4190 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
4191 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
4192 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
4193 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
4194 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
4195 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
4196 
4197 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4198 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
4199 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
4200 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
4201 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
4202 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
4203 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
4204 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
4205 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
4206 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
4207 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
4208 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
4209 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
4210 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
4211 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
4212 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
4213 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
4214 
4215 /******************  Bits definition for GPIO_BSRR register  ******************/
4216 #define GPIO_BSRR_BS0_Pos              (0U)
4217 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
4218 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
4219 #define GPIO_BSRR_BS1_Pos              (1U)
4220 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
4221 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
4222 #define GPIO_BSRR_BS2_Pos              (2U)
4223 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
4224 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
4225 #define GPIO_BSRR_BS3_Pos              (3U)
4226 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
4227 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
4228 #define GPIO_BSRR_BS4_Pos              (4U)
4229 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
4230 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
4231 #define GPIO_BSRR_BS5_Pos              (5U)
4232 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
4233 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
4234 #define GPIO_BSRR_BS6_Pos              (6U)
4235 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
4236 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
4237 #define GPIO_BSRR_BS7_Pos              (7U)
4238 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
4239 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
4240 #define GPIO_BSRR_BS8_Pos              (8U)
4241 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
4242 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
4243 #define GPIO_BSRR_BS9_Pos              (9U)
4244 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
4245 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
4246 #define GPIO_BSRR_BS10_Pos             (10U)
4247 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
4248 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
4249 #define GPIO_BSRR_BS11_Pos             (11U)
4250 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
4251 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
4252 #define GPIO_BSRR_BS12_Pos             (12U)
4253 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
4254 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
4255 #define GPIO_BSRR_BS13_Pos             (13U)
4256 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
4257 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
4258 #define GPIO_BSRR_BS14_Pos             (14U)
4259 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
4260 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
4261 #define GPIO_BSRR_BS15_Pos             (15U)
4262 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
4263 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
4264 #define GPIO_BSRR_BR0_Pos              (16U)
4265 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
4266 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
4267 #define GPIO_BSRR_BR1_Pos              (17U)
4268 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
4269 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
4270 #define GPIO_BSRR_BR2_Pos              (18U)
4271 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
4272 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
4273 #define GPIO_BSRR_BR3_Pos              (19U)
4274 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
4275 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
4276 #define GPIO_BSRR_BR4_Pos              (20U)
4277 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
4278 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
4279 #define GPIO_BSRR_BR5_Pos              (21U)
4280 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
4281 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
4282 #define GPIO_BSRR_BR6_Pos              (22U)
4283 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
4284 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
4285 #define GPIO_BSRR_BR7_Pos              (23U)
4286 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
4287 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
4288 #define GPIO_BSRR_BR8_Pos              (24U)
4289 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
4290 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
4291 #define GPIO_BSRR_BR9_Pos              (25U)
4292 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
4293 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
4294 #define GPIO_BSRR_BR10_Pos             (26U)
4295 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
4296 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
4297 #define GPIO_BSRR_BR11_Pos             (27U)
4298 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
4299 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
4300 #define GPIO_BSRR_BR12_Pos             (28U)
4301 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
4302 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
4303 #define GPIO_BSRR_BR13_Pos             (29U)
4304 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
4305 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
4306 #define GPIO_BSRR_BR14_Pos             (30U)
4307 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
4308 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
4309 #define GPIO_BSRR_BR15_Pos             (31U)
4310 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
4311 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
4312 
4313 /* Legacy defines */
4314 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
4315 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
4316 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
4317 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
4318 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
4319 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
4320 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
4321 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
4322 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
4323 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
4324 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
4325 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
4326 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
4327 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
4328 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
4329 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
4330 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
4331 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
4332 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
4333 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
4334 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
4335 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
4336 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
4337 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
4338 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
4339 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
4340 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
4341 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
4342 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
4343 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
4344 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
4345 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
4346 
4347 /****************** Bit definition for GPIO_LCKR register *********************/
4348 #define GPIO_LCKR_LCK0_Pos             (0U)
4349 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
4350 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
4351 #define GPIO_LCKR_LCK1_Pos             (1U)
4352 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
4353 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
4354 #define GPIO_LCKR_LCK2_Pos             (2U)
4355 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
4356 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
4357 #define GPIO_LCKR_LCK3_Pos             (3U)
4358 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
4359 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
4360 #define GPIO_LCKR_LCK4_Pos             (4U)
4361 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
4362 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
4363 #define GPIO_LCKR_LCK5_Pos             (5U)
4364 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
4365 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
4366 #define GPIO_LCKR_LCK6_Pos             (6U)
4367 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
4368 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
4369 #define GPIO_LCKR_LCK7_Pos             (7U)
4370 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
4371 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
4372 #define GPIO_LCKR_LCK8_Pos             (8U)
4373 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
4374 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
4375 #define GPIO_LCKR_LCK9_Pos             (9U)
4376 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
4377 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
4378 #define GPIO_LCKR_LCK10_Pos            (10U)
4379 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
4380 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
4381 #define GPIO_LCKR_LCK11_Pos            (11U)
4382 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
4383 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
4384 #define GPIO_LCKR_LCK12_Pos            (12U)
4385 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
4386 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
4387 #define GPIO_LCKR_LCK13_Pos            (13U)
4388 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
4389 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
4390 #define GPIO_LCKR_LCK14_Pos            (14U)
4391 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
4392 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
4393 #define GPIO_LCKR_LCK15_Pos            (15U)
4394 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
4395 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
4396 #define GPIO_LCKR_LCKK_Pos             (16U)
4397 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
4398 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
4399 
4400 /****************** Bit definition for GPIO_AFRL register *********************/
4401 #define GPIO_AFRL_AFSEL0_Pos           (0U)
4402 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
4403 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
4404 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
4405 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
4406 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
4407 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
4408 #define GPIO_AFRL_AFSEL1_Pos           (4U)
4409 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
4410 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
4411 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
4412 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
4413 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
4414 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
4415 #define GPIO_AFRL_AFSEL2_Pos           (8U)
4416 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
4417 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
4418 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
4419 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
4420 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
4421 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
4422 #define GPIO_AFRL_AFSEL3_Pos           (12U)
4423 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
4424 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
4425 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
4426 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
4427 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
4428 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
4429 #define GPIO_AFRL_AFSEL4_Pos           (16U)
4430 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
4431 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
4432 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
4433 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
4434 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
4435 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
4436 #define GPIO_AFRL_AFSEL5_Pos           (20U)
4437 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
4438 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
4439 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
4440 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
4441 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
4442 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
4443 #define GPIO_AFRL_AFSEL6_Pos           (24U)
4444 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
4445 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
4446 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
4447 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
4448 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
4449 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
4450 #define GPIO_AFRL_AFSEL7_Pos           (28U)
4451 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
4452 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
4453 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
4454 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
4455 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
4456 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
4457 
4458 /* Legacy defines */
4459 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
4460 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
4461 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
4462 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
4463 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
4464 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
4465 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
4466 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
4467 
4468 /****************** Bit definition for GPIO_AFRH register *********************/
4469 #define GPIO_AFRH_AFSEL8_Pos           (0U)
4470 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
4471 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
4472 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
4473 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
4474 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
4475 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
4476 #define GPIO_AFRH_AFSEL9_Pos           (4U)
4477 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
4478 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
4479 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
4480 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
4481 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
4482 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
4483 #define GPIO_AFRH_AFSEL10_Pos          (8U)
4484 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
4485 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
4486 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
4487 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
4488 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
4489 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
4490 #define GPIO_AFRH_AFSEL11_Pos          (12U)
4491 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
4492 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
4493 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
4494 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
4495 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
4496 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
4497 #define GPIO_AFRH_AFSEL12_Pos          (16U)
4498 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
4499 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
4500 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
4501 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
4502 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
4503 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
4504 #define GPIO_AFRH_AFSEL13_Pos          (20U)
4505 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
4506 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
4507 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
4508 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
4509 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
4510 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
4511 #define GPIO_AFRH_AFSEL14_Pos          (24U)
4512 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
4513 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
4514 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
4515 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
4516 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
4517 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
4518 #define GPIO_AFRH_AFSEL15_Pos          (28U)
4519 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
4520 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
4521 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
4522 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
4523 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
4524 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
4525 
4526 /* Legacy defines */
4527 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
4528 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
4529 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
4530 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
4531 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
4532 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
4533 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
4534 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
4535 
4536 /******************  Bits definition for GPIO_BRR register  ******************/
4537 #define GPIO_BRR_BR0_Pos               (0U)
4538 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
4539 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
4540 #define GPIO_BRR_BR1_Pos               (1U)
4541 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
4542 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
4543 #define GPIO_BRR_BR2_Pos               (2U)
4544 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
4545 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
4546 #define GPIO_BRR_BR3_Pos               (3U)
4547 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
4548 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
4549 #define GPIO_BRR_BR4_Pos               (4U)
4550 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
4551 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
4552 #define GPIO_BRR_BR5_Pos               (5U)
4553 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
4554 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
4555 #define GPIO_BRR_BR6_Pos               (6U)
4556 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
4557 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
4558 #define GPIO_BRR_BR7_Pos               (7U)
4559 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
4560 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
4561 #define GPIO_BRR_BR8_Pos               (8U)
4562 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
4563 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
4564 #define GPIO_BRR_BR9_Pos               (9U)
4565 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
4566 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
4567 #define GPIO_BRR_BR10_Pos              (10U)
4568 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
4569 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
4570 #define GPIO_BRR_BR11_Pos              (11U)
4571 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
4572 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
4573 #define GPIO_BRR_BR12_Pos              (12U)
4574 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
4575 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
4576 #define GPIO_BRR_BR13_Pos              (13U)
4577 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
4578 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
4579 #define GPIO_BRR_BR14_Pos              (14U)
4580 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
4581 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
4582 #define GPIO_BRR_BR15_Pos              (15U)
4583 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
4584 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
4585 
4586 /* Legacy defines */
4587 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
4588 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
4589 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
4590 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
4591 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
4592 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
4593 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
4594 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
4595 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
4596 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
4597 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
4598 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
4599 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
4600 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
4601 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
4602 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
4603 
4604 
4605 
4606 /******************************************************************************/
4607 /*                                                                            */
4608 /*                      Inter-integrated Circuit Interface (I2C)              */
4609 /*                                                                            */
4610 /******************************************************************************/
4611 /*******************  Bit definition for I2C_CR1 register  *******************/
4612 #define I2C_CR1_PE_Pos               (0U)
4613 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
4614 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
4615 #define I2C_CR1_TXIE_Pos             (1U)
4616 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
4617 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
4618 #define I2C_CR1_RXIE_Pos             (2U)
4619 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
4620 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
4621 #define I2C_CR1_ADDRIE_Pos           (3U)
4622 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
4623 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
4624 #define I2C_CR1_NACKIE_Pos           (4U)
4625 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
4626 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
4627 #define I2C_CR1_STOPIE_Pos           (5U)
4628 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
4629 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
4630 #define I2C_CR1_TCIE_Pos             (6U)
4631 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
4632 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
4633 #define I2C_CR1_ERRIE_Pos            (7U)
4634 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
4635 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
4636 #define I2C_CR1_DNF_Pos              (8U)
4637 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
4638 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
4639 #define I2C_CR1_ANFOFF_Pos           (12U)
4640 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
4641 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
4642 #define I2C_CR1_SWRST_Pos            (13U)
4643 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
4644 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
4645 #define I2C_CR1_TXDMAEN_Pos          (14U)
4646 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
4647 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
4648 #define I2C_CR1_RXDMAEN_Pos          (15U)
4649 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
4650 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
4651 #define I2C_CR1_SBC_Pos              (16U)
4652 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
4653 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
4654 #define I2C_CR1_NOSTRETCH_Pos        (17U)
4655 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
4656 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
4657 #define I2C_CR1_WUPEN_Pos            (18U)
4658 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
4659 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
4660 #define I2C_CR1_GCEN_Pos             (19U)
4661 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
4662 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
4663 #define I2C_CR1_SMBHEN_Pos           (20U)
4664 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
4665 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
4666 #define I2C_CR1_SMBDEN_Pos           (21U)
4667 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
4668 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
4669 #define I2C_CR1_ALERTEN_Pos          (22U)
4670 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
4671 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
4672 #define I2C_CR1_PECEN_Pos            (23U)
4673 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
4674 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
4675 
4676 /******************  Bit definition for I2C_CR2 register  ********************/
4677 #define I2C_CR2_SADD_Pos             (0U)
4678 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
4679 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
4680 #define I2C_CR2_RD_WRN_Pos           (10U)
4681 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
4682 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
4683 #define I2C_CR2_ADD10_Pos            (11U)
4684 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
4685 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
4686 #define I2C_CR2_HEAD10R_Pos          (12U)
4687 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
4688 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
4689 #define I2C_CR2_START_Pos            (13U)
4690 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
4691 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
4692 #define I2C_CR2_STOP_Pos             (14U)
4693 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
4694 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
4695 #define I2C_CR2_NACK_Pos             (15U)
4696 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
4697 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
4698 #define I2C_CR2_NBYTES_Pos           (16U)
4699 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
4700 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
4701 #define I2C_CR2_RELOAD_Pos           (24U)
4702 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
4703 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
4704 #define I2C_CR2_AUTOEND_Pos          (25U)
4705 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
4706 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
4707 #define I2C_CR2_PECBYTE_Pos          (26U)
4708 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
4709 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
4710 
4711 /*******************  Bit definition for I2C_OAR1 register  ******************/
4712 #define I2C_OAR1_OA1_Pos             (0U)
4713 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
4714 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
4715 #define I2C_OAR1_OA1MODE_Pos         (10U)
4716 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
4717 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
4718 #define I2C_OAR1_OA1EN_Pos           (15U)
4719 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
4720 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
4721 
4722 /*******************  Bit definition for I2C_OAR2 register  ******************/
4723 #define I2C_OAR2_OA2_Pos             (1U)
4724 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
4725 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
4726 #define I2C_OAR2_OA2MSK_Pos          (8U)
4727 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
4728 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
4729 #define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
4730 #define I2C_OAR2_OA2MASK01_Pos       (8U)
4731 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
4732 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
4733 #define I2C_OAR2_OA2MASK02_Pos       (9U)
4734 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
4735 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4736 #define I2C_OAR2_OA2MASK03_Pos       (8U)
4737 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
4738 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4739 #define I2C_OAR2_OA2MASK04_Pos       (10U)
4740 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
4741 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4742 #define I2C_OAR2_OA2MASK05_Pos       (8U)
4743 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
4744 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4745 #define I2C_OAR2_OA2MASK06_Pos       (9U)
4746 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
4747 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
4748 #define I2C_OAR2_OA2MASK07_Pos       (8U)
4749 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
4750 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
4751 #define I2C_OAR2_OA2EN_Pos           (15U)
4752 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
4753 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
4754 
4755 /*******************  Bit definition for I2C_TIMINGR register *******************/
4756 #define I2C_TIMINGR_SCLL_Pos         (0U)
4757 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
4758 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
4759 #define I2C_TIMINGR_SCLH_Pos         (8U)
4760 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
4761 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
4762 #define I2C_TIMINGR_SDADEL_Pos       (16U)
4763 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
4764 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
4765 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
4766 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
4767 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
4768 #define I2C_TIMINGR_PRESC_Pos        (28U)
4769 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
4770 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
4771 
4772 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4773 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
4774 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
4775 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
4776 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
4777 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
4778 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
4779 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
4780 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
4781 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
4782 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
4783 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
4784 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
4785 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
4786 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
4787 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
4788 
4789 /******************  Bit definition for I2C_ISR register  *********************/
4790 #define I2C_ISR_TXE_Pos              (0U)
4791 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
4792 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
4793 #define I2C_ISR_TXIS_Pos             (1U)
4794 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
4795 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
4796 #define I2C_ISR_RXNE_Pos             (2U)
4797 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
4798 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
4799 #define I2C_ISR_ADDR_Pos             (3U)
4800 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
4801 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
4802 #define I2C_ISR_NACKF_Pos            (4U)
4803 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
4804 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
4805 #define I2C_ISR_STOPF_Pos            (5U)
4806 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
4807 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
4808 #define I2C_ISR_TC_Pos               (6U)
4809 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
4810 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
4811 #define I2C_ISR_TCR_Pos              (7U)
4812 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
4813 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
4814 #define I2C_ISR_BERR_Pos             (8U)
4815 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
4816 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
4817 #define I2C_ISR_ARLO_Pos             (9U)
4818 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
4819 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
4820 #define I2C_ISR_OVR_Pos              (10U)
4821 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
4822 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
4823 #define I2C_ISR_PECERR_Pos           (11U)
4824 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
4825 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
4826 #define I2C_ISR_TIMEOUT_Pos          (12U)
4827 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
4828 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
4829 #define I2C_ISR_ALERT_Pos            (13U)
4830 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
4831 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
4832 #define I2C_ISR_BUSY_Pos             (15U)
4833 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
4834 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
4835 #define I2C_ISR_DIR_Pos              (16U)
4836 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
4837 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
4838 #define I2C_ISR_ADDCODE_Pos          (17U)
4839 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
4840 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
4841 
4842 /******************  Bit definition for I2C_ICR register  *********************/
4843 #define I2C_ICR_ADDRCF_Pos           (3U)
4844 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
4845 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
4846 #define I2C_ICR_NACKCF_Pos           (4U)
4847 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
4848 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
4849 #define I2C_ICR_STOPCF_Pos           (5U)
4850 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
4851 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
4852 #define I2C_ICR_BERRCF_Pos           (8U)
4853 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
4854 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
4855 #define I2C_ICR_ARLOCF_Pos           (9U)
4856 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
4857 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
4858 #define I2C_ICR_OVRCF_Pos            (10U)
4859 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
4860 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
4861 #define I2C_ICR_PECCF_Pos            (11U)
4862 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
4863 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
4864 #define I2C_ICR_TIMOUTCF_Pos         (12U)
4865 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
4866 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
4867 #define I2C_ICR_ALERTCF_Pos          (13U)
4868 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
4869 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
4870 
4871 /******************  Bit definition for I2C_PECR register  *********************/
4872 #define I2C_PECR_PEC_Pos             (0U)
4873 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
4874 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
4875 
4876 /******************  Bit definition for I2C_RXDR register  *********************/
4877 #define I2C_RXDR_RXDATA_Pos          (0U)
4878 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
4879 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
4880 
4881 /******************  Bit definition for I2C_TXDR register  *********************/
4882 #define I2C_TXDR_TXDATA_Pos          (0U)
4883 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
4884 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
4885 
4886 /******************************************************************************/
4887 /*                                                                            */
4888 /*                           Independent WATCHDOG                             */
4889 /*                                                                            */
4890 /******************************************************************************/
4891 /*******************  Bit definition for IWDG_KR register  ********************/
4892 #define IWDG_KR_KEY_Pos      (0U)
4893 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
4894 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
4895 
4896 /*******************  Bit definition for IWDG_PR register  ********************/
4897 #define IWDG_PR_PR_Pos       (0U)
4898 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
4899 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
4900 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
4901 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
4902 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
4903 
4904 /*******************  Bit definition for IWDG_RLR register  *******************/
4905 #define IWDG_RLR_RL_Pos      (0U)
4906 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
4907 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
4908 
4909 /*******************  Bit definition for IWDG_SR register  ********************/
4910 #define IWDG_SR_PVU_Pos      (0U)
4911 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
4912 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
4913 #define IWDG_SR_RVU_Pos      (1U)
4914 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
4915 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
4916 #define IWDG_SR_WVU_Pos      (2U)
4917 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
4918 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
4919 
4920 /*******************  Bit definition for IWDG_KR register  ********************/
4921 #define IWDG_WINR_WIN_Pos    (0U)
4922 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
4923 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
4924 
4925 /******************************************************************************/
4926 /*                                                                            */
4927 /*                                     Firewall                               */
4928 /*                                                                            */
4929 /******************************************************************************/
4930 
4931 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
4932 #define FW_CSSA_ADD_Pos      (8U)
4933 #define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                     /*!< 0x00FFFF00 */
4934 #define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
4935 #define FW_CSL_LENG_Pos      (8U)
4936 #define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                     /*!< 0x003FFF00 */
4937 #define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
4938 #define FW_NVDSSA_ADD_Pos    (8U)
4939 #define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                   /*!< 0x00FFFF00 */
4940 #define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
4941 #define FW_NVDSL_LENG_Pos    (8U)
4942 #define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                   /*!< 0x003FFF00 */
4943 #define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
4944 #define FW_VDSSA_ADD_Pos     (6U)
4945 #define FW_VDSSA_ADD_Msk     (0x7FFUL << FW_VDSSA_ADD_Pos)                     /*!< 0x0001FFC0 */
4946 #define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
4947 #define FW_VDSL_LENG_Pos     (6U)
4948 #define FW_VDSL_LENG_Msk     (0x7FFUL << FW_VDSL_LENG_Pos)                     /*!< 0x0001FFC0 */
4949 #define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
4950 
4951 /**************************Bit definition for CR register *********************/
4952 #define FW_CR_FPA_Pos        (0U)
4953 #define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                          /*!< 0x00000001 */
4954 #define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
4955 #define FW_CR_VDS_Pos        (1U)
4956 #define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                          /*!< 0x00000002 */
4957 #define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
4958 #define FW_CR_VDE_Pos        (2U)
4959 #define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                          /*!< 0x00000004 */
4960 #define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
4961 
4962 /******************************************************************************/
4963 /*                                                                            */
4964 /*                             Power Control                                  */
4965 /*                                                                            */
4966 /******************************************************************************/
4967 
4968 /********************  Bit definition for PWR_CR1 register  ********************/
4969 
4970 #define PWR_CR1_LPR_Pos              (14U)
4971 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
4972 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
4973 #define PWR_CR1_VOS_Pos              (9U)
4974 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
4975 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
4976 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
4977 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
4978 #define PWR_CR1_DBP_Pos              (8U)
4979 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
4980 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
4981 #define PWR_CR1_LPMS_Pos             (0U)
4982 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
4983 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
4984 #define PWR_CR1_LPMS_STOP0           (0x00000000UL)                            /*!< Stop 0 mode */
4985 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
4986 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
4987 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
4988 #define PWR_CR1_LPMS_STOP2_Pos       (1U)
4989 #define PWR_CR1_LPMS_STOP2_Msk       (0x1UL << PWR_CR1_LPMS_STOP2_Pos)         /*!< 0x00000002 */
4990 #define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
4991 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
4992 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
4993 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
4994 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
4995 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
4996 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
4997 
4998 
4999 /********************  Bit definition for PWR_CR2 register  ********************/
5000 #define PWR_CR2_USV_Pos              (10U)
5001 #define PWR_CR2_USV_Msk              (0x1UL << PWR_CR2_USV_Pos)                /*!< 0x00000400 */
5002 #define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
5003 /*!< PVME  Peripheral Voltage Monitor Enable */
5004 #define PWR_CR2_PVME_Pos             (4U)
5005 #define PWR_CR2_PVME_Msk             (0xDUL << PWR_CR2_PVME_Pos)               /*!< 0x000000D0 */
5006 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
5007 #define PWR_CR2_PVME4_Pos            (7U)
5008 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
5009 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
5010 #define PWR_CR2_PVME3_Pos            (6U)
5011 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
5012 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
5013 #define PWR_CR2_PVME1_Pos            (4U)
5014 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
5015 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
5016 /*!< PVD level configuration */
5017 #define PWR_CR2_PLS_Pos              (1U)
5018 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
5019 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
5020 #define PWR_CR2_PLS_LEV0             (0x00000000UL)                            /*!< PVD level 0 */
5021 #define PWR_CR2_PLS_LEV1_Pos         (1U)
5022 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
5023 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
5024 #define PWR_CR2_PLS_LEV2_Pos         (2U)
5025 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
5026 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
5027 #define PWR_CR2_PLS_LEV3_Pos         (1U)
5028 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
5029 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
5030 #define PWR_CR2_PLS_LEV4_Pos         (3U)
5031 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
5032 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
5033 #define PWR_CR2_PLS_LEV5_Pos         (1U)
5034 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
5035 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
5036 #define PWR_CR2_PLS_LEV6_Pos         (2U)
5037 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
5038 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
5039 #define PWR_CR2_PLS_LEV7_Pos         (1U)
5040 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
5041 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
5042 #define PWR_CR2_PVDE_Pos             (0U)
5043 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
5044 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
5045 
5046 /********************  Bit definition for PWR_CR3 register  ********************/
5047 #define PWR_CR3_EIWUL_Pos            (15U)
5048 #define PWR_CR3_EIWUL_Msk            (0x1UL << PWR_CR3_EIWUL_Pos)              /*!< 0x00008000 */
5049 #define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */
5050 #define PWR_CR3_ENULP_Pos            (11U)
5051 #define PWR_CR3_ENULP_Msk            (0x1UL << PWR_CR3_ENULP_Pos)              /*!< 0x00000800 */
5052 #define PWR_CR3_ENULP                PWR_CR3_ENULP_Msk                         /*!< Enable ULP BORL, BORH and PVD for STOP2 and Standby modes */
5053 #define PWR_CR3_APC_Pos              (10U)
5054 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
5055 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
5056 #define PWR_CR3_RRS_Pos              (8U)
5057 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
5058 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
5059 #define PWR_CR3_EWUP5_Pos            (4U)
5060 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
5061 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
5062 #define PWR_CR3_EWUP4_Pos            (3U)
5063 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
5064 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
5065 #define PWR_CR3_EWUP3_Pos            (2U)
5066 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
5067 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
5068 #define PWR_CR3_EWUP2_Pos            (1U)
5069 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
5070 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
5071 #define PWR_CR3_EWUP1_Pos            (0U)
5072 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
5073 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
5074 #define PWR_CR3_EWUP_Pos             (0U)
5075 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
5076 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
5077 
5078 /* Legacy defines */
5079 #define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos
5080 #define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk
5081 #define PWR_CR3_EIWF                 PWR_CR3_EIWUL
5082 
5083 
5084 /********************  Bit definition for PWR_CR4 register  ********************/
5085 #define PWR_CR4_EXT_SMPS_ON_Pos      (13U)
5086 #define PWR_CR4_EXT_SMPS_ON_Msk      (0x1UL << PWR_CR4_EXT_SMPS_ON_Pos)         /*!< 0x00002000 */
5087 #define PWR_CR4_EXT_SMPS_ON          PWR_CR4_EXT_SMPS_ON_Msk                   /*!< Inform the internal regulator on external SMPS switch status */
5088 #define PWR_CR4_VBRS_Pos             (9U)
5089 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
5090 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
5091 #define PWR_CR4_VBE_Pos              (8U)
5092 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
5093 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
5094 #define PWR_CR4_WP5_Pos              (4U)
5095 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
5096 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
5097 #define PWR_CR4_WP4_Pos              (3U)
5098 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
5099 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
5100 #define PWR_CR4_WP3_Pos              (2U)
5101 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
5102 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
5103 #define PWR_CR4_WP2_Pos              (1U)
5104 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
5105 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
5106 #define PWR_CR4_WP1_Pos              (0U)
5107 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
5108 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
5109 
5110 /********************  Bit definition for PWR_SR1 register  ********************/
5111 #define PWR_SR1_WUFI_Pos             (15U)
5112 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
5113 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
5114 #define PWR_SR1_EXT_SMPS_RDY_Pos     (13U)
5115 #define PWR_SR1_EXT_SMPS_RDY_Msk     (0x1UL << PWR_SR1_EXT_SMPS_RDY_Pos)        /*!< 0x00002000 */
5116 #define PWR_SR1_EXT_SMPS_RDY         PWR_SR1_EXT_SMPS_RDY_Msk                  /*!< Switching to external SMPS Ready Flag */
5117 #define PWR_SR1_SBF_Pos              (8U)
5118 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
5119 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
5120 #define PWR_SR1_WUF_Pos              (0U)
5121 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
5122 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
5123 #define PWR_SR1_WUF5_Pos             (4U)
5124 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
5125 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
5126 #define PWR_SR1_WUF4_Pos             (3U)
5127 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
5128 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
5129 #define PWR_SR1_WUF3_Pos             (2U)
5130 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
5131 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
5132 #define PWR_SR1_WUF2_Pos             (1U)
5133 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
5134 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
5135 #define PWR_SR1_WUF1_Pos             (0U)
5136 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
5137 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
5138 
5139 /********************  Bit definition for PWR_SR2 register  ********************/
5140 #define PWR_SR2_PVMO4_Pos            (15U)
5141 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
5142 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
5143 #define PWR_SR2_PVMO3_Pos            (14U)
5144 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
5145 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
5146 #define PWR_SR2_PVMO1_Pos            (12U)
5147 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
5148 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
5149 #define PWR_SR2_PVDO_Pos             (11U)
5150 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
5151 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
5152 #define PWR_SR2_VOSF_Pos             (10U)
5153 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
5154 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
5155 #define PWR_SR2_REGLPF_Pos           (9U)
5156 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
5157 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
5158 #define PWR_SR2_REGLPS_Pos           (8U)
5159 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
5160 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
5161 
5162 /********************  Bit definition for PWR_SCR register  ********************/
5163 #define PWR_SCR_CSBF_Pos             (8U)
5164 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
5165 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
5166 #define PWR_SCR_CWUF_Pos             (0U)
5167 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
5168 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
5169 #define PWR_SCR_CWUF5_Pos            (4U)
5170 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
5171 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
5172 #define PWR_SCR_CWUF4_Pos            (3U)
5173 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
5174 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
5175 #define PWR_SCR_CWUF3_Pos            (2U)
5176 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
5177 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
5178 #define PWR_SCR_CWUF2_Pos            (1U)
5179 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
5180 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
5181 #define PWR_SCR_CWUF1_Pos            (0U)
5182 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
5183 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
5184 
5185 /********************  Bit definition for PWR_PUCRA register  ********************/
5186 #define PWR_PUCRA_PA15_Pos           (15U)
5187 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
5188 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
5189 #define PWR_PUCRA_PA13_Pos           (13U)
5190 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
5191 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
5192 #define PWR_PUCRA_PA12_Pos           (12U)
5193 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
5194 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
5195 #define PWR_PUCRA_PA11_Pos           (11U)
5196 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
5197 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
5198 #define PWR_PUCRA_PA10_Pos           (10U)
5199 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
5200 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
5201 #define PWR_PUCRA_PA9_Pos            (9U)
5202 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
5203 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
5204 #define PWR_PUCRA_PA8_Pos            (8U)
5205 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
5206 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
5207 #define PWR_PUCRA_PA7_Pos            (7U)
5208 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
5209 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
5210 #define PWR_PUCRA_PA6_Pos            (6U)
5211 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
5212 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
5213 #define PWR_PUCRA_PA5_Pos            (5U)
5214 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
5215 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
5216 #define PWR_PUCRA_PA4_Pos            (4U)
5217 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
5218 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
5219 #define PWR_PUCRA_PA3_Pos            (3U)
5220 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
5221 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
5222 #define PWR_PUCRA_PA2_Pos            (2U)
5223 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
5224 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
5225 #define PWR_PUCRA_PA1_Pos            (1U)
5226 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
5227 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
5228 #define PWR_PUCRA_PA0_Pos            (0U)
5229 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
5230 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
5231 
5232 /********************  Bit definition for PWR_PDCRA register  ********************/
5233 #define PWR_PDCRA_PA14_Pos           (14U)
5234 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
5235 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
5236 #define PWR_PDCRA_PA12_Pos           (12U)
5237 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
5238 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
5239 #define PWR_PDCRA_PA11_Pos           (11U)
5240 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
5241 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
5242 #define PWR_PDCRA_PA10_Pos           (10U)
5243 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
5244 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
5245 #define PWR_PDCRA_PA9_Pos            (9U)
5246 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
5247 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
5248 #define PWR_PDCRA_PA8_Pos            (8U)
5249 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
5250 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
5251 #define PWR_PDCRA_PA7_Pos            (7U)
5252 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
5253 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
5254 #define PWR_PDCRA_PA6_Pos            (6U)
5255 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
5256 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
5257 #define PWR_PDCRA_PA5_Pos            (5U)
5258 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
5259 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
5260 #define PWR_PDCRA_PA4_Pos            (4U)
5261 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
5262 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
5263 #define PWR_PDCRA_PA3_Pos            (3U)
5264 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
5265 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
5266 #define PWR_PDCRA_PA2_Pos            (2U)
5267 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
5268 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
5269 #define PWR_PDCRA_PA1_Pos            (1U)
5270 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
5271 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
5272 #define PWR_PDCRA_PA0_Pos            (0U)
5273 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
5274 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
5275 
5276 /********************  Bit definition for PWR_PUCRB register  ********************/
5277 #define PWR_PUCRB_PB15_Pos           (15U)
5278 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
5279 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
5280 #define PWR_PUCRB_PB14_Pos           (14U)
5281 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
5282 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
5283 #define PWR_PUCRB_PB13_Pos           (13U)
5284 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
5285 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
5286 #define PWR_PUCRB_PB12_Pos           (12U)
5287 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
5288 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
5289 #define PWR_PUCRB_PB11_Pos           (11U)
5290 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
5291 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
5292 #define PWR_PUCRB_PB10_Pos           (10U)
5293 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
5294 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
5295 #define PWR_PUCRB_PB9_Pos            (9U)
5296 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
5297 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
5298 #define PWR_PUCRB_PB8_Pos            (8U)
5299 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
5300 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
5301 #define PWR_PUCRB_PB7_Pos            (7U)
5302 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
5303 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
5304 #define PWR_PUCRB_PB6_Pos            (6U)
5305 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
5306 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
5307 #define PWR_PUCRB_PB5_Pos            (5U)
5308 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
5309 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
5310 #define PWR_PUCRB_PB4_Pos            (4U)
5311 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
5312 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
5313 #define PWR_PUCRB_PB3_Pos            (3U)
5314 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
5315 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
5316 #define PWR_PUCRB_PB2_Pos            (2U)
5317 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
5318 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
5319 #define PWR_PUCRB_PB1_Pos            (1U)
5320 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
5321 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
5322 #define PWR_PUCRB_PB0_Pos            (0U)
5323 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
5324 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
5325 
5326 /********************  Bit definition for PWR_PDCRB register  ********************/
5327 #define PWR_PDCRB_PB15_Pos           (15U)
5328 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
5329 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
5330 #define PWR_PDCRB_PB14_Pos           (14U)
5331 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
5332 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
5333 #define PWR_PDCRB_PB13_Pos           (13U)
5334 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
5335 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
5336 #define PWR_PDCRB_PB12_Pos           (12U)
5337 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
5338 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
5339 #define PWR_PDCRB_PB11_Pos           (11U)
5340 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
5341 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
5342 #define PWR_PDCRB_PB10_Pos           (10U)
5343 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
5344 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
5345 #define PWR_PDCRB_PB9_Pos            (9U)
5346 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
5347 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
5348 #define PWR_PDCRB_PB8_Pos            (8U)
5349 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
5350 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
5351 #define PWR_PDCRB_PB7_Pos            (7U)
5352 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
5353 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
5354 #define PWR_PDCRB_PB6_Pos            (6U)
5355 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
5356 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
5357 #define PWR_PDCRB_PB5_Pos            (5U)
5358 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
5359 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
5360 #define PWR_PDCRB_PB3_Pos            (3U)
5361 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
5362 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
5363 #define PWR_PDCRB_PB2_Pos            (2U)
5364 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
5365 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
5366 #define PWR_PDCRB_PB1_Pos            (1U)
5367 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
5368 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
5369 #define PWR_PDCRB_PB0_Pos            (0U)
5370 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
5371 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
5372 
5373 /********************  Bit definition for PWR_PUCRC register  ********************/
5374 #define PWR_PUCRC_PC15_Pos           (15U)
5375 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
5376 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
5377 #define PWR_PUCRC_PC14_Pos           (14U)
5378 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
5379 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
5380 #define PWR_PUCRC_PC13_Pos           (13U)
5381 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
5382 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
5383 #define PWR_PUCRC_PC12_Pos           (12U)
5384 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
5385 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
5386 #define PWR_PUCRC_PC11_Pos           (11U)
5387 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
5388 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
5389 #define PWR_PUCRC_PC10_Pos           (10U)
5390 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
5391 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
5392 #define PWR_PUCRC_PC9_Pos            (9U)
5393 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
5394 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
5395 #define PWR_PUCRC_PC8_Pos            (8U)
5396 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
5397 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
5398 #define PWR_PUCRC_PC7_Pos            (7U)
5399 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
5400 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
5401 #define PWR_PUCRC_PC6_Pos            (6U)
5402 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
5403 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
5404 #define PWR_PUCRC_PC5_Pos            (5U)
5405 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
5406 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
5407 #define PWR_PUCRC_PC4_Pos            (4U)
5408 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
5409 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
5410 #define PWR_PUCRC_PC3_Pos            (3U)
5411 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
5412 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
5413 #define PWR_PUCRC_PC2_Pos            (2U)
5414 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
5415 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
5416 #define PWR_PUCRC_PC1_Pos            (1U)
5417 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
5418 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
5419 #define PWR_PUCRC_PC0_Pos            (0U)
5420 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
5421 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
5422 
5423 /********************  Bit definition for PWR_PDCRC register  ********************/
5424 #define PWR_PDCRC_PC15_Pos           (15U)
5425 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
5426 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
5427 #define PWR_PDCRC_PC14_Pos           (14U)
5428 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
5429 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
5430 #define PWR_PDCRC_PC13_Pos           (13U)
5431 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
5432 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
5433 #define PWR_PDCRC_PC12_Pos           (12U)
5434 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
5435 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
5436 #define PWR_PDCRC_PC11_Pos           (11U)
5437 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
5438 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
5439 #define PWR_PDCRC_PC10_Pos           (10U)
5440 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
5441 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
5442 #define PWR_PDCRC_PC9_Pos            (9U)
5443 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
5444 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
5445 #define PWR_PDCRC_PC8_Pos            (8U)
5446 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
5447 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
5448 #define PWR_PDCRC_PC7_Pos            (7U)
5449 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
5450 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
5451 #define PWR_PDCRC_PC6_Pos            (6U)
5452 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
5453 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
5454 #define PWR_PDCRC_PC5_Pos            (5U)
5455 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
5456 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
5457 #define PWR_PDCRC_PC4_Pos            (4U)
5458 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
5459 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
5460 #define PWR_PDCRC_PC3_Pos            (3U)
5461 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
5462 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
5463 #define PWR_PDCRC_PC2_Pos            (2U)
5464 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
5465 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
5466 #define PWR_PDCRC_PC1_Pos            (1U)
5467 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
5468 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
5469 #define PWR_PDCRC_PC0_Pos            (0U)
5470 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
5471 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
5472 
5473 /********************  Bit definition for PWR_PUCRD register  ********************/
5474 #define PWR_PUCRD_PD15_Pos           (15U)
5475 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
5476 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
5477 #define PWR_PUCRD_PD14_Pos           (14U)
5478 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
5479 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
5480 #define PWR_PUCRD_PD13_Pos           (13U)
5481 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
5482 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
5483 #define PWR_PUCRD_PD12_Pos           (12U)
5484 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
5485 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
5486 #define PWR_PUCRD_PD11_Pos           (11U)
5487 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
5488 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
5489 #define PWR_PUCRD_PD10_Pos           (10U)
5490 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
5491 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
5492 #define PWR_PUCRD_PD9_Pos            (9U)
5493 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
5494 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
5495 #define PWR_PUCRD_PD8_Pos            (8U)
5496 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
5497 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
5498 #define PWR_PUCRD_PD7_Pos            (7U)
5499 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
5500 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
5501 #define PWR_PUCRD_PD6_Pos            (6U)
5502 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
5503 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
5504 #define PWR_PUCRD_PD5_Pos            (5U)
5505 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
5506 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
5507 #define PWR_PUCRD_PD4_Pos            (4U)
5508 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
5509 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
5510 #define PWR_PUCRD_PD3_Pos            (3U)
5511 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
5512 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
5513 #define PWR_PUCRD_PD2_Pos            (2U)
5514 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
5515 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
5516 #define PWR_PUCRD_PD1_Pos            (1U)
5517 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
5518 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
5519 #define PWR_PUCRD_PD0_Pos            (0U)
5520 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
5521 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
5522 
5523 /********************  Bit definition for PWR_PDCRD register  ********************/
5524 #define PWR_PDCRD_PD15_Pos           (15U)
5525 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
5526 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
5527 #define PWR_PDCRD_PD14_Pos           (14U)
5528 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
5529 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
5530 #define PWR_PDCRD_PD13_Pos           (13U)
5531 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
5532 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
5533 #define PWR_PDCRD_PD12_Pos           (12U)
5534 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
5535 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
5536 #define PWR_PDCRD_PD11_Pos           (11U)
5537 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
5538 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
5539 #define PWR_PDCRD_PD10_Pos           (10U)
5540 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
5541 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
5542 #define PWR_PDCRD_PD9_Pos            (9U)
5543 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
5544 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
5545 #define PWR_PDCRD_PD8_Pos            (8U)
5546 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
5547 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
5548 #define PWR_PDCRD_PD7_Pos            (7U)
5549 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
5550 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
5551 #define PWR_PDCRD_PD6_Pos            (6U)
5552 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
5553 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
5554 #define PWR_PDCRD_PD5_Pos            (5U)
5555 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
5556 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
5557 #define PWR_PDCRD_PD4_Pos            (4U)
5558 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
5559 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
5560 #define PWR_PDCRD_PD3_Pos            (3U)
5561 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
5562 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
5563 #define PWR_PDCRD_PD2_Pos            (2U)
5564 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
5565 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
5566 #define PWR_PDCRD_PD1_Pos            (1U)
5567 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
5568 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
5569 #define PWR_PDCRD_PD0_Pos            (0U)
5570 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
5571 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
5572 
5573 
5574 
5575 /********************  Bit definition for PWR_PUCRH register  ********************/
5576 #define PWR_PUCRH_PH3_Pos            (3U)
5577 #define PWR_PUCRH_PH3_Msk            (0x1UL << PWR_PUCRH_PH3_Pos)              /*!< 0x00000008 */
5578 #define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
5579 #define PWR_PUCRH_PH1_Pos            (1U)
5580 #define PWR_PUCRH_PH1_Msk            (0x1UL << PWR_PUCRH_PH1_Pos)              /*!< 0x00000002 */
5581 #define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
5582 #define PWR_PUCRH_PH0_Pos            (0U)
5583 #define PWR_PUCRH_PH0_Msk            (0x1UL << PWR_PUCRH_PH0_Pos)              /*!< 0x00000001 */
5584 #define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
5585 
5586 /********************  Bit definition for PWR_PDCRH register  ********************/
5587 #define PWR_PDCRH_PH3_Pos            (3U)
5588 #define PWR_PDCRH_PH3_Msk            (0x1UL << PWR_PDCRH_PH3_Pos)              /*!< 0x00000008 */
5589 #define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
5590 #define PWR_PDCRH_PH1_Pos            (1U)
5591 #define PWR_PDCRH_PH1_Msk            (0x1UL << PWR_PDCRH_PH1_Pos)              /*!< 0x00000002 */
5592 #define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
5593 #define PWR_PDCRH_PH0_Pos            (0U)
5594 #define PWR_PDCRH_PH0_Msk            (0x1UL << PWR_PDCRH_PH0_Pos)              /*!< 0x00000001 */
5595 #define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
5596 
5597 
5598 /******************************************************************************/
5599 /*                                                                            */
5600 /*                         Reset and Clock Control                            */
5601 /*                                                                            */
5602 /******************************************************************************/
5603 /*
5604 * @brief Specific device feature definitions  (not present on all devices in the STM32L4 series)
5605 */
5606 #define RCC_HSI48_SUPPORT
5607 
5608 /********************  Bit definition for RCC_CR register  ********************/
5609 #define RCC_CR_MSION_Pos                     (0U)
5610 #define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
5611 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
5612 #define RCC_CR_MSIRDY_Pos                    (1U)
5613 #define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
5614 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
5615 #define RCC_CR_MSIPLLEN_Pos                  (2U)
5616 #define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
5617 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
5618 #define RCC_CR_MSIRGSEL_Pos                  (3U)
5619 #define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
5620 #define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
5621 
5622 /*!< MSIRANGE configuration : 12 frequency ranges available */
5623 #define RCC_CR_MSIRANGE_Pos                  (4U)
5624 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
5625 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
5626 #define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
5627 #define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
5628 #define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
5629 #define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
5630 #define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
5631 #define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
5632 #define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
5633 #define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
5634 #define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
5635 #define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
5636 #define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
5637 #define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
5638 
5639 #define RCC_CR_HSION_Pos                     (8U)
5640 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
5641 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
5642 #define RCC_CR_HSIKERON_Pos                  (9U)
5643 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
5644 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
5645 #define RCC_CR_HSIRDY_Pos                    (10U)
5646 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
5647 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
5648 #define RCC_CR_HSIASFS_Pos                   (11U)
5649 #define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
5650 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
5651 
5652 #define RCC_CR_HSEON_Pos                     (16U)
5653 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
5654 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
5655 #define RCC_CR_HSERDY_Pos                    (17U)
5656 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
5657 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
5658 #define RCC_CR_HSEBYP_Pos                    (18U)
5659 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
5660 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
5661 #define RCC_CR_CSSON_Pos                     (19U)
5662 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
5663 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
5664 
5665 #define RCC_CR_PLLON_Pos                     (24U)
5666 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
5667 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
5668 #define RCC_CR_PLLRDY_Pos                    (25U)
5669 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
5670 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
5671 
5672 /********************  Bit definition for RCC_ICSCR register  ***************/
5673 /*!< MSICAL configuration */
5674 #define RCC_ICSCR_MSICAL_Pos                 (0U)
5675 #define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
5676 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
5677 #define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */
5678 #define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */
5679 #define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */
5680 #define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */
5681 #define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */
5682 #define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */
5683 #define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */
5684 #define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */
5685 
5686 /*!< MSITRIM configuration */
5687 #define RCC_ICSCR_MSITRIM_Pos                (8U)
5688 #define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
5689 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
5690 #define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
5691 #define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
5692 #define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
5693 #define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
5694 #define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
5695 #define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
5696 #define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
5697 #define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
5698 
5699 /*!< HSICAL configuration */
5700 #define RCC_ICSCR_HSICAL_Pos                 (16U)
5701 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
5702 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
5703 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
5704 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
5705 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
5706 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
5707 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
5708 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
5709 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
5710 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
5711 
5712 /*!< HSITRIM configuration */
5713 #define RCC_ICSCR_HSITRIM_Pos                (24U)
5714 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
5715 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
5716 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
5717 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
5718 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
5719 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
5720 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
5721 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
5722 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
5723 
5724 /********************  Bit definition for RCC_CFGR register  ******************/
5725 /*!< SW configuration */
5726 #define RCC_CFGR_SW_Pos                      (0U)
5727 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
5728 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
5729 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
5730 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
5731 
5732 #define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */
5733 #define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */
5734 #define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */
5735 #define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */
5736 
5737 /*!< SWS configuration */
5738 #define RCC_CFGR_SWS_Pos                     (2U)
5739 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
5740 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
5741 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
5742 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
5743 
5744 #define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */
5745 #define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */
5746 #define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */
5747 #define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */
5748 
5749 /*!< HPRE configuration */
5750 #define RCC_CFGR_HPRE_Pos                    (4U)
5751 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
5752 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
5753 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
5754 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
5755 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
5756 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
5757 
5758 #define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */
5759 #define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */
5760 #define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */
5761 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */
5762 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */
5763 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */
5764 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */
5765 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */
5766 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */
5767 
5768 /*!< PPRE1 configuration */
5769 #define RCC_CFGR_PPRE1_Pos                   (8U)
5770 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
5771 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
5772 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
5773 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
5774 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
5775 
5776 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
5777 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */
5778 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */
5779 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */
5780 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */
5781 
5782 /*!< PPRE2 configuration */
5783 #define RCC_CFGR_PPRE2_Pos                   (11U)
5784 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
5785 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
5786 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
5787 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
5788 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
5789 
5790 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
5791 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */
5792 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */
5793 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */
5794 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */
5795 
5796 #define RCC_CFGR_STOPWUCK_Pos                (15U)
5797 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
5798 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
5799 
5800 /*!< MCOSEL configuration */
5801 #define RCC_CFGR_MCOSEL_Pos                  (24U)
5802 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
5803 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
5804 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
5805 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
5806 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
5807 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
5808 
5809 #define RCC_CFGR_MCOPRE_Pos                  (28U)
5810 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
5811 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
5812 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
5813 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
5814 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
5815 
5816 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */
5817 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */
5818 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */
5819 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */
5820 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */
5821 
5822 /* Legacy aliases */
5823 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
5824 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
5825 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
5826 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
5827 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
5828 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
5829 
5830 /********************  Bit definition for RCC_PLLCFGR register  ***************/
5831 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
5832 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5833 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
5834 
5835 #define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)
5836 #define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
5837 #define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
5838 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
5839 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
5840 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
5841 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
5842 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
5843 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
5844 
5845 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
5846 #define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000070 */
5847 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
5848 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
5849 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
5850 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
5851 
5852 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
5853 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
5854 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
5855 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
5856 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
5857 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
5858 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
5859 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
5860 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
5861 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
5862 
5863 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
5864 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
5865 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
5866 
5867 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
5868 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
5869 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
5870 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
5871 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
5872 
5873 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
5874 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
5875 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
5876 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
5877 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
5878 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
5879 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
5880 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
5881 
5882 /********************  Bit definition for RCC_CIER register  ******************/
5883 #define RCC_CIER_LSIRDYIE_Pos                (0U)
5884 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
5885 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
5886 #define RCC_CIER_LSERDYIE_Pos                (1U)
5887 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
5888 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
5889 #define RCC_CIER_MSIRDYIE_Pos                (2U)
5890 #define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)  /*!< 0x00000004 */
5891 #define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
5892 #define RCC_CIER_HSIRDYIE_Pos                (3U)
5893 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
5894 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
5895 #define RCC_CIER_HSERDYIE_Pos                (4U)
5896 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
5897 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
5898 #define RCC_CIER_PLLRDYIE_Pos                (5U)
5899 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
5900 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
5901 #define RCC_CIER_LSECSSIE_Pos                (9U)
5902 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
5903 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
5904 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
5905 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
5906 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
5907 
5908 /********************  Bit definition for RCC_CIFR register  ******************/
5909 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
5910 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
5911 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
5912 #define RCC_CIFR_LSERDYF_Pos                 (1U)
5913 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
5914 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
5915 #define RCC_CIFR_MSIRDYF_Pos                 (2U)
5916 #define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
5917 #define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
5918 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
5919 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
5920 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
5921 #define RCC_CIFR_HSERDYF_Pos                 (4U)
5922 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
5923 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
5924 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
5925 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
5926 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
5927 #define RCC_CIFR_CSSF_Pos                    (8U)
5928 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
5929 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
5930 #define RCC_CIFR_LSECSSF_Pos                 (9U)
5931 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
5932 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
5933 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
5934 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
5935 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
5936 
5937 /********************  Bit definition for RCC_CICR register  ******************/
5938 #define RCC_CICR_LSIRDYC_Pos                 (0U)
5939 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
5940 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
5941 #define RCC_CICR_LSERDYC_Pos                 (1U)
5942 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
5943 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
5944 #define RCC_CICR_MSIRDYC_Pos                 (2U)
5945 #define RCC_CICR_MSIRDYC_Msk                 (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
5946 #define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk
5947 #define RCC_CICR_HSIRDYC_Pos                 (3U)
5948 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
5949 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
5950 #define RCC_CICR_HSERDYC_Pos                 (4U)
5951 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
5952 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
5953 #define RCC_CICR_PLLRDYC_Pos                 (5U)
5954 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
5955 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
5956 #define RCC_CICR_CSSC_Pos                    (8U)
5957 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
5958 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
5959 #define RCC_CICR_LSECSSC_Pos                 (9U)
5960 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
5961 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
5962 #define RCC_CICR_HSI48RDYC_Pos               (10U)
5963 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
5964 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
5965 
5966 /********************  Bit definition for RCC_AHB1RSTR register  **************/
5967 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
5968 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
5969 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
5970 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
5971 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
5972 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
5973 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
5974 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
5975 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
5976 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
5977 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
5978 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
5979 #define RCC_AHB1RSTR_TSCRST_Pos              (16U)
5980 #define RCC_AHB1RSTR_TSCRST_Msk              (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
5981 #define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk
5982 
5983 /********************  Bit definition for RCC_AHB2RSTR register  **************/
5984 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
5985 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
5986 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
5987 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
5988 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
5989 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
5990 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
5991 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
5992 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
5993 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
5994 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
5995 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
5996 #define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)
5997 #define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
5998 #define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk
5999 #define RCC_AHB2RSTR_ADCRST_Pos              (13U)
6000 #define RCC_AHB2RSTR_ADCRST_Msk              (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
6001 #define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk
6002 #define RCC_AHB2RSTR_AESRST_Pos              (16U)
6003 #define RCC_AHB2RSTR_AESRST_Msk              (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */
6004 #define RCC_AHB2RSTR_AESRST                  RCC_AHB2RSTR_AESRST_Msk
6005 #define RCC_AHB2RSTR_RNGRST_Pos              (18U)
6006 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
6007 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
6008 
6009 /********************  Bit definition for RCC_AHB3RSTR register  **************/
6010 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
6011 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
6012 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
6013 
6014 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
6015 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
6016 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
6017 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
6018 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
6019 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
6020 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
6021 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
6022 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
6023 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
6024 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
6025 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
6026 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
6027 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
6028 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
6029 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
6030 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
6031 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
6032 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
6033 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
6034 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
6035 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
6036 #define RCC_APB1RSTR1_I2C3RST_Pos            (23U)
6037 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
6038 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
6039 #define RCC_APB1RSTR1_CRSRST_Pos             (24U)
6040 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
6041 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
6042 #define RCC_APB1RSTR1_USBFSRST_Pos           (26U)
6043 #define RCC_APB1RSTR1_USBFSRST_Msk           (0x1UL << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
6044 #define RCC_APB1RSTR1_USBFSRST               RCC_APB1RSTR1_USBFSRST_Msk
6045 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
6046 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
6047 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
6048 #define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)
6049 #define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
6050 #define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk
6051 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
6052 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
6053 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
6054 
6055 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
6056 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
6057 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
6058 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
6059 #define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)
6060 #define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
6061 #define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk
6062 
6063 /********************  Bit definition for RCC_APB2RSTR register  **************/
6064 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
6065 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
6066 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
6067 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
6068 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
6069 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
6070 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
6071 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
6072 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
6073 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
6074 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
6075 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
6076 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
6077 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
6078 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
6079 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
6080 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
6081 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
6082 
6083 /********************  Bit definition for RCC_AHB1ENR register  ***************/
6084 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
6085 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
6086 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
6087 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
6088 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
6089 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
6090 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
6091 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
6092 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
6093 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
6094 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
6095 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
6096 #define RCC_AHB1ENR_TSCEN_Pos                (16U)
6097 #define RCC_AHB1ENR_TSCEN_Msk                (0x1UL << RCC_AHB1ENR_TSCEN_Pos)  /*!< 0x00010000 */
6098 #define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk
6099 
6100 /********************  Bit definition for RCC_AHB2ENR register  ***************/
6101 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
6102 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
6103 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
6104 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
6105 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
6106 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
6107 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
6108 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
6109 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
6110 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
6111 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
6112 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
6113 #define RCC_AHB2ENR_GPIOHEN_Pos              (7U)
6114 #define RCC_AHB2ENR_GPIOHEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
6115 #define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk
6116 #define RCC_AHB2ENR_ADCEN_Pos                (13U)
6117 #define RCC_AHB2ENR_ADCEN_Msk                (0x1UL << RCC_AHB2ENR_ADCEN_Pos)  /*!< 0x00002000 */
6118 #define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk
6119 #define RCC_AHB2ENR_AESEN_Pos                (16U)
6120 #define RCC_AHB2ENR_AESEN_Msk                (0x1UL << RCC_AHB2ENR_AESEN_Pos)  /*!< 0x00010000 */
6121 #define RCC_AHB2ENR_AESEN                    RCC_AHB2ENR_AESEN_Msk
6122 #define RCC_AHB2ENR_RNGEN_Pos                (18U)
6123 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x00040000 */
6124 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
6125 
6126 /********************  Bit definition for RCC_AHB3ENR register  ***************/
6127 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
6128 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
6129 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
6130 
6131 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
6132 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
6133 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
6134 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
6135 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
6136 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
6137 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
6138 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
6139 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
6140 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
6141 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
6142 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
6143 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
6144 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
6145 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
6146 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
6147 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
6148 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
6149 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
6150 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
6151 #define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
6152 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
6153 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
6154 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
6155 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
6156 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
6157 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
6158 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
6159 #define RCC_APB1ENR1_I2C3EN_Pos              (23U)
6160 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
6161 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
6162 #define RCC_APB1ENR1_CRSEN_Pos               (24U)
6163 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
6164 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
6165 #define RCC_APB1ENR1_USBFSEN_Pos             (26U)
6166 #define RCC_APB1ENR1_USBFSEN_Msk             (0x1UL << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
6167 #define RCC_APB1ENR1_USBFSEN                 RCC_APB1ENR1_USBFSEN_Msk
6168 #define RCC_APB1ENR1_PWREN_Pos               (28U)
6169 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
6170 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
6171 #define RCC_APB1ENR1_OPAMPEN_Pos             (30U)
6172 #define RCC_APB1ENR1_OPAMPEN_Msk             (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
6173 #define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk
6174 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
6175 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
6176 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
6177 
6178 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
6179 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
6180 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
6181 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
6182 #define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)
6183 #define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
6184 #define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk
6185 
6186 /********************  Bit definition for RCC_APB2ENR register  ***************/
6187 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
6188 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
6189 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
6190 #define RCC_APB2ENR_FWEN_Pos                 (7U)
6191 #define RCC_APB2ENR_FWEN_Msk                 (0x1UL << RCC_APB2ENR_FWEN_Pos)   /*!< 0x00000080 */
6192 #define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk
6193 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
6194 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
6195 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
6196 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
6197 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
6198 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
6199 #define RCC_APB2ENR_USART1EN_Pos             (14U)
6200 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
6201 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
6202 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
6203 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
6204 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
6205 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
6206 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
6207 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
6208 
6209 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
6210 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
6211 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
6212 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
6213 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
6214 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
6215 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
6216 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
6217 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
6218 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
6219 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
6220 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
6221 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
6222 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
6223 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
6224 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
6225 #define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)
6226 #define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
6227 #define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk
6228 
6229 /********************  Bit definition for RCC_AHB2SMENR register  *************/
6230 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
6231 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
6232 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
6233 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
6234 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
6235 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
6236 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
6237 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
6238 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
6239 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
6240 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
6241 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
6242 #define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)
6243 #define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
6244 #define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk
6245 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)
6246 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
6247 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
6248 #define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)
6249 #define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
6250 #define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk
6251 #define RCC_AHB2SMENR_AESSMEN_Pos            (16U)
6252 #define RCC_AHB2SMENR_AESSMEN_Msk            (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
6253 #define RCC_AHB2SMENR_AESSMEN                RCC_AHB2SMENR_AESSMEN_Msk
6254 #define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)
6255 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
6256 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
6257 
6258 /********************  Bit definition for RCC_AHB3SMENR register  *************/
6259 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
6260 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
6261 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
6262 
6263 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
6264 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
6265 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
6266 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
6267 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
6268 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
6269 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
6270 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
6271 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
6272 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
6273 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
6274 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
6275 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
6276 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
6277 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
6278 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
6279 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
6280 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
6281 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
6282 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
6283 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
6284 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
6285 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
6286 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
6287 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
6288 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
6289 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
6290 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
6291 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)
6292 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
6293 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
6294 #define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)
6295 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
6296 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
6297 #define RCC_APB1SMENR1_USBFSSMEN_Pos         (26U)
6298 #define RCC_APB1SMENR1_USBFSSMEN_Msk         (0x1UL << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
6299 #define RCC_APB1SMENR1_USBFSSMEN             RCC_APB1SMENR1_USBFSSMEN_Msk
6300 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
6301 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
6302 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
6303 #define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)
6304 #define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
6305 #define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk
6306 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
6307 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
6308 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
6309 
6310 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
6311 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
6312 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
6313 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
6314 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)
6315 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
6316 #define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk
6317 
6318 /********************  Bit definition for RCC_APB2SMENR register  *************/
6319 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
6320 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
6321 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
6322 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
6323 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
6324 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
6325 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
6326 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
6327 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
6328 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
6329 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
6330 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
6331 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
6332 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
6333 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
6334 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
6335 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
6336 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
6337 
6338 /********************  Bit definition for RCC_CCIPR register  ******************/
6339 #define RCC_CCIPR_USART1SEL_Pos              (0U)
6340 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
6341 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
6342 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
6343 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
6344 
6345 #define RCC_CCIPR_USART2SEL_Pos              (2U)
6346 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
6347 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
6348 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
6349 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
6350 
6351 #define RCC_CCIPR_USART3SEL_Pos              (4U)
6352 #define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
6353 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
6354 #define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
6355 #define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
6356 
6357 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
6358 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
6359 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
6360 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
6361 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
6362 
6363 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
6364 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
6365 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
6366 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
6367 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
6368 
6369 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
6370 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
6371 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
6372 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
6373 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
6374 
6375 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
6376 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
6377 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
6378 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
6379 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
6380 
6381 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
6382 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
6383 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
6384 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
6385 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
6386 
6387 #define RCC_CCIPR_LPTIM2SEL_Pos              (20U)
6388 #define RCC_CCIPR_LPTIM2SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
6389 #define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk
6390 #define RCC_CCIPR_LPTIM2SEL_0                (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
6391 #define RCC_CCIPR_LPTIM2SEL_1                (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
6392 
6393 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
6394 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
6395 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
6396 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
6397 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
6398 
6399 
6400 /********************  Bit definition for RCC_BDCR register  ******************/
6401 #define RCC_BDCR_LSEON_Pos                   (0U)
6402 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
6403 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
6404 #define RCC_BDCR_LSERDY_Pos                  (1U)
6405 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
6406 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
6407 #define RCC_BDCR_LSEBYP_Pos                  (2U)
6408 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
6409 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
6410 
6411 #define RCC_BDCR_LSEDRV_Pos                  (3U)
6412 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
6413 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
6414 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
6415 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
6416 
6417 #define RCC_BDCR_LSECSSON_Pos                (5U)
6418 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
6419 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
6420 #define RCC_BDCR_LSECSSD_Pos                 (6U)
6421 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
6422 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
6423 
6424 #define RCC_BDCR_LSESYSDIS_Pos               (7U)
6425 #define RCC_BDCR_LSESYSDIS_Msk               (0x1UL << RCC_BDCR_LSESYSDIS_Pos) /*!< 0x00000080 */
6426 #define RCC_BDCR_LSESYSDIS                   RCC_BDCR_LSESYSDIS_Msk
6427 
6428 #define RCC_BDCR_RTCSEL_Pos                  (8U)
6429 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
6430 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
6431 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
6432 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
6433 
6434 #define RCC_BDCR_RTCEN_Pos                   (15U)
6435 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
6436 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
6437 #define RCC_BDCR_BDRST_Pos                   (16U)
6438 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
6439 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
6440 #define RCC_BDCR_LSCOEN_Pos                  (24U)
6441 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
6442 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
6443 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
6444 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
6445 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
6446 
6447 /********************  Bit definition for RCC_CSR register  *******************/
6448 #define RCC_CSR_LSION_Pos                    (0U)
6449 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
6450 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
6451 #define RCC_CSR_LSIRDY_Pos                   (1U)
6452 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
6453 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
6454 
6455 #define RCC_CSR_LSIPREDIV_Pos                (4U)
6456 #define RCC_CSR_LSIPREDIV_Msk                (0x1UL << RCC_CSR_LSIPREDIV_Pos)  /*!< 0x00000010 */
6457 #define RCC_CSR_LSIPREDIV                    RCC_CSR_LSIPREDIV_Msk
6458 
6459 #define RCC_CSR_MSISRANGE_Pos                (8U)
6460 #define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
6461 #define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk
6462 #define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
6463 #define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
6464 #define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
6465 #define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
6466 
6467 #define RCC_CSR_RMVF_Pos                     (23U)
6468 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
6469 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
6470 #define RCC_CSR_FWRSTF_Pos                   (24U)
6471 #define RCC_CSR_FWRSTF_Msk                   (0x1UL << RCC_CSR_FWRSTF_Pos)     /*!< 0x01000000 */
6472 #define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk
6473 #define RCC_CSR_OBLRSTF_Pos                  (25U)
6474 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
6475 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
6476 #define RCC_CSR_PINRSTF_Pos                  (26U)
6477 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
6478 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
6479 #define RCC_CSR_BORRSTF_Pos                  (27U)
6480 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
6481 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
6482 #define RCC_CSR_SFTRSTF_Pos                  (28U)
6483 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
6484 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
6485 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
6486 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
6487 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
6488 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
6489 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
6490 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
6491 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
6492 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
6493 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
6494 
6495 /********************  Bit definition for RCC_CRRCR register  *****************/
6496 #define RCC_CRRCR_HSI48ON_Pos                (0U)
6497 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
6498 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
6499 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
6500 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
6501 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
6502 
6503 /*!< HSI48CAL configuration */
6504 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
6505 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
6506 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
6507 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
6508 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
6509 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
6510 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
6511 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
6512 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
6513 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
6514 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
6515 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
6516 
6517 /******************************************************************************/
6518 /*                                                                            */
6519 /*                                    RNG                                     */
6520 /*                                                                            */
6521 /******************************************************************************/
6522 /********************  Bits definition for RNG_CR register  *******************/
6523 #define RNG_CR_RNGEN_Pos    (2U)
6524 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
6525 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
6526 #define RNG_CR_IE_Pos       (3U)
6527 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
6528 #define RNG_CR_IE           RNG_CR_IE_Msk
6529 
6530 /********************  Bits definition for RNG_SR register  *******************/
6531 #define RNG_SR_DRDY_Pos     (0U)
6532 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
6533 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
6534 #define RNG_SR_CECS_Pos     (1U)
6535 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
6536 #define RNG_SR_CECS         RNG_SR_CECS_Msk
6537 #define RNG_SR_SECS_Pos     (2U)
6538 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
6539 #define RNG_SR_SECS         RNG_SR_SECS_Msk
6540 #define RNG_SR_CEIS_Pos     (5U)
6541 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
6542 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
6543 #define RNG_SR_SEIS_Pos     (6U)
6544 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
6545 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
6546 
6547 /******************************************************************************/
6548 /*                                                                            */
6549 /*                           Real-Time Clock (RTC)                            */
6550 /*                                                                            */
6551 /******************************************************************************/
6552 /*
6553 * @brief Specific device feature definitions
6554 */
6555 #define RTC_TAMPER1_SUPPORT
6556 #define RTC_TAMPER2_SUPPORT
6557 
6558 #define RTC_WAKEUP_SUPPORT
6559 #define RTC_BACKUP_SUPPORT
6560 /******************** Number of backup registers ******************************/
6561 #define RTC_BKP_NUMBER                32U
6562 
6563 
6564 /********************  Bits definition for RTC_TR register  *******************/
6565 #define RTC_TR_PM_Pos                (22U)
6566 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
6567 #define RTC_TR_PM                    RTC_TR_PM_Msk
6568 #define RTC_TR_HT_Pos                (20U)
6569 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
6570 #define RTC_TR_HT                    RTC_TR_HT_Msk
6571 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
6572 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
6573 #define RTC_TR_HU_Pos                (16U)
6574 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
6575 #define RTC_TR_HU                    RTC_TR_HU_Msk
6576 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
6577 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
6578 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
6579 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
6580 #define RTC_TR_MNT_Pos               (12U)
6581 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
6582 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
6583 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
6584 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
6585 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
6586 #define RTC_TR_MNU_Pos               (8U)
6587 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
6588 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
6589 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
6590 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
6591 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
6592 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
6593 #define RTC_TR_ST_Pos                (4U)
6594 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
6595 #define RTC_TR_ST                    RTC_TR_ST_Msk
6596 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
6597 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
6598 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
6599 #define RTC_TR_SU_Pos                (0U)
6600 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
6601 #define RTC_TR_SU                    RTC_TR_SU_Msk
6602 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
6603 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
6604 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
6605 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
6606 
6607 /********************  Bits definition for RTC_DR register  *******************/
6608 #define RTC_DR_YT_Pos                (20U)
6609 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
6610 #define RTC_DR_YT                    RTC_DR_YT_Msk
6611 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
6612 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
6613 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
6614 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
6615 #define RTC_DR_YU_Pos                (16U)
6616 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
6617 #define RTC_DR_YU                    RTC_DR_YU_Msk
6618 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
6619 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
6620 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
6621 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
6622 #define RTC_DR_WDU_Pos               (13U)
6623 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
6624 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
6625 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
6626 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
6627 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
6628 #define RTC_DR_MT_Pos                (12U)
6629 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
6630 #define RTC_DR_MT                    RTC_DR_MT_Msk
6631 #define RTC_DR_MU_Pos                (8U)
6632 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
6633 #define RTC_DR_MU                    RTC_DR_MU_Msk
6634 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
6635 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
6636 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
6637 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
6638 #define RTC_DR_DT_Pos                (4U)
6639 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
6640 #define RTC_DR_DT                    RTC_DR_DT_Msk
6641 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
6642 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
6643 #define RTC_DR_DU_Pos                (0U)
6644 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
6645 #define RTC_DR_DU                    RTC_DR_DU_Msk
6646 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
6647 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
6648 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
6649 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
6650 
6651 /********************  Bits definition for RTC_SSR register  ******************/
6652 #define RTC_SSR_SS_Pos               (0U)
6653 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
6654 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
6655 
6656 /********************  Bits definition for RTC_ICSR register  ******************/
6657 #define RTC_ICSR_RECALPF_Pos         (16U)
6658 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
6659 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
6660 #define RTC_ICSR_INIT_Pos            (7U)
6661 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
6662 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
6663 #define RTC_ICSR_INITF_Pos           (6U)
6664 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
6665 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
6666 #define RTC_ICSR_RSF_Pos             (5U)
6667 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
6668 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
6669 #define RTC_ICSR_INITS_Pos           (4U)
6670 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
6671 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
6672 #define RTC_ICSR_SHPF_Pos            (3U)
6673 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
6674 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
6675 #define RTC_ICSR_WUTWF_Pos           (2U)
6676 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
6677 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
6678 
6679 /********************  Bits definition for RTC_PRER register  *****************/
6680 #define RTC_PRER_PREDIV_A_Pos        (16U)
6681 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
6682 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
6683 #define RTC_PRER_PREDIV_S_Pos        (0U)
6684 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
6685 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
6686 
6687 /********************  Bits definition for RTC_WUTR register  *****************/
6688 #define RTC_WUTR_WUTOCLR_Pos         (16U)
6689 #define RTC_WUTR_WUTOCLR_Msk         (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)        /*!< 0xFFFF0000 */
6690 #define RTC_WUTR_WUTOCLR             RTC_WUTR_WUTOCLR_Msk
6691 #define RTC_WUTR_WUT_Pos             (0U)
6692 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
6693 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
6694 
6695 /********************  Bits definition for RTC_CR register  *******************/
6696 #define RTC_CR_OUT2EN_Pos            (31U)
6697 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
6698 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
6699 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
6700 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
6701 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
6702 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
6703 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
6704 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
6705 #define RTC_CR_TAMPOE_Pos            (26U)
6706 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
6707 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
6708 #define RTC_CR_TAMPTS_Pos            (25U)
6709 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
6710 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
6711 #define RTC_CR_ITSE_Pos              (24U)
6712 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
6713 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
6714 #define RTC_CR_COE_Pos               (23U)
6715 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
6716 #define RTC_CR_COE                   RTC_CR_COE_Msk
6717 #define RTC_CR_OSEL_Pos              (21U)
6718 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
6719 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
6720 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
6721 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
6722 #define RTC_CR_POL_Pos               (20U)
6723 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
6724 #define RTC_CR_POL                   RTC_CR_POL_Msk
6725 #define RTC_CR_COSEL_Pos             (19U)
6726 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
6727 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
6728 #define RTC_CR_BKP_Pos               (18U)
6729 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
6730 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
6731 #define RTC_CR_SUB1H_Pos             (17U)
6732 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
6733 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
6734 #define RTC_CR_ADD1H_Pos             (16U)
6735 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
6736 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
6737 #define RTC_CR_TSIE_Pos              (15U)
6738 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
6739 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
6740 #define RTC_CR_WUTIE_Pos             (14U)
6741 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
6742 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
6743 #define RTC_CR_ALRBIE_Pos            (13U)
6744 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
6745 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
6746 #define RTC_CR_ALRAIE_Pos            (12U)
6747 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
6748 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
6749 #define RTC_CR_TSE_Pos               (11U)
6750 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
6751 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
6752 #define RTC_CR_WUTE_Pos              (10U)
6753 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
6754 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
6755 #define RTC_CR_ALRBE_Pos             (9U)
6756 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
6757 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
6758 #define RTC_CR_ALRAE_Pos             (8U)
6759 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
6760 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
6761 #define RTC_CR_FMT_Pos               (6U)
6762 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
6763 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
6764 #define RTC_CR_BYPSHAD_Pos           (5U)
6765 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
6766 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
6767 #define RTC_CR_REFCKON_Pos           (4U)
6768 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
6769 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
6770 #define RTC_CR_TSEDGE_Pos            (3U)
6771 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
6772 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
6773 #define RTC_CR_WUCKSEL_Pos           (0U)
6774 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
6775 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
6776 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
6777 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
6778 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
6779 
6780 /********************  Bits definition for RTC_WPR register  ******************/
6781 #define RTC_WPR_KEY_Pos              (0U)
6782 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
6783 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
6784 
6785 /********************  Bits definition for RTC_CALR register  *****************/
6786 #define RTC_CALR_CALP_Pos            (15U)
6787 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
6788 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
6789 #define RTC_CALR_CALW8_Pos           (14U)
6790 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
6791 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
6792 #define RTC_CALR_CALW16_Pos          (13U)
6793 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
6794 #define RTC_CALR_LPCAL               RTC_CALR_LPCAL_Msk
6795 #define RTC_CALR_LPCAL_Pos           (12U)
6796 #define RTC_CALR_LPCAL_Msk           (0x1UL << RTC_CALR_LPCAL_Pos)             /*!< 0x00001000 */
6797 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
6798 #define RTC_CALR_CALM_Pos            (0U)
6799 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
6800 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
6801 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
6802 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
6803 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
6804 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
6805 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
6806 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
6807 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
6808 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
6809 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
6810 
6811 /********************  Bits definition for RTC_SHIFTR register  ***************/
6812 #define RTC_SHIFTR_ADD1S_Pos         (31U)
6813 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
6814 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
6815 #define RTC_SHIFTR_SUBFS_Pos         (0U)
6816 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
6817 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
6818 
6819 /********************  Bits definition for RTC_TSTR register  *****************/
6820 #define RTC_TSTR_PM_Pos              (22U)
6821 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
6822 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
6823 #define RTC_TSTR_HT_Pos              (20U)
6824 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
6825 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
6826 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
6827 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
6828 #define RTC_TSTR_HU_Pos              (16U)
6829 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
6830 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
6831 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
6832 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
6833 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
6834 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
6835 #define RTC_TSTR_MNT_Pos             (12U)
6836 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
6837 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
6838 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
6839 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
6840 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
6841 #define RTC_TSTR_MNU_Pos             (8U)
6842 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
6843 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
6844 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
6845 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
6846 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
6847 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
6848 #define RTC_TSTR_ST_Pos              (4U)
6849 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
6850 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
6851 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
6852 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
6853 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
6854 #define RTC_TSTR_SU_Pos              (0U)
6855 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
6856 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
6857 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
6858 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
6859 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
6860 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
6861 
6862 /********************  Bits definition for RTC_TSDR register  *****************/
6863 #define RTC_TSDR_WDU_Pos             (13U)
6864 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
6865 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
6866 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
6867 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
6868 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
6869 #define RTC_TSDR_MT_Pos              (12U)
6870 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
6871 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
6872 #define RTC_TSDR_MU_Pos              (8U)
6873 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
6874 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
6875 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
6876 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
6877 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
6878 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
6879 #define RTC_TSDR_DT_Pos              (4U)
6880 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
6881 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
6882 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
6883 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
6884 #define RTC_TSDR_DU_Pos              (0U)
6885 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
6886 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
6887 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
6888 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
6889 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
6890 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
6891 
6892 /********************  Bits definition for RTC_TSSSR register  ****************/
6893 #define RTC_TSSSR_SS_Pos             (0U)
6894 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
6895 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
6896 
6897 /********************  Bits definition for RTC_ALRMAR register  ***************/
6898 #define RTC_ALRMAR_MSK4_Pos          (31U)
6899 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
6900 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
6901 #define RTC_ALRMAR_WDSEL_Pos         (30U)
6902 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
6903 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
6904 #define RTC_ALRMAR_DT_Pos            (28U)
6905 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
6906 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
6907 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
6908 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
6909 #define RTC_ALRMAR_DU_Pos            (24U)
6910 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
6911 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
6912 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
6913 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
6914 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
6915 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
6916 #define RTC_ALRMAR_MSK3_Pos          (23U)
6917 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
6918 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
6919 #define RTC_ALRMAR_PM_Pos            (22U)
6920 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
6921 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
6922 #define RTC_ALRMAR_HT_Pos            (20U)
6923 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
6924 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
6925 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
6926 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
6927 #define RTC_ALRMAR_HU_Pos            (16U)
6928 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
6929 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
6930 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
6931 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
6932 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
6933 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
6934 #define RTC_ALRMAR_MSK2_Pos          (15U)
6935 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
6936 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
6937 #define RTC_ALRMAR_MNT_Pos           (12U)
6938 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
6939 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
6940 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
6941 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
6942 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
6943 #define RTC_ALRMAR_MNU_Pos           (8U)
6944 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
6945 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
6946 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
6947 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
6948 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
6949 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
6950 #define RTC_ALRMAR_MSK1_Pos          (7U)
6951 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
6952 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
6953 #define RTC_ALRMAR_ST_Pos            (4U)
6954 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
6955 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
6956 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
6957 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
6958 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
6959 #define RTC_ALRMAR_SU_Pos            (0U)
6960 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
6961 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
6962 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
6963 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
6964 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
6965 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
6966 
6967 /********************  Bits definition for RTC_ALRMASSR register  *************/
6968 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
6969 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
6970 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
6971 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
6972 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
6973 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
6974 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
6975 #define RTC_ALRMASSR_SS_Pos          (0U)
6976 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
6977 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
6978 
6979 /********************  Bits definition for RTC_ALRMBR register  ***************/
6980 #define RTC_ALRMBR_MSK4_Pos          (31U)
6981 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
6982 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
6983 #define RTC_ALRMBR_WDSEL_Pos         (30U)
6984 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
6985 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
6986 #define RTC_ALRMBR_DT_Pos            (28U)
6987 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
6988 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
6989 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
6990 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
6991 #define RTC_ALRMBR_DU_Pos            (24U)
6992 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
6993 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
6994 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
6995 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
6996 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
6997 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
6998 #define RTC_ALRMBR_MSK3_Pos          (23U)
6999 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
7000 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
7001 #define RTC_ALRMBR_PM_Pos            (22U)
7002 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
7003 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
7004 #define RTC_ALRMBR_HT_Pos            (20U)
7005 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
7006 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
7007 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
7008 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
7009 #define RTC_ALRMBR_HU_Pos            (16U)
7010 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
7011 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
7012 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
7013 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
7014 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
7015 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
7016 #define RTC_ALRMBR_MSK2_Pos          (15U)
7017 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
7018 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
7019 #define RTC_ALRMBR_MNT_Pos           (12U)
7020 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
7021 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
7022 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
7023 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
7024 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
7025 #define RTC_ALRMBR_MNU_Pos           (8U)
7026 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
7027 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
7028 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
7029 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
7030 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
7031 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
7032 #define RTC_ALRMBR_MSK1_Pos          (7U)
7033 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
7034 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
7035 #define RTC_ALRMBR_ST_Pos            (4U)
7036 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
7037 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
7038 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
7039 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
7040 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
7041 #define RTC_ALRMBR_SU_Pos            (0U)
7042 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
7043 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
7044 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
7045 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
7046 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
7047 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
7048 
7049 /********************  Bits definition for RTC_ALRMBSSR register  *************/
7050 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
7051 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x0F000000 */
7052 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
7053 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
7054 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
7055 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
7056 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
7057 #define RTC_ALRMBSSR_SS_Pos          (0U)
7058 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
7059 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
7060 
7061 /********************  Bits definition for RTC_SR register  *******************/
7062 #define RTC_SR_ITSF_Pos              (5U)
7063 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
7064 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
7065 #define RTC_SR_TSOVF_Pos             (4U)
7066 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
7067 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
7068 #define RTC_SR_TSF_Pos               (3U)
7069 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
7070 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
7071 #define RTC_SR_WUTF_Pos              (2U)
7072 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
7073 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
7074 #define RTC_SR_ALRBF_Pos             (1U)
7075 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
7076 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
7077 #define RTC_SR_ALRAF_Pos             (0U)
7078 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
7079 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
7080 
7081 /********************  Bits definition for RTC_MISR register  *****************/
7082 #define RTC_MISR_ITSMF_Pos           (5U)
7083 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
7084 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
7085 #define RTC_MISR_TSOVMF_Pos          (4U)
7086 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
7087 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
7088 #define RTC_MISR_TSMF_Pos            (3U)
7089 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
7090 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
7091 #define RTC_MISR_WUTMF_Pos           (2U)
7092 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
7093 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
7094 #define RTC_MISR_ALRBMF_Pos          (1U)
7095 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
7096 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
7097 #define RTC_MISR_ALRAMF_Pos          (0U)
7098 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
7099 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
7100 
7101 /********************  Bits definition for RTC_SCR register  ******************/
7102 #define RTC_SCR_CITSF_Pos            (5U)
7103 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
7104 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
7105 #define RTC_SCR_CTSOVF_Pos           (4U)
7106 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
7107 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
7108 #define RTC_SCR_CTSF_Pos             (3U)
7109 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
7110 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
7111 #define RTC_SCR_CWUTF_Pos            (2U)
7112 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
7113 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
7114 #define RTC_SCR_CALRBF_Pos           (1U)
7115 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
7116 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
7117 #define RTC_SCR_CALRAF_Pos           (0U)
7118 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
7119 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
7120 
7121 /******************************************************************************/
7122 /*                                                                            */
7123 /*                     Tamper and backup register (TAMP)                      */
7124 /*                                                                            */
7125 /******************************************************************************/
7126 /********************  Bits definition for TAMP_CR1 register  *****************/
7127 #define TAMP_CR1_TAMP1E_Pos          (0U)
7128 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)             /*!< 0x00000001 */
7129 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
7130 #define TAMP_CR1_TAMP2E_Pos          (1U)
7131 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)             /*!< 0x00000002 */
7132 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
7133 
7134 /********************  Bits definition for TAMP_CR2 register  *****************/
7135 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
7136 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)       /*!< 0x00000001 */
7137 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
7138 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
7139 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)       /*!< 0x00000002 */
7140 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
7141 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
7142 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
7143 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
7144 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
7145 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
7146 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
7147 #define TAMP_CR2_BKERASE_Pos         (23U)
7148 #define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)            /*!< 0x00800000 */
7149 #define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
7150 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
7151 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)           /*!< 0x01000000 */
7152 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
7153 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
7154 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)           /*!< 0x02000000 */
7155 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
7156 
7157 /********************  Bits definition for TAMP_FLTCR register  ***************/
7158 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
7159 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
7160 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
7161 #define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */
7162 #define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */
7163 #define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */
7164 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
7165 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
7166 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
7167 #define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */
7168 #define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */
7169 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
7170 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
7171 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
7172 #define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */
7173 #define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */
7174 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
7175 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
7176 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
7177 
7178 /********************  Bits definition for TAMP_IER register  *****************/
7179 #define TAMP_IER_TAMP1IE_Pos         (0U)
7180 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)            /*!< 0x00000001 */
7181 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
7182 #define TAMP_IER_TAMP2IE_Pos         (1U)
7183 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)            /*!< 0x00000002 */
7184 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
7185 
7186 /********************  Bits definition for TAMP_SR register  *****************/
7187 #define TAMP_SR_TAMP1F_Pos           (0U)
7188 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)              /*!< 0x00000001 */
7189 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
7190 #define TAMP_SR_TAMP2F_Pos           (1U)
7191 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)              /*!< 0x00000002 */
7192 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
7193 
7194 /********************  Bits definition for TAMP_MISR register  ************ *****/
7195 #define TAMP_MISR_TAMP1MF_Pos        (0U)
7196 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
7197 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
7198 #define TAMP_MISR_TAMP2MF_Pos        (1U)
7199 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
7200 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
7201 
7202 
7203 /********************  Bits definition for TAMP_SCR register  *****************/
7204 #define TAMP_SCR_CTAMP1F_Pos         (0U)
7205 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
7206 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
7207 #define TAMP_SCR_CTAMP2F_Pos         (1U)
7208 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
7209 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
7210 
7211 
7212 /********************  Bits definition for TAMP_COUNTR register  ***************/
7213 #define TAMP_COUNTR_Pos               (16U)
7214 #define TAMP_COUNTR_Msk               (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */
7215 #define TAMP_COUNTR                   TAMP_COUNTR_Msk
7216 
7217 /********************  Bits definition for TAMP_BKP0R register  ***************/
7218 #define TAMP_BKP0R_Pos               (0U)
7219 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
7220 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
7221 
7222 /********************  Bits definition for TAMP_BKP1R register  ****************/
7223 #define TAMP_BKP1R_Pos               (0U)
7224 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
7225 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
7226 
7227 /********************  Bits definition for TAMP_BKP2R register  ****************/
7228 #define TAMP_BKP2R_Pos               (0U)
7229 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
7230 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
7231 
7232 /********************  Bits definition for TAMP_BKP3R register  ****************/
7233 #define TAMP_BKP3R_Pos               (0U)
7234 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
7235 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
7236 
7237 /********************  Bits definition for TAMP_BKP4R register  ****************/
7238 #define TAMP_BKP4R_Pos               (0U)
7239 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
7240 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
7241 
7242 /********************  Bits definition for TAMP_BKP5R register  ****************/
7243 #define TAMP_BKP5R_Pos               (0U)
7244 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)           /*!< 0xFFFFFFFF */
7245 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
7246 
7247 /********************  Bits definition for TAMP_BKP6R register  ****************/
7248 #define TAMP_BKP6R_Pos               (0U)
7249 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)           /*!< 0xFFFFFFFF */
7250 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
7251 
7252 /********************  Bits definition for TAMP_BKP7R register  ****************/
7253 #define TAMP_BKP7R_Pos               (0U)
7254 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)           /*!< 0xFFFFFFFF */
7255 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
7256 
7257 /********************  Bits definition for TAMP_BKP8R register  ****************/
7258 #define TAMP_BKP8R_Pos               (0U)
7259 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)           /*!< 0xFFFFFFFF */
7260 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
7261 
7262 /********************  Bits definition for TAMP_BKP9R register  ****************/
7263 #define TAMP_BKP9R_Pos               (0U)
7264 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)           /*!< 0xFFFFFFFF */
7265 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
7266 
7267 /********************  Bits definition for TAMP_BKP10R register  ***************/
7268 #define TAMP_BKP10R_Pos              (0U)
7269 #define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
7270 #define TAMP_BKP10R                  TAMP_BKP10R_Msk
7271 
7272 /********************  Bits definition for TAMP_BKP11R register  ***************/
7273 #define TAMP_BKP11R_Pos              (0U)
7274 #define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
7275 #define TAMP_BKP11R                  TAMP_BKP11R_Msk
7276 
7277 /********************  Bits definition for TAMP_BKP12R register  ***************/
7278 #define TAMP_BKP12R_Pos              (0U)
7279 #define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
7280 #define TAMP_BKP12R                  TAMP_BKP12R_Msk
7281 
7282 /********************  Bits definition for TAMP_BKP13R register  ***************/
7283 #define TAMP_BKP13R_Pos              (0U)
7284 #define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
7285 #define TAMP_BKP13R                  TAMP_BKP13R_Msk
7286 
7287 /********************  Bits definition for TAMP_BKP14R register  ***************/
7288 #define TAMP_BKP14R_Pos              (0U)
7289 #define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
7290 #define TAMP_BKP14R                  TAMP_BKP14R_Msk
7291 
7292 /********************  Bits definition for TAMP_BKP15R register  ***************/
7293 #define TAMP_BKP15R_Pos              (0U)
7294 #define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
7295 #define TAMP_BKP15R                  TAMP_BKP15R_Msk
7296 
7297 /********************  Bits definition for TAMP_BKP16R register  ***************/
7298 #define TAMP_BKP16R_Pos              (0U)
7299 #define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
7300 #define TAMP_BKP16R                  TAMP_BKP16R_Msk
7301 
7302 /********************  Bits definition for TAMP_BKP17R register  ***************/
7303 #define TAMP_BKP17R_Pos              (0U)
7304 #define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
7305 #define TAMP_BKP17R                  TAMP_BKP17R_Msk
7306 
7307 /********************  Bits definition for TAMP_BKP18R register  ***************/
7308 #define TAMP_BKP18R_Pos              (0U)
7309 #define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
7310 #define TAMP_BKP18R                  TAMP_BKP18R_Msk
7311 
7312 /********************  Bits definition for TAMP_BKP19R register  ***************/
7313 #define TAMP_BKP19R_Pos              (0U)
7314 #define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
7315 #define TAMP_BKP19R                  TAMP_BKP19R_Msk
7316 
7317 /********************  Bits definition for TAMP_BKP20R register  ***************/
7318 #define TAMP_BKP20R_Pos              (0U)
7319 #define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
7320 #define TAMP_BKP20R                  TAMP_BKP20R_Msk
7321 
7322 /********************  Bits definition for TAMP_BKP21R register  ***************/
7323 #define TAMP_BKP21R_Pos              (0U)
7324 #define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
7325 #define TAMP_BKP21R                  TAMP_BKP21R_Msk
7326 
7327 /********************  Bits definition for TAMP_BKP22R register  ***************/
7328 #define TAMP_BKP22R_Pos              (0U)
7329 #define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
7330 #define TAMP_BKP22R                  TAMP_BKP22R_Msk
7331 
7332 /********************  Bits definition for TAMP_BKP23R register  ***************/
7333 #define TAMP_BKP23R_Pos              (0U)
7334 #define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
7335 #define TAMP_BKP23R                  TAMP_BKP23R_Msk
7336 
7337 /********************  Bits definition for TAMP_BKP24R register  ***************/
7338 #define TAMP_BKP24R_Pos              (0U)
7339 #define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
7340 #define TAMP_BKP24R                  TAMP_BKP24R_Msk
7341 
7342 /********************  Bits definition for TAMP_BKP25R register  ***************/
7343 #define TAMP_BKP25R_Pos              (0U)
7344 #define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
7345 #define TAMP_BKP25R                  TAMP_BKP25R_Msk
7346 
7347 /********************  Bits definition for TAMP_BKP26R register  ***************/
7348 #define TAMP_BKP26R_Pos              (0U)
7349 #define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
7350 #define TAMP_BKP26R                  TAMP_BKP26R_Msk
7351 
7352 /********************  Bits definition for TAMP_BKP27R register  ***************/
7353 #define TAMP_BKP27R_Pos              (0U)
7354 #define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
7355 #define TAMP_BKP27R                  TAMP_BKP27R_Msk
7356 
7357 /********************  Bits definition for TAMP_BKP28R register  ***************/
7358 #define TAMP_BKP28R_Pos              (0U)
7359 #define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
7360 #define TAMP_BKP28R                  TAMP_BKP28R_Msk
7361 
7362 /********************  Bits definition for TAMP_BKP29R register  ***************/
7363 #define TAMP_BKP29R_Pos              (0U)
7364 #define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
7365 #define TAMP_BKP29R                  TAMP_BKP29R_Msk
7366 
7367 /********************  Bits definition for TAMP_BKP30R register  ***************/
7368 #define TAMP_BKP30R_Pos              (0U)
7369 #define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
7370 #define TAMP_BKP30R                  TAMP_BKP30R_Msk
7371 
7372 /********************  Bits definition for TAMP_BKP31R register  ***************/
7373 #define TAMP_BKP31R_Pos              (0U)
7374 #define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
7375 #define TAMP_BKP31R                  TAMP_BKP31R_Msk
7376 
7377 
7378 /******************************************************************************/
7379 /*                                                                            */
7380 /*                        Serial Peripheral Interface (SPI)                   */
7381 /*                                                                            */
7382 /******************************************************************************/
7383 /*******************  Bit definition for SPI_CR1 register  ********************/
7384 #define SPI_CR1_CPHA_Pos         (0U)
7385 #define SPI_CR1_CPHA_Msk         (0x1UL << SPI_CR1_CPHA_Pos)                   /*!< 0x00000001 */
7386 #define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
7387 #define SPI_CR1_CPOL_Pos         (1U)
7388 #define SPI_CR1_CPOL_Msk         (0x1UL << SPI_CR1_CPOL_Pos)                   /*!< 0x00000002 */
7389 #define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
7390 #define SPI_CR1_MSTR_Pos         (2U)
7391 #define SPI_CR1_MSTR_Msk         (0x1UL << SPI_CR1_MSTR_Pos)                   /*!< 0x00000004 */
7392 #define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
7393 
7394 #define SPI_CR1_BR_Pos           (3U)
7395 #define SPI_CR1_BR_Msk           (0x7UL << SPI_CR1_BR_Pos)                     /*!< 0x00000038 */
7396 #define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
7397 #define SPI_CR1_BR_0             (0x1UL << SPI_CR1_BR_Pos)                     /*!< 0x00000008 */
7398 #define SPI_CR1_BR_1             (0x2UL << SPI_CR1_BR_Pos)                     /*!< 0x00000010 */
7399 #define SPI_CR1_BR_2             (0x4UL << SPI_CR1_BR_Pos)                     /*!< 0x00000020 */
7400 
7401 #define SPI_CR1_SPE_Pos          (6U)
7402 #define SPI_CR1_SPE_Msk          (0x1UL << SPI_CR1_SPE_Pos)                    /*!< 0x00000040 */
7403 #define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
7404 #define SPI_CR1_LSBFIRST_Pos     (7U)
7405 #define SPI_CR1_LSBFIRST_Msk     (0x1UL << SPI_CR1_LSBFIRST_Pos)               /*!< 0x00000080 */
7406 #define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
7407 #define SPI_CR1_SSI_Pos          (8U)
7408 #define SPI_CR1_SSI_Msk          (0x1UL << SPI_CR1_SSI_Pos)                    /*!< 0x00000100 */
7409 #define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
7410 #define SPI_CR1_SSM_Pos          (9U)
7411 #define SPI_CR1_SSM_Msk          (0x1UL << SPI_CR1_SSM_Pos)                    /*!< 0x00000200 */
7412 #define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
7413 #define SPI_CR1_RXONLY_Pos       (10U)
7414 #define SPI_CR1_RXONLY_Msk       (0x1UL << SPI_CR1_RXONLY_Pos)                 /*!< 0x00000400 */
7415 #define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
7416 #define SPI_CR1_CRCL_Pos         (11U)
7417 #define SPI_CR1_CRCL_Msk         (0x1UL << SPI_CR1_CRCL_Pos)                   /*!< 0x00000800 */
7418 #define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
7419 #define SPI_CR1_CRCNEXT_Pos      (12U)
7420 #define SPI_CR1_CRCNEXT_Msk      (0x1UL << SPI_CR1_CRCNEXT_Pos)                /*!< 0x00001000 */
7421 #define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
7422 #define SPI_CR1_CRCEN_Pos        (13U)
7423 #define SPI_CR1_CRCEN_Msk        (0x1UL << SPI_CR1_CRCEN_Pos)                  /*!< 0x00002000 */
7424 #define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
7425 #define SPI_CR1_BIDIOE_Pos       (14U)
7426 #define SPI_CR1_BIDIOE_Msk       (0x1UL << SPI_CR1_BIDIOE_Pos)                 /*!< 0x00004000 */
7427 #define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
7428 #define SPI_CR1_BIDIMODE_Pos     (15U)
7429 #define SPI_CR1_BIDIMODE_Msk     (0x1UL << SPI_CR1_BIDIMODE_Pos)               /*!< 0x00008000 */
7430 #define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
7431 
7432 /*******************  Bit definition for SPI_CR2 register  ********************/
7433 #define SPI_CR2_RXDMAEN_Pos      (0U)
7434 #define SPI_CR2_RXDMAEN_Msk      (0x1UL << SPI_CR2_RXDMAEN_Pos)                /*!< 0x00000001 */
7435 #define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
7436 #define SPI_CR2_TXDMAEN_Pos      (1U)
7437 #define SPI_CR2_TXDMAEN_Msk      (0x1UL << SPI_CR2_TXDMAEN_Pos)                /*!< 0x00000002 */
7438 #define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
7439 #define SPI_CR2_SSOE_Pos         (2U)
7440 #define SPI_CR2_SSOE_Msk         (0x1UL << SPI_CR2_SSOE_Pos)                   /*!< 0x00000004 */
7441 #define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
7442 #define SPI_CR2_NSSP_Pos         (3U)
7443 #define SPI_CR2_NSSP_Msk         (0x1UL << SPI_CR2_NSSP_Pos)                   /*!< 0x00000008 */
7444 #define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
7445 #define SPI_CR2_FRF_Pos          (4U)
7446 #define SPI_CR2_FRF_Msk          (0x1UL << SPI_CR2_FRF_Pos)                    /*!< 0x00000010 */
7447 #define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
7448 #define SPI_CR2_ERRIE_Pos        (5U)
7449 #define SPI_CR2_ERRIE_Msk        (0x1UL << SPI_CR2_ERRIE_Pos)                  /*!< 0x00000020 */
7450 #define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
7451 #define SPI_CR2_RXNEIE_Pos       (6U)
7452 #define SPI_CR2_RXNEIE_Msk       (0x1UL << SPI_CR2_RXNEIE_Pos)                 /*!< 0x00000040 */
7453 #define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
7454 #define SPI_CR2_TXEIE_Pos        (7U)
7455 #define SPI_CR2_TXEIE_Msk        (0x1UL << SPI_CR2_TXEIE_Pos)                  /*!< 0x00000080 */
7456 #define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
7457 #define SPI_CR2_DS_Pos           (8U)
7458 #define SPI_CR2_DS_Msk           (0xFUL << SPI_CR2_DS_Pos)                     /*!< 0x00000F00 */
7459 #define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
7460 #define SPI_CR2_DS_0             (0x1UL << SPI_CR2_DS_Pos)                     /*!< 0x00000100 */
7461 #define SPI_CR2_DS_1             (0x2UL << SPI_CR2_DS_Pos)                     /*!< 0x00000200 */
7462 #define SPI_CR2_DS_2             (0x4UL << SPI_CR2_DS_Pos)                     /*!< 0x00000400 */
7463 #define SPI_CR2_DS_3             (0x8UL << SPI_CR2_DS_Pos)                     /*!< 0x00000800 */
7464 #define SPI_CR2_FRXTH_Pos        (12U)
7465 #define SPI_CR2_FRXTH_Msk        (0x1UL << SPI_CR2_FRXTH_Pos)                  /*!< 0x00001000 */
7466 #define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
7467 #define SPI_CR2_LDMARX_Pos       (13U)
7468 #define SPI_CR2_LDMARX_Msk       (0x1UL << SPI_CR2_LDMARX_Pos)                 /*!< 0x00002000 */
7469 #define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
7470 #define SPI_CR2_LDMATX_Pos       (14U)
7471 #define SPI_CR2_LDMATX_Msk       (0x1UL << SPI_CR2_LDMATX_Pos)                 /*!< 0x00004000 */
7472 #define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
7473 
7474 /********************  Bit definition for SPI_SR register  ********************/
7475 #define SPI_SR_RXNE_Pos          (0U)
7476 #define SPI_SR_RXNE_Msk          (0x1UL << SPI_SR_RXNE_Pos)                    /*!< 0x00000001 */
7477 #define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
7478 #define SPI_SR_TXE_Pos           (1U)
7479 #define SPI_SR_TXE_Msk           (0x1UL << SPI_SR_TXE_Pos)                     /*!< 0x00000002 */
7480 #define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
7481 #define SPI_SR_CHSIDE_Pos        (2U)
7482 #define SPI_SR_CHSIDE_Msk        (0x1UL << SPI_SR_CHSIDE_Pos)                  /*!< 0x00000004 */
7483 #define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
7484 #define SPI_SR_UDR_Pos           (3U)
7485 #define SPI_SR_UDR_Msk           (0x1UL << SPI_SR_UDR_Pos)                     /*!< 0x00000008 */
7486 #define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
7487 #define SPI_SR_CRCERR_Pos        (4U)
7488 #define SPI_SR_CRCERR_Msk        (0x1UL << SPI_SR_CRCERR_Pos)                  /*!< 0x00000010 */
7489 #define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
7490 #define SPI_SR_MODF_Pos          (5U)
7491 #define SPI_SR_MODF_Msk          (0x1UL << SPI_SR_MODF_Pos)                    /*!< 0x00000020 */
7492 #define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
7493 #define SPI_SR_OVR_Pos           (6U)
7494 #define SPI_SR_OVR_Msk           (0x1UL << SPI_SR_OVR_Pos)                     /*!< 0x00000040 */
7495 #define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
7496 #define SPI_SR_BSY_Pos           (7U)
7497 #define SPI_SR_BSY_Msk           (0x1UL << SPI_SR_BSY_Pos)                     /*!< 0x00000080 */
7498 #define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
7499 #define SPI_SR_FRE_Pos           (8U)
7500 #define SPI_SR_FRE_Msk           (0x1UL << SPI_SR_FRE_Pos)                     /*!< 0x00000100 */
7501 #define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
7502 #define SPI_SR_FRLVL_Pos         (9U)
7503 #define SPI_SR_FRLVL_Msk         (0x3UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000600 */
7504 #define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
7505 #define SPI_SR_FRLVL_0           (0x1UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000200 */
7506 #define SPI_SR_FRLVL_1           (0x2UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000400 */
7507 #define SPI_SR_FTLVL_Pos         (11U)
7508 #define SPI_SR_FTLVL_Msk         (0x3UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001800 */
7509 #define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
7510 #define SPI_SR_FTLVL_0           (0x1UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00000800 */
7511 #define SPI_SR_FTLVL_1           (0x2UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001000 */
7512 
7513 /********************  Bit definition for SPI_DR register  ********************/
7514 #define SPI_DR_DR_Pos            (0U)
7515 #define SPI_DR_DR_Msk            (0xFFFFUL << SPI_DR_DR_Pos)                   /*!< 0x0000FFFF */
7516 #define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
7517 
7518 /*******************  Bit definition for SPI_CRCPR register  ******************/
7519 #define SPI_CRCPR_CRCPOLY_Pos    (0U)
7520 #define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)           /*!< 0x0000FFFF */
7521 #define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
7522 
7523 /******************  Bit definition for SPI_RXCRCR register  ******************/
7524 #define SPI_RXCRCR_RXCRC_Pos     (0U)
7525 #define SPI_RXCRCR_RXCRC_Msk     (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)            /*!< 0x0000FFFF */
7526 #define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
7527 
7528 /******************  Bit definition for SPI_TXCRCR register  ******************/
7529 #define SPI_TXCRCR_TXCRC_Pos     (0U)
7530 #define SPI_TXCRCR_TXCRC_Msk     (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)            /*!< 0x0000FFFF */
7531 #define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
7532 
7533 /******************************************************************************/
7534 /*                                                                            */
7535 /*                                    QUADSPI                                 */
7536 /*                                                                            */
7537 /******************************************************************************/
7538 /*****************  Bit definition for QUADSPI_CR register  *******************/
7539 #define QUADSPI_CR_EN_Pos              (0U)
7540 #define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */
7541 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
7542 #define QUADSPI_CR_ABORT_Pos           (1U)
7543 #define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
7544 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
7545 #define QUADSPI_CR_DMAEN_Pos           (2U)
7546 #define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
7547 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
7548 #define QUADSPI_CR_TCEN_Pos            (3U)
7549 #define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
7550 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
7551 #define QUADSPI_CR_SSHIFT_Pos          (4U)
7552 #define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */
7553 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
7554 #define QUADSPI_CR_DFM_Pos             (6U)
7555 #define QUADSPI_CR_DFM_Msk             (0x1UL << QUADSPI_CR_DFM_Pos)           /*!< 0x00000040 */
7556 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
7557 #define QUADSPI_CR_FSEL_Pos            (7U)
7558 #define QUADSPI_CR_FSEL_Msk            (0x1UL << QUADSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
7559 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
7560 #define QUADSPI_CR_FTHRES_Pos          (8U)
7561 #define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */
7562 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
7563 #define QUADSPI_CR_TEIE_Pos            (16U)
7564 #define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
7565 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
7566 #define QUADSPI_CR_TCIE_Pos            (17U)
7567 #define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
7568 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
7569 #define QUADSPI_CR_FTIE_Pos            (18U)
7570 #define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
7571 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
7572 #define QUADSPI_CR_SMIE_Pos            (19U)
7573 #define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
7574 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
7575 #define QUADSPI_CR_TOIE_Pos            (20U)
7576 #define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
7577 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
7578 #define QUADSPI_CR_APMS_Pos            (22U)
7579 #define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */
7580 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
7581 #define QUADSPI_CR_PMM_Pos             (23U)
7582 #define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */
7583 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
7584 #define QUADSPI_CR_PRESCALER_Pos       (24U)
7585 #define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */
7586 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
7587 
7588 /*****************  Bit definition for QUADSPI_DCR register  ******************/
7589 #define QUADSPI_DCR_CKMODE_Pos         (0U)
7590 #define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */
7591 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
7592 #define QUADSPI_DCR_CSHT_Pos           (8U)
7593 #define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */
7594 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
7595 #define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */
7596 #define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */
7597 #define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */
7598 #define QUADSPI_DCR_FSIZE_Pos          (16U)
7599 #define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */
7600 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
7601 
7602 /******************  Bit definition for QUADSPI_SR register  *******************/
7603 #define QUADSPI_SR_TEF_Pos             (0U)
7604 #define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */
7605 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
7606 #define QUADSPI_SR_TCF_Pos             (1U)
7607 #define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */
7608 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
7609 #define QUADSPI_SR_FTF_Pos             (2U)
7610 #define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */
7611 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
7612 #define QUADSPI_SR_SMF_Pos             (3U)
7613 #define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */
7614 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
7615 #define QUADSPI_SR_TOF_Pos             (4U)
7616 #define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */
7617 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
7618 #define QUADSPI_SR_BUSY_Pos            (5U)
7619 #define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
7620 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
7621 #define QUADSPI_SR_FLEVEL_Pos          (8U)
7622 #define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */
7623 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
7624 
7625 /******************  Bit definition for QUADSPI_FCR register  ******************/
7626 #define QUADSPI_FCR_CTEF_Pos           (0U)
7627 #define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
7628 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
7629 #define QUADSPI_FCR_CTCF_Pos           (1U)
7630 #define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
7631 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
7632 #define QUADSPI_FCR_CSMF_Pos           (3U)
7633 #define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
7634 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
7635 #define QUADSPI_FCR_CTOF_Pos           (4U)
7636 #define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
7637 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
7638 
7639 /******************  Bit definition for QUADSPI_DLR register  ******************/
7640 #define QUADSPI_DLR_DL_Pos             (0U)
7641 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
7642 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
7643 
7644 /******************  Bit definition for QUADSPI_CCR register  ******************/
7645 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
7646 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
7647 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
7648 #define QUADSPI_CCR_IMODE_Pos          (8U)
7649 #define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
7650 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
7651 #define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
7652 #define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
7653 #define QUADSPI_CCR_ADMODE_Pos         (10U)
7654 #define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
7655 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
7656 #define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
7657 #define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
7658 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
7659 #define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
7660 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
7661 #define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
7662 #define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
7663 #define QUADSPI_CCR_ABMODE_Pos         (14U)
7664 #define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
7665 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
7666 #define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
7667 #define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
7668 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
7669 #define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
7670 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
7671 #define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
7672 #define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
7673 #define QUADSPI_CCR_DCYC_Pos           (18U)
7674 #define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
7675 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
7676 #define QUADSPI_CCR_DMODE_Pos          (24U)
7677 #define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
7678 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
7679 #define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
7680 #define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
7681 #define QUADSPI_CCR_FMODE_Pos          (26U)
7682 #define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
7683 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
7684 #define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
7685 #define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
7686 #define QUADSPI_CCR_SIOO_Pos           (28U)
7687 #define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
7688 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
7689 #define QUADSPI_CCR_DHHC_Pos           (30U)
7690 #define QUADSPI_CCR_DHHC_Msk           (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
7691 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
7692 #define QUADSPI_CCR_DDRM_Pos           (31U)
7693 #define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
7694 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
7695 
7696 /******************  Bit definition for QUADSPI_AR register  *******************/
7697 #define QUADSPI_AR_ADDRESS_Pos         (0U)
7698 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
7699 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
7700 
7701 /******************  Bit definition for QUADSPI_ABR register  ******************/
7702 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
7703 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
7704 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
7705 
7706 /******************  Bit definition for QUADSPI_DR register  *******************/
7707 #define QUADSPI_DR_DATA_Pos            (0U)
7708 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
7709 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
7710 
7711 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
7712 #define QUADSPI_PSMKR_MASK_Pos         (0U)
7713 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
7714 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
7715 
7716 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
7717 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
7718 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
7719 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
7720 
7721 /******************  Bit definition for QUADSPI_PIR register  *****************/
7722 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
7723 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
7724 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
7725 
7726 /******************  Bit definition for QUADSPI_LPTR register  *****************/
7727 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
7728 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
7729 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
7730 
7731 /******************************************************************************/
7732 /*                                                                            */
7733 /*                                 SYSCFG                                     */
7734 /*                                                                            */
7735 /******************************************************************************/
7736 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
7737 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
7738 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
7739 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
7740 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
7741 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
7742 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
7743 
7744 /******************  Bit definition for SYSCFG_CFGR1 register  ******************/
7745 #define SYSCFG_CFGR1_FWDIS_Pos          (0U)
7746 #define SYSCFG_CFGR1_FWDIS_Msk          (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)      /*!< 0x00000001 */
7747 #define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
7748 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
7749 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
7750 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
7751 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
7752 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
7753 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
7754 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
7755 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
7756 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
7757 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
7758 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
7759 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
7760 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
7761 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
7762 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
7763 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
7764 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
7765 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
7766 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
7767 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
7768 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
7769 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
7770 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
7771 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
7772 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000UL)                         /*!<  Invalid operation Interrupt enable */
7773 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000UL)                         /*!<  Divide-by-zero Interrupt enable */
7774 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000UL)                         /*!<  Underflow Interrupt enable */
7775 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000UL)                         /*!<  Overflow Interrupt enable */
7776 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000UL)                         /*!<  Input denormal Interrupt enable */
7777 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000UL)                         /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
7778 
7779 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
7780 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
7781 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x00000007 */
7782 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
7783 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
7784 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x00000070 */
7785 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
7786 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
7787 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000700 */
7788 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
7789 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
7790 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x00007000 */
7791 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
7792 
7793 /**
7794   * @brief   EXTI0 configuration
7795   */
7796 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000UL)                     /*!<PA[0] pin */
7797 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001UL)                     /*!<PB[0] pin */
7798 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002UL)                     /*!<PC[0] pin */
7799 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003UL)                     /*!<PD[0] pin */
7800 #define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007UL)                     /*!<PH[0] pin */
7801 
7802 /**
7803   * @brief   EXTI1 configuration
7804   */
7805 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000UL)                     /*!<PA[1] pin */
7806 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010UL)                     /*!<PB[1] pin */
7807 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020UL)                     /*!<PC[1] pin */
7808 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030UL)                     /*!<PD[1] pin */
7809 #define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070UL)                     /*!<PH[1] pin */
7810 
7811 /**
7812   * @brief   EXTI2 configuration
7813   */
7814 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000UL)                     /*!<PA[2] pin */
7815 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100UL)                     /*!<PB[2] pin */
7816 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200UL)                     /*!<PC[2] pin */
7817 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300UL)                     /*!<PD[2] pin */
7818 
7819 /**
7820   * @brief   EXTI3 configuration
7821   */
7822 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000UL)                     /*!<PA[3] pin */
7823 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000UL)                     /*!<PB[3] pin */
7824 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000UL)                     /*!<PC[3] pin */
7825 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000UL)                     /*!<PD[3] pin */
7826 #define SYSCFG_EXTICR1_EXTI3_PH             (0x00007000UL)                     /*!<PH[3] pin */
7827 
7828 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
7829 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
7830 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x00000007 */
7831 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
7832 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
7833 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x00000070 */
7834 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
7835 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
7836 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000700 */
7837 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
7838 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
7839 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x00007000 */
7840 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
7841 /**
7842   * @brief   EXTI4 configuration
7843   */
7844 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000UL)                     /*!<PA[4] pin */
7845 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001UL)                     /*!<PB[4] pin */
7846 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002UL)                     /*!<PC[4] pin */
7847 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003UL)                     /*!<PD[4] pin */
7848 
7849 /**
7850   * @brief   EXTI5 configuration
7851   */
7852 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000UL)                     /*!<PA[5] pin */
7853 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010UL)                     /*!<PB[5] pin */
7854 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020UL)                     /*!<PC[5] pin */
7855 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030UL)                     /*!<PD[5] pin */
7856 
7857 /**
7858   * @brief   EXTI6 configuration
7859   */
7860 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000UL)                     /*!<PA[6] pin */
7861 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100UL)                     /*!<PB[6] pin */
7862 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200UL)                     /*!<PC[6] pin */
7863 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300UL)                     /*!<PD[6] pin */
7864 
7865 /**
7866   * @brief   EXTI7 configuration
7867   */
7868 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000UL)                     /*!<PA[7] pin */
7869 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000UL)                     /*!<PB[7] pin */
7870 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000UL)                     /*!<PC[7] pin */
7871 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000UL)                     /*!<PD[7] pin */
7872 
7873 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
7874 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
7875 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x00000007 */
7876 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
7877 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
7878 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x00000070 */
7879 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
7880 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
7881 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000700 */
7882 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
7883 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
7884 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x00007000 */
7885 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
7886 
7887 /**
7888   * @brief   EXTI8 configuration
7889   */
7890 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000UL)                     /*!<PA[8] pin */
7891 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001UL)                     /*!<PB[8] pin */
7892 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002UL)                     /*!<PC[8] pin */
7893 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003UL)                     /*!<PD[8] pin */
7894 
7895 /**
7896   * @brief   EXTI9 configuration
7897   */
7898 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000UL)                     /*!<PA[9] pin */
7899 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010UL)                     /*!<PB[9] pin */
7900 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020UL)                     /*!<PC[9] pin */
7901 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030UL)                     /*!<PD[9] pin */
7902 
7903 /**
7904   * @brief   EXTI10 configuration
7905   */
7906 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000UL)                     /*!<PA[10] pin */
7907 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100UL)                     /*!<PB[10] pin */
7908 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200UL)                     /*!<PC[10] pin */
7909 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300UL)                     /*!<PD[10] pin */
7910 
7911 /**
7912   * @brief   EXTI11 configuration
7913   */
7914 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000UL)                     /*!<PA[11] pin */
7915 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000UL)                     /*!<PB[11] pin */
7916 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000UL)                     /*!<PC[11] pin */
7917 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000UL)                     /*!<PD[11] pin */
7918 
7919 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
7920 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
7921 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
7922 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
7923 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
7924 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
7925 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
7926 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
7927 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
7928 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
7929 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
7930 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
7931 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
7932 
7933 /**
7934   * @brief   EXTI12 configuration
7935   */
7936 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000UL)                     /*!<PA[12] pin */
7937 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001UL)                     /*!<PB[12] pin */
7938 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002UL)                     /*!<PC[12] pin */
7939 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003UL)                     /*!<PD[12] pin */
7940 
7941 /**
7942   * @brief   EXTI13 configuration
7943   */
7944 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000UL)                     /*!<PA[13] pin */
7945 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010UL)                     /*!<PB[13] pin */
7946 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020UL)                     /*!<PC[13] pin */
7947 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030UL)                     /*!<PD[13] pin */
7948 
7949 /**
7950   * @brief   EXTI14 configuration
7951   */
7952 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000UL)                     /*!<PA[14] pin */
7953 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100UL)                     /*!<PB[14] pin */
7954 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200UL)                     /*!<PC[14] pin */
7955 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300UL)                     /*!<PD[14] pin */
7956 
7957 /**
7958   * @brief   EXTI15 configuration
7959   */
7960 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000UL)                     /*!<PA[15] pin */
7961 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000UL)                     /*!<PB[15] pin */
7962 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000UL)                     /*!<PC[15] pin */
7963 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000UL)                     /*!<PD[15] pin */
7964 
7965 /******************  Bit definition for SYSCFG_SCSR register  ****************/
7966 #define SYSCFG_SCSR_SRAM2ER_Pos         (0U)
7967 #define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)     /*!< 0x00000001 */
7968 #define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
7969 #define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)
7970 #define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)    /*!< 0x00000002 */
7971 #define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
7972 
7973 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
7974 #define SYSCFG_CFGR2_CLL_Pos            (0U)
7975 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
7976 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
7977 #define SYSCFG_CFGR2_SPL_Pos            (1U)
7978 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
7979 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
7980 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
7981 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
7982 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
7983 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
7984 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
7985 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
7986 #define SYSCFG_CFGR2_SPF_Pos            (8U)
7987 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
7988 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
7989 
7990 /******************  Bit definition for SYSCFG_SWPR register  ****************/
7991 #define SYSCFG_SWPR_PAGE0_Pos           (0U)
7992 #define SYSCFG_SWPR_PAGE0_Msk           (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
7993 #define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
7994 #define SYSCFG_SWPR_PAGE1_Pos           (1U)
7995 #define SYSCFG_SWPR_PAGE1_Msk           (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
7996 #define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
7997 #define SYSCFG_SWPR_PAGE2_Pos           (2U)
7998 #define SYSCFG_SWPR_PAGE2_Msk           (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
7999 #define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
8000 #define SYSCFG_SWPR_PAGE3_Pos           (3U)
8001 #define SYSCFG_SWPR_PAGE3_Msk           (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
8002 #define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
8003 #define SYSCFG_SWPR_PAGE4_Pos           (4U)
8004 #define SYSCFG_SWPR_PAGE4_Msk           (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
8005 #define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
8006 #define SYSCFG_SWPR_PAGE5_Pos           (5U)
8007 #define SYSCFG_SWPR_PAGE5_Msk           (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
8008 #define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
8009 #define SYSCFG_SWPR_PAGE6_Pos           (6U)
8010 #define SYSCFG_SWPR_PAGE6_Msk           (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
8011 #define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
8012 #define SYSCFG_SWPR_PAGE7_Pos           (7U)
8013 #define SYSCFG_SWPR_PAGE7_Msk           (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
8014 #define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
8015 #define SYSCFG_SWPR_PAGE8_Pos           (8U)
8016 #define SYSCFG_SWPR_PAGE8_Msk           (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
8017 #define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
8018 #define SYSCFG_SWPR_PAGE9_Pos           (9U)
8019 #define SYSCFG_SWPR_PAGE9_Msk           (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
8020 #define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
8021 #define SYSCFG_SWPR_PAGE10_Pos          (10U)
8022 #define SYSCFG_SWPR_PAGE10_Msk          (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
8023 #define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
8024 #define SYSCFG_SWPR_PAGE11_Pos          (11U)
8025 #define SYSCFG_SWPR_PAGE11_Msk          (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
8026 #define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
8027 #define SYSCFG_SWPR_PAGE12_Pos          (12U)
8028 #define SYSCFG_SWPR_PAGE12_Msk          (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
8029 #define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
8030 #define SYSCFG_SWPR_PAGE13_Pos          (13U)
8031 #define SYSCFG_SWPR_PAGE13_Msk          (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
8032 #define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
8033 #define SYSCFG_SWPR_PAGE14_Pos          (14U)
8034 #define SYSCFG_SWPR_PAGE14_Msk          (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
8035 #define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
8036 #define SYSCFG_SWPR_PAGE15_Pos          (15U)
8037 #define SYSCFG_SWPR_PAGE15_Msk          (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
8038 #define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
8039 
8040 /******************  Bit definition for SYSCFG_SKR register  ****************/
8041 #define SYSCFG_SKR_KEY_Pos              (0U)
8042 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
8043 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
8044 
8045 
8046 
8047 
8048 /******************************************************************************/
8049 /*                                                                            */
8050 /*                                    TIM                                     */
8051 /*                                                                            */
8052 /******************************************************************************/
8053 /*******************  Bit definition for TIM_CR1 register  ********************/
8054 #define TIM_CR1_CEN_Pos           (0U)
8055 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
8056 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
8057 #define TIM_CR1_UDIS_Pos          (1U)
8058 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
8059 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
8060 #define TIM_CR1_URS_Pos           (2U)
8061 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
8062 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
8063 #define TIM_CR1_OPM_Pos           (3U)
8064 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
8065 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
8066 #define TIM_CR1_DIR_Pos           (4U)
8067 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
8068 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
8069 
8070 #define TIM_CR1_CMS_Pos           (5U)
8071 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
8072 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
8073 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
8074 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
8075 
8076 #define TIM_CR1_ARPE_Pos          (7U)
8077 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
8078 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
8079 
8080 #define TIM_CR1_CKD_Pos           (8U)
8081 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
8082 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
8083 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
8084 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
8085 
8086 #define TIM_CR1_UIFREMAP_Pos      (11U)
8087 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
8088 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
8089 
8090 /*******************  Bit definition for TIM_CR2 register  ********************/
8091 #define TIM_CR2_CCPC_Pos          (0U)
8092 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
8093 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
8094 #define TIM_CR2_CCUS_Pos          (2U)
8095 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
8096 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
8097 #define TIM_CR2_CCDS_Pos          (3U)
8098 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
8099 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
8100 
8101 #define TIM_CR2_MMS_Pos           (4U)
8102 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
8103 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
8104 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
8105 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
8106 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
8107 
8108 #define TIM_CR2_TI1S_Pos          (7U)
8109 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
8110 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
8111 #define TIM_CR2_OIS1_Pos          (8U)
8112 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
8113 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
8114 #define TIM_CR2_OIS1N_Pos         (9U)
8115 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
8116 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
8117 #define TIM_CR2_OIS2_Pos          (10U)
8118 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
8119 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
8120 #define TIM_CR2_OIS2N_Pos         (11U)
8121 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
8122 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
8123 #define TIM_CR2_OIS3_Pos          (12U)
8124 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
8125 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
8126 #define TIM_CR2_OIS3N_Pos         (13U)
8127 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
8128 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
8129 #define TIM_CR2_OIS4_Pos          (14U)
8130 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
8131 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
8132 #define TIM_CR2_OIS5_Pos          (16U)
8133 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
8134 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
8135 #define TIM_CR2_OIS6_Pos          (18U)
8136 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
8137 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
8138 
8139 #define TIM_CR2_MMS2_Pos          (20U)
8140 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
8141 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
8142 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
8143 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
8144 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
8145 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
8146 
8147 /*******************  Bit definition for TIM_SMCR register  *******************/
8148 #define TIM_SMCR_SMS_Pos          (0U)
8149 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
8150 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
8151 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
8152 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
8153 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
8154 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
8155 
8156 #define TIM_SMCR_OCCS_Pos         (3U)
8157 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
8158 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
8159 
8160 #define TIM_SMCR_TS_Pos           (4U)
8161 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000070 */
8162 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
8163 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000010 */
8164 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000020 */
8165 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000040 */
8166 
8167 #define TIM_SMCR_MSM_Pos          (7U)
8168 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
8169 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
8170 
8171 #define TIM_SMCR_ETF_Pos          (8U)
8172 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
8173 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
8174 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
8175 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
8176 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
8177 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
8178 
8179 #define TIM_SMCR_ETPS_Pos         (12U)
8180 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
8181 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
8182 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
8183 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
8184 
8185 #define TIM_SMCR_ECE_Pos          (14U)
8186 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
8187 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
8188 #define TIM_SMCR_ETP_Pos          (15U)
8189 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
8190 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
8191 
8192 /*******************  Bit definition for TIM_DIER register  *******************/
8193 #define TIM_DIER_UIE_Pos          (0U)
8194 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
8195 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
8196 #define TIM_DIER_CC1IE_Pos        (1U)
8197 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
8198 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
8199 #define TIM_DIER_CC2IE_Pos        (2U)
8200 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
8201 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
8202 #define TIM_DIER_CC3IE_Pos        (3U)
8203 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
8204 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
8205 #define TIM_DIER_CC4IE_Pos        (4U)
8206 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
8207 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
8208 #define TIM_DIER_COMIE_Pos        (5U)
8209 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
8210 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
8211 #define TIM_DIER_TIE_Pos          (6U)
8212 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
8213 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
8214 #define TIM_DIER_BIE_Pos          (7U)
8215 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
8216 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
8217 #define TIM_DIER_UDE_Pos          (8U)
8218 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
8219 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
8220 #define TIM_DIER_CC1DE_Pos        (9U)
8221 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
8222 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
8223 #define TIM_DIER_CC2DE_Pos        (10U)
8224 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
8225 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
8226 #define TIM_DIER_CC3DE_Pos        (11U)
8227 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
8228 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
8229 #define TIM_DIER_CC4DE_Pos        (12U)
8230 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
8231 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
8232 #define TIM_DIER_COMDE_Pos        (13U)
8233 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
8234 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
8235 #define TIM_DIER_TDE_Pos          (14U)
8236 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
8237 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
8238 
8239 /********************  Bit definition for TIM_SR register  ********************/
8240 #define TIM_SR_UIF_Pos            (0U)
8241 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
8242 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
8243 #define TIM_SR_CC1IF_Pos          (1U)
8244 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
8245 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
8246 #define TIM_SR_CC2IF_Pos          (2U)
8247 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
8248 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
8249 #define TIM_SR_CC3IF_Pos          (3U)
8250 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
8251 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
8252 #define TIM_SR_CC4IF_Pos          (4U)
8253 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
8254 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
8255 #define TIM_SR_COMIF_Pos          (5U)
8256 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
8257 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
8258 #define TIM_SR_TIF_Pos            (6U)
8259 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
8260 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
8261 #define TIM_SR_BIF_Pos            (7U)
8262 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
8263 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
8264 #define TIM_SR_B2IF_Pos           (8U)
8265 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
8266 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
8267 #define TIM_SR_CC1OF_Pos          (9U)
8268 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
8269 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
8270 #define TIM_SR_CC2OF_Pos          (10U)
8271 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
8272 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
8273 #define TIM_SR_CC3OF_Pos          (11U)
8274 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
8275 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
8276 #define TIM_SR_CC4OF_Pos          (12U)
8277 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
8278 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
8279 #define TIM_SR_SBIF_Pos           (13U)
8280 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
8281 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
8282 #define TIM_SR_CC5IF_Pos          (16U)
8283 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
8284 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
8285 #define TIM_SR_CC6IF_Pos          (17U)
8286 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
8287 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
8288 
8289 
8290 /*******************  Bit definition for TIM_EGR register  ********************/
8291 #define TIM_EGR_UG_Pos            (0U)
8292 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
8293 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
8294 #define TIM_EGR_CC1G_Pos          (1U)
8295 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
8296 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
8297 #define TIM_EGR_CC2G_Pos          (2U)
8298 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
8299 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
8300 #define TIM_EGR_CC3G_Pos          (3U)
8301 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
8302 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
8303 #define TIM_EGR_CC4G_Pos          (4U)
8304 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
8305 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
8306 #define TIM_EGR_COMG_Pos          (5U)
8307 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
8308 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
8309 #define TIM_EGR_TG_Pos            (6U)
8310 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
8311 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
8312 #define TIM_EGR_BG_Pos            (7U)
8313 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
8314 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
8315 #define TIM_EGR_B2G_Pos           (8U)
8316 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
8317 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
8318 
8319 
8320 /******************  Bit definition for TIM_CCMR1 register  *******************/
8321 #define TIM_CCMR1_CC1S_Pos        (0U)
8322 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
8323 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
8324 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
8325 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
8326 
8327 #define TIM_CCMR1_OC1FE_Pos       (2U)
8328 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
8329 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
8330 #define TIM_CCMR1_OC1PE_Pos       (3U)
8331 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
8332 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
8333 
8334 #define TIM_CCMR1_OC1M_Pos        (4U)
8335 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
8336 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
8337 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
8338 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
8339 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
8340 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
8341 
8342 #define TIM_CCMR1_OC1CE_Pos       (7U)
8343 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
8344 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
8345 
8346 #define TIM_CCMR1_CC2S_Pos        (8U)
8347 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
8348 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
8349 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
8350 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
8351 
8352 #define TIM_CCMR1_OC2FE_Pos       (10U)
8353 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
8354 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
8355 #define TIM_CCMR1_OC2PE_Pos       (11U)
8356 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
8357 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
8358 
8359 #define TIM_CCMR1_OC2M_Pos        (12U)
8360 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
8361 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
8362 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
8363 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
8364 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
8365 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
8366 
8367 #define TIM_CCMR1_OC2CE_Pos       (15U)
8368 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
8369 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
8370 
8371 /*----------------------------------------------------------------------------*/
8372 #define TIM_CCMR1_IC1PSC_Pos      (2U)
8373 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
8374 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
8375 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
8376 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
8377 
8378 #define TIM_CCMR1_IC1F_Pos        (4U)
8379 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
8380 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
8381 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
8382 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
8383 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
8384 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
8385 
8386 #define TIM_CCMR1_IC2PSC_Pos      (10U)
8387 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
8388 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
8389 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
8390 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
8391 
8392 #define TIM_CCMR1_IC2F_Pos        (12U)
8393 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
8394 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
8395 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
8396 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
8397 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
8398 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
8399 
8400 /******************  Bit definition for TIM_CCMR2 register  *******************/
8401 #define TIM_CCMR2_CC3S_Pos        (0U)
8402 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
8403 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
8404 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
8405 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
8406 
8407 #define TIM_CCMR2_OC3FE_Pos       (2U)
8408 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
8409 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
8410 #define TIM_CCMR2_OC3PE_Pos       (3U)
8411 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
8412 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
8413 
8414 #define TIM_CCMR2_OC3M_Pos        (4U)
8415 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
8416 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
8417 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
8418 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
8419 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
8420 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
8421 
8422 #define TIM_CCMR2_OC3CE_Pos       (7U)
8423 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
8424 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
8425 
8426 #define TIM_CCMR2_CC4S_Pos        (8U)
8427 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
8428 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
8429 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
8430 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
8431 
8432 #define TIM_CCMR2_OC4FE_Pos       (10U)
8433 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
8434 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
8435 #define TIM_CCMR2_OC4PE_Pos       (11U)
8436 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
8437 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
8438 
8439 #define TIM_CCMR2_OC4M_Pos        (12U)
8440 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
8441 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
8442 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
8443 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
8444 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
8445 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
8446 
8447 #define TIM_CCMR2_OC4CE_Pos       (15U)
8448 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
8449 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
8450 
8451 /*----------------------------------------------------------------------------*/
8452 #define TIM_CCMR2_IC3PSC_Pos      (2U)
8453 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
8454 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
8455 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
8456 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
8457 
8458 #define TIM_CCMR2_IC3F_Pos        (4U)
8459 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
8460 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
8461 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
8462 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
8463 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
8464 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
8465 
8466 #define TIM_CCMR2_IC4PSC_Pos      (10U)
8467 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
8468 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
8469 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
8470 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
8471 
8472 #define TIM_CCMR2_IC4F_Pos        (12U)
8473 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
8474 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
8475 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
8476 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
8477 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
8478 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
8479 
8480 /******************  Bit definition for TIM_CCMR3 register  *******************/
8481 #define TIM_CCMR3_OC5FE_Pos       (2U)
8482 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
8483 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
8484 #define TIM_CCMR3_OC5PE_Pos       (3U)
8485 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
8486 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
8487 
8488 #define TIM_CCMR3_OC5M_Pos        (4U)
8489 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
8490 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
8491 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
8492 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
8493 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
8494 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
8495 
8496 #define TIM_CCMR3_OC5CE_Pos       (7U)
8497 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
8498 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
8499 
8500 #define TIM_CCMR3_OC6FE_Pos       (10U)
8501 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
8502 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
8503 #define TIM_CCMR3_OC6PE_Pos       (11U)
8504 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
8505 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
8506 
8507 #define TIM_CCMR3_OC6M_Pos        (12U)
8508 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
8509 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
8510 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
8511 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
8512 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
8513 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
8514 
8515 #define TIM_CCMR3_OC6CE_Pos       (15U)
8516 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
8517 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
8518 
8519 /*******************  Bit definition for TIM_CCER register  *******************/
8520 #define TIM_CCER_CC1E_Pos         (0U)
8521 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
8522 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
8523 #define TIM_CCER_CC1P_Pos         (1U)
8524 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
8525 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
8526 #define TIM_CCER_CC1NE_Pos        (2U)
8527 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
8528 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
8529 #define TIM_CCER_CC1NP_Pos        (3U)
8530 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
8531 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
8532 #define TIM_CCER_CC2E_Pos         (4U)
8533 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
8534 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
8535 #define TIM_CCER_CC2P_Pos         (5U)
8536 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
8537 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
8538 #define TIM_CCER_CC2NE_Pos        (6U)
8539 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
8540 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
8541 #define TIM_CCER_CC2NP_Pos        (7U)
8542 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
8543 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
8544 #define TIM_CCER_CC3E_Pos         (8U)
8545 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
8546 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
8547 #define TIM_CCER_CC3P_Pos         (9U)
8548 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
8549 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
8550 #define TIM_CCER_CC3NE_Pos        (10U)
8551 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
8552 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
8553 #define TIM_CCER_CC3NP_Pos        (11U)
8554 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
8555 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
8556 #define TIM_CCER_CC4E_Pos         (12U)
8557 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
8558 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
8559 #define TIM_CCER_CC4P_Pos         (13U)
8560 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
8561 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
8562 #define TIM_CCER_CC4NP_Pos        (15U)
8563 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
8564 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
8565 #define TIM_CCER_CC5E_Pos         (16U)
8566 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
8567 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
8568 #define TIM_CCER_CC5P_Pos         (17U)
8569 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
8570 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
8571 #define TIM_CCER_CC6E_Pos         (20U)
8572 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
8573 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
8574 #define TIM_CCER_CC6P_Pos         (21U)
8575 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
8576 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
8577 
8578 /*******************  Bit definition for TIM_CNT register  ********************/
8579 #define TIM_CNT_CNT_Pos           (0U)
8580 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
8581 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
8582 #define TIM_CNT_UIFCPY_Pos        (31U)
8583 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
8584 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
8585 
8586 /*******************  Bit definition for TIM_PSC register  ********************/
8587 #define TIM_PSC_PSC_Pos           (0U)
8588 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
8589 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
8590 
8591 /*******************  Bit definition for TIM_ARR register  ********************/
8592 #define TIM_ARR_ARR_Pos           (0U)
8593 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
8594 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
8595 
8596 /*******************  Bit definition for TIM_RCR register  ********************/
8597 #define TIM_RCR_REP_Pos           (0U)
8598 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
8599 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
8600 
8601 /*******************  Bit definition for TIM_CCR1 register  *******************/
8602 #define TIM_CCR1_CCR1_Pos         (0U)
8603 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
8604 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
8605 
8606 /*******************  Bit definition for TIM_CCR2 register  *******************/
8607 #define TIM_CCR2_CCR2_Pos         (0U)
8608 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
8609 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
8610 
8611 /*******************  Bit definition for TIM_CCR3 register  *******************/
8612 #define TIM_CCR3_CCR3_Pos         (0U)
8613 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
8614 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
8615 
8616 /*******************  Bit definition for TIM_CCR4 register  *******************/
8617 #define TIM_CCR4_CCR4_Pos         (0U)
8618 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
8619 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
8620 
8621 /*******************  Bit definition for TIM_CCR5 register  *******************/
8622 #define TIM_CCR5_CCR5_Pos         (0U)
8623 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
8624 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
8625 #define TIM_CCR5_GC5C1_Pos        (29U)
8626 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
8627 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
8628 #define TIM_CCR5_GC5C2_Pos        (30U)
8629 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
8630 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
8631 #define TIM_CCR5_GC5C3_Pos        (31U)
8632 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
8633 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
8634 
8635 /*******************  Bit definition for TIM_CCR6 register  *******************/
8636 #define TIM_CCR6_CCR6_Pos         (0U)
8637 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
8638 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
8639 
8640 /*******************  Bit definition for TIM_BDTR register  *******************/
8641 #define TIM_BDTR_DTG_Pos          (0U)
8642 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
8643 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
8644 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
8645 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
8646 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
8647 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
8648 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
8649 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
8650 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
8651 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
8652 
8653 #define TIM_BDTR_LOCK_Pos         (8U)
8654 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
8655 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
8656 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
8657 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
8658 
8659 #define TIM_BDTR_OSSI_Pos         (10U)
8660 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
8661 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
8662 #define TIM_BDTR_OSSR_Pos         (11U)
8663 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
8664 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
8665 #define TIM_BDTR_BKE_Pos          (12U)
8666 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
8667 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
8668 #define TIM_BDTR_BKP_Pos          (13U)
8669 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
8670 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
8671 #define TIM_BDTR_AOE_Pos          (14U)
8672 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
8673 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
8674 #define TIM_BDTR_MOE_Pos          (15U)
8675 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
8676 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
8677 
8678 #define TIM_BDTR_BKF_Pos          (16U)
8679 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
8680 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
8681 #define TIM_BDTR_BK2F_Pos         (20U)
8682 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
8683 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
8684 
8685 #define TIM_BDTR_BK2E_Pos         (24U)
8686 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
8687 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
8688 #define TIM_BDTR_BK2P_Pos         (25U)
8689 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
8690 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
8691 
8692 /*******************  Bit definition for TIM_DCR register  ********************/
8693 #define TIM_DCR_DBA_Pos           (0U)
8694 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
8695 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
8696 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
8697 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
8698 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
8699 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
8700 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
8701 
8702 #define TIM_DCR_DBL_Pos           (8U)
8703 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
8704 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
8705 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
8706 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
8707 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
8708 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
8709 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
8710 
8711 /*******************  Bit definition for TIM_DMAR register  *******************/
8712 #define TIM_DMAR_DMAB_Pos         (0U)
8713 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
8714 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
8715 
8716 /*******************  Bit definition for TIM1_OR1 register  *******************/
8717 #define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)
8718 #define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000003 */
8719 #define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
8720 #define TIM1_OR1_ETR_ADC1_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000001 */
8721 #define TIM1_OR1_ETR_ADC1_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000002 */
8722 
8723 #define TIM1_OR1_TI1_RMP_Pos           (4U)
8724 #define TIM1_OR1_TI1_RMP_Msk           (0x1UL << TIM1_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */
8725 #define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
8726 
8727 /*******************  Bit definition for TIM1_OR2 register  *******************/
8728 #define TIM1_OR2_BKINE_Pos             (0U)
8729 #define TIM1_OR2_BKINE_Msk             (0x1UL << TIM1_OR2_BKINE_Pos)           /*!< 0x00000001 */
8730 #define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
8731 #define TIM1_OR2_BKCMP1E_Pos           (1U)
8732 #define TIM1_OR2_BKCMP1E_Msk           (0x1UL << TIM1_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */
8733 #define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
8734 #define TIM1_OR2_BKCMP2E_Pos           (2U)
8735 #define TIM1_OR2_BKCMP2E_Msk           (0x1UL << TIM1_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */
8736 #define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
8737 #define TIM1_OR2_BKINP_Pos             (9U)
8738 #define TIM1_OR2_BKINP_Msk             (0x1UL << TIM1_OR2_BKINP_Pos)           /*!< 0x00000200 */
8739 #define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
8740 #define TIM1_OR2_BKCMP1P_Pos           (10U)
8741 #define TIM1_OR2_BKCMP1P_Msk           (0x1UL << TIM1_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */
8742 #define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
8743 #define TIM1_OR2_BKCMP2P_Pos           (11U)
8744 #define TIM1_OR2_BKCMP2P_Msk           (0x1UL << TIM1_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */
8745 #define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
8746 
8747 #define TIM1_OR2_ETRSEL_Pos            (14U)
8748 #define TIM1_OR2_ETRSEL_Msk            (0x7UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */
8749 #define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
8750 #define TIM1_OR2_ETRSEL_0              (0x1UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00004000 */
8751 #define TIM1_OR2_ETRSEL_1              (0x2UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00008000 */
8752 #define TIM1_OR2_ETRSEL_2              (0x4UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00010000 */
8753 
8754 /*******************  Bit definition for TIM1_OR3 register  *******************/
8755 #define TIM1_OR3_BK2INE_Pos            (0U)
8756 #define TIM1_OR3_BK2INE_Msk            (0x1UL << TIM1_OR3_BK2INE_Pos)          /*!< 0x00000001 */
8757 #define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
8758 #define TIM1_OR3_BK2CMP1E_Pos          (1U)
8759 #define TIM1_OR3_BK2CMP1E_Msk          (0x1UL << TIM1_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */
8760 #define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
8761 #define TIM1_OR3_BK2CMP2E_Pos          (2U)
8762 #define TIM1_OR3_BK2CMP2E_Msk          (0x1UL << TIM1_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */
8763 #define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
8764 #define TIM1_OR3_BK2INP_Pos            (9U)
8765 #define TIM1_OR3_BK2INP_Msk            (0x1UL << TIM1_OR3_BK2INP_Pos)          /*!< 0x00000200 */
8766 #define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
8767 #define TIM1_OR3_BK2CMP1P_Pos          (10U)
8768 #define TIM1_OR3_BK2CMP1P_Msk          (0x1UL << TIM1_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */
8769 #define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
8770 #define TIM1_OR3_BK2CMP2P_Pos          (11U)
8771 #define TIM1_OR3_BK2CMP2P_Msk          (0x1UL << TIM1_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */
8772 #define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
8773 
8774 
8775 /*******************  Bit definition for TIM2_OR1 register  *******************/
8776 #define TIM2_OR1_ITR1_RMP_Pos     (0U)
8777 #define TIM2_OR1_ITR1_RMP_Msk     (0x1UL << TIM2_OR1_ITR1_RMP_Pos)             /*!< 0x00000001 */
8778 #define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
8779 #define TIM2_OR1_ETR1_RMP_Pos     (1U)
8780 #define TIM2_OR1_ETR1_RMP_Msk     (0x1UL << TIM2_OR1_ETR1_RMP_Pos)             /*!< 0x00000002 */
8781 #define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
8782 
8783 #define TIM2_OR1_TI4_RMP_Pos      (2U)
8784 #define TIM2_OR1_TI4_RMP_Msk      (0x3UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x0000000C */
8785 #define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
8786 #define TIM2_OR1_TI4_RMP_0        (0x1UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000004 */
8787 #define TIM2_OR1_TI4_RMP_1        (0x2UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000008 */
8788 
8789 /*******************  Bit definition for TIM2_OR2 register  *******************/
8790 #define TIM2_OR2_ETRSEL_Pos       (14U)
8791 #define TIM2_OR2_ETRSEL_Msk       (0x7UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */
8792 #define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
8793 #define TIM2_OR2_ETRSEL_0         (0x1UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00004000 */
8794 #define TIM2_OR2_ETRSEL_1         (0x2UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00008000 */
8795 #define TIM2_OR2_ETRSEL_2         (0x4UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00010000 */
8796 
8797 
8798 /*******************  Bit definition for TIM15_OR1 register  ******************/
8799 #define TIM15_OR1_TI1_RMP_Pos           (0U)
8800 #define TIM15_OR1_TI1_RMP_Msk           (0x1UL << TIM15_OR1_TI1_RMP_Pos)       /*!< 0x00000001 */
8801 #define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
8802 
8803 #define TIM15_OR1_ENCODER_MODE_Pos      (1U)
8804 #define TIM15_OR1_ENCODER_MODE_Msk      (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000006 */
8805 #define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
8806 #define TIM15_OR1_ENCODER_MODE_0        (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000002 */
8807 #define TIM15_OR1_ENCODER_MODE_1        (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000004 */
8808 
8809 /*******************  Bit definition for TIM15_OR2 register  ******************/
8810 #define TIM15_OR2_BKINE_Pos             (0U)
8811 #define TIM15_OR2_BKINE_Msk             (0x1UL << TIM15_OR2_BKINE_Pos)         /*!< 0x00000001 */
8812 #define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
8813 #define TIM15_OR2_BKCMP1E_Pos           (1U)
8814 #define TIM15_OR2_BKCMP1E_Msk           (0x1UL << TIM15_OR2_BKCMP1E_Pos)       /*!< 0x00000002 */
8815 #define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
8816 #define TIM15_OR2_BKINP_Pos             (9U)
8817 #define TIM15_OR2_BKINP_Msk             (0x1UL << TIM15_OR2_BKINP_Pos)         /*!< 0x00000200 */
8818 #define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
8819 #define TIM15_OR2_BKCMP1P_Pos           (10U)
8820 #define TIM15_OR2_BKCMP1P_Msk           (0x1UL << TIM15_OR2_BKCMP1P_Pos)       /*!< 0x00000400 */
8821 #define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
8822 
8823 /*******************  Bit definition for TIM16_OR1 register  ******************/
8824 #define TIM16_OR1_TI1_RMP_Pos      (0U)
8825 #define TIM16_OR1_TI1_RMP_Msk      (0x7UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000007 */
8826 #define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
8827 #define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
8828 #define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
8829 #define TIM16_OR1_TI1_RMP_2        (0x4UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000004 */
8830 
8831 /*******************  Bit definition for TIM16_OR2 register  ******************/
8832 #define TIM16_OR2_BKINE_Pos        (0U)
8833 #define TIM16_OR2_BKINE_Msk        (0x1UL << TIM16_OR2_BKINE_Pos)              /*!< 0x00000001 */
8834 #define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
8835 #define TIM16_OR2_BKCMP1E_Pos      (1U)
8836 #define TIM16_OR2_BKCMP1E_Msk      (0x1UL << TIM16_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */
8837 #define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
8838 #define TIM16_OR2_BKINP_Pos        (9U)
8839 #define TIM16_OR2_BKINP_Msk        (0x1UL << TIM16_OR2_BKINP_Pos)              /*!< 0x00000200 */
8840 #define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
8841 #define TIM16_OR2_BKCMP1P_Pos      (10U)
8842 #define TIM16_OR2_BKCMP1P_Msk      (0x1UL << TIM16_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */
8843 #define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
8844 
8845 
8846 /******************************************************************************/
8847 /*                                                                            */
8848 /*                         Low Power Timer (LPTIM)                            */
8849 /*                                                                            */
8850 /******************************************************************************/
8851 /******************  Bit definition for LPTIM_ISR register  *******************/
8852 #define LPTIM_ISR_CMPM_Pos          (0U)
8853 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
8854 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
8855 #define LPTIM_ISR_ARRM_Pos          (1U)
8856 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
8857 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
8858 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
8859 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
8860 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
8861 #define LPTIM_ISR_CMPOK_Pos         (3U)
8862 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
8863 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
8864 #define LPTIM_ISR_ARROK_Pos         (4U)
8865 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
8866 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
8867 #define LPTIM_ISR_UP_Pos            (5U)
8868 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
8869 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
8870 #define LPTIM_ISR_DOWN_Pos          (6U)
8871 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
8872 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
8873 #define LPTIM_ISR_UE_Pos            (7U)
8874 #define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
8875 #define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
8876 #define LPTIM_ISR_REPOK_Pos         (8U)
8877 #define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
8878 #define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
8879 
8880 /******************  Bit definition for LPTIM_ICR register  *******************/
8881 #define LPTIM_ICR_CMPMCF_Pos        (0U)
8882 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
8883 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
8884 #define LPTIM_ICR_ARRMCF_Pos        (1U)
8885 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
8886 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
8887 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
8888 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
8889 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
8890 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
8891 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
8892 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
8893 #define LPTIM_ICR_ARROKCF_Pos       (4U)
8894 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
8895 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
8896 #define LPTIM_ICR_UPCF_Pos          (5U)
8897 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
8898 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
8899 #define LPTIM_ICR_DOWNCF_Pos        (6U)
8900 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
8901 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
8902 #define LPTIM_ICR_UECF_Pos          (7U)
8903 #define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)               /*!< 0x00000080 */
8904 #define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
8905 #define LPTIM_ICR_REPOKCF_Pos       (8U)
8906 #define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)            /*!< 0x00000100 */
8907 #define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
8908 
8909 /******************  Bit definition for LPTIM_IER register ********************/
8910 #define LPTIM_IER_CMPMIE_Pos        (0U)
8911 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
8912 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
8913 #define LPTIM_IER_ARRMIE_Pos        (1U)
8914 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
8915 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
8916 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
8917 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
8918 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
8919 #define LPTIM_IER_CMPOKIE_Pos       (3U)
8920 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
8921 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
8922 #define LPTIM_IER_ARROKIE_Pos       (4U)
8923 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
8924 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
8925 #define LPTIM_IER_UPIE_Pos          (5U)
8926 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
8927 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
8928 #define LPTIM_IER_DOWNIE_Pos        (6U)
8929 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
8930 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
8931 #define LPTIM_IER_UEIE_Pos          (7U)
8932 #define LPTIM_IER_UEIE_Msk          (0x1UL << LPTIM_IER_UEIE_Pos)              /*!< 0x00000080 */
8933 #define LPTIM_IER_UEIE              LPTIM_IER_UEIE_Msk                         /*!< Update event Interrupt Enable */
8934 #define LPTIM_IER_REPOKIE_Pos       (8U)
8935 #define LPTIM_IER_REPOKIE_Msk       (0x1UL << LPTIM_IER_REPOKIE_Pos)           /*!< 0x00000100 */
8936 #define LPTIM_IER_REPOKIE           LPTIM_IER_REPOKIE_Msk                      /*!< Repetition register update OK Interrupt Enable */
8937 
8938 /******************  Bit definition for LPTIM_CFGR register *******************/
8939 #define LPTIM_CFGR_CKSEL_Pos        (0U)
8940 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
8941 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
8942 
8943 #define LPTIM_CFGR_CKPOL_Pos        (1U)
8944 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
8945 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
8946 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
8947 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
8948 
8949 #define LPTIM_CFGR_CKFLT_Pos        (3U)
8950 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
8951 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
8952 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
8953 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
8954 
8955 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
8956 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
8957 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
8958 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
8959 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
8960 
8961 #define LPTIM_CFGR_PRESC_Pos        (9U)
8962 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
8963 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
8964 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
8965 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
8966 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
8967 
8968 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
8969 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
8970 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
8971 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
8972 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
8973 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
8974 
8975 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
8976 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
8977 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
8978 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
8979 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
8980 
8981 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
8982 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
8983 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
8984 #define LPTIM_CFGR_WAVE_Pos         (20U)
8985 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
8986 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
8987 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
8988 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
8989 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
8990 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
8991 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
8992 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
8993 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
8994 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
8995 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
8996 #define LPTIM_CFGR_ENC_Pos          (24U)
8997 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
8998 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
8999 
9000 /******************  Bit definition for LPTIM_CR register  ********************/
9001 #define LPTIM_CR_ENABLE_Pos         (0U)
9002 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
9003 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
9004 #define LPTIM_CR_SNGSTRT_Pos        (1U)
9005 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
9006 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
9007 #define LPTIM_CR_CNTSTRT_Pos        (2U)
9008 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
9009 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
9010 #define LPTIM_CR_COUNTRST_Pos       (3U)
9011 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
9012 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
9013 #define LPTIM_CR_RSTARE_Pos         (4U)
9014 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
9015 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
9016 
9017 /******************  Bit definition for LPTIM_CMP register  *******************/
9018 #define LPTIM_CMP_CMP_Pos           (0U)
9019 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
9020 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
9021 
9022 /******************  Bit definition for LPTIM_ARR register  *******************/
9023 #define LPTIM_ARR_ARR_Pos           (0U)
9024 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
9025 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
9026 
9027 /******************  Bit definition for LPTIM_CNT register  *******************/
9028 #define LPTIM_CNT_CNT_Pos           (0U)
9029 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
9030 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
9031 
9032 /******************  Bit definition for LPTIM_OR register  ********************/
9033 #define LPTIM_OR_OR_Pos             (0U)
9034 #define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
9035 #define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
9036 #define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
9037 #define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
9038 
9039 /******************  Bit definition for LPTIM_RCR register  *******************/
9040 #define LPTIM_RCR_REP_Pos           (0U)
9041 #define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
9042 #define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!<Repetition Counter Value */
9043 
9044 /******************************************************************************/
9045 /*                                                                            */
9046 /*                      Analog Comparators (COMP)                             */
9047 /*                                                                            */
9048 /******************************************************************************/
9049 /**********************  Bit definition for COMP_CSR register  ****************/
9050 #define COMP_CSR_EN_Pos            (0U)
9051 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
9052 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
9053 
9054 #define COMP_CSR_PWRMODE_Pos       (2U)
9055 #define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
9056 #define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
9057 #define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
9058 #define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
9059 
9060 #define COMP_CSR_INMSEL_Pos        (4U)
9061 #define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
9062 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
9063 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
9064 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
9065 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
9066 
9067 #define COMP_CSR_INPSEL_Pos        (7U)
9068 #define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
9069 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
9070 #define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
9071 #define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
9072 
9073 #define COMP_CSR_POLARITY_Pos      (15U)
9074 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
9075 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
9076 
9077 #define COMP_CSR_HYST_Pos          (16U)
9078 #define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
9079 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
9080 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
9081 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
9082 
9083 #define COMP_CSR_BLANKING_Pos      (18U)
9084 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
9085 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
9086 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
9087 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
9088 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
9089 
9090 #define COMP_CSR_BRGEN_Pos         (22U)
9091 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
9092 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
9093 #define COMP_CSR_SCALEN_Pos        (23U)
9094 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
9095 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
9096 
9097 #define COMP_CSR_INMESEL_Pos       (25U)
9098 #define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
9099 #define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
9100 #define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
9101 #define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
9102 
9103 #define COMP_CSR_VALUE_Pos         (30U)
9104 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
9105 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
9106 
9107 #define COMP_CSR_LOCK_Pos          (31U)
9108 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
9109 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
9110 
9111 /******************************************************************************/
9112 /*                                                                            */
9113 /*                         Operational Amplifier (OPAMP)                      */
9114 /*                                                                            */
9115 /******************************************************************************/
9116 /*********************  Bit definition for OPAMPx_CSR register  ***************/
9117 #define OPAMP_CSR_OPAMPxEN_Pos           (0U)
9118 #define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
9119 #define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
9120 #define OPAMP_CSR_OPALPM_Pos             (1U)
9121 #define OPAMP_CSR_OPALPM_Msk             (0x1UL << OPAMP_CSR_OPALPM_Pos)       /*!< 0x00000002 */
9122 #define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
9123 
9124 #define OPAMP_CSR_OPAMODE_Pos            (2U)
9125 #define OPAMP_CSR_OPAMODE_Msk            (0x3UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x0000000C */
9126 #define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
9127 #define OPAMP_CSR_OPAMODE_0              (0x1UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000004 */
9128 #define OPAMP_CSR_OPAMODE_1              (0x2UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000008 */
9129 
9130 #define OPAMP_CSR_PGGAIN_Pos             (4U)
9131 #define OPAMP_CSR_PGGAIN_Msk             (0x3UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000030 */
9132 #define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
9133 #define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000010 */
9134 #define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000020 */
9135 
9136 #define OPAMP_CSR_VMSEL_Pos              (8U)
9137 #define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000300 */
9138 #define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
9139 #define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000100 */
9140 #define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000200 */
9141 
9142 #define OPAMP_CSR_VPSEL_Pos              (10U)
9143 #define OPAMP_CSR_VPSEL_Msk              (0x1UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x00000400 */
9144 #define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
9145 #define OPAMP_CSR_CALON_Pos              (12U)
9146 #define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00001000 */
9147 #define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
9148 #define OPAMP_CSR_CALSEL_Pos             (13U)
9149 #define OPAMP_CSR_CALSEL_Msk             (0x1UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00002000 */
9150 #define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
9151 #define OPAMP_CSR_USERTRIM_Pos           (14U)
9152 #define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00004000 */
9153 #define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
9154 #define OPAMP_CSR_CALOUT_Pos             (15U)
9155 #define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x00008000 */
9156 #define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
9157 
9158 /*********************  Bit definition for OPAMP1_CSR register  ***************/
9159 #define OPAMP1_CSR_OPAEN_Pos              (0U)
9160 #define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
9161 #define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
9162 #define OPAMP1_CSR_OPALPM_Pos             (1U)
9163 #define OPAMP1_CSR_OPALPM_Msk             (0x1UL << OPAMP1_CSR_OPALPM_Pos)     /*!< 0x00000002 */
9164 #define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
9165 
9166 #define OPAMP1_CSR_OPAMODE_Pos            (2U)
9167 #define OPAMP1_CSR_OPAMODE_Msk            (0x3UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x0000000C */
9168 #define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
9169 #define OPAMP1_CSR_OPAMODE_0              (0x1UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000004 */
9170 #define OPAMP1_CSR_OPAMODE_1              (0x2UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000008 */
9171 
9172 #define OPAMP1_CSR_PGAGAIN_Pos            (4U)
9173 #define OPAMP1_CSR_PGAGAIN_Msk            (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */
9174 #define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
9175 #define OPAMP1_CSR_PGAGAIN_0              (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */
9176 #define OPAMP1_CSR_PGAGAIN_1              (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */
9177 
9178 #define OPAMP1_CSR_VMSEL_Pos              (8U)
9179 #define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000300 */
9180 #define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
9181 #define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000100 */
9182 #define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000200 */
9183 
9184 #define OPAMP1_CSR_VPSEL_Pos              (10U)
9185 #define OPAMP1_CSR_VPSEL_Msk              (0x1UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x00000400 */
9186 #define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
9187 #define OPAMP1_CSR_CALON_Pos              (12U)
9188 #define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00001000 */
9189 #define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
9190 #define OPAMP1_CSR_CALSEL_Pos             (13U)
9191 #define OPAMP1_CSR_CALSEL_Msk             (0x1UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00002000 */
9192 #define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
9193 #define OPAMP1_CSR_USERTRIM_Pos           (14U)
9194 #define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00004000 */
9195 #define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
9196 #define OPAMP1_CSR_CALOUT_Pos             (15U)
9197 #define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x00008000 */
9198 #define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
9199 
9200 #define OPAMP1_CSR_OPARANGE_Pos           (31U)
9201 #define OPAMP1_CSR_OPARANGE_Msk           (0x1UL << OPAMP1_CSR_OPARANGE_Pos)   /*!< 0x80000000 */
9202 #define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
9203 
9204 /*******************  Bit definition for OPAMP_OTR register  ******************/
9205 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
9206 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
9207 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
9208 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
9209 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
9210 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
9211 
9212 /*******************  Bit definition for OPAMP1_OTR register  ******************/
9213 #define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
9214 #define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
9215 #define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
9216 #define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
9217 #define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
9218 #define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
9219 
9220 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
9221 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)
9222 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
9223 #define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
9224 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)
9225 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
9226 #define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
9227 
9228 /*******************  Bit definition for OPAMP1_LPOTR register  ****************/
9229 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)
9230 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
9231 #define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
9232 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)
9233 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
9234 #define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
9235 
9236 /******************************************************************************/
9237 /*                                                                            */
9238 /*                          Touch Sensing Controller (TSC)                    */
9239 /*                                                                            */
9240 /******************************************************************************/
9241 /*******************  Bit definition for TSC_CR register  *********************/
9242 #define TSC_CR_TSCE_Pos          (0U)
9243 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
9244 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
9245 #define TSC_CR_START_Pos         (1U)
9246 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
9247 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
9248 #define TSC_CR_AM_Pos            (2U)
9249 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
9250 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
9251 #define TSC_CR_SYNCPOL_Pos       (3U)
9252 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
9253 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
9254 #define TSC_CR_IODEF_Pos         (4U)
9255 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
9256 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
9257 
9258 #define TSC_CR_MCV_Pos           (5U)
9259 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
9260 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
9261 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
9262 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
9263 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */
9264 
9265 #define TSC_CR_PGPSC_Pos         (12U)
9266 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
9267 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
9268 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
9269 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
9270 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */
9271 
9272 #define TSC_CR_SSPSC_Pos         (15U)
9273 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
9274 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
9275 #define TSC_CR_SSE_Pos           (16U)
9276 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
9277 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
9278 
9279 #define TSC_CR_SSD_Pos           (17U)
9280 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
9281 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
9282 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
9283 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
9284 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
9285 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
9286 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
9287 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
9288 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */
9289 
9290 #define TSC_CR_CTPL_Pos          (24U)
9291 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
9292 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
9293 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
9294 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
9295 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
9296 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */
9297 
9298 #define TSC_CR_CTPH_Pos          (28U)
9299 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
9300 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
9301 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
9302 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
9303 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
9304 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */
9305 
9306 /*******************  Bit definition for TSC_IER register  ********************/
9307 #define TSC_IER_EOAIE_Pos        (0U)
9308 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
9309 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
9310 #define TSC_IER_MCEIE_Pos        (1U)
9311 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
9312 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
9313 
9314 /*******************  Bit definition for TSC_ICR register  ********************/
9315 #define TSC_ICR_EOAIC_Pos        (0U)
9316 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
9317 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
9318 #define TSC_ICR_MCEIC_Pos        (1U)
9319 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
9320 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
9321 
9322 /*******************  Bit definition for TSC_ISR register  ********************/
9323 #define TSC_ISR_EOAF_Pos         (0U)
9324 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
9325 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
9326 #define TSC_ISR_MCEF_Pos         (1U)
9327 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
9328 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
9329 
9330 /*******************  Bit definition for TSC_IOHCR register  ******************/
9331 #define TSC_IOHCR_G1_IO1_Pos     (0U)
9332 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
9333 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
9334 #define TSC_IOHCR_G1_IO2_Pos     (1U)
9335 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
9336 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
9337 #define TSC_IOHCR_G1_IO3_Pos     (2U)
9338 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
9339 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
9340 #define TSC_IOHCR_G1_IO4_Pos     (3U)
9341 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
9342 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
9343 #define TSC_IOHCR_G2_IO1_Pos     (4U)
9344 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
9345 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
9346 #define TSC_IOHCR_G2_IO2_Pos     (5U)
9347 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
9348 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
9349 #define TSC_IOHCR_G2_IO3_Pos     (6U)
9350 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
9351 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
9352 #define TSC_IOHCR_G2_IO4_Pos     (7U)
9353 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
9354 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
9355 #define TSC_IOHCR_G3_IO1_Pos     (8U)
9356 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
9357 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
9358 #define TSC_IOHCR_G3_IO2_Pos     (9U)
9359 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
9360 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
9361 #define TSC_IOHCR_G3_IO3_Pos     (10U)
9362 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
9363 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
9364 #define TSC_IOHCR_G3_IO4_Pos     (11U)
9365 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
9366 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
9367 #define TSC_IOHCR_G4_IO1_Pos     (12U)
9368 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
9369 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
9370 #define TSC_IOHCR_G4_IO2_Pos     (13U)
9371 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
9372 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
9373 #define TSC_IOHCR_G4_IO3_Pos     (14U)
9374 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
9375 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
9376 #define TSC_IOHCR_G4_IO4_Pos     (15U)
9377 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
9378 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
9379 
9380 /*******************  Bit definition for TSC_IOASCR register  *****************/
9381 #define TSC_IOASCR_G1_IO1_Pos    (0U)
9382 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
9383 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
9384 #define TSC_IOASCR_G1_IO2_Pos    (1U)
9385 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
9386 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
9387 #define TSC_IOASCR_G1_IO3_Pos    (2U)
9388 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
9389 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
9390 #define TSC_IOASCR_G1_IO4_Pos    (3U)
9391 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
9392 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
9393 #define TSC_IOASCR_G2_IO1_Pos    (4U)
9394 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
9395 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
9396 #define TSC_IOASCR_G2_IO2_Pos    (5U)
9397 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
9398 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
9399 #define TSC_IOASCR_G2_IO3_Pos    (6U)
9400 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
9401 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
9402 #define TSC_IOASCR_G2_IO4_Pos    (7U)
9403 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
9404 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
9405 #define TSC_IOASCR_G3_IO1_Pos    (8U)
9406 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
9407 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
9408 #define TSC_IOASCR_G3_IO2_Pos    (9U)
9409 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
9410 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
9411 #define TSC_IOASCR_G3_IO3_Pos    (10U)
9412 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
9413 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
9414 #define TSC_IOASCR_G3_IO4_Pos    (11U)
9415 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
9416 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
9417 #define TSC_IOASCR_G4_IO1_Pos    (12U)
9418 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
9419 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
9420 #define TSC_IOASCR_G4_IO2_Pos    (13U)
9421 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
9422 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
9423 #define TSC_IOASCR_G4_IO3_Pos    (14U)
9424 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
9425 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
9426 #define TSC_IOASCR_G4_IO4_Pos    (15U)
9427 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
9428 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
9429 
9430 /*******************  Bit definition for TSC_IOSCR register  ******************/
9431 #define TSC_IOSCR_G1_IO1_Pos     (0U)
9432 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
9433 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
9434 #define TSC_IOSCR_G1_IO2_Pos     (1U)
9435 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
9436 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
9437 #define TSC_IOSCR_G1_IO3_Pos     (2U)
9438 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
9439 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
9440 #define TSC_IOSCR_G1_IO4_Pos     (3U)
9441 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
9442 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
9443 #define TSC_IOSCR_G2_IO1_Pos     (4U)
9444 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
9445 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
9446 #define TSC_IOSCR_G2_IO2_Pos     (5U)
9447 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
9448 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
9449 #define TSC_IOSCR_G2_IO3_Pos     (6U)
9450 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
9451 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
9452 #define TSC_IOSCR_G2_IO4_Pos     (7U)
9453 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
9454 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
9455 #define TSC_IOSCR_G3_IO1_Pos     (8U)
9456 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
9457 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
9458 #define TSC_IOSCR_G3_IO2_Pos     (9U)
9459 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
9460 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
9461 #define TSC_IOSCR_G3_IO3_Pos     (10U)
9462 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
9463 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
9464 #define TSC_IOSCR_G3_IO4_Pos     (11U)
9465 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
9466 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
9467 #define TSC_IOSCR_G4_IO1_Pos     (12U)
9468 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
9469 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
9470 #define TSC_IOSCR_G4_IO2_Pos     (13U)
9471 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
9472 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
9473 #define TSC_IOSCR_G4_IO3_Pos     (14U)
9474 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
9475 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
9476 #define TSC_IOSCR_G4_IO4_Pos     (15U)
9477 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
9478 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
9479 
9480 /*******************  Bit definition for TSC_IOCCR register  ******************/
9481 #define TSC_IOCCR_G1_IO1_Pos     (0U)
9482 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
9483 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
9484 #define TSC_IOCCR_G1_IO2_Pos     (1U)
9485 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
9486 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
9487 #define TSC_IOCCR_G1_IO3_Pos     (2U)
9488 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
9489 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
9490 #define TSC_IOCCR_G1_IO4_Pos     (3U)
9491 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
9492 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
9493 #define TSC_IOCCR_G2_IO1_Pos     (4U)
9494 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
9495 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
9496 #define TSC_IOCCR_G2_IO2_Pos     (5U)
9497 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
9498 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
9499 #define TSC_IOCCR_G2_IO3_Pos     (6U)
9500 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
9501 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
9502 #define TSC_IOCCR_G2_IO4_Pos     (7U)
9503 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
9504 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
9505 #define TSC_IOCCR_G3_IO1_Pos     (8U)
9506 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
9507 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
9508 #define TSC_IOCCR_G3_IO2_Pos     (9U)
9509 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
9510 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
9511 #define TSC_IOCCR_G3_IO3_Pos     (10U)
9512 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
9513 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
9514 #define TSC_IOCCR_G3_IO4_Pos     (11U)
9515 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
9516 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
9517 #define TSC_IOCCR_G4_IO1_Pos     (12U)
9518 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
9519 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
9520 #define TSC_IOCCR_G4_IO2_Pos     (13U)
9521 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
9522 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
9523 #define TSC_IOCCR_G4_IO3_Pos     (14U)
9524 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
9525 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
9526 #define TSC_IOCCR_G4_IO4_Pos     (15U)
9527 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
9528 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
9529 
9530 /*******************  Bit definition for TSC_IOGCSR register  *****************/
9531 #define TSC_IOGCSR_G1E_Pos       (0U)
9532 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
9533 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
9534 #define TSC_IOGCSR_G2E_Pos       (1U)
9535 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
9536 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
9537 #define TSC_IOGCSR_G3E_Pos       (2U)
9538 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
9539 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
9540 #define TSC_IOGCSR_G4E_Pos       (3U)
9541 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
9542 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
9543 #define TSC_IOGCSR_G1S_Pos       (16U)
9544 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
9545 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
9546 #define TSC_IOGCSR_G2S_Pos       (17U)
9547 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
9548 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
9549 #define TSC_IOGCSR_G3S_Pos       (18U)
9550 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
9551 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
9552 #define TSC_IOGCSR_G4S_Pos       (19U)
9553 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
9554 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
9555 
9556 /*******************  Bit definition for TSC_IOGXCR register  *****************/
9557 #define TSC_IOGXCR_CNT_Pos       (0U)
9558 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
9559 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
9560 
9561 /******************************************************************************/
9562 /*                                                                            */
9563 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
9564 /*                                                                            */
9565 /******************************************************************************/
9566 
9567 /*
9568 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
9569 */
9570 #define USART_TCBGT_SUPPORT
9571 
9572 /******************  Bit definition for USART_CR1 register  *******************/
9573 #define USART_CR1_UE_Pos              (0U)
9574 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)              /*!< 0x00000001 */
9575 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
9576 #define USART_CR1_UESM_Pos            (1U)
9577 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)            /*!< 0x00000002 */
9578 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
9579 #define USART_CR1_RE_Pos              (2U)
9580 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)              /*!< 0x00000004 */
9581 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
9582 #define USART_CR1_TE_Pos              (3U)
9583 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)              /*!< 0x00000008 */
9584 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
9585 #define USART_CR1_IDLEIE_Pos          (4U)
9586 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)          /*!< 0x00000010 */
9587 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
9588 #define USART_CR1_RXNEIE_Pos          (5U)
9589 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)          /*!< 0x00000020 */
9590 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
9591 #define USART_CR1_TCIE_Pos            (6U)
9592 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)            /*!< 0x00000040 */
9593 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
9594 #define USART_CR1_TXEIE_Pos           (7U)
9595 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)           /*!< 0x00000080 */
9596 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
9597 #define USART_CR1_PEIE_Pos            (8U)
9598 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)            /*!< 0x00000100 */
9599 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
9600 #define USART_CR1_PS_Pos              (9U)
9601 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)              /*!< 0x00000200 */
9602 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
9603 #define USART_CR1_PCE_Pos             (10U)
9604 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)             /*!< 0x00000400 */
9605 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
9606 #define USART_CR1_WAKE_Pos            (11U)
9607 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)            /*!< 0x00000800 */
9608 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
9609 #define USART_CR1_M_Pos               (12U)
9610 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)           /*!< 0x10001000 */
9611 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
9612 #define USART_CR1_M0_Pos              (12U)
9613 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)              /*!< 0x00001000 */
9614 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
9615 #define USART_CR1_MME_Pos             (13U)
9616 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)             /*!< 0x00002000 */
9617 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
9618 #define USART_CR1_CMIE_Pos            (14U)
9619 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)            /*!< 0x00004000 */
9620 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
9621 #define USART_CR1_OVER8_Pos           (15U)
9622 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)           /*!< 0x00008000 */
9623 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
9624 #define USART_CR1_DEDT_Pos            (16U)
9625 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)           /*!< 0x001F0000 */
9626 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
9627 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)           /*!< 0x00010000 */
9628 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)           /*!< 0x00020000 */
9629 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)           /*!< 0x00040000 */
9630 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)           /*!< 0x00080000 */
9631 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)           /*!< 0x00100000 */
9632 #define USART_CR1_DEAT_Pos            (21U)
9633 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)           /*!< 0x03E00000 */
9634 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
9635 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)           /*!< 0x00200000 */
9636 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)           /*!< 0x00400000 */
9637 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)           /*!< 0x00800000 */
9638 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)           /*!< 0x01000000 */
9639 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)           /*!< 0x02000000 */
9640 #define USART_CR1_RTOIE_Pos           (26U)
9641 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)           /*!< 0x04000000 */
9642 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
9643 #define USART_CR1_EOBIE_Pos           (27U)
9644 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)           /*!< 0x08000000 */
9645 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
9646 #define USART_CR1_M1_Pos              (28U)
9647 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)              /*!< 0x10000000 */
9648 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
9649 
9650 /******************  Bit definition for USART_CR2 register  *******************/
9651 #define USART_CR2_ADDM7_Pos           (4U)
9652 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)           /*!< 0x00000010 */
9653 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
9654 #define USART_CR2_LBDL_Pos            (5U)
9655 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)            /*!< 0x00000020 */
9656 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
9657 #define USART_CR2_LBDIE_Pos           (6U)
9658 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)           /*!< 0x00000040 */
9659 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
9660 #define USART_CR2_LBCL_Pos            (8U)
9661 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)            /*!< 0x00000100 */
9662 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
9663 #define USART_CR2_CPHA_Pos            (9U)
9664 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)            /*!< 0x00000200 */
9665 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
9666 #define USART_CR2_CPOL_Pos            (10U)
9667 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)            /*!< 0x00000400 */
9668 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
9669 #define USART_CR2_CLKEN_Pos           (11U)
9670 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)           /*!< 0x00000800 */
9671 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
9672 #define USART_CR2_STOP_Pos            (12U)
9673 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)            /*!< 0x00003000 */
9674 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
9675 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)            /*!< 0x00001000 */
9676 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)            /*!< 0x00002000 */
9677 #define USART_CR2_LINEN_Pos           (14U)
9678 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)           /*!< 0x00004000 */
9679 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
9680 #define USART_CR2_SWAP_Pos            (15U)
9681 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)            /*!< 0x00008000 */
9682 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
9683 #define USART_CR2_RXINV_Pos           (16U)
9684 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)           /*!< 0x00010000 */
9685 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
9686 #define USART_CR2_TXINV_Pos           (17U)
9687 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)           /*!< 0x00020000 */
9688 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
9689 #define USART_CR2_DATAINV_Pos         (18U)
9690 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)         /*!< 0x00040000 */
9691 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
9692 #define USART_CR2_MSBFIRST_Pos        (19U)
9693 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)        /*!< 0x00080000 */
9694 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
9695 #define USART_CR2_ABREN_Pos           (20U)
9696 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)           /*!< 0x00100000 */
9697 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
9698 #define USART_CR2_ABRMODE_Pos         (21U)
9699 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00600000 */
9700 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
9701 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00200000 */
9702 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00400000 */
9703 #define USART_CR2_RTOEN_Pos           (23U)
9704 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)           /*!< 0x00800000 */
9705 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
9706 #define USART_CR2_ADD_Pos             (24U)
9707 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)            /*!< 0xFF000000 */
9708 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
9709 
9710 /******************  Bit definition for USART_CR3 register  *******************/
9711 #define USART_CR3_EIE_Pos             (0U)
9712 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)             /*!< 0x00000001 */
9713 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
9714 #define USART_CR3_IREN_Pos            (1U)
9715 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)            /*!< 0x00000002 */
9716 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
9717 #define USART_CR3_IRLP_Pos            (2U)
9718 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)            /*!< 0x00000004 */
9719 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
9720 #define USART_CR3_HDSEL_Pos           (3U)
9721 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)           /*!< 0x00000008 */
9722 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
9723 #define USART_CR3_NACK_Pos            (4U)
9724 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)            /*!< 0x00000010 */
9725 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
9726 #define USART_CR3_SCEN_Pos            (5U)
9727 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)            /*!< 0x00000020 */
9728 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
9729 #define USART_CR3_DMAR_Pos            (6U)
9730 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)            /*!< 0x00000040 */
9731 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
9732 #define USART_CR3_DMAT_Pos            (7U)
9733 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)            /*!< 0x00000080 */
9734 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
9735 #define USART_CR3_RTSE_Pos            (8U)
9736 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)            /*!< 0x00000100 */
9737 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
9738 #define USART_CR3_CTSE_Pos            (9U)
9739 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)            /*!< 0x00000200 */
9740 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
9741 #define USART_CR3_CTSIE_Pos           (10U)
9742 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)           /*!< 0x00000400 */
9743 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
9744 #define USART_CR3_ONEBIT_Pos          (11U)
9745 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)          /*!< 0x00000800 */
9746 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
9747 #define USART_CR3_OVRDIS_Pos          (12U)
9748 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)          /*!< 0x00001000 */
9749 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
9750 #define USART_CR3_DDRE_Pos            (13U)
9751 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)            /*!< 0x00002000 */
9752 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
9753 #define USART_CR3_DEM_Pos             (14U)
9754 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)             /*!< 0x00004000 */
9755 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
9756 #define USART_CR3_DEP_Pos             (15U)
9757 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)             /*!< 0x00008000 */
9758 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
9759 #define USART_CR3_SCARCNT_Pos         (17U)
9760 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)         /*!< 0x000E0000 */
9761 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
9762 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00020000 */
9763 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00040000 */
9764 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00080000 */
9765 #define USART_CR3_WUS_Pos             (20U)
9766 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)             /*!< 0x00300000 */
9767 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
9768 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)             /*!< 0x00100000 */
9769 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)             /*!< 0x00200000 */
9770 #define USART_CR3_WUFIE_Pos           (22U)
9771 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)           /*!< 0x00400000 */
9772 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
9773 #define USART_CR3_UCESM_Pos           (23U)
9774 #define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)           /*!< 0x02000000 */
9775 #define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< USART Clock enable in Stop mode */
9776 #define USART_CR3_TCBGTIE_Pos         (24U)
9777 #define USART_CR3_TCBGTIE_Msk         (0x1UL << USART_CR3_TCBGTIE_Pos)         /*!< 0x01000000 */
9778 #define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
9779 
9780 /******************  Bit definition for USART_BRR register  *******************/
9781 #define USART_BRR_DIV_FRACTION_Pos    (0U)
9782 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)    /*!< 0x0000000F */
9783 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
9784 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
9785 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)  /*!< 0x0000FFF0 */
9786 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
9787 
9788 /******************  Bit definition for USART_GTPR register  ******************/
9789 #define USART_GTPR_PSC_Pos            (0U)
9790 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)           /*!< 0x000000FF */
9791 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
9792 #define USART_GTPR_GT_Pos             (8U)
9793 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)            /*!< 0x0000FF00 */
9794 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
9795 
9796 /*******************  Bit definition for USART_RTOR register  *****************/
9797 #define USART_RTOR_RTO_Pos            (0U)
9798 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)       /*!< 0x00FFFFFF */
9799 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
9800 #define USART_RTOR_BLEN_Pos           (24U)
9801 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)          /*!< 0xFF000000 */
9802 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
9803 
9804 /*******************  Bit definition for USART_RQR register  ******************/
9805 #define USART_RQR_ABRRQ_Pos           (0U)
9806 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)           /*!< 0x00000001 */
9807 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
9808 #define USART_RQR_SBKRQ_Pos           (1U)
9809 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)           /*!< 0x00000002 */
9810 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
9811 #define USART_RQR_MMRQ_Pos            (2U)
9812 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)            /*!< 0x00000004 */
9813 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
9814 #define USART_RQR_RXFRQ_Pos           (3U)
9815 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)           /*!< 0x00000008 */
9816 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
9817 #define USART_RQR_TXFRQ_Pos           (4U)
9818 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)           /*!< 0x00000010 */
9819 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
9820 
9821 /*******************  Bit definition for USART_ISR register  ******************/
9822 #define USART_ISR_PE_Pos              (0U)
9823 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)              /*!< 0x00000001 */
9824 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
9825 #define USART_ISR_FE_Pos              (1U)
9826 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)              /*!< 0x00000002 */
9827 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
9828 #define USART_ISR_NE_Pos              (2U)
9829 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)              /*!< 0x00000004 */
9830 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */
9831 #define USART_ISR_ORE_Pos             (3U)
9832 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)             /*!< 0x00000008 */
9833 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
9834 #define USART_ISR_IDLE_Pos            (4U)
9835 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)            /*!< 0x00000010 */
9836 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
9837 #define USART_ISR_RXNE_Pos            (5U)
9838 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)            /*!< 0x00000020 */
9839 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
9840 #define USART_ISR_TC_Pos              (6U)
9841 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)              /*!< 0x00000040 */
9842 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
9843 #define USART_ISR_TXE_Pos             (7U)
9844 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)             /*!< 0x00000080 */
9845 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
9846 #define USART_ISR_LBDF_Pos            (8U)
9847 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)            /*!< 0x00000100 */
9848 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
9849 #define USART_ISR_CTSIF_Pos           (9U)
9850 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)           /*!< 0x00000200 */
9851 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
9852 #define USART_ISR_CTS_Pos             (10U)
9853 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)             /*!< 0x00000400 */
9854 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
9855 #define USART_ISR_RTOF_Pos            (11U)
9856 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)            /*!< 0x00000800 */
9857 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
9858 #define USART_ISR_EOBF_Pos            (12U)
9859 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)            /*!< 0x00001000 */
9860 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
9861 #define USART_ISR_ABRE_Pos            (14U)
9862 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)            /*!< 0x00004000 */
9863 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
9864 #define USART_ISR_ABRF_Pos            (15U)
9865 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)            /*!< 0x00008000 */
9866 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
9867 #define USART_ISR_BUSY_Pos            (16U)
9868 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)            /*!< 0x00010000 */
9869 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
9870 #define USART_ISR_CMF_Pos             (17U)
9871 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)             /*!< 0x00020000 */
9872 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
9873 #define USART_ISR_SBKF_Pos            (18U)
9874 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)            /*!< 0x00040000 */
9875 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
9876 #define USART_ISR_RWU_Pos             (19U)
9877 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)             /*!< 0x00080000 */
9878 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
9879 #define USART_ISR_WUF_Pos             (20U)
9880 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)             /*!< 0x00100000 */
9881 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
9882 #define USART_ISR_TEACK_Pos           (21U)
9883 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)           /*!< 0x00200000 */
9884 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
9885 #define USART_ISR_REACK_Pos           (22U)
9886 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)           /*!< 0x00400000 */
9887 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
9888 #define USART_ISR_TCBGT_Pos           (25U)
9889 #define USART_ISR_TCBGT_Msk           (0x1UL << USART_ISR_TCBGT_Pos)           /*!< 0x02000000 */
9890 #define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
9891 
9892 /*******************  Bit definition for USART_ICR register  ******************/
9893 #define USART_ICR_PECF_Pos            (0U)
9894 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)            /*!< 0x00000001 */
9895 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
9896 #define USART_ICR_FECF_Pos            (1U)
9897 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)            /*!< 0x00000002 */
9898 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
9899 #define USART_ICR_NECF_Pos            (2U)
9900 #define USART_ICR_NECF_Msk            (0x1UL << USART_ICR_NECF_Pos)            /*!< 0x00000004 */
9901 #define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */
9902 #define USART_ICR_ORECF_Pos           (3U)
9903 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)           /*!< 0x00000008 */
9904 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
9905 #define USART_ICR_IDLECF_Pos          (4U)
9906 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)          /*!< 0x00000010 */
9907 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
9908 #define USART_ICR_TCCF_Pos            (6U)
9909 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)            /*!< 0x00000040 */
9910 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
9911 #define USART_ICR_TCBGTCF_Pos         (7U)
9912 #define USART_ICR_TCBGTCF_Msk         (0x1UL << USART_ICR_TCBGTCF_Pos)         /*!< 0x00000080 */
9913 #define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
9914 #define USART_ICR_LBDCF_Pos           (8U)
9915 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)           /*!< 0x00000100 */
9916 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
9917 #define USART_ICR_CTSCF_Pos           (9U)
9918 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)           /*!< 0x00000200 */
9919 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
9920 #define USART_ICR_RTOCF_Pos           (11U)
9921 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)           /*!< 0x00000800 */
9922 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
9923 #define USART_ICR_EOBCF_Pos           (12U)
9924 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)           /*!< 0x00001000 */
9925 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
9926 #define USART_ICR_CMCF_Pos            (17U)
9927 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)            /*!< 0x00020000 */
9928 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
9929 #define USART_ICR_WUCF_Pos            (20U)
9930 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)            /*!< 0x00100000 */
9931 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
9932 
9933 /* Legacy defines */
9934 #define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos
9935 #define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk
9936 #define USART_ICR_NCF                 USART_ICR_NECF
9937 
9938 /*******************  Bit definition for USART_RDR register  ******************/
9939 #define USART_RDR_RDR_Pos             (0U)
9940 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
9941 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
9942 
9943 /*******************  Bit definition for USART_TDR register  ******************/
9944 #define USART_TDR_TDR_Pos             (0U)
9945 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
9946 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
9947 
9948 
9949 /******************************************************************************/
9950 /*                                                                            */
9951 /*                            Window WATCHDOG                                 */
9952 /*                                                                            */
9953 /******************************************************************************/
9954 /*******************  Bit definition for WWDG_CR register  ********************/
9955 #define WWDG_CR_T_Pos           (0U)
9956 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
9957 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
9958 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
9959 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
9960 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
9961 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
9962 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
9963 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
9964 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
9965 
9966 #define WWDG_CR_WDGA_Pos        (7U)
9967 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
9968 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
9969 
9970 /*******************  Bit definition for WWDG_CFR register  *******************/
9971 #define WWDG_CFR_W_Pos          (0U)
9972 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
9973 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
9974 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
9975 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
9976 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
9977 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
9978 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
9979 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
9980 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
9981 
9982 #define WWDG_CFR_WDGTB_Pos      (7U)
9983 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000180 */
9984 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
9985 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000080 */
9986 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000100 */
9987 
9988 #define WWDG_CFR_EWI_Pos        (9U)
9989 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
9990 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
9991 
9992 /*******************  Bit definition for WWDG_SR register  ********************/
9993 #define WWDG_SR_EWIF_Pos        (0U)
9994 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
9995 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
9996 
9997 
9998 /******************************************************************************/
9999 /*                                                                            */
10000 /*                                 Debug MCU                                  */
10001 /*                                                                            */
10002 /******************************************************************************/
10003 /********************  Bit definition for DBGMCU_IDCODE register  *************/
10004 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
10005 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
10006 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
10007 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
10008 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
10009 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
10010 
10011 /********************  Bit definition for DBGMCU_CR register  *****************/
10012 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
10013 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
10014 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
10015 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
10016 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
10017 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
10018 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
10019 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
10020 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
10021 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
10022 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
10023 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
10024 
10025 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
10026 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
10027 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
10028 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
10029 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
10030 
10031 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
10032 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
10033 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
10034 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
10035 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
10036 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
10037 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
10038 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
10039 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
10040 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
10041 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
10042 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
10043 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
10044 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
10045 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
10046 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
10047 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
10048 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
10049 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
10050 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
10051 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
10052 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
10053 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)
10054 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
10055 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
10056 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
10057 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
10058 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
10059 
10060 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
10061 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)
10062 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
10063 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
10064 
10065 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
10066 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
10067 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
10068 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
10069 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
10070 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
10071 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
10072 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
10073 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
10074 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
10075 
10076 /******************************************************************************/
10077 /*                                                                            */
10078 /*                         USB Device FS Endpoint registers                   */
10079 /*                                                                            */
10080 /******************************************************************************/
10081 #define USB_EP0R                                 USB_BASE                  /*!< endpoint 0 register address */
10082 #define USB_EP1R                                 (USB_BASE + 0x00000004UL)   /*!< endpoint 1 register address */
10083 #define USB_EP2R                                 (USB_BASE + 0x00000008UL)   /*!< endpoint 2 register address */
10084 #define USB_EP3R                                 (USB_BASE + 0x0000000CUL)   /*!< endpoint 3 register address */
10085 #define USB_EP4R                                 (USB_BASE + 0x00000010UL)   /*!< endpoint 4 register address */
10086 #define USB_EP5R                                 (USB_BASE + 0x00000014UL)   /*!< endpoint 5 register address */
10087 #define USB_EP6R                                 (USB_BASE + 0x00000018UL)   /*!< endpoint 6 register address */
10088 #define USB_EP7R                                 (USB_BASE + 0x0000001CUL)   /*!< endpoint 7 register address */
10089 
10090 /* bit positions */
10091 #define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
10092 #define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
10093 #define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
10094 #define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
10095 #define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
10096 #define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
10097 #define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
10098 #define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
10099 #define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
10100 #define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
10101 
10102 /* EndPoint REGister MASK (no toggle fields) */
10103 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
10104                                                                          /*!< EP_TYPE[1:0] EndPoint TYPE */
10105 #define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
10106 #define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
10107 #define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
10108 #define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
10109 #define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
10110 #define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
10111 
10112 #define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
10113                                                                          /*!< STAT_TX[1:0] STATus for TX transfer */
10114 #define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
10115 #define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
10116 #define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
10117 #define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
10118 #define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
10119 #define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
10120 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
10121                                                                          /*!< STAT_RX[1:0] STATus for RX transfer */
10122 #define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
10123 #define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
10124 #define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
10125 #define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
10126 #define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
10127 #define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
10128 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
10129 
10130 /******************************************************************************/
10131 /*                                                                            */
10132 /*                         USB Device FS General registers                    */
10133 /*                                                                            */
10134 /******************************************************************************/
10135 #define USB_CNTR                             (USB_BASE + 0x00000040UL)     /*!< Control register */
10136 #define USB_ISTR                             (USB_BASE + 0x00000044UL)     /*!< Interrupt status register */
10137 #define USB_FNR                              (USB_BASE + 0x00000048UL)     /*!< Frame number register */
10138 #define USB_DADDR                            (USB_BASE + 0x0000004CUL)     /*!< Device address register */
10139 #define USB_BTABLE                           (USB_BASE + 0x00000050UL)     /*!< Buffer Table address register */
10140 #define USB_LPMCSR                           (USB_BASE + 0x00000054UL)     /*!< LPM Control and Status register */
10141 #define USB_BCDR                             (USB_BASE + 0x00000058UL)     /*!< Battery Charging detector register*/
10142 
10143 /******************  Bits definition for USB_CNTR register  *******************/
10144 #define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
10145 #define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
10146 #define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
10147 #define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
10148 #define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
10149 #define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
10150 #define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
10151 #define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
10152 #define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
10153 #define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
10154 #define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
10155 #define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
10156 #define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
10157 #define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
10158 #define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
10159 
10160 /******************  Bits definition for USB_ISTR register  *******************/
10161 #define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
10162 #define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
10163 #define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
10164 #define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
10165 #define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
10166 #define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
10167 #define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
10168 #define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
10169 #define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
10170 #define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
10171 #define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
10172 
10173 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
10174 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
10175 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
10176 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
10177 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
10178 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
10179 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
10180 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
10181 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
10182 
10183 /******************  Bits definition for USB_FNR register  ********************/
10184 #define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
10185 #define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
10186 #define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
10187 #define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
10188 #define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
10189 
10190 /******************  Bits definition for USB_DADDR register    ****************/
10191 #define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
10192 #define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
10193 #define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
10194 #define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
10195 #define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
10196 #define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
10197 #define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
10198 #define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
10199 
10200 #define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
10201 
10202 /******************  Bit definition for USB_BTABLE register  ******************/
10203 #define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
10204 
10205 /******************  Bits definition for USB_BCDR register  *******************/
10206 #define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
10207 #define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
10208 #define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */
10209 #define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */
10210 #define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */
10211 #define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */
10212 #define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */
10213 #define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */
10214 #define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */
10215 
10216 /*******************  Bit definition for LPMCSR register  *********************/
10217 #define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
10218 #define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
10219 #define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */
10220 #define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */
10221 
10222 /*!< Buffer descriptor table */
10223 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
10224 #define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)
10225 #define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
10226 #define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
10227 
10228 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
10229 #define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)
10230 #define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
10231 #define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
10232 
10233 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
10234 #define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)
10235 #define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
10236 #define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
10237 
10238 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
10239 #define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)
10240 #define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
10241 #define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
10242 
10243 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
10244 #define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)
10245 #define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
10246 #define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
10247 
10248 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
10249 #define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)
10250 #define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
10251 #define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
10252 
10253 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
10254 #define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)
10255 #define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
10256 #define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
10257 
10258 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
10259 #define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)
10260 #define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
10261 #define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
10262 
10263 /*----------------------------------------------------------------------------*/
10264 
10265 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
10266 #define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)
10267 #define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
10268 #define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
10269 
10270 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
10271 #define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)
10272 #define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
10273 #define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
10274 
10275 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
10276 #define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)
10277 #define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
10278 #define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
10279 
10280 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
10281 #define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)
10282 #define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
10283 #define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
10284 
10285 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
10286 #define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)
10287 #define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
10288 #define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
10289 
10290 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
10291 #define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)
10292 #define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
10293 #define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
10294 
10295 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
10296 #define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)
10297 #define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
10298 #define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
10299 
10300 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
10301 #define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)
10302 #define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
10303 #define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
10304 
10305 /*----------------------------------------------------------------------------*/
10306 
10307 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
10308 #define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 0 (low) */
10309 
10310 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
10311 #define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 0 (high) */
10312 
10313 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
10314 #define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 1 (low) */
10315 
10316 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
10317 #define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 1 (high) */
10318 
10319 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
10320 #define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 2 (low) */
10321 
10322 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
10323 #define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 2 (high) */
10324 
10325 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
10326 #define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 3 (low) */
10327 
10328 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
10329 #define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 3 (high) */
10330 
10331 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
10332 #define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 4 (low) */
10333 
10334 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
10335 #define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 4 (high) */
10336 
10337 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
10338 #define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 5 (low) */
10339 
10340 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
10341 #define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 5 (high) */
10342 
10343 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
10344 #define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 6 (low) */
10345 
10346 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
10347 #define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 6 (high) */
10348 
10349 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
10350 #define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 7 (low) */
10351 
10352 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
10353 #define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 7 (high) */
10354 
10355 /*----------------------------------------------------------------------------*/
10356 
10357 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
10358 #define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)
10359 #define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
10360 #define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
10361 
10362 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
10363 #define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)
10364 #define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
10365 #define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
10366 
10367 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
10368 #define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)
10369 #define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
10370 #define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
10371 
10372 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
10373 #define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)
10374 #define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
10375 #define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
10376 
10377 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
10378 #define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)
10379 #define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
10380 #define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
10381 
10382 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
10383 #define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)
10384 #define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
10385 #define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
10386 
10387 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
10388 #define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)
10389 #define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
10390 #define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
10391 
10392 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
10393 #define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)
10394 #define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
10395 #define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
10396 
10397 /*----------------------------------------------------------------------------*/
10398 
10399 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
10400 #define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)
10401 #define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
10402 #define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
10403 
10404 #define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)
10405 #define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10406 #define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10407 #define USB_COUNT0_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10408 #define USB_COUNT0_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10409 #define USB_COUNT0_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10410 #define USB_COUNT0_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10411 #define USB_COUNT0_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10412 
10413 #define USB_COUNT0_RX_BLSIZE_Pos                 (15U)
10414 #define USB_COUNT0_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
10415 #define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
10416 
10417 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
10418 #define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)
10419 #define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
10420 #define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
10421 
10422 #define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)
10423 #define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10424 #define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10425 #define USB_COUNT1_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10426 #define USB_COUNT1_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10427 #define USB_COUNT1_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10428 #define USB_COUNT1_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10429 #define USB_COUNT1_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10430 
10431 #define USB_COUNT1_RX_BLSIZE_Pos                 (15U)
10432 #define USB_COUNT1_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
10433 #define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
10434 
10435 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
10436 #define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)
10437 #define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
10438 #define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
10439 
10440 #define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)
10441 #define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10442 #define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10443 #define USB_COUNT2_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10444 #define USB_COUNT2_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10445 #define USB_COUNT2_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10446 #define USB_COUNT2_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10447 #define USB_COUNT2_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10448 
10449 #define USB_COUNT2_RX_BLSIZE_Pos                 (15U)
10450 #define USB_COUNT2_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
10451 #define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
10452 
10453 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
10454 #define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)
10455 #define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
10456 #define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
10457 
10458 #define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)
10459 #define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10460 #define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10461 #define USB_COUNT3_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10462 #define USB_COUNT3_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10463 #define USB_COUNT3_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10464 #define USB_COUNT3_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10465 #define USB_COUNT3_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10466 
10467 #define USB_COUNT3_RX_BLSIZE_Pos                 (15U)
10468 #define USB_COUNT3_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
10469 #define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
10470 
10471 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
10472 #define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)
10473 #define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
10474 #define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
10475 
10476 #define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)
10477 #define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10478 #define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10479 #define USB_COUNT4_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10480 #define USB_COUNT4_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10481 #define USB_COUNT4_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10482 #define USB_COUNT4_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10483 #define USB_COUNT4_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10484 
10485 #define USB_COUNT4_RX_BLSIZE_Pos                 (15U)
10486 #define USB_COUNT4_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
10487 #define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
10488 
10489 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
10490 #define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)
10491 #define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
10492 #define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
10493 
10494 #define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)
10495 #define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10496 #define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10497 #define USB_COUNT5_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10498 #define USB_COUNT5_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10499 #define USB_COUNT5_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10500 #define USB_COUNT5_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10501 #define USB_COUNT5_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10502 
10503 #define USB_COUNT5_RX_BLSIZE_Pos                 (15U)
10504 #define USB_COUNT5_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
10505 #define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
10506 
10507 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
10508 #define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)
10509 #define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
10510 #define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
10511 
10512 #define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)
10513 #define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10514 #define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10515 #define USB_COUNT6_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10516 #define USB_COUNT6_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10517 #define USB_COUNT6_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10518 #define USB_COUNT6_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10519 #define USB_COUNT6_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10520 
10521 #define USB_COUNT6_RX_BLSIZE_Pos                 (15U)
10522 #define USB_COUNT6_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
10523 #define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
10524 
10525 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
10526 #define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)
10527 #define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
10528 #define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
10529 
10530 #define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)
10531 #define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10532 #define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10533 #define USB_COUNT7_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10534 #define USB_COUNT7_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10535 #define USB_COUNT7_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10536 #define USB_COUNT7_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10537 #define USB_COUNT7_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10538 
10539 #define USB_COUNT7_RX_BLSIZE_Pos                 (15U)
10540 #define USB_COUNT7_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
10541 #define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
10542 
10543 /*----------------------------------------------------------------------------*/
10544 
10545 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
10546 #define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10547 
10548 #define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10549 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10550 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10551 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10552 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10553 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10554 
10555 #define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10556 
10557 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
10558 #define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10559 
10560 #define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10561 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 1 */
10562 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10563 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10564 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10565 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10566 
10567 #define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10568 
10569 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
10570 #define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10571 
10572 #define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10573 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10574 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10575 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10576 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10577 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10578 
10579 #define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10580 
10581 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
10582 #define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10583 
10584 #define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10585 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10586 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10587 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10588 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10589 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10590 
10591 #define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10592 
10593 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
10594 #define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10595 
10596 #define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10597 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10598 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10599 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10600 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10601 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10602 
10603 #define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10604 
10605 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
10606 #define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10607 
10608 #define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10609 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10610 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10611 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10612 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10613 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10614 
10615 #define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10616 
10617 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
10618 #define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10619 
10620 #define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10621 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10622 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10623 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10624 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10625 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10626 
10627 #define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10628 
10629 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
10630 #define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10631 
10632 #define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10633 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10634 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10635 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10636 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10637 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10638 
10639 #define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10640 
10641 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
10642 #define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10643 
10644 #define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10645 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10646 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10647 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10648 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10649 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10650 
10651 #define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10652 
10653 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
10654 #define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10655 
10656 #define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10657 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10658 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10659 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10660 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10661 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10662 
10663 #define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10664 
10665 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
10666 #define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10667 
10668 #define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10669 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10670 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10671 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10672 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10673 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10674 
10675 #define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10676 
10677 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
10678 #define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10679 
10680 #define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10681 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10682 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10683 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10684 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10685 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10686 
10687 #define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10688 
10689 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
10690 #define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10691 
10692 #define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10693 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10694 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10695 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10696 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10697 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10698 
10699 #define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10700 
10701 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
10702 #define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10703 
10704 #define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10705 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10706 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10707 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10708 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10709 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10710 
10711 #define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10712 
10713 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
10714 #define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10715 
10716 #define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10717 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10718 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10719 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10720 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10721 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10722 
10723 #define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10724 
10725 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
10726 #define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10727 
10728 #define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10729 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10730 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10731 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10732 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10733 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10734 
10735 #define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10736 
10737 
10738 /**
10739   * @}
10740   */
10741 
10742 /**
10743   * @}
10744   */
10745 
10746 /** @addtogroup Exported_macros
10747   * @{
10748   */
10749 
10750 /******************************* ADC Instances ********************************/
10751 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
10752                                        ((INSTANCE) == ADC2))
10753 
10754 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10755 
10756 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
10757 
10758 /******************************* AES Instances ********************************/
10759 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
10760 
10761 /******************************** CAN Instances ******************************/
10762 
10763 /******************************** COMP Instances ******************************/
10764 #define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
10765 
10766 /******************************* CRC Instances ********************************/
10767 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10768 
10769 
10770 /******************************** DMA Instances *******************************/
10771 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
10772                                        ((INSTANCE) == DMA1_Channel2) || \
10773                                        ((INSTANCE) == DMA1_Channel3) || \
10774                                        ((INSTANCE) == DMA1_Channel4) || \
10775                                        ((INSTANCE) == DMA1_Channel5) || \
10776                                        ((INSTANCE) == DMA1_Channel6) || \
10777                                        ((INSTANCE) == DMA1_Channel7) || \
10778                                        ((INSTANCE) == DMA2_Channel1) || \
10779                                        ((INSTANCE) == DMA2_Channel2) || \
10780                                        ((INSTANCE) == DMA2_Channel3) || \
10781                                        ((INSTANCE) == DMA2_Channel4) || \
10782                                        ((INSTANCE) == DMA2_Channel5) || \
10783                                        ((INSTANCE) == DMA2_Channel6) || \
10784                                        ((INSTANCE) == DMA2_Channel7))
10785 
10786 /******************************* GPIO Instances *******************************/
10787 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10788                                         ((INSTANCE) == GPIOB) || \
10789                                         ((INSTANCE) == GPIOC) || \
10790                                         ((INSTANCE) == GPIOD) || \
10791                                         ((INSTANCE) == GPIOH))
10792 
10793 /******************************* GPIO AF Instances ****************************/
10794 /* On L4, all GPIO Bank support AF */
10795 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
10796 
10797 /**************************** GPIO Lock Instances *****************************/
10798 /* On L4, all GPIO Bank support the Lock mechanism */
10799 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
10800 
10801 /******************************** I2C Instances *******************************/
10802 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10803                                        ((INSTANCE) == I2C2) || \
10804                                        ((INSTANCE) == I2C3))
10805 
10806 /****************** I2C Instances : wakeup capability from stop modes *********/
10807 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
10808 
10809 /****************************** OPAMP Instances *******************************/
10810 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
10811 
10812 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
10813 
10814 /******************************* QSPI Instances *******************************/
10815 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
10816 
10817 /******************************* RNG Instances ********************************/
10818 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
10819 
10820 /****************************** RTC Instances *********************************/
10821 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
10822 
10823 /******************************** SAI Instances *******************************/
10824 
10825 /****************************** SMBUS Instances *******************************/
10826 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10827                                          ((INSTANCE) == I2C2) || \
10828                                          ((INSTANCE) == I2C3))
10829 
10830 /******************************** SPI Instances *******************************/
10831 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
10832                                        ((INSTANCE) == SPI2))
10833 
10834 /****************** LPTIM Instances : All supported instances *****************/
10835 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
10836                                          ((INSTANCE) == LPTIM2))
10837 
10838 /****************** LPTIM Instances : supporting the encoder mode *************/
10839 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
10840 
10841 /****************** TIM Instances : All supported instances *******************/
10842 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
10843                                          ((INSTANCE) == TIM2)   || \
10844                                          ((INSTANCE) == TIM6)   || \
10845                                          ((INSTANCE) == TIM15)  || \
10846                                          ((INSTANCE) == TIM16))
10847 
10848 /****************** TIM Instances : supporting 32 bits counter ****************/
10849 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
10850 
10851 /****************** TIM Instances : supporting the break function *************/
10852 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
10853                                             ((INSTANCE) == TIM15)   || \
10854                                             ((INSTANCE) == TIM16))
10855 
10856 /************** TIM Instances : supporting Break source selection *************/
10857 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10858                                                ((INSTANCE) == TIM15)  || \
10859                                                ((INSTANCE) == TIM16))
10860 
10861 /****************** TIM Instances : supporting 2 break inputs *****************/
10862 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10863 
10864 /************* TIM Instances : at least 1 capture/compare channel *************/
10865 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10866                                          ((INSTANCE) == TIM2)   || \
10867                                          ((INSTANCE) == TIM15)  || \
10868                                          ((INSTANCE) == TIM16))
10869 
10870 /************ TIM Instances : at least 2 capture/compare channels *************/
10871 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10872                                          ((INSTANCE) == TIM2)   || \
10873                                          ((INSTANCE) == TIM15))
10874 
10875 /************ TIM Instances : at least 3 capture/compare channels *************/
10876 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10877                                          ((INSTANCE) == TIM2))
10878 
10879 /************ TIM Instances : at least 4 capture/compare channels *************/
10880 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10881                                          ((INSTANCE) == TIM2))
10882 
10883 /****************** TIM Instances : at least 5 capture/compare channels *******/
10884 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
10885 
10886 /****************** TIM Instances : at least 6 capture/compare channels *******/
10887 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
10888 
10889 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
10890 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
10891                                             ((INSTANCE) == TIM15)  || \
10892                                             ((INSTANCE) == TIM16))
10893 
10894 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
10895 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
10896                                             ((INSTANCE) == TIM2)   || \
10897                                             ((INSTANCE) == TIM6)   || \
10898                                             ((INSTANCE) == TIM15)  || \
10899                                             ((INSTANCE) == TIM16))
10900 
10901 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
10902 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10903                                             ((INSTANCE) == TIM2)   || \
10904                                             ((INSTANCE) == TIM15)  || \
10905                                             ((INSTANCE) == TIM16))
10906 
10907 /******************** TIM Instances : DMA burst feature ***********************/
10908 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10909                                             ((INSTANCE) == TIM2)   || \
10910                                             ((INSTANCE) == TIM15)  || \
10911                                             ((INSTANCE) == TIM16))
10912 
10913 /******************* TIM Instances : output(s) available **********************/
10914 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10915     ((((INSTANCE) == TIM1) &&                  \
10916      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10917       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10918       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10919       ((CHANNEL) == TIM_CHANNEL_4) ||          \
10920       ((CHANNEL) == TIM_CHANNEL_5) ||          \
10921       ((CHANNEL) == TIM_CHANNEL_6)))           \
10922      ||                                        \
10923      (((INSTANCE) == TIM2) &&                  \
10924      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10925       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10926       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10927       ((CHANNEL) == TIM_CHANNEL_4)))           \
10928      ||                                        \
10929      (((INSTANCE) == TIM15) &&                 \
10930      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10931       ((CHANNEL) == TIM_CHANNEL_2)))           \
10932      ||                                        \
10933      (((INSTANCE) == TIM16) &&                 \
10934      (((CHANNEL) == TIM_CHANNEL_1))))
10935 
10936 /****************** TIM Instances : supporting complementary output(s) ********/
10937 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10938    ((((INSTANCE) == TIM1) &&                    \
10939      (((CHANNEL) == TIM_CHANNEL_1) ||           \
10940       ((CHANNEL) == TIM_CHANNEL_2) ||           \
10941       ((CHANNEL) == TIM_CHANNEL_3)))            \
10942     ||                                          \
10943     (((INSTANCE) == TIM15) &&                   \
10944      ((CHANNEL) == TIM_CHANNEL_1))              \
10945     ||                                          \
10946     (((INSTANCE) == TIM16) &&                   \
10947      ((CHANNEL) == TIM_CHANNEL_1)))
10948 
10949 /****************** TIM Instances : supporting clock division *****************/
10950 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
10951                                                     ((INSTANCE) == TIM2)    || \
10952                                                     ((INSTANCE) == TIM15)   || \
10953                                                     ((INSTANCE) == TIM16))
10954 
10955 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
10956 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10957                                                         ((INSTANCE) == TIM2) || \
10958                                                         ((INSTANCE) == TIM15))
10959 
10960 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
10961 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10962                                                         ((INSTANCE) == TIM2))
10963 
10964 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
10965 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
10966                                                         ((INSTANCE) == TIM2) || \
10967                                                         ((INSTANCE) == TIM15))
10968 
10969 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
10970 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
10971                                                         ((INSTANCE) == TIM2) || \
10972                                                         ((INSTANCE) == TIM15))
10973 
10974 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
10975 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10976 
10977 /****************** TIM Instances : supporting commutation event generation ***/
10978 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10979                                                      ((INSTANCE) == TIM15)  || \
10980                                                      ((INSTANCE) == TIM16))
10981 
10982 /****************** TIM Instances : supporting counting mode selection ********/
10983 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
10984                                                         ((INSTANCE) == TIM2))
10985 
10986 /****************** TIM Instances : supporting encoder interface **************/
10987 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
10988                                                       ((INSTANCE) == TIM2))
10989 
10990 /****************** TIM Instances : supporting Hall sensor interface **********/
10991 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
10992                                                           ((INSTANCE) == TIM2))
10993 
10994 /**************** TIM Instances : external trigger input available ************/
10995 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
10996                                             ((INSTANCE) == TIM2))
10997 
10998 /************* TIM Instances : supporting ETR source selection ***************/
10999 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11000                                              ((INSTANCE) == TIM2))
11001 
11002 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
11003 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
11004                                             ((INSTANCE) == TIM2)  || \
11005                                             ((INSTANCE) == TIM6)  || \
11006                                             ((INSTANCE) == TIM15))
11007 
11008 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
11009 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11010                                             ((INSTANCE) == TIM2)  || \
11011                                             ((INSTANCE) == TIM15))
11012 
11013 /****************** TIM Instances : supporting OCxREF clear *******************/
11014 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
11015                                                        ((INSTANCE) == TIM2))
11016 
11017 /****************** TIM Instances : remapping capability **********************/
11018 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
11019                                             ((INSTANCE) == TIM2)  || \
11020                                             ((INSTANCE) == TIM15) || \
11021                                             ((INSTANCE) == TIM16))
11022 
11023 /****************** TIM Instances : supporting repetition counter *************/
11024 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
11025                                                        ((INSTANCE) == TIM15) || \
11026                                                        ((INSTANCE) == TIM16))
11027 
11028 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
11029 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
11030 
11031 /******************* TIM Instances : Timer input XOR function *****************/
11032 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
11033                                             ((INSTANCE) == TIM2)   || \
11034                                             ((INSTANCE) == TIM15))
11035 
11036 /****************** TIM Instances : Advanced timer instances *******************/
11037 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
11038 
11039 /****************************** TSC Instances *********************************/
11040 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
11041 
11042 /******************** USART Instances : Synchronous mode **********************/
11043 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11044                                      ((INSTANCE) == USART2) || \
11045                                      ((INSTANCE) == USART3))
11046 
11047 /******************** UART Instances : Asynchronous mode **********************/
11048 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11049                                     ((INSTANCE) == USART2) || \
11050                                     ((INSTANCE) == USART3))
11051 
11052 /****************** UART Instances : Auto Baud Rate detection ****************/
11053 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11054                                                             ((INSTANCE) == USART2) || \
11055                                                             ((INSTANCE) == USART3))
11056 
11057 /****************** UART Instances : Driver Enable *****************/
11058 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
11059                                                       ((INSTANCE) == USART2) || \
11060                                                       ((INSTANCE) == USART3) || \
11061                                                       ((INSTANCE) == LPUART1))
11062 
11063 /******************** UART Instances : Half-Duplex mode **********************/
11064 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11065                                                  ((INSTANCE) == USART2) || \
11066                                                  ((INSTANCE) == USART3) || \
11067                                                  ((INSTANCE) == LPUART1))
11068 
11069 /****************** UART Instances : Hardware Flow control ********************/
11070 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11071                                            ((INSTANCE) == USART2) || \
11072                                            ((INSTANCE) == USART3) || \
11073                                            ((INSTANCE) == LPUART1))
11074 
11075 /******************** UART Instances : LIN mode **********************/
11076 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11077                                           ((INSTANCE) == USART2) || \
11078                                           ((INSTANCE) == USART3))
11079 
11080 /******************** UART Instances : Wake-up from Stop mode **********************/
11081 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
11082                                                       ((INSTANCE) == USART2) || \
11083                                                       ((INSTANCE) == USART3) || \
11084                                                       ((INSTANCE) == LPUART1))
11085 
11086 /*********************** UART Instances : IRDA mode ***************************/
11087 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11088                                     ((INSTANCE) == USART2) || \
11089                                     ((INSTANCE) == USART3))
11090 
11091 /********************* USART Instances : Smard card mode ***********************/
11092 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11093                                          ((INSTANCE) == USART2) || \
11094                                          ((INSTANCE) == USART3))
11095 
11096 /******************** LPUART Instance *****************************************/
11097 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
11098 
11099 /****************************** IWDG Instances ********************************/
11100 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
11101 
11102 /****************************** WWDG Instances ********************************/
11103 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
11104 
11105 /******************************* USB Instances *******************************/
11106 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
11107 #define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
11108 /**
11109   * @}
11110   */
11111 
11112 
11113 /******************************************************************************/
11114 /*  For a painless codes migration between the STM32L4xx device product       */
11115 /*  lines, the aliases defined below are put in place to overcome the         */
11116 /*  differences in the interrupt handlers and IRQn definitions.               */
11117 /*  No need to update developed interrupt code when moving across             */
11118 /*  product lines within the same STM32L4 Family                              */
11119 /******************************************************************************/
11120 
11121 /* Aliases for __IRQn */
11122 #define ADC1_IRQn                      ADC1_2_IRQn
11123 #define HASH_RNG_IRQn                  RNG_IRQn
11124 #define HASH_CRS_IRQn                  CRS_IRQn
11125 #define TIM1_TRG_COM_TIM17_IRQn        TIM1_TRG_COM_IRQn
11126 #define TIM6_DAC_IRQn                  TIM6_IRQn
11127 
11128 /* Aliases for __IRQHandler */
11129 #define ADC1_IRQHandler                ADC1_2_IRQHandler
11130 #define HASH_RNG_IRQHandler            RNG_IRQHandler
11131 #define HASH_CRS_IRQHandler            CRS_IRQHandler
11132 #define TIM1_TRG_COM_TIM17_IRQHandler  TIM1_TRG_COM_IRQHandler
11133 #define TIM6_DAC_IRQHandler            TIM6_IRQHandler
11134 
11135 #ifdef __cplusplus
11136 }
11137 #endif /* __cplusplus */
11138 
11139 #endif /* __STM32L422xx_H */
11140 
11141 /**
11142   * @}
11143   */
11144 
11145   /**
11146   * @}
11147   */
11148 
11149