1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_LPTIM_H
21 #define STM32L4xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 #if defined(LPTIM_RCR_REP)
113 #define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */
114 #define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */
115 #endif
116 /**
117 * @}
118 */
119
120 /** @defgroup LPTIM_LL_EC_IT IT Defines
121 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
122 * @{
123 */
124 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
125 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
126 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
127 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
128 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
129 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
130 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
131 #if defined(LPTIM_RCR_REP)
132 #define LL_LPTIM_IER_UEIE LPTIM_IER_UEIE /*!< Update event */
133 #define LL_LPTIM_IER_REPOKIE LPTIM_IER_REPOKIE /*!< Repetition register update OK */
134 #endif
135 /**
136 * @}
137 */
138
139 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
140 * @{
141 */
142 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
143 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
144 /**
145 * @}
146 */
147
148 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
149 * @{
150 */
151 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
152 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
153 /**
154 * @}
155 */
156
157 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
158 * @{
159 */
160 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
161 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
162 /**
163 * @}
164 */
165
166 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
167 * @{
168 */
169 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
170 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
171 /**
172 * @}
173 */
174
175 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
176 * @{
177 */
178 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
179 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
180 /**
181 * @}
182 */
183
184 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
185 * @{
186 */
187 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
188 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
189 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
190 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
191 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
192 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
193 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
194 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
195 /**
196 * @}
197 */
198
199 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
200 * @{
201 */
202 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
203 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
204 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
205 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
206 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
207 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
208 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
209 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
210 /**
211 * @}
212 */
213
214 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
215 * @{
216 */
217 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
218 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
219 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
220 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
226 * @{
227 */
228 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
229 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
230 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
231 /**
232 * @}
233 */
234
235 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
236 * @{
237 */
238 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
239 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
240 /**
241 * @}
242 */
243
244 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
245 * @{
246 */
247 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
248 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
249 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
250 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
251 /**
252 * @}
253 */
254
255 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
256 * @{
257 */
258 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
259 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
260 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
261 /**
262 * @}
263 */
264
265 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
266 * @{
267 */
268 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
269 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
270 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
271 /**
272 * @}
273 */
274
275 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
276 * @{
277 */
278 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
279 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
280 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */
281 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */
282 /**
283 * @}
284 */
285
286 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
287 * @{
288 */
289 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */
290 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
291 /**
292 * @}
293 */
294
295 /**
296 * @}
297 */
298
299 /* Exported macro ------------------------------------------------------------*/
300 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
301 * @{
302 */
303
304 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
305 * @{
306 */
307
308 /**
309 * @brief Write a value in LPTIM register
310 * @param __INSTANCE__ LPTIM Instance
311 * @param __REG__ Register to be written
312 * @param __VALUE__ Value to be written in the register
313 * @retval None
314 */
315 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
316
317 /**
318 * @brief Read a value in LPTIM register
319 * @param __INSTANCE__ LPTIM Instance
320 * @param __REG__ Register to be read
321 * @retval Register value
322 */
323 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /* Exported functions --------------------------------------------------------*/
333 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
334 * @{
335 */
336
337 /** Legacy definitions for compatibility purpose
338 @cond 0
339 */
340 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
341 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
342 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
343 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
344 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
345 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
346 /**
347 @endcond
348 */
349
350 #if defined(USE_FULL_LL_DRIVER)
351 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
352 * @{
353 */
354
355 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
356 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
357 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
358 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
359 /**
360 * @}
361 */
362 #endif /* USE_FULL_LL_DRIVER */
363
364 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
365 * @{
366 */
367
368 /**
369 * @brief Enable the LPTIM instance
370 * @note After setting the ENABLE bit, a delay of two counter clock is needed
371 * before the LPTIM instance is actually enabled.
372 * @rmtoll CR ENABLE LL_LPTIM_Enable
373 * @param LPTIMx Low-Power Timer instance
374 * @retval None
375 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)376 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
377 {
378 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
379 }
380
381 /**
382 * @brief Indicates whether the LPTIM instance is enabled.
383 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
384 * @param LPTIMx Low-Power Timer instance
385 * @retval State of bit (1 or 0).
386 */
LL_LPTIM_IsEnabled(const LPTIM_TypeDef * LPTIMx)387 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
388 {
389 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
390 }
391
392 /**
393 * @brief Starts the LPTIM counter in the desired mode.
394 * @note LPTIM instance must be enabled before starting the counter.
395 * @note It is possible to change on the fly from One Shot mode to
396 * Continuous mode.
397 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
398 * CR SNGSTRT LL_LPTIM_StartCounter
399 * @param LPTIMx Low-Power Timer instance
400 * @param OperatingMode This parameter can be one of the following values:
401 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
402 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
403 * @retval None
404 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)405 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
406 {
407 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
408 }
409
410 #if defined(LPTIM_CR_RSTARE)
411 /**
412 * @brief Enable reset after read.
413 * @note After calling this function any read access to LPTIM_CNT
414 * register will asynchronously reset the LPTIM_CNT register content.
415 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
416 * @param LPTIMx Low-Power Timer instance
417 * @retval None
418 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)419 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
420 {
421 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
422 }
423
424 /**
425 * @brief Disable reset after read.
426 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
427 * @param LPTIMx Low-Power Timer instance
428 * @retval None
429 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)430 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
431 {
432 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
433 }
434
435 /**
436 * @brief Indicate whether the reset after read feature is enabled.
437 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
438 * @param LPTIMx Low-Power Timer instance
439 * @retval State of bit (1 or 0).
440 */
LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef * LPTIMx)441 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
442 {
443 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
444 }
445 #endif
446
447 #if defined(LPTIM_CR_COUNTRST)
448 /**
449 * @brief Reset of the LPTIM_CNT counter register (synchronous).
450 * @note Due to the synchronous nature of this reset, it only takes
451 * place after a synchronization delay of 3 LPTIM core clock cycles
452 * (LPTIM core clock may be different from APB clock).
453 * @note COUNTRST is automatically cleared by hardware
454 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
455 * @param LPTIMx Low-Power Timer instance
456 * @retval None
457 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)458 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
459 {
460 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
461 }
462 #endif
463
464 /**
465 * @brief Set the LPTIM registers update mode (enable/disable register preload)
466 * @note This function must be called when the LPTIM instance is disabled.
467 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
468 * @param LPTIMx Low-Power Timer instance
469 * @param UpdateMode This parameter can be one of the following values:
470 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
471 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
472 * @retval None
473 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)474 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
475 {
476 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
477 }
478
479 /**
480 * @brief Get the LPTIM registers update mode
481 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
482 * @param LPTIMx Low-Power Timer instance
483 * @retval Returned value can be one of the following values:
484 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
485 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
486 */
LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef * LPTIMx)487 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
488 {
489 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
490 }
491
492 /**
493 * @brief Set the auto reload value
494 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
495 * @note After a write to the LPTIMx_ARR register a new write operation to the
496 * same register can only be performed when the previous write operation
497 * is completed. Any successive write before the ARROK flag is set, will
498 * lead to unpredictable results.
499 * @note autoreload value be strictly greater than the compare value.
500 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
501 * @param LPTIMx Low-Power Timer instance
502 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
503 * @retval None
504 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)505 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
506 {
507 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
508 }
509
510 /**
511 * @brief Get actual auto reload value
512 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
513 * @param LPTIMx Low-Power Timer instance
514 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
515 */
LL_LPTIM_GetAutoReload(const LPTIM_TypeDef * LPTIMx)516 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
517 {
518 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
519 }
520
521 #if defined(LPTIM_RCR_REP)
522 /**
523 * @brief Set the repetition value
524 * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled
525 * @rmtoll RCR REP LL_LPTIM_SetRepetition
526 * @param LPTIMx Low-Power Timer instance
527 * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF
528 * @retval None
529 */
LL_LPTIM_SetRepetition(LPTIM_TypeDef * LPTIMx,uint32_t Repetition)530 __STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition)
531 {
532 MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition);
533 }
534
535 /**
536 * @brief Get the repetition value
537 * @rmtoll RCR REP LL_LPTIM_GetRepetition
538 * @param LPTIMx Low-Power Timer instance
539 * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF
540 */
LL_LPTIM_GetRepetition(const LPTIM_TypeDef * LPTIMx)541 __STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx)
542 {
543 return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP));
544 }
545 #endif
546
547 /**
548 * @brief Set the compare value
549 * @note After a write to the LPTIMx_CMP register a new write operation to the
550 * same register can only be performed when the previous write operation
551 * is completed. Any successive write before the CMPOK flag is set, will
552 * lead to unpredictable results.
553 * @rmtoll CMP CMP LL_LPTIM_SetCompare
554 * @param LPTIMx Low-Power Timer instance
555 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
556 * @retval None
557 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)558 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
559 {
560 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
561 }
562
563 /**
564 * @brief Get actual compare value
565 * @rmtoll CMP CMP LL_LPTIM_GetCompare
566 * @param LPTIMx Low-Power Timer instance
567 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
568 */
LL_LPTIM_GetCompare(const LPTIM_TypeDef * LPTIMx)569 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
570 {
571 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
572 }
573
574 /**
575 * @brief Get actual counter value
576 * @note When the LPTIM instance is running with an asynchronous clock, reading
577 * the LPTIMx_CNT register may return unreliable values. So in this case
578 * it is necessary to perform two consecutive read accesses and verify
579 * that the two returned values are identical.
580 * @rmtoll CNT CNT LL_LPTIM_GetCounter
581 * @param LPTIMx Low-Power Timer instance
582 * @retval Counter value
583 */
LL_LPTIM_GetCounter(const LPTIM_TypeDef * LPTIMx)584 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
585 {
586 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
587 }
588
589 /**
590 * @brief Set the counter mode (selection of the LPTIM counter clock source).
591 * @note The counter mode can be set only when the LPTIM instance is disabled.
592 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
593 * @param LPTIMx Low-Power Timer instance
594 * @param CounterMode This parameter can be one of the following values:
595 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
596 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
597 * @retval None
598 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)599 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
600 {
601 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
602 }
603
604 /**
605 * @brief Get the counter mode
606 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
607 * @param LPTIMx Low-Power Timer instance
608 * @retval Returned value can be one of the following values:
609 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
610 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
611 */
LL_LPTIM_GetCounterMode(const LPTIM_TypeDef * LPTIMx)612 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
613 {
614 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
615 }
616
617 /**
618 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
619 * @note This function must be called when the LPTIM instance is disabled.
620 * @note Regarding the LPTIM output polarity the change takes effect
621 * immediately, so the output default value will change immediately after
622 * the polarity is re-configured, even before the timer is enabled.
623 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
624 * CFGR WAVPOL LL_LPTIM_ConfigOutput
625 * @param LPTIMx Low-Power Timer instance
626 * @param Waveform This parameter can be one of the following values:
627 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
628 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
629 * @param Polarity This parameter can be one of the following values:
630 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
631 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
632 * @retval None
633 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)634 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
635 {
636 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
637 }
638
639 /**
640 * @brief Set waveform shape
641 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
642 * @param LPTIMx Low-Power Timer instance
643 * @param Waveform This parameter can be one of the following values:
644 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
645 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
646 * @retval None
647 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)648 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
649 {
650 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
651 }
652
653 /**
654 * @brief Get actual waveform shape
655 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
656 * @param LPTIMx Low-Power Timer instance
657 * @retval Returned value can be one of the following values:
658 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
659 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
660 */
LL_LPTIM_GetWaveform(const LPTIM_TypeDef * LPTIMx)661 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
662 {
663 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
664 }
665
666 /**
667 * @brief Set output polarity
668 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
669 * @param LPTIMx Low-Power Timer instance
670 * @param Polarity This parameter can be one of the following values:
671 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
672 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
673 * @retval None
674 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)675 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
676 {
677 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
678 }
679
680 /**
681 * @brief Get actual output polarity
682 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
683 * @param LPTIMx Low-Power Timer instance
684 * @retval Returned value can be one of the following values:
685 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
686 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
687 */
LL_LPTIM_GetPolarity(const LPTIM_TypeDef * LPTIMx)688 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
689 {
690 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
691 }
692
693 /**
694 * @brief Set actual prescaler division ratio.
695 * @note This function must be called when the LPTIM instance is disabled.
696 * @note When the LPTIM is configured to be clocked by an internal clock source
697 * and the LPTIM counter is configured to be updated by active edges
698 * detected on the LPTIM external Input1, the internal clock provided to
699 * the LPTIM must be not be prescaled.
700 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
701 * @param LPTIMx Low-Power Timer instance
702 * @param Prescaler This parameter can be one of the following values:
703 * @arg @ref LL_LPTIM_PRESCALER_DIV1
704 * @arg @ref LL_LPTIM_PRESCALER_DIV2
705 * @arg @ref LL_LPTIM_PRESCALER_DIV4
706 * @arg @ref LL_LPTIM_PRESCALER_DIV8
707 * @arg @ref LL_LPTIM_PRESCALER_DIV16
708 * @arg @ref LL_LPTIM_PRESCALER_DIV32
709 * @arg @ref LL_LPTIM_PRESCALER_DIV64
710 * @arg @ref LL_LPTIM_PRESCALER_DIV128
711 * @retval None
712 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)713 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
714 {
715 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
716 }
717
718 /**
719 * @brief Get actual prescaler division ratio.
720 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
721 * @param LPTIMx Low-Power Timer instance
722 * @retval Returned value can be one of the following values:
723 * @arg @ref LL_LPTIM_PRESCALER_DIV1
724 * @arg @ref LL_LPTIM_PRESCALER_DIV2
725 * @arg @ref LL_LPTIM_PRESCALER_DIV4
726 * @arg @ref LL_LPTIM_PRESCALER_DIV8
727 * @arg @ref LL_LPTIM_PRESCALER_DIV16
728 * @arg @ref LL_LPTIM_PRESCALER_DIV32
729 * @arg @ref LL_LPTIM_PRESCALER_DIV64
730 * @arg @ref LL_LPTIM_PRESCALER_DIV128
731 */
LL_LPTIM_GetPrescaler(const LPTIM_TypeDef * LPTIMx)732 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
733 {
734 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
735 }
736
737 /**
738 * @brief Set LPTIM input 1 source (default GPIO).
739 * @rmtoll OR OR LL_LPTIM_SetInput1Src
740 * @param LPTIMx Low-Power Timer instance
741 * @param Src This parameter can be one of the following values:
742 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
743 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
744 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2
745 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2
746 * @retval None
747 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)748 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
749 {
750 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
751 }
752
753 /**
754 * @brief Set LPTIM input 2 source (default GPIO).
755 * @rmtoll OR OR LL_LPTIM_SetInput2Src
756 * @param LPTIMx Low-Power Timer instance
757 * @param Src This parameter can be one of the following values:
758 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
759 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
760 * @retval None
761 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)762 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
763 {
764 MODIFY_REG(LPTIMx->OR, LPTIM_OR_OR, Src);
765 }
766
767 /**
768 * @}
769 */
770
771 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
772 * @{
773 */
774
775 /**
776 * @brief Enable the timeout function
777 * @note This function must be called when the LPTIM instance is disabled.
778 * @note The first trigger event will start the timer, any successive trigger
779 * event will reset the counter and the timer will restart.
780 * @note The timeout value corresponds to the compare value; if no trigger
781 * occurs within the expected time frame, the MCU is waked-up by the
782 * compare match event.
783 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
784 * @param LPTIMx Low-Power Timer instance
785 * @retval None
786 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)787 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
788 {
789 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
790 }
791
792 /**
793 * @brief Disable the timeout function
794 * @note This function must be called when the LPTIM instance is disabled.
795 * @note A trigger event arriving when the timer is already started will be
796 * ignored.
797 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
798 * @param LPTIMx Low-Power Timer instance
799 * @retval None
800 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)801 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
802 {
803 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
804 }
805
806 /**
807 * @brief Indicate whether the timeout function is enabled.
808 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
809 * @param LPTIMx Low-Power Timer instance
810 * @retval State of bit (1 or 0).
811 */
LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef * LPTIMx)812 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
813 {
814 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
815 }
816
817 /**
818 * @brief Start the LPTIM counter
819 * @note This function must be called when the LPTIM instance is disabled.
820 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
821 * @param LPTIMx Low-Power Timer instance
822 * @retval None
823 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)824 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
825 {
826 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
827 }
828
829 /**
830 * @brief Configure the external trigger used as a trigger event for the LPTIM.
831 * @note This function must be called when the LPTIM instance is disabled.
832 * @note An internal clock source must be present when a digital filter is
833 * required for the trigger.
834 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
835 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
836 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
837 * @param LPTIMx Low-Power Timer instance
838 * @param Source This parameter can be one of the following values:
839 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
840 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
841 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
842 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
843 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
844 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
845 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
846 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
847 * @param Filter This parameter can be one of the following values:
848 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
849 * @arg @ref LL_LPTIM_TRIG_FILTER_2
850 * @arg @ref LL_LPTIM_TRIG_FILTER_4
851 * @arg @ref LL_LPTIM_TRIG_FILTER_8
852 * @param Polarity This parameter can be one of the following values:
853 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
854 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
855 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
856 * @retval None
857 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)858 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
859 {
860 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
861 }
862
863 /**
864 * @brief Get actual external trigger source.
865 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
866 * @param LPTIMx Low-Power Timer instance
867 * @retval Returned value can be one of the following values:
868 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
869 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
870 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
871 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
872 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
873 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
874 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
875 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
876 */
LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef * LPTIMx)877 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
878 {
879 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
880 }
881
882 /**
883 * @brief Get actual external trigger filter.
884 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
885 * @param LPTIMx Low-Power Timer instance
886 * @retval Returned value can be one of the following values:
887 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
888 * @arg @ref LL_LPTIM_TRIG_FILTER_2
889 * @arg @ref LL_LPTIM_TRIG_FILTER_4
890 * @arg @ref LL_LPTIM_TRIG_FILTER_8
891 */
LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef * LPTIMx)892 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
893 {
894 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
895 }
896
897 /**
898 * @brief Get actual external trigger polarity.
899 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
900 * @param LPTIMx Low-Power Timer instance
901 * @retval Returned value can be one of the following values:
902 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
903 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
904 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
905 */
LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef * LPTIMx)906 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
907 {
908 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
909 }
910
911 /**
912 * @}
913 */
914
915 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
916 * @{
917 */
918
919 /**
920 * @brief Set the source of the clock used by the LPTIM instance.
921 * @note This function must be called when the LPTIM instance is disabled.
922 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
923 * @param LPTIMx Low-Power Timer instance
924 * @param ClockSource This parameter can be one of the following values:
925 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
926 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
927 * @retval None
928 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)929 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
930 {
931 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
932 }
933
934 /**
935 * @brief Get actual LPTIM instance clock source.
936 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
937 * @param LPTIMx Low-Power Timer instance
938 * @retval Returned value can be one of the following values:
939 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
940 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
941 */
LL_LPTIM_GetClockSource(const LPTIM_TypeDef * LPTIMx)942 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
943 {
944 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
945 }
946
947 /**
948 * @brief Configure the active edge or edges used by the counter when
949 the LPTIM is clocked by an external clock source.
950 * @note This function must be called when the LPTIM instance is disabled.
951 * @note When both external clock signal edges are considered active ones,
952 * the LPTIM must also be clocked by an internal clock source with a
953 * frequency equal to at least four times the external clock frequency.
954 * @note An internal clock source must be present when a digital filter is
955 * required for external clock.
956 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
957 * CFGR CKPOL LL_LPTIM_ConfigClock
958 * @param LPTIMx Low-Power Timer instance
959 * @param ClockFilter This parameter can be one of the following values:
960 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
961 * @arg @ref LL_LPTIM_CLK_FILTER_2
962 * @arg @ref LL_LPTIM_CLK_FILTER_4
963 * @arg @ref LL_LPTIM_CLK_FILTER_8
964 * @param ClockPolarity This parameter can be one of the following values:
965 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
966 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
967 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
968 * @retval None
969 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)970 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
971 {
972 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
973 }
974
975 /**
976 * @brief Get actual clock polarity
977 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
978 * @param LPTIMx Low-Power Timer instance
979 * @retval Returned value can be one of the following values:
980 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
981 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
982 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
983 */
LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef * LPTIMx)984 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
985 {
986 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
987 }
988
989 /**
990 * @brief Get actual clock digital filter
991 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
992 * @param LPTIMx Low-Power Timer instance
993 * @retval Returned value can be one of the following values:
994 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
995 * @arg @ref LL_LPTIM_CLK_FILTER_2
996 * @arg @ref LL_LPTIM_CLK_FILTER_4
997 * @arg @ref LL_LPTIM_CLK_FILTER_8
998 */
LL_LPTIM_GetClockFilter(const LPTIM_TypeDef * LPTIMx)999 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
1000 {
1001 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
1002 }
1003
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
1009 * @{
1010 */
1011
1012 /**
1013 * @brief Configure the encoder mode.
1014 * @note This function must be called when the LPTIM instance is disabled.
1015 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1016 * @param LPTIMx Low-Power Timer instance
1017 * @param EncoderMode This parameter can be one of the following values:
1018 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1019 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1020 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1021 * @retval None
1022 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)1023 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1024 {
1025 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1026 }
1027
1028 /**
1029 * @brief Get actual encoder mode.
1030 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1031 * @param LPTIMx Low-Power Timer instance
1032 * @retval Returned value can be one of the following values:
1033 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1034 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1035 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1036 */
LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef * LPTIMx)1037 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
1038 {
1039 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1040 }
1041
1042 /**
1043 * @brief Enable the encoder mode
1044 * @note This function must be called when the LPTIM instance is disabled.
1045 * @note In this mode the LPTIM instance must be clocked by an internal clock
1046 * source. Also, the prescaler division ratio must be equal to 1.
1047 * @note LPTIM instance must be configured in continuous mode prior enabling
1048 * the encoder mode.
1049 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1050 * @param LPTIMx Low-Power Timer instance
1051 * @retval None
1052 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1053 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1054 {
1055 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1056 }
1057
1058 /**
1059 * @brief Disable the encoder mode
1060 * @note This function must be called when the LPTIM instance is disabled.
1061 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1062 * @param LPTIMx Low-Power Timer instance
1063 * @retval None
1064 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1065 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1066 {
1067 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1068 }
1069
1070 /**
1071 * @brief Indicates whether the LPTIM operates in encoder mode.
1072 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1073 * @param LPTIMx Low-Power Timer instance
1074 * @retval State of bit (1 or 0).
1075 */
LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef * LPTIMx)1076 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
1077 {
1078 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1079 }
1080
1081 /**
1082 * @}
1083 */
1084
1085 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1086 * @{
1087 */
1088
1089
1090 /**
1091 * @brief Clear the compare match flag (CMPMCF)
1092 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
1093 * @param LPTIMx Low-Power Timer instance
1094 * @retval None
1095 */
LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef * LPTIMx)1096 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1097 {
1098 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1099 }
1100
1101 /**
1102 * @brief Inform application whether a compare match interrupt has occurred.
1103 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1104 * @param LPTIMx Low-Power Timer instance
1105 * @retval State of bit (1 or 0).
1106 */
LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef * LPTIMx)1107 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
1108 {
1109 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1110 }
1111
1112 /**
1113 * @brief Clear the autoreload match flag (ARRMCF)
1114 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
1115 * @param LPTIMx Low-Power Timer instance
1116 * @retval None
1117 */
LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef * LPTIMx)1118 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1119 {
1120 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1121 }
1122
1123 /**
1124 * @brief Inform application whether a autoreload match interrupt has occurred.
1125 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1126 * @param LPTIMx Low-Power Timer instance
1127 * @retval State of bit (1 or 0).
1128 */
LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef * LPTIMx)1129 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
1130 {
1131 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1132 }
1133
1134 /**
1135 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1136 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1137 * @param LPTIMx Low-Power Timer instance
1138 * @retval None
1139 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1140 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1141 {
1142 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1143 }
1144
1145 /**
1146 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1147 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1148 * @param LPTIMx Low-Power Timer instance
1149 * @retval State of bit (1 or 0).
1150 */
LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1151 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1152 {
1153 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1154 }
1155
1156 /**
1157 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1158 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1159 * @param LPTIMx Low-Power Timer instance
1160 * @retval None
1161 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1162 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1163 {
1164 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1165 }
1166
1167 /**
1168 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1169 completed. If so, a new one can be initiated.
1170 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1171 * @param LPTIMx Low-Power Timer instance
1172 * @retval State of bit (1 or 0).
1173 */
LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef * LPTIMx)1174 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
1175 {
1176 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1177 }
1178
1179 /**
1180 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1181 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1182 * @param LPTIMx Low-Power Timer instance
1183 * @retval None
1184 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1185 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1186 {
1187 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1188 }
1189
1190 /**
1191 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1192 completed. If so, a new one can be initiated.
1193 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1194 * @param LPTIMx Low-Power Timer instance
1195 * @retval State of bit (1 or 0).
1196 */
LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef * LPTIMx)1197 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
1198 {
1199 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1200 }
1201
1202 /**
1203 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1204 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1205 * @param LPTIMx Low-Power Timer instance
1206 * @retval None
1207 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1208 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1209 {
1210 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1211 }
1212
1213 /**
1214 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1215 operates in encoder mode).
1216 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1217 * @param LPTIMx Low-Power Timer instance
1218 * @retval State of bit (1 or 0).
1219 */
LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef * LPTIMx)1220 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
1221 {
1222 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1223 }
1224
1225 /**
1226 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1227 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1228 * @param LPTIMx Low-Power Timer instance
1229 * @retval None
1230 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1231 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1232 {
1233 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1234 }
1235
1236 /**
1237 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1238 operates in encoder mode).
1239 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1240 * @param LPTIMx Low-Power Timer instance
1241 * @retval State of bit (1 or 0).
1242 */
LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef * LPTIMx)1243 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
1244 {
1245 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1246 }
1247
1248 #if defined(LPTIM_RCR_REP)
1249 /**
1250 * @brief Clear the repetition register update interrupt flag (REPOKCF).
1251 * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK
1252 * @param LPTIMx Low-Power Timer instance
1253 * @retval None
1254 */
LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef * LPTIMx)1255 __STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx)
1256 {
1257 SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF);
1258 }
1259
1260 /**
1261 * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully
1262 completed; If so, a new one can be initiated.
1263 * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK
1264 * @param LPTIMx Low-Power Timer instance
1265 * @retval State of bit (1 or 0).
1266 */
LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef * LPTIMx)1267 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx)
1268 {
1269 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL);
1270 }
1271
1272 /**
1273 * @brief Clear the update event flag (UECF).
1274 * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE
1275 * @param LPTIMx Low-Power Timer instance
1276 * @retval None
1277 */
LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef * LPTIMx)1278 __STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx)
1279 {
1280 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF);
1281 }
1282
1283 /**
1284 * @brief Informs application whether the LPTIMx update event has occurred.
1285 * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE
1286 * @param LPTIMx Low-Power Timer instance
1287 * @retval State of bit (1 or 0).
1288 */
LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef * LPTIMx)1289 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx)
1290 {
1291 return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL);
1292 }
1293 #endif
1294
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1300 * @{
1301 */
1302
1303 /**
1304 * @brief Enable compare match interrupt (CMPMIE).
1305 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1306 * @param LPTIMx Low-Power Timer instance
1307 * @retval None
1308 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1309 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1310 {
1311 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1312 }
1313
1314 /**
1315 * @brief Disable compare match interrupt (CMPMIE).
1316 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1317 * @param LPTIMx Low-Power Timer instance
1318 * @retval None
1319 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1320 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1321 {
1322 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1323 }
1324
1325 /**
1326 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1327 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1328 * @param LPTIMx Low-Power Timer instance
1329 * @retval State of bit (1 or 0).
1330 */
LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef * LPTIMx)1331 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
1332 {
1333 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1334 }
1335
1336 /**
1337 * @brief Enable autoreload match interrupt (ARRMIE).
1338 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1339 * @param LPTIMx Low-Power Timer instance
1340 * @retval None
1341 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1342 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1343 {
1344 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1345 }
1346
1347 /**
1348 * @brief Disable autoreload match interrupt (ARRMIE).
1349 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1350 * @param LPTIMx Low-Power Timer instance
1351 * @retval None
1352 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1353 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1354 {
1355 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1356 }
1357
1358 /**
1359 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1360 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1361 * @param LPTIMx Low-Power Timer instance
1362 * @retval State of bit (1 or 0).
1363 */
LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef * LPTIMx)1364 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
1365 {
1366 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1367 }
1368
1369 /**
1370 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1371 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1372 * @param LPTIMx Low-Power Timer instance
1373 * @retval None
1374 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1375 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1376 {
1377 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1378 }
1379
1380 /**
1381 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1382 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1383 * @param LPTIMx Low-Power Timer instance
1384 * @retval None
1385 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1386 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1387 {
1388 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1389 }
1390
1391 /**
1392 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1393 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1394 * @param LPTIMx Low-Power Timer instance
1395 * @retval State of bit (1 or 0).
1396 */
LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef * LPTIMx)1397 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
1398 {
1399 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1400 }
1401
1402 /**
1403 * @brief Enable compare register write completed interrupt (CMPOKIE).
1404 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1405 * @param LPTIMx Low-Power Timer instance
1406 * @retval None
1407 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1408 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1409 {
1410 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1411 }
1412
1413 /**
1414 * @brief Disable compare register write completed interrupt (CMPOKIE).
1415 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1416 * @param LPTIMx Low-Power Timer instance
1417 * @retval None
1418 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1419 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1420 {
1421 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1422 }
1423
1424 /**
1425 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1426 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1427 * @param LPTIMx Low-Power Timer instance
1428 * @retval State of bit (1 or 0).
1429 */
LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef * LPTIMx)1430 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
1431 {
1432 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1433 }
1434
1435 /**
1436 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1437 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1438 * @param LPTIMx Low-Power Timer instance
1439 * @retval None
1440 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1441 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1442 {
1443 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1444 }
1445
1446 /**
1447 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1448 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1449 * @param LPTIMx Low-Power Timer instance
1450 * @retval None
1451 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1452 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1453 {
1454 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1455 }
1456
1457 /**
1458 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1459 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1460 * @param LPTIMx Low-Power Timer instance
1461 * @retval State of bit(1 or 0).
1462 */
LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef * LPTIMx)1463 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
1464 {
1465 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1466 }
1467
1468 /**
1469 * @brief Enable direction change to up interrupt (UPIE).
1470 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1471 * @param LPTIMx Low-Power Timer instance
1472 * @retval None
1473 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1474 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1475 {
1476 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1477 }
1478
1479 /**
1480 * @brief Disable direction change to up interrupt (UPIE).
1481 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1482 * @param LPTIMx Low-Power Timer instance
1483 * @retval None
1484 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1485 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1486 {
1487 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1488 }
1489
1490 /**
1491 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1492 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1493 * @param LPTIMx Low-Power Timer instance
1494 * @retval State of bit(1 or 0).
1495 */
LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef * LPTIMx)1496 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
1497 {
1498 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1499 }
1500
1501 /**
1502 * @brief Enable direction change to down interrupt (DOWNIE).
1503 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1504 * @param LPTIMx Low-Power Timer instance
1505 * @retval None
1506 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1507 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1508 {
1509 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1510 }
1511
1512 /**
1513 * @brief Disable direction change to down interrupt (DOWNIE).
1514 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1515 * @param LPTIMx Low-Power Timer instance
1516 * @retval None
1517 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1518 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1519 {
1520 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1521 }
1522
1523 /**
1524 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1525 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1526 * @param LPTIMx Low-Power Timer instance
1527 * @retval State of bit(1 or 0).
1528 */
LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef * LPTIMx)1529 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
1530 {
1531 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1532 }
1533
1534 #if defined(LPTIM_RCR_REP)
1535 /**
1536 * @brief Enable repetition register update successfully completed interrupt (REPOKIE).
1537 * @rmtoll IER REPOKIE LL_LPTIM_EnableIT_REPOK
1538 * @param LPTIMx Low-Power Timer instance
1539 * @retval None
1540 */
LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef * LPTIMx)1541 __STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1542 {
1543 SET_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1544 }
1545
1546 /**
1547 * @brief Disable repetition register update successfully completed interrupt (REPOKIE).
1548 * @rmtoll IER REPOKIE LL_LPTIM_DisableIT_REPOK
1549 * @param LPTIMx Low-Power Timer instance
1550 * @retval None
1551 */
LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef * LPTIMx)1552 __STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx)
1553 {
1554 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE);
1555 }
1556
1557 /**
1558 * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
1559 * @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
1560 * @param LPTIMx Low-Power Timer instance
1561 * @retval State of bit(1 or 0).
1562 */
LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef * LPTIMx)1563 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx)
1564 {
1565 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_REPOKIE) == (LPTIM_IER_REPOKIE)) ? 1UL : 0UL);
1566 }
1567
1568 /**
1569 * @brief Enable update event interrupt (UEIE).
1570 * @rmtoll IER UEIE LL_LPTIM_EnableIT_UE
1571 * @param LPTIMx Low-Power Timer instance
1572 * @retval None
1573 */
LL_LPTIM_EnableIT_UE(LPTIM_TypeDef * LPTIMx)1574 __STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx)
1575 {
1576 SET_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1577 }
1578
1579 /**
1580 * @brief Disable update event interrupt (UEIE).
1581 * @rmtoll IER UEIE LL_LPTIM_DisableIT_UE
1582 * @param LPTIMx Low-Power Timer instance
1583 * @retval None
1584 */
LL_LPTIM_DisableIT_UE(LPTIM_TypeDef * LPTIMx)1585 __STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx)
1586 {
1587 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UEIE);
1588 }
1589
1590 /**
1591 * @brief Indicates whether the update event interrupt (UEIE) is enabled.
1592 * @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
1593 * @param LPTIMx Low-Power Timer instance
1594 *@ retval State of bit(1 or 0).
1595 */
LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef * LPTIMx)1596 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx)
1597 {
1598 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_UEIE) == (LPTIM_IER_UEIE)) ? 1UL : 0UL);
1599 }
1600 #endif
1601 /**
1602 * @}
1603 */
1604
1605 /**
1606 * @}
1607 */
1608
1609 /**
1610 * @}
1611 */
1612
1613 #endif /* LPTIM1 || LPTIM2 */
1614
1615 /**
1616 * @}
1617 */
1618
1619 #ifdef __cplusplus
1620 }
1621 #endif
1622
1623 #endif /* STM32L4xx_LL_LPTIM_H */
1624
