1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L0xx_LL_DAC_H
21 #define __STM32L0xx_LL_DAC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l0xx.h"
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DAC1)
35
36 /** @defgroup DAC_LL DAC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
45 * @{
46 */
47
48 /* Internal masks for DAC channels definition */
49 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50 /* - channel bits position into register CR */
51 /* - channel bits position into register SWTRIG */
52 /* - channel register offset of data holding register DHRx */
53 /* - channel register offset of data output register DORx */
54 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
55 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
56 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
57
58 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
59 #if defined(DAC_CHANNEL2_SUPPORT)
60 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
61 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
62 #else
63 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
64 #endif /* DAC_CHANNEL2_SUPPORT */
65
66 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
67 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
68 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
69 #if defined(DAC_CHANNEL2_SUPPORT)
70 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
71 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
72 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
73 #endif /* DAC_CHANNEL2_SUPPORT */
74 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
75 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
76 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
77 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
78
79 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
80 #if defined(DAC_CHANNEL2_SUPPORT)
81 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
82 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
83 #else
84 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
85 #endif /* DAC_CHANNEL2_SUPPORT */
86
87 #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
88
89 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
90 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
91 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
92 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
93
94 /* DAC registers bits positions */
95 #if defined(DAC_CHANNEL2_SUPPORT)
96 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
97 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
98 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
99 #endif /* DAC_CHANNEL2_SUPPORT */
100
101 /* Miscellaneous data */
102 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
103
104 /**
105 * @}
106 */
107
108
109 /* Private macros ------------------------------------------------------------*/
110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
111 * @{
112 */
113
114 /**
115 * @brief Driver macro reserved for internal use: set a pointer to
116 * a register from a register basis from which an offset
117 * is applied.
118 * @param __REG__ Register basis from which the offset is applied.
119 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
120 * @retval Pointer to register address
121 */
122 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
123 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
124
125 /**
126 * @}
127 */
128
129
130 /* Exported types ------------------------------------------------------------*/
131 #if defined(USE_FULL_LL_DRIVER)
132 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
133 * @{
134 */
135
136 /**
137 * @brief Structure definition of some features of DAC instance.
138 */
139 typedef struct
140 {
141 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
142 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
143
144 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
145
146 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
147 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
148
149 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
150
151 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
152 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
153 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
154 @note If waveform automatic generation mode is disabled, this parameter is discarded.
155
156 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
157
158 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
159 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
160
161 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
162
163 } LL_DAC_InitTypeDef;
164
165 /**
166 * @}
167 */
168 #endif /* USE_FULL_LL_DRIVER */
169
170 /* Exported constants --------------------------------------------------------*/
171 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
172 * @{
173 */
174
175 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
176 * @brief Flags defines which can be used with LL_DAC_ReadReg function
177 * @{
178 */
179 /* DAC channel 1 flags */
180 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
181
182 #if defined(DAC_CHANNEL2_SUPPORT)
183 /* DAC channel 2 flags */
184 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
185 #endif /* DAC_CHANNEL2_SUPPORT */
186 /**
187 * @}
188 */
189
190 /** @defgroup DAC_LL_EC_IT DAC interruptions
191 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
192 * @{
193 */
194 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
195 #if defined(DAC_CHANNEL2_SUPPORT)
196 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
197 #endif /* DAC_CHANNEL2_SUPPORT */
198 /**
199 * @}
200 */
201
202 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
203 * @{
204 */
205 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
206 #if defined(DAC_CHANNEL2_SUPPORT)
207 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
208 #endif /* DAC_CHANNEL2_SUPPORT */
209 /**
210 * @}
211 */
212
213 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
214 * @{
215 */
216 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
217 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
218 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
219 #define LL_DAC_TRIG_EXT_TIM3_CH3 ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM3 CH3 event. */
220 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
221 #define LL_DAC_TRIG_EXT_TIM7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
222 #define LL_DAC_TRIG_EXT_TIM21_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM21 TRGO. */
223 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
224 /**
225 * @}
226 */
227
228 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
229 * @{
230 */
231 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
232 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
233 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
234 /**
235 * @}
236 */
237
238 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
239 * @{
240 */
241 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
242 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
243 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
244 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
245 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
253 /**
254 * @}
255 */
256
257 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
258 * @{
259 */
260 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
261 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
262 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
263 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
264 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
265 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
266 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
267 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
268 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
269 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
270 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
271 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
272 /**
273 * @}
274 */
275
276 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
277 * @{
278 */
279 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
280 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
281 /**
282 * @}
283 */
284
285
286 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
287 * @{
288 */
289 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
290 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
291 /**
292 * @}
293 */
294
295 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
296 * @{
297 */
298 /* List of DAC registers intended to be used (most commonly) with */
299 /* DMA transfer. */
300 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
301 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
302 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
303 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
304 /**
305 * @}
306 */
307
308 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
309 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
310 * not timeout values.
311 * For details on delays values, refer to descriptions in source code
312 * above each literal definition.
313 * @{
314 */
315
316 /* Delay for DAC channel voltage settling time from DAC channel startup */
317 /* (transition from disable to enable). */
318 /* Note: DAC channel startup time depends on board application environment: */
319 /* impedance connected to DAC channel output. */
320 /* The delay below is specified under conditions: */
321 /* - voltage maximum transition (lowest to highest value) */
322 /* - until voltage reaches final value +-1LSB */
323 /* - DAC channel output buffer enabled */
324 /* - load impedance of 5kOhm (min), 50pF (max) */
325 /* Literal set to maximum value (refer to device datasheet, */
326 /* parameter "tWAKEUP"). */
327 /* Unit: us */
328 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
329
330 /* Delay for DAC channel voltage settling time. */
331 /* Note: DAC channel startup time depends on board application environment: */
332 /* impedance connected to DAC channel output. */
333 /* The delay below is specified under conditions: */
334 /* - voltage maximum transition (lowest to highest value) */
335 /* - until voltage reaches final value +-1LSB */
336 /* - DAC channel output buffer enabled */
337 /* - load impedance of 5kOhm min, 50pF max */
338 /* Literal set to maximum value (refer to device datasheet, */
339 /* parameter "tSETTLING"). */
340 /* Unit: us */
341 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
342 /**
343 * @}
344 */
345
346 /**
347 * @}
348 */
349
350 /* Exported macro ------------------------------------------------------------*/
351 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
352 * @{
353 */
354
355 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
356 * @{
357 */
358
359 /**
360 * @brief Write a value in DAC register
361 * @param __INSTANCE__ DAC Instance
362 * @param __REG__ Register to be written
363 * @param __VALUE__ Value to be written in the register
364 * @retval None
365 */
366 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
367
368 /**
369 * @brief Read a value in DAC register
370 * @param __INSTANCE__ DAC Instance
371 * @param __REG__ Register to be read
372 * @retval Register value
373 */
374 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
375
376 /**
377 * @}
378 */
379
380 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
381 * @{
382 */
383
384 /**
385 * @brief Helper macro to get DAC channel number in decimal format
386 * from literals LL_DAC_CHANNEL_x.
387 * Example:
388 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
389 * will return decimal number "1".
390 * @note The input can be a value from functions where a channel
391 * number is returned.
392 * @param __CHANNEL__ This parameter can be one of the following values:
393 * @arg @ref LL_DAC_CHANNEL_1
394 * @arg @ref LL_DAC_CHANNEL_2 (1)
395 *
396 * (1) On this STM32 series, parameter not available on all devices.
397 * Refer to device datasheet for channels availability.
398 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
399 */
400 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
401 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
402
403 /**
404 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
405 * from number in decimal format.
406 * Example:
407 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
408 * will return a data equivalent to "LL_DAC_CHANNEL_1".
409 * @note If the input parameter does not correspond to a DAC channel,
410 * this macro returns value '0'.
411 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
412 * @retval Returned value can be one of the following values:
413 * @arg @ref LL_DAC_CHANNEL_1
414 * @arg @ref LL_DAC_CHANNEL_2 (1)
415 *
416 * (1) On this STM32 series, parameter not available on all devices.
417 * Refer to device datasheet for channels availability.
418 */
419 #if defined(DAC_CHANNEL2_SUPPORT)
420 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
421 (((__DECIMAL_NB__) == 1U) \
422 ? ( \
423 LL_DAC_CHANNEL_1 \
424 ) \
425 : \
426 (((__DECIMAL_NB__) == 2U) \
427 ? ( \
428 LL_DAC_CHANNEL_2 \
429 ) \
430 : \
431 ( \
432 0 \
433 ) \
434 ) \
435 )
436 #else
437 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
438 (((__DECIMAL_NB__) == 1U) \
439 ? ( \
440 LL_DAC_CHANNEL_1 \
441 ) \
442 : \
443 ( \
444 0 \
445 ) \
446 )
447 #endif /* DAC_CHANNEL2_SUPPORT */
448
449 /**
450 * @brief Helper macro to define the DAC conversion data full-scale digital
451 * value corresponding to the selected DAC resolution.
452 * @note DAC conversion data full-scale corresponds to voltage range
453 * determined by analog voltage references Vref+ and Vref-
454 * (refer to reference manual).
455 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
456 * @arg @ref LL_DAC_RESOLUTION_12B
457 * @arg @ref LL_DAC_RESOLUTION_8B
458 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
459 */
460 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
461 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
462
463 /**
464 * @brief Helper macro to calculate the DAC conversion data (unit: digital
465 * value) corresponding to a voltage (unit: mVolt).
466 * @note This helper macro is intended to provide input data in voltage
467 * rather than digital value,
468 * to be used with LL DAC functions such as
469 * @ref LL_DAC_ConvertData12RightAligned().
470 * @note Analog reference voltage (Vref+) must be either known from
471 * user board environment or can be calculated using ADC measurement
472 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
473 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
474 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
475 * (unit: mVolt).
476 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
477 * @arg @ref LL_DAC_RESOLUTION_12B
478 * @arg @ref LL_DAC_RESOLUTION_8B
479 * @retval DAC conversion data (unit: digital value)
480 */
481 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
482 __DAC_VOLTAGE__,\
483 __DAC_RESOLUTION__) \
484 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
485 / (__VREFANALOG_VOLTAGE__) \
486 )
487
488 /**
489 * @}
490 */
491
492 /**
493 * @}
494 */
495
496
497 /* Exported functions --------------------------------------------------------*/
498 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
499 * @{
500 */
501 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
502 * @{
503 */
504
505 /**
506 * @brief Set the conversion trigger source for the selected DAC channel.
507 * @note For conversion trigger source to be effective, DAC trigger
508 * must be enabled using function @ref LL_DAC_EnableTrigger().
509 * @note To set conversion trigger source, DAC channel must be disabled.
510 * Otherwise, the setting is discarded.
511 * @note Availability of parameters of trigger sources from timer
512 * depends on timers availability on the selected device.
513 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
514 * CR TSEL2 LL_DAC_SetTriggerSource
515 * @param DACx DAC instance
516 * @param DAC_Channel This parameter can be one of the following values:
517 * @arg @ref LL_DAC_CHANNEL_1
518 * @arg @ref LL_DAC_CHANNEL_2 (1)
519 *
520 * (1) On this STM32 series, parameter not available on all devices.
521 * Refer to device datasheet for channels availability.
522 * @param TriggerSource This parameter can be one of the following values:
523 * @arg @ref LL_DAC_TRIG_SOFTWARE
524 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
525 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
526 * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
527 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
528 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
529 * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
530 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
531 * @retval None
532 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)533 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
534 {
535 MODIFY_REG(DACx->CR,
536 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
537 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
538 }
539
540 /**
541 * @brief Get the conversion trigger source for the selected DAC channel.
542 * @note For conversion trigger source to be effective, DAC trigger
543 * must be enabled using function @ref LL_DAC_EnableTrigger().
544 * @note Availability of parameters of trigger sources from timer
545 * depends on timers availability on the selected device.
546 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
547 * CR TSEL2 LL_DAC_GetTriggerSource
548 * @param DACx DAC instance
549 * @param DAC_Channel This parameter can be one of the following values:
550 * @arg @ref LL_DAC_CHANNEL_1
551 * @arg @ref LL_DAC_CHANNEL_2 (1)
552 *
553 * (1) On this STM32 series, parameter not available on all devices.
554 * Refer to device datasheet for channels availability.
555 * @retval Returned value can be one of the following values:
556 * @arg @ref LL_DAC_TRIG_SOFTWARE
557 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
558 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
559 * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
560 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
561 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
562 * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
563 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
564 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)565 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
566 {
567 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
568 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
569 );
570 }
571
572 /**
573 * @brief Set the waveform automatic generation mode
574 * for the selected DAC channel.
575 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
576 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
577 * @param DACx DAC instance
578 * @param DAC_Channel This parameter can be one of the following values:
579 * @arg @ref LL_DAC_CHANNEL_1
580 * @arg @ref LL_DAC_CHANNEL_2 (1)
581 *
582 * (1) On this STM32 series, parameter not available on all devices.
583 * Refer to device datasheet for channels availability.
584 * @param WaveAutoGeneration This parameter can be one of the following values:
585 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
586 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
587 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
588 * @retval None
589 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)590 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
591 {
592 MODIFY_REG(DACx->CR,
593 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
594 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
595 }
596
597 /**
598 * @brief Get the waveform automatic generation mode
599 * for the selected DAC channel.
600 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
601 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
602 * @param DACx DAC instance
603 * @param DAC_Channel This parameter can be one of the following values:
604 * @arg @ref LL_DAC_CHANNEL_1
605 * @arg @ref LL_DAC_CHANNEL_2 (1)
606 *
607 * (1) On this STM32 series, parameter not available on all devices.
608 * Refer to device datasheet for channels availability.
609 * @retval Returned value can be one of the following values:
610 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
611 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
612 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
613 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)614 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
615 {
616 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
617 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
618 );
619 }
620
621 /**
622 * @brief Set the noise waveform generation for the selected DAC channel:
623 * Noise mode and parameters LFSR (linear feedback shift register).
624 * @note For wave generation to be effective, DAC channel
625 * wave generation mode must be enabled using
626 * function @ref LL_DAC_SetWaveAutoGeneration().
627 * @note This setting can be set when the selected DAC channel is disabled
628 * (otherwise, the setting operation is ignored).
629 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
630 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
631 * @param DACx DAC instance
632 * @param DAC_Channel This parameter can be one of the following values:
633 * @arg @ref LL_DAC_CHANNEL_1
634 * @arg @ref LL_DAC_CHANNEL_2 (1)
635 *
636 * (1) On this STM32 series, parameter not available on all devices.
637 * Refer to device datasheet for channels availability.
638 * @param NoiseLFSRMask This parameter can be one of the following values:
639 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
640 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
641 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
651 * @retval None
652 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)653 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
654 {
655 MODIFY_REG(DACx->CR,
656 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
657 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
658 }
659
660 /**
661 * @brief Set the noise waveform generation for the selected DAC channel:
662 * Noise mode and parameters LFSR (linear feedback shift register).
663 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
664 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
665 * @param DACx DAC instance
666 * @param DAC_Channel This parameter can be one of the following values:
667 * @arg @ref LL_DAC_CHANNEL_1
668 * @arg @ref LL_DAC_CHANNEL_2 (1)
669 *
670 * (1) On this STM32 series, parameter not available on all devices.
671 * Refer to device datasheet for channels availability.
672 * @retval Returned value can be one of the following values:
673 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
674 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
675 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
676 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
683 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
684 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
685 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)686 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
687 {
688 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
689 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
690 );
691 }
692
693 /**
694 * @brief Set the triangle waveform generation for the selected DAC channel:
695 * triangle mode and amplitude.
696 * @note For wave generation to be effective, DAC channel
697 * wave generation mode must be enabled using
698 * function @ref LL_DAC_SetWaveAutoGeneration().
699 * @note This setting can be set when the selected DAC channel is disabled
700 * (otherwise, the setting operation is ignored).
701 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
702 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
703 * @param DACx DAC instance
704 * @param DAC_Channel This parameter can be one of the following values:
705 * @arg @ref LL_DAC_CHANNEL_1
706 * @arg @ref LL_DAC_CHANNEL_2 (1)
707 *
708 * (1) On this STM32 series, parameter not available on all devices.
709 * Refer to device datasheet for channels availability.
710 * @param TriangleAmplitude This parameter can be one of the following values:
711 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
723 * @retval None
724 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)725 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
726 {
727 MODIFY_REG(DACx->CR,
728 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
729 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
730 }
731
732 /**
733 * @brief Set the triangle waveform generation for the selected DAC channel:
734 * triangle mode and amplitude.
735 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
736 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
737 * @param DACx DAC instance
738 * @param DAC_Channel This parameter can be one of the following values:
739 * @arg @ref LL_DAC_CHANNEL_1
740 * @arg @ref LL_DAC_CHANNEL_2 (1)
741 *
742 * (1) On this STM32 series, parameter not available on all devices.
743 * Refer to device datasheet for channels availability.
744 * @retval Returned value can be one of the following values:
745 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
746 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
747 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
748 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
755 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
756 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
757 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)758 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
759 {
760 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
761 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
762 );
763 }
764
765 /**
766 * @brief Set the output buffer for the selected DAC channel.
767 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
768 * CR BOFF2 LL_DAC_SetOutputBuffer
769 * @param DACx DAC instance
770 * @param DAC_Channel This parameter can be one of the following values:
771 * @arg @ref LL_DAC_CHANNEL_1
772 * @arg @ref LL_DAC_CHANNEL_2 (1)
773 *
774 * (1) On this STM32 series, parameter not available on all devices.
775 * Refer to device datasheet for channels availability.
776 * @param OutputBuffer This parameter can be one of the following values:
777 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
778 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
779 * @retval None
780 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)781 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
782 {
783 MODIFY_REG(DACx->CR,
784 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
785 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
786 }
787
788 /**
789 * @brief Get the output buffer state for the selected DAC channel.
790 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
791 * CR BOFF2 LL_DAC_GetOutputBuffer
792 * @param DACx DAC instance
793 * @param DAC_Channel This parameter can be one of the following values:
794 * @arg @ref LL_DAC_CHANNEL_1
795 * @arg @ref LL_DAC_CHANNEL_2 (1)
796 *
797 * (1) On this STM32 series, parameter not available on all devices.
798 * Refer to device datasheet for channels availability.
799 * @retval Returned value can be one of the following values:
800 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
801 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
802 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)803 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
804 {
805 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
806 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
807 );
808 }
809
810 /**
811 * @}
812 */
813
814 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
815 * @{
816 */
817
818 /**
819 * @brief Enable DAC DMA transfer request of the selected channel.
820 * @note To configure DMA source address (peripheral address),
821 * use function @ref LL_DAC_DMA_GetRegAddr().
822 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
823 * CR DMAEN2 LL_DAC_EnableDMAReq
824 * @param DACx DAC instance
825 * @param DAC_Channel This parameter can be one of the following values:
826 * @arg @ref LL_DAC_CHANNEL_1
827 * @arg @ref LL_DAC_CHANNEL_2 (1)
828 *
829 * (1) On this STM32 series, parameter not available on all devices.
830 * Refer to device datasheet for channels availability.
831 * @retval None
832 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)833 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
834 {
835 SET_BIT(DACx->CR,
836 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
837 }
838
839 /**
840 * @brief Disable DAC DMA transfer request of the selected channel.
841 * @note To configure DMA source address (peripheral address),
842 * use function @ref LL_DAC_DMA_GetRegAddr().
843 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
844 * CR DMAEN2 LL_DAC_DisableDMAReq
845 * @param DACx DAC instance
846 * @param DAC_Channel This parameter can be one of the following values:
847 * @arg @ref LL_DAC_CHANNEL_1
848 * @arg @ref LL_DAC_CHANNEL_2 (1)
849 *
850 * (1) On this STM32 series, parameter not available on all devices.
851 * Refer to device datasheet for channels availability.
852 * @retval None
853 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)854 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
855 {
856 CLEAR_BIT(DACx->CR,
857 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
858 }
859
860 /**
861 * @brief Get DAC DMA transfer request state of the selected channel.
862 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
863 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
864 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
865 * @param DACx DAC instance
866 * @param DAC_Channel This parameter can be one of the following values:
867 * @arg @ref LL_DAC_CHANNEL_1
868 * @arg @ref LL_DAC_CHANNEL_2 (1)
869 *
870 * (1) On this STM32 series, parameter not available on all devices.
871 * Refer to device datasheet for channels availability.
872 * @retval State of bit (1 or 0).
873 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)874 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
875 {
876 return (READ_BIT(DACx->CR,
877 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
878 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
879 }
880
881 /**
882 * @brief Function to help to configure DMA transfer to DAC: retrieve the
883 * DAC register address from DAC instance and a list of DAC registers
884 * intended to be used (most commonly) with DMA transfer.
885 * @note These DAC registers are data holding registers:
886 * when DAC conversion is requested, DAC generates a DMA transfer
887 * request to have data available in DAC data holding registers.
888 * @note This macro is intended to be used with LL DMA driver, refer to
889 * function "LL_DMA_ConfigAddresses()".
890 * Example:
891 * LL_DMA_ConfigAddresses(DMA1,
892 * LL_DMA_CHANNEL_1,
893 * (uint32_t)&< array or variable >,
894 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
895 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
896 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
897 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
898 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
899 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
900 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
901 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
902 * @param DACx DAC instance
903 * @param DAC_Channel This parameter can be one of the following values:
904 * @arg @ref LL_DAC_CHANNEL_1
905 * @arg @ref LL_DAC_CHANNEL_2 (1)
906 *
907 * (1) On this STM32 series, parameter not available on all devices.
908 * Refer to device datasheet for channels availability.
909 * @param Register This parameter can be one of the following values:
910 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
911 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
912 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
913 * @retval DAC register address
914 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)915 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
916 {
917 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
918 /* DAC channel selected. */
919 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
920 }
921 /**
922 * @}
923 */
924
925 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
926 * @{
927 */
928
929 /**
930 * @brief Enable DAC selected channel.
931 * @rmtoll CR EN1 LL_DAC_Enable\n
932 * CR EN2 LL_DAC_Enable
933 * @note After enable from off state, DAC channel requires a delay
934 * for output voltage to reach accuracy +/- 1 LSB.
935 * Refer to device datasheet, parameter "tWAKEUP".
936 * @param DACx DAC instance
937 * @param DAC_Channel This parameter can be one of the following values:
938 * @arg @ref LL_DAC_CHANNEL_1
939 * @arg @ref LL_DAC_CHANNEL_2 (1)
940 *
941 * (1) On this STM32 series, parameter not available on all devices.
942 * Refer to device datasheet for channels availability.
943 * @retval None
944 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)945 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
946 {
947 SET_BIT(DACx->CR,
948 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
949 }
950
951 /**
952 * @brief Disable DAC selected channel.
953 * @rmtoll CR EN1 LL_DAC_Disable\n
954 * CR EN2 LL_DAC_Disable
955 * @param DACx DAC instance
956 * @param DAC_Channel This parameter can be one of the following values:
957 * @arg @ref LL_DAC_CHANNEL_1
958 * @arg @ref LL_DAC_CHANNEL_2 (1)
959 *
960 * (1) On this STM32 series, parameter not available on all devices.
961 * Refer to device datasheet for channels availability.
962 * @retval None
963 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)964 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
965 {
966 CLEAR_BIT(DACx->CR,
967 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
968 }
969
970 /**
971 * @brief Get DAC enable state of the selected channel.
972 * (0: DAC channel is disabled, 1: DAC channel is enabled)
973 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
974 * CR EN2 LL_DAC_IsEnabled
975 * @param DACx DAC instance
976 * @param DAC_Channel This parameter can be one of the following values:
977 * @arg @ref LL_DAC_CHANNEL_1
978 * @arg @ref LL_DAC_CHANNEL_2 (1)
979 *
980 * (1) On this STM32 series, parameter not available on all devices.
981 * Refer to device datasheet for channels availability.
982 * @retval State of bit (1 or 0).
983 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)984 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
985 {
986 return (READ_BIT(DACx->CR,
987 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
988 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
989 }
990
991 /**
992 * @brief Enable DAC trigger of the selected channel.
993 * @note - If DAC trigger is disabled, DAC conversion is performed
994 * automatically once the data holding register is updated,
995 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
996 * @ref LL_DAC_ConvertData12RightAligned(), ...
997 * - If DAC trigger is enabled, DAC conversion is performed
998 * only when a hardware of software trigger event is occurring.
999 * Select trigger source using
1000 * function @ref LL_DAC_SetTriggerSource().
1001 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1002 * CR TEN2 LL_DAC_EnableTrigger
1003 * @param DACx DAC instance
1004 * @param DAC_Channel This parameter can be one of the following values:
1005 * @arg @ref LL_DAC_CHANNEL_1
1006 * @arg @ref LL_DAC_CHANNEL_2 (1)
1007 *
1008 * (1) On this STM32 series, parameter not available on all devices.
1009 * Refer to device datasheet for channels availability.
1010 * @retval None
1011 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1012 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1013 {
1014 SET_BIT(DACx->CR,
1015 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1016 }
1017
1018 /**
1019 * @brief Disable DAC trigger of the selected channel.
1020 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1021 * CR TEN2 LL_DAC_DisableTrigger
1022 * @param DACx DAC instance
1023 * @param DAC_Channel This parameter can be one of the following values:
1024 * @arg @ref LL_DAC_CHANNEL_1
1025 * @arg @ref LL_DAC_CHANNEL_2 (1)
1026 *
1027 * (1) On this STM32 series, parameter not available on all devices.
1028 * Refer to device datasheet for channels availability.
1029 * @retval None
1030 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1031 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1032 {
1033 CLEAR_BIT(DACx->CR,
1034 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1035 }
1036
1037 /**
1038 * @brief Get DAC trigger state of the selected channel.
1039 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1040 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1041 * CR TEN2 LL_DAC_IsTriggerEnabled
1042 * @param DACx DAC instance
1043 * @param DAC_Channel This parameter can be one of the following values:
1044 * @arg @ref LL_DAC_CHANNEL_1
1045 * @arg @ref LL_DAC_CHANNEL_2 (1)
1046 *
1047 * (1) On this STM32 series, parameter not available on all devices.
1048 * Refer to device datasheet for channels availability.
1049 * @retval State of bit (1 or 0).
1050 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1051 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1052 {
1053 return (READ_BIT(DACx->CR,
1054 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1055 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1056 }
1057
1058 /**
1059 * @brief Trig DAC conversion by software for the selected DAC channel.
1060 * @note Preliminarily, DAC trigger must be set to software trigger
1061 * using function @ref LL_DAC_SetTriggerSource()
1062 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1063 * and DAC trigger must be enabled using
1064 * function @ref LL_DAC_EnableTrigger().
1065 * @note For devices featuring DAC with 2 channels: this function
1066 * can perform a SW start of both DAC channels simultaneously.
1067 * Two channels can be selected as parameter.
1068 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1069 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1070 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1071 * @param DACx DAC instance
1072 * @param DAC_Channel This parameter can a combination of the following values:
1073 * @arg @ref LL_DAC_CHANNEL_1
1074 * @arg @ref LL_DAC_CHANNEL_2 (1)
1075 *
1076 * (1) On this STM32 series, parameter not available on all devices.
1077 * Refer to device datasheet for channels availability.
1078 * @retval None
1079 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1080 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1081 {
1082 SET_BIT(DACx->SWTRIGR,
1083 (DAC_Channel & DAC_SWTR_CHX_MASK));
1084 }
1085
1086 /**
1087 * @brief Set the data to be loaded in the data holding register
1088 * in format 12 bits left alignment (LSB aligned on bit 0),
1089 * for the selected DAC channel.
1090 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1091 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1092 * @param DACx DAC instance
1093 * @param DAC_Channel This parameter can be one of the following values:
1094 * @arg @ref LL_DAC_CHANNEL_1
1095 * @arg @ref LL_DAC_CHANNEL_2 (1)
1096 *
1097 * (1) On this STM32 series, parameter not available on all devices.
1098 * Refer to device datasheet for channels availability.
1099 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1100 * @retval None
1101 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1102 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1103 {
1104 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1105
1106 MODIFY_REG(*preg,
1107 DAC_DHR12R1_DACC1DHR,
1108 Data);
1109 }
1110
1111 /**
1112 * @brief Set the data to be loaded in the data holding register
1113 * in format 12 bits left alignment (MSB aligned on bit 15),
1114 * for the selected DAC channel.
1115 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1116 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1117 * @param DACx DAC instance
1118 * @param DAC_Channel This parameter can be one of the following values:
1119 * @arg @ref LL_DAC_CHANNEL_1
1120 * @arg @ref LL_DAC_CHANNEL_2 (1)
1121 *
1122 * (1) On this STM32 series, parameter not available on all devices.
1123 * Refer to device datasheet for channels availability.
1124 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1125 * @retval None
1126 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1127 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1128 {
1129 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1130
1131 MODIFY_REG(*preg,
1132 DAC_DHR12L1_DACC1DHR,
1133 Data);
1134 }
1135
1136 /**
1137 * @brief Set the data to be loaded in the data holding register
1138 * in format 8 bits left alignment (LSB aligned on bit 0),
1139 * for the selected DAC channel.
1140 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1141 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1142 * @param DACx DAC instance
1143 * @param DAC_Channel This parameter can be one of the following values:
1144 * @arg @ref LL_DAC_CHANNEL_1
1145 * @arg @ref LL_DAC_CHANNEL_2 (1)
1146 *
1147 * (1) On this STM32 series, parameter not available on all devices.
1148 * Refer to device datasheet for channels availability.
1149 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1150 * @retval None
1151 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1152 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1153 {
1154 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1155
1156 MODIFY_REG(*preg,
1157 DAC_DHR8R1_DACC1DHR,
1158 Data);
1159 }
1160
1161 #if defined(DAC_CHANNEL2_SUPPORT)
1162 /**
1163 * @brief Set the data to be loaded in the data holding register
1164 * in format 12 bits left alignment (LSB aligned on bit 0),
1165 * for both DAC channels.
1166 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1167 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1168 * @param DACx DAC instance
1169 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1170 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1171 * @retval None
1172 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1173 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1174 {
1175 MODIFY_REG(DACx->DHR12RD,
1176 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1177 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1178 }
1179
1180 /**
1181 * @brief Set the data to be loaded in the data holding register
1182 * in format 12 bits left alignment (MSB aligned on bit 15),
1183 * for both DAC channels.
1184 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1185 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1186 * @param DACx DAC instance
1187 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1188 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1189 * @retval None
1190 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1191 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1192 {
1193 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1194 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1195 /* the 4 LSB must be taken into account for the shift value. */
1196 MODIFY_REG(DACx->DHR12LD,
1197 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1198 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1199 }
1200
1201 /**
1202 * @brief Set the data to be loaded in the data holding register
1203 * in format 8 bits left alignment (LSB aligned on bit 0),
1204 * for both DAC channels.
1205 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1206 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1207 * @param DACx DAC instance
1208 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1209 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1210 * @retval None
1211 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1212 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1213 {
1214 MODIFY_REG(DACx->DHR8RD,
1215 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1216 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1217 }
1218
1219 #endif /* DAC_CHANNEL2_SUPPORT */
1220 /**
1221 * @brief Retrieve output data currently generated for the selected DAC channel.
1222 * @note Whatever alignment and resolution settings
1223 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1224 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1225 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1226 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1227 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1228 * @param DACx DAC instance
1229 * @param DAC_Channel This parameter can be one of the following values:
1230 * @arg @ref LL_DAC_CHANNEL_1
1231 * @arg @ref LL_DAC_CHANNEL_2 (1)
1232 *
1233 * (1) On this STM32 series, parameter not available on all devices.
1234 * Refer to device datasheet for channels availability.
1235 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1236 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1237 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1238 {
1239 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1240
1241 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1242 }
1243
1244 /**
1245 * @}
1246 */
1247
1248 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1249 * @{
1250 */
1251 /**
1252 * @brief Get DAC underrun flag for DAC channel 1
1253 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1254 * @param DACx DAC instance
1255 * @retval State of bit (1 or 0).
1256 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1257 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1258 {
1259 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1260 }
1261
1262 #if defined(DAC_CHANNEL2_SUPPORT)
1263 /**
1264 * @brief Get DAC underrun flag for DAC channel 2
1265 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1266 * @param DACx DAC instance
1267 * @retval State of bit (1 or 0).
1268 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1269 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1270 {
1271 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1272 }
1273 #endif /* DAC_CHANNEL2_SUPPORT */
1274
1275 /**
1276 * @brief Clear DAC underrun flag for DAC channel 1
1277 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1278 * @param DACx DAC instance
1279 * @retval None
1280 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1281 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1282 {
1283 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1284 }
1285
1286 #if defined(DAC_CHANNEL2_SUPPORT)
1287 /**
1288 * @brief Clear DAC underrun flag for DAC channel 2
1289 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1290 * @param DACx DAC instance
1291 * @retval None
1292 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1293 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1294 {
1295 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1296 }
1297 #endif /* DAC_CHANNEL2_SUPPORT */
1298
1299 /**
1300 * @}
1301 */
1302
1303 /** @defgroup DAC_LL_EF_IT_Management IT management
1304 * @{
1305 */
1306
1307 /**
1308 * @brief Enable DMA underrun interrupt for DAC channel 1
1309 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1310 * @param DACx DAC instance
1311 * @retval None
1312 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1313 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1314 {
1315 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1316 }
1317
1318 #if defined(DAC_CHANNEL2_SUPPORT)
1319 /**
1320 * @brief Enable DMA underrun interrupt for DAC channel 2
1321 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1322 * @param DACx DAC instance
1323 * @retval None
1324 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1325 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1326 {
1327 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1328 }
1329 #endif /* DAC_CHANNEL2_SUPPORT */
1330
1331 /**
1332 * @brief Disable DMA underrun interrupt for DAC channel 1
1333 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1334 * @param DACx DAC instance
1335 * @retval None
1336 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1337 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1338 {
1339 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1340 }
1341
1342 #if defined(DAC_CHANNEL2_SUPPORT)
1343 /**
1344 * @brief Disable DMA underrun interrupt for DAC channel 2
1345 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1346 * @param DACx DAC instance
1347 * @retval None
1348 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1349 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1350 {
1351 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1352 }
1353 #endif /* DAC_CHANNEL2_SUPPORT */
1354
1355 /**
1356 * @brief Get DMA underrun interrupt for DAC channel 1
1357 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1358 * @param DACx DAC instance
1359 * @retval State of bit (1 or 0).
1360 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1361 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1362 {
1363 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1364 }
1365
1366 #if defined(DAC_CHANNEL2_SUPPORT)
1367 /**
1368 * @brief Get DMA underrun interrupt for DAC channel 2
1369 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1370 * @param DACx DAC instance
1371 * @retval State of bit (1 or 0).
1372 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1373 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1374 {
1375 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1376 }
1377 #endif /* DAC_CHANNEL2_SUPPORT */
1378
1379 /**
1380 * @}
1381 */
1382
1383 #if defined(USE_FULL_LL_DRIVER)
1384 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1385 * @{
1386 */
1387
1388 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1389 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1390 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1391
1392 /**
1393 * @}
1394 */
1395 #endif /* USE_FULL_LL_DRIVER */
1396
1397 /**
1398 * @}
1399 */
1400
1401 /**
1402 * @}
1403 */
1404
1405 #endif /* DAC1 */
1406
1407 /**
1408 * @}
1409 */
1410
1411 #ifdef __cplusplus
1412 }
1413 #endif
1414
1415 #endif /* __STM32L0xx_LL_DAC_H */
1416
1417
