1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L0xx_LL_CRS_H
21 #define __STM32L0xx_LL_CRS_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l0xx.h"
29
30 /** @addtogroup STM32L0xx_LL_Driver
31 * @{
32 */
33
34 #if defined(CRS)
35
36 /** @defgroup CRS_LL CRS
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
45 * @{
46 */
47
48 /* Defines used for the bit position in the register and perform offsets*/
49 #define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
50 #define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
51 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
52
53
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
63 * @{
64 */
65
66 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
67 * @brief Flags defines which can be used with LL_CRS_ReadReg function
68 * @{
69 */
70 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
71 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
72 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
73 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
74 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
75 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
76 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
77 /**
78 * @}
79 */
80
81 /** @defgroup CRS_LL_EC_IT IT Defines
82 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
83 * @{
84 */
85 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
86 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
87 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
88 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
89 /**
90 * @}
91 */
92
93 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
94 * @{
95 */
96 #define LL_CRS_SYNC_DIV_1 (0x00U) /*!< Synchro Signal not divided (default) */
97 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
98 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
99 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
100 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
101 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
102 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
103 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
104 /**
105 * @}
106 */
107
108 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
109 * @{
110 */
111 #define LL_CRS_SYNC_SOURCE_GPIO (0x00U) /*!< Synchro Signal source GPIO */
112 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
113 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
114 /**
115 * @}
116 */
117
118 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
119 * @{
120 */
121 #define LL_CRS_SYNC_POLARITY_RISING (0x00U) /*!< Synchro Active on rising edge (default) */
122 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
123 /**
124 * @}
125 */
126
127 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
128 * @{
129 */
130 #define LL_CRS_FREQ_ERROR_DIR_UP (0x00U) /*!< Upcounting direction, the actual frequency is above the target */
131 #define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
132 /**
133 * @}
134 */
135
136 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
137 * @{
138 */
139 /**
140 * @brief Reset value of the RELOAD field
141 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
142 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
143 */
144 #define LL_CRS_RELOADVALUE_DEFAULT (0xBB7FU)
145
146 /**
147 * @brief Reset value of Frequency error limit.
148 */
149 #define LL_CRS_ERRORLIMIT_DEFAULT (0x22U)
150
151 /**
152 * @brief Reset value of the HSI48 Calibration field
153 * @note The default value is 32, which corresponds to the middle of the trimming interval.
154 * The trimming step is around 67 kHz between two consecutive TRIM steps.
155 * A higher TRIM value corresponds to a higher output frequency
156 */
157 #define LL_CRS_HSI48CALIBRATION_DEFAULT (0x20U)
158 /**
159 * @}
160 */
161
162 /**
163 * @}
164 */
165
166 /* Exported macro ------------------------------------------------------------*/
167 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
168 * @{
169 */
170
171 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
172 * @{
173 */
174
175 /**
176 * @brief Write a value in CRS register
177 * @param __INSTANCE__ CRS Instance
178 * @param __REG__ Register to be written
179 * @param __VALUE__ Value to be written in the register
180 * @retval None
181 */
182 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
183
184 /**
185 * @brief Read a value in CRS register
186 * @param __INSTANCE__ CRS Instance
187 * @param __REG__ Register to be read
188 * @retval Register value
189 */
190 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
191 /**
192 * @}
193 */
194
195 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
196 * @{
197 */
198
199 /**
200 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
201 * @note The RELOAD value should be selected according to the ratio between
202 * the target frequency and the frequency of the synchronization source after
203 * prescaling. It is then decreased by one in order to reach the expected
204 * synchronization on the zero value. The formula is the following:
205 * RELOAD = (fTARGET / fSYNC) -1
206 * @param __FTARGET__ Target frequency (value in Hz)
207 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
208 * @retval Reload value (in Hz)
209 */
210 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
211
212 /**
213 * @}
214 */
215
216 /**
217 * @}
218 */
219
220 /* Exported functions --------------------------------------------------------*/
221 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
222 * @{
223 */
224
225 /** @defgroup CRS_LL_EF_Configuration Configuration
226 * @{
227 */
228
229 /**
230 * @brief Enable Frequency error counter
231 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
232 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
233 * @retval None
234 */
LL_CRS_EnableFreqErrorCounter(void)235 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
236 {
237 SET_BIT(CRS->CR, CRS_CR_CEN);
238 }
239
240 /**
241 * @brief Disable Frequency error counter
242 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
243 * @retval None
244 */
LL_CRS_DisableFreqErrorCounter(void)245 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
246 {
247 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
248 }
249
250 /**
251 * @brief Check if Frequency error counter is enabled or not
252 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
253 * @retval State of bit (1 or 0).
254 */
LL_CRS_IsEnabledFreqErrorCounter(void)255 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
256 {
257 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
258 }
259
260 /**
261 * @brief Enable Automatic trimming counter
262 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
263 * @retval None
264 */
LL_CRS_EnableAutoTrimming(void)265 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
266 {
267 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
268 }
269
270 /**
271 * @brief Disable Automatic trimming counter
272 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
273 * @retval None
274 */
LL_CRS_DisableAutoTrimming(void)275 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
276 {
277 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
278 }
279
280 /**
281 * @brief Check if Automatic trimming is enabled or not
282 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
283 * @retval State of bit (1 or 0).
284 */
LL_CRS_IsEnabledAutoTrimming(void)285 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
286 {
287 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
288 }
289
290 /**
291 * @brief Set HSI48 oscillator smooth trimming
292 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
293 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
294 * @param Value a number between Min_Data = 0 and Max_Data = 63
295 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
296 * @retval None
297 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)298 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
299 {
300 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
301 }
302
303 /**
304 * @brief Get HSI48 oscillator smooth trimming
305 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
306 * @retval a number between Min_Data = 0 and Max_Data = 63
307 */
LL_CRS_GetHSI48SmoothTrimming(void)308 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
309 {
310 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
311 }
312
313 /**
314 * @brief Set counter reload value
315 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
316 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
317 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
318 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
319 * @retval None
320 */
LL_CRS_SetReloadCounter(uint32_t Value)321 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
322 {
323 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
324 }
325
326 /**
327 * @brief Get counter reload value
328 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
329 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
330 */
LL_CRS_GetReloadCounter(void)331 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
332 {
333 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
334 }
335
336 /**
337 * @brief Set frequency error limit
338 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
339 * @param Value a number between Min_Data = 0 and Max_Data = 255
340 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
341 * @retval None
342 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)343 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
344 {
345 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
346 }
347
348 /**
349 * @brief Get frequency error limit
350 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
351 * @retval A number between Min_Data = 0 and Max_Data = 255
352 */
LL_CRS_GetFreqErrorLimit(void)353 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
354 {
355 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
356 }
357
358 /**
359 * @brief Set division factor for SYNC signal
360 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
361 * @param Divider This parameter can be one of the following values:
362 * @arg @ref LL_CRS_SYNC_DIV_1
363 * @arg @ref LL_CRS_SYNC_DIV_2
364 * @arg @ref LL_CRS_SYNC_DIV_4
365 * @arg @ref LL_CRS_SYNC_DIV_8
366 * @arg @ref LL_CRS_SYNC_DIV_16
367 * @arg @ref LL_CRS_SYNC_DIV_32
368 * @arg @ref LL_CRS_SYNC_DIV_64
369 * @arg @ref LL_CRS_SYNC_DIV_128
370 * @retval None
371 */
LL_CRS_SetSyncDivider(uint32_t Divider)372 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
373 {
374 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
375 }
376
377 /**
378 * @brief Get division factor for SYNC signal
379 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
380 * @retval Returned value can be one of the following values:
381 * @arg @ref LL_CRS_SYNC_DIV_1
382 * @arg @ref LL_CRS_SYNC_DIV_2
383 * @arg @ref LL_CRS_SYNC_DIV_4
384 * @arg @ref LL_CRS_SYNC_DIV_8
385 * @arg @ref LL_CRS_SYNC_DIV_16
386 * @arg @ref LL_CRS_SYNC_DIV_32
387 * @arg @ref LL_CRS_SYNC_DIV_64
388 * @arg @ref LL_CRS_SYNC_DIV_128
389 */
LL_CRS_GetSyncDivider(void)390 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
391 {
392 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
393 }
394
395 /**
396 * @brief Set SYNC signal source
397 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
398 * @param Source This parameter can be one of the following values:
399 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
400 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
401 * @arg @ref LL_CRS_SYNC_SOURCE_USB
402 * @retval None
403 */
LL_CRS_SetSyncSignalSource(uint32_t Source)404 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
405 {
406 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
407 }
408
409 /**
410 * @brief Get SYNC signal source
411 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
412 * @retval Returned value can be one of the following values:
413 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
414 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
415 * @arg @ref LL_CRS_SYNC_SOURCE_USB
416 */
LL_CRS_GetSyncSignalSource(void)417 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
418 {
419 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
420 }
421
422 /**
423 * @brief Set input polarity for the SYNC signal source
424 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
425 * @param Polarity This parameter can be one of the following values:
426 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
427 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
428 * @retval None
429 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)430 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
431 {
432 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
433 }
434
435 /**
436 * @brief Get input polarity for the SYNC signal source
437 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
438 * @retval Returned value can be one of the following values:
439 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
440 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
441 */
LL_CRS_GetSyncPolarity(void)442 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
443 {
444 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
445 }
446
447 /**
448 * @brief Configure CRS for the synchronization
449 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
450 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
451 * CFGR FELIM LL_CRS_ConfigSynchronization\n
452 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
453 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
454 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
455 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
456 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
457 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
458 * @param Settings This parameter can be a combination of the following values:
459 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
460 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
461 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
462 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
463 * @retval None
464 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)465 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
466 {
467 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
468 MODIFY_REG(CRS->CFGR,
469 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
470 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
471 }
472
473 /**
474 * @}
475 */
476
477 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
478 * @{
479 */
480
481 /**
482 * @brief Generate software SYNC event
483 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
484 * @retval None
485 */
LL_CRS_GenerateEvent_SWSYNC(void)486 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
487 {
488 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
489 }
490
491 /**
492 * @brief Get the frequency error direction latched in the time of the last
493 * SYNC event
494 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
495 * @retval Returned value can be one of the following values:
496 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
497 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
498 */
LL_CRS_GetFreqErrorDirection(void)499 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
500 {
501 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
502 }
503
504 /**
505 * @brief Get the frequency error counter value latched in the time of the last SYNC event
506 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
507 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
508 */
LL_CRS_GetFreqErrorCapture(void)509 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
510 {
511 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
512 }
513
514 /**
515 * @}
516 */
517
518 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
519 * @{
520 */
521
522 /**
523 * @brief Check if SYNC event OK signal occurred or not
524 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
525 * @retval State of bit (1 or 0).
526 */
LL_CRS_IsActiveFlag_SYNCOK(void)527 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
528 {
529 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
530 }
531
532 /**
533 * @brief Check if SYNC warning signal occurred or not
534 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
535 * @retval State of bit (1 or 0).
536 */
LL_CRS_IsActiveFlag_SYNCWARN(void)537 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
538 {
539 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
540 }
541
542 /**
543 * @brief Check if Synchronization or trimming error signal occurred or not
544 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
545 * @retval State of bit (1 or 0).
546 */
LL_CRS_IsActiveFlag_ERR(void)547 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
548 {
549 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
550 }
551
552 /**
553 * @brief Check if Expected SYNC signal occurred or not
554 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
555 * @retval State of bit (1 or 0).
556 */
LL_CRS_IsActiveFlag_ESYNC(void)557 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
558 {
559 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
560 }
561
562 /**
563 * @brief Check if SYNC error signal occurred or not
564 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
565 * @retval State of bit (1 or 0).
566 */
LL_CRS_IsActiveFlag_SYNCERR(void)567 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
568 {
569 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
570 }
571
572 /**
573 * @brief Check if SYNC missed error signal occurred or not
574 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
575 * @retval State of bit (1 or 0).
576 */
LL_CRS_IsActiveFlag_SYNCMISS(void)577 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
578 {
579 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
580 }
581
582 /**
583 * @brief Check if Trimming overflow or underflow occurred or not
584 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
585 * @retval State of bit (1 or 0).
586 */
LL_CRS_IsActiveFlag_TRIMOVF(void)587 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
588 {
589 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
590 }
591
592 /**
593 * @brief Clear the SYNC event OK flag
594 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
595 * @retval None
596 */
LL_CRS_ClearFlag_SYNCOK(void)597 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
598 {
599 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
600 }
601
602 /**
603 * @brief Clear the SYNC warning flag
604 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
605 * @retval None
606 */
LL_CRS_ClearFlag_SYNCWARN(void)607 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
608 {
609 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
610 }
611
612 /**
613 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
614 * the ERR flag
615 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
616 * @retval None
617 */
LL_CRS_ClearFlag_ERR(void)618 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
619 {
620 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
621 }
622
623 /**
624 * @brief Clear Expected SYNC flag
625 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
626 * @retval None
627 */
LL_CRS_ClearFlag_ESYNC(void)628 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
629 {
630 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
631 }
632
633 /**
634 * @}
635 */
636
637 /** @defgroup CRS_LL_EF_IT_Management IT_Management
638 * @{
639 */
640
641 /**
642 * @brief Enable SYNC event OK interrupt
643 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
644 * @retval None
645 */
LL_CRS_EnableIT_SYNCOK(void)646 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
647 {
648 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
649 }
650
651 /**
652 * @brief Disable SYNC event OK interrupt
653 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
654 * @retval None
655 */
LL_CRS_DisableIT_SYNCOK(void)656 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
657 {
658 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
659 }
660
661 /**
662 * @brief Check if SYNC event OK interrupt is enabled or not
663 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
664 * @retval State of bit (1 or 0).
665 */
LL_CRS_IsEnabledIT_SYNCOK(void)666 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
667 {
668 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
669 }
670
671 /**
672 * @brief Enable SYNC warning interrupt
673 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
674 * @retval None
675 */
LL_CRS_EnableIT_SYNCWARN(void)676 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
677 {
678 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
679 }
680
681 /**
682 * @brief Disable SYNC warning interrupt
683 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
684 * @retval None
685 */
LL_CRS_DisableIT_SYNCWARN(void)686 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
687 {
688 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
689 }
690
691 /**
692 * @brief Check if SYNC warning interrupt is enabled or not
693 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
694 * @retval State of bit (1 or 0).
695 */
LL_CRS_IsEnabledIT_SYNCWARN(void)696 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
697 {
698 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
699 }
700
701 /**
702 * @brief Enable Synchronization or trimming error interrupt
703 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
704 * @retval None
705 */
LL_CRS_EnableIT_ERR(void)706 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
707 {
708 SET_BIT(CRS->CR, CRS_CR_ERRIE);
709 }
710
711 /**
712 * @brief Disable Synchronization or trimming error interrupt
713 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
714 * @retval None
715 */
LL_CRS_DisableIT_ERR(void)716 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
717 {
718 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
719 }
720
721 /**
722 * @brief Check if Synchronization or trimming error interrupt is enabled or not
723 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
724 * @retval State of bit (1 or 0).
725 */
LL_CRS_IsEnabledIT_ERR(void)726 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
727 {
728 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
729 }
730
731 /**
732 * @brief Enable Expected SYNC interrupt
733 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
734 * @retval None
735 */
LL_CRS_EnableIT_ESYNC(void)736 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
737 {
738 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
739 }
740
741 /**
742 * @brief Disable Expected SYNC interrupt
743 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
744 * @retval None
745 */
LL_CRS_DisableIT_ESYNC(void)746 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
747 {
748 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
749 }
750
751 /**
752 * @brief Check if Expected SYNC interrupt is enabled or not
753 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
754 * @retval State of bit (1 or 0).
755 */
LL_CRS_IsEnabledIT_ESYNC(void)756 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
757 {
758 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
759 }
760
761 /**
762 * @}
763 */
764
765 #if defined(USE_FULL_LL_DRIVER)
766 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
767 * @{
768 */
769
770 ErrorStatus LL_CRS_DeInit(void);
771
772 /**
773 * @}
774 */
775 #endif /* USE_FULL_LL_DRIVER */
776
777 /**
778 * @}
779 */
780
781 /**
782 * @}
783 */
784
785 #endif /* defined(CRS) */
786
787 /**
788 * @}
789 */
790
791 #ifdef __cplusplus
792 }
793 #endif
794
795 #endif /* __STM32L0xx_LL_CRS_H */
796
