1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2022 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7RSxx_LL_RCC_H
22 #define STM32H7RSxx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7rsxx.h"
30 #include <math.h>
31
32 /** @addtogroup STM32H7RSxx_LL_Driver
33 * @{
34 */
35
36 #if defined(RCC)
37
38 /** @defgroup RCC_LL RCC
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
46 * @{
47 */
48 /*
49 LL_CLKSOURCE() macro output description
50
51 31 24 16 8 0
52 --------------------------------------------------------
53 | Mask | ClkSource | Bit | Register |
54 | | Config | Position | Offset |
55 --------------------------------------------------------
56 */
57 #define LL_RCC_REG_SHIFT 0U
58 #define LL_RCC_POS_SHIFT 8U
59 #define LL_RCC_CONFIG_SHIFT 16U
60 #define LL_RCC_MASK_SHIFT 24U
61
62 /* Clock source register offset vs CCIPR1 register */
63 #define CCIPR1_OFFSET 0x0UL
64 #define CCIPR2_OFFSET 0x4UL
65 #define CCIPR3_OFFSET 0x8UL
66 #define CCIPR4_OFFSET 0xCUL
67
68 /**
69 * @}
70 */
71
72 /* Private macros ------------------------------------------------------------*/
73 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
74 * @{
75 */
76 #if !defined(UNUSED)
77 #define UNUSED(x) ((void)(x))
78 #endif
79
80 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
81
82 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) &\
83 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
84
85 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) &\
86 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
87
88 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
89
90 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
91 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
92 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
93 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
94
95 /**
96 * @}
97 */
98
99 /* Exported types ------------------------------------------------------------*/
100 #if defined(USE_FULL_LL_DRIVER)
101 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
102 * @{
103 */
104
105 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
106 * @{
107 */
108
109 /**
110 * @brief RCC Clocks Frequency Structure
111 */
112 typedef struct
113 {
114 uint32_t SYSCLK_Frequency;
115 uint32_t CPUCLK_Frequency;
116 uint32_t HCLK_Frequency;
117 uint32_t PCLK1_Frequency;
118 uint32_t PCLK2_Frequency;
119 uint32_t PCLK4_Frequency;
120 uint32_t PCLK5_Frequency;
121 } LL_RCC_ClocksTypeDef;
122
123 /**
124 * @}
125 */
126
127 /**
128 * @brief PLL Clocks Frequency Structure
129 */
130 typedef struct
131 {
132 uint32_t PLL_P_Frequency;
133 uint32_t PLL_Q_Frequency;
134 uint32_t PLL_R_Frequency;
135 uint32_t PLL_S_Frequency;
136 uint32_t PLL_T_Frequency;
137 } LL_PLL_ClocksTypeDef;
138
139 /**
140 * @brief PLL Spread Spectrum Mode Structure
141 */
142 typedef struct
143 {
144 uint16_t ModulationPeriod; /* Modulation Period (value between 0 to 2^13-1) */
145 uint16_t IncrementStep; /* Modulation Depth (value between 0 to 2^15-1) */
146 uint16_t SpreadMode; /* LL_RCC_PLL_SPREAD_CENTER or LL_RCC_PLL_SPREAD_DOWN */
147 uint16_t DitheringRPDFN; /* Rectangular probability density function noise enable/disable */
148 uint16_t DitheringTPDFN; /* Triangular probability density function noise enable/disable */
149 } LL_PLL_SpreadSpectrumTypeDef;
150
151 /**
152 * @}
153 */
154
155 #endif /* USE_FULL_LL_DRIVER */
156
157 /* Exported variables --------------------------------------------------------*/
158 /** @defgroup RCC_LL_Exported_Variables RCC Exported Variables
159 * @{
160 */
161 extern const uint8_t LL_RCC_PrescTable[16];
162
163 /**
164 * @}
165 */
166
167 /* Exported constants --------------------------------------------------------*/
168 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
169 * @{
170 */
171
172 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
173 * @brief Defines used to adapt values of different oscillators
174 * @note These values could be modified in the user environment according to
175 * HW set-up.
176 * @{
177 */
178 #if !defined (HSE_VALUE)
179 #define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */
180 #endif /* HSE_VALUE */
181
182 #if !defined (HSI_VALUE)
183 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
184 #endif /* HSI_VALUE */
185
186 #if !defined (CSI_VALUE)
187 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */
188 #endif /* CSI_VALUE */
189
190 #if !defined (LSE_VALUE)
191 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
192 #endif /* LSE_VALUE */
193
194 #if !defined (LSI_VALUE)
195 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
196 #endif /* LSI_VALUE */
197
198 #if !defined (EXTERNAL_CLOCK_VALUE)
199 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
200 #endif /* EXTERNAL_CLOCK_VALUE */
201
202 #if !defined (HSI48_VALUE)
203 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
204 #endif /* HSI48_VALUE */
205
206 /**
207 * @}
208 */
209
210 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
211 * @{
212 */
213 #define LL_RCC_HSI_DIV_1 0U
214 #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0
215 #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1
216 #define LL_RCC_HSI_DIV_8 RCC_CR_HSIDIV
217 /**
218 * @}
219 */
220
221 /** @defgroup LL_RCC_EC_XSPI1SWP XSXPI1 kernel clock switch position
222 * @{
223 */
224 #define LL_RCC_SWP_XSPI1_NEUTRAL 0U
225 #define LL_RCC_SWP_XSPI1_HCLK5 RCC_CKPROTR_XSPI1SWP_0
226 #define LL_RCC_SWP_XSPI1_PLL2S RCC_CKPROTR_XSPI1SWP_1
227 #define LL_RCC_SWP_XSPI1_PLL2T (RCC_CKPROTR_XSPI1SWP_1 | RCC_CKPROTR_XSPI1SWP_0)
228 #define LL_RCC_SWP_XSPI1_HCLK_DIV4 RCC_CKPROTR_XSPI1SWP_2
229 /**
230 * @}
231 */
232
233 /** @defgroup LL_RCC_EC_XSPI2SWP SXPI2 kernel clock switch position
234 * @{
235 */
236 #define LL_RCC_SWP_XSPI2_NEUTRAL 0U
237 #define LL_RCC_SWP_XSPI2_HCLK5 RCC_CKPROTR_XSPI2SWP_0
238 #define LL_RCC_SWP_XSPI2_PLL2S RCC_CKPROTR_XSPI2SWP_1
239 #define LL_RCC_SWP_XSPI2_PLL2T (RCC_CKPROTR_XSPI2SWP_1 | RCC_CKPROTR_XSPI2SWP_0)
240 #define LL_RCC_SWP_XSPI2_HCLK_DIV4 RCC_CKPROTR_XSPI2SWP_2
241 /**
242 * @}
243 */
244
245 /** @defgroup RCC_LL_EC_FMCSWP FMC kernel clock switch position
246 * @{
247 */
248 #define LL_RCC_SWP_FMC_NEUTRAL 0U
249 #define LL_RCC_SWP_FMC_HCLK5 RCC_CKPROTR_FMCSWP_0
250 #define LL_RCC_SWP_FMC_PLL1Q RCC_CKPROTR_FMCSWP_1
251 #define LL_RCC_SWP_FMC_PLL2R (RCC_CKPROTR_FMCSWP_1 | RCC_CKPROTR_FMCSWP_0)
252 #define LL_RCC_SWP_FMC_HSI RCC_CKPROTR_FMCSWP_2
253 #define LL_RCC_SWP_FMC_HCLK_DIV4 (RCC_CKPROTR_FMCSWP_2 | RCC_CKPROTR_FMCSWP_0)
254 /**
255 * @}
256 */
257
258 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
259 * @{
260 */
261 #define LL_RCC_LSEDRIVE_LOW 0U
262 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0
263 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1
264 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
265 /**
266 * @}
267 */
268
269 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
270 * @{
271 */
272 #define LL_RCC_SYS_CLKSOURCE_HSI 0U
273 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_0
274 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1
275 #define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
276 /**
277 * @}
278 */
279
280 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
281 * @{
282 */
283 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */
284 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_0 /*!< CSI used as system clock */
285 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
286 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL1 used as system clock */
287 /**
288 * @}
289 */
290
291 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source
292 * @{
293 */
294 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI 0U
295 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI RCC_CFGR_STOPWUCK
296 /**
297 * @}
298 */
299
300 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source
301 * @{
302 */
303 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI 0U
304 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI RCC_CFGR_STOPKERWUCK
305 /**
306 * @}
307 */
308
309 /** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler
310 * @{
311 */
312 #define LL_RCC_SYSCLK_DIV_1 0U
313 #define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR_CPRE_3
314 #define LL_RCC_SYSCLK_DIV_4 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_0)
315 #define LL_RCC_SYSCLK_DIV_8 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1)
316 #define LL_RCC_SYSCLK_DIV_16 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_1 | RCC_CDCFGR_CPRE_0)
317 #define LL_RCC_SYSCLK_DIV_64 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2)
318 #define LL_RCC_SYSCLK_DIV_128 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_0)
319 #define LL_RCC_SYSCLK_DIV_256 (RCC_CDCFGR_CPRE_3 | RCC_CDCFGR_CPRE_2 | RCC_CDCFGR_CPRE_1)
320 #define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR_CPRE
321 /**
322 * @}
323 */
324
325 /** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler
326 * @{
327 */
328 #define LL_RCC_AHB_DIV_1 0U
329 #define LL_RCC_AHB_DIV_2 RCC_BMCFGR_BMPRE_3
330 #define LL_RCC_AHB_DIV_4 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_0)
331 #define LL_RCC_AHB_DIV_8 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1)
332 #define LL_RCC_AHB_DIV_16 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_1 | RCC_BMCFGR_BMPRE_0)
333 #define LL_RCC_AHB_DIV_64 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2)
334 #define LL_RCC_AHB_DIV_128 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_0)
335 #define LL_RCC_AHB_DIV_256 (RCC_BMCFGR_BMPRE_3 | RCC_BMCFGR_BMPRE_2 | RCC_BMCFGR_BMPRE_1)
336 #define LL_RCC_AHB_DIV_512 RCC_BMCFGR_BMPRE
337 /**
338 * @}
339 */
340
341 /** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
342 * @{
343 */
344 #define LL_RCC_APB1_DIV_1 0U
345 #define LL_RCC_APB1_DIV_2 RCC_APBCFGR_PPRE1_2
346 #define LL_RCC_APB1_DIV_4 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_0)
347 #define LL_RCC_APB1_DIV_8 (RCC_APBCFGR_PPRE1_2 | RCC_APBCFGR_PPRE1_1)
348 #define LL_RCC_APB1_DIV_16 RCC_APBCFGR_PPRE1
349 /**
350 * @}
351 */
352
353 /** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
354 * @{
355 */
356 #define LL_RCC_APB2_DIV_1 0U
357 #define LL_RCC_APB2_DIV_2 RCC_APBCFGR_PPRE2_2
358 #define LL_RCC_APB2_DIV_4 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_0)
359 #define LL_RCC_APB2_DIV_8 (RCC_APBCFGR_PPRE2_2 | RCC_APBCFGR_PPRE2_1)
360 #define LL_RCC_APB2_DIV_16 RCC_APBCFGR_PPRE2
361 /**
362 * @}
363 */
364
365 /** @defgroup RCC_LL_EC_APB4_DIV APB4 prescaler
366 * @{
367 */
368 #define LL_RCC_APB4_DIV_1 0U
369 #define LL_RCC_APB4_DIV_2 RCC_APBCFGR_PPRE4_2
370 #define LL_RCC_APB4_DIV_4 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_0)
371 #define LL_RCC_APB4_DIV_8 (RCC_APBCFGR_PPRE4_2 | RCC_APBCFGR_PPRE4_1)
372 #define LL_RCC_APB4_DIV_16 RCC_APBCFGR_PPRE4
373 /**
374 * @}
375 */
376
377 /** @defgroup RCC_LL_EC_APB5_DIV APB5 prescaler
378 * @{
379 */
380 #define LL_RCC_APB5_DIV_1 0U
381 #define LL_RCC_APB5_DIV_2 RCC_APBCFGR_PPRE5_2
382 #define LL_RCC_APB5_DIV_4 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_0)
383 #define LL_RCC_APB5_DIV_8 (RCC_APBCFGR_PPRE5_2 | RCC_APBCFGR_PPRE5_1)
384 #define LL_RCC_APB5_DIV_16 RCC_APBCFGR_PPRE5
385 /**
386 * @}
387 */
388
389
390 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
391 * @{
392 */
393 #define LL_RCC_MCO1SOURCE_HSI ((RCC_CFGR_MCO1SEL>>16U) | 0U)
394 #define LL_RCC_MCO1SOURCE_LSE ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_0)
395 #define LL_RCC_MCO1SOURCE_HSE ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_1)
396 #define LL_RCC_MCO1SOURCE_PLL1Q ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_1 | RCC_CFGR_MCO1SEL_0)
397 #define LL_RCC_MCO1SOURCE_HSI48 ((RCC_CFGR_MCO1SEL>>16U) | RCC_CFGR_MCO1SEL_2)
398 #define LL_RCC_MCO2SOURCE_SYSCLK ((RCC_CFGR_MCO2SEL>>16U) | 0U)
399 #define LL_RCC_MCO2SOURCE_PLL2P ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_0)
400 #define LL_RCC_MCO2SOURCE_HSE ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_1)
401 #define LL_RCC_MCO2SOURCE_PLL1P ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0)
402 #define LL_RCC_MCO2SOURCE_CSI ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2)
403 #define LL_RCC_MCO2SOURCE_LSI ((RCC_CFGR_MCO2SEL>>16U) | RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0)
404 /**
405 * @}
406 */
407
408 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
409 * @{
410 */
411 #define LL_RCC_MCO1_DIV_1 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
412 #define LL_RCC_MCO1_DIV_2 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
413 #define LL_RCC_MCO1_DIV_3 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
414 #define LL_RCC_MCO1_DIV_4 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
415 #define LL_RCC_MCO1_DIV_5 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
416 #define LL_RCC_MCO1_DIV_6 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
417 #define LL_RCC_MCO1_DIV_7 ((RCC_CFGR_MCO1PRE>>16U) |\
418 RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
419 #define LL_RCC_MCO1_DIV_8 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
420 #define LL_RCC_MCO1_DIV_9 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
421 #define LL_RCC_MCO1_DIV_10 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
422 #define LL_RCC_MCO1_DIV_11 ((RCC_CFGR_MCO1PRE>>16U) |\
423 RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
424 #define LL_RCC_MCO1_DIV_12 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
425 #define LL_RCC_MCO1_DIV_13 ((RCC_CFGR_MCO1PRE>>16U) |\
426 RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
427 #define LL_RCC_MCO1_DIV_14 ((RCC_CFGR_MCO1PRE>>16U) |\
428 RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
429 #define LL_RCC_MCO1_DIV_15 ((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
430 #define LL_RCC_MCO2_DIV_1 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
431 #define LL_RCC_MCO2_DIV_2 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
432 #define LL_RCC_MCO2_DIV_3 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
433 #define LL_RCC_MCO2_DIV_4 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
434 #define LL_RCC_MCO2_DIV_5 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
435 #define LL_RCC_MCO2_DIV_6 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
436 #define LL_RCC_MCO2_DIV_7 ((RCC_CFGR_MCO2PRE>>16U) |\
437 RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
438 #define LL_RCC_MCO2_DIV_8 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
439 #define LL_RCC_MCO2_DIV_9 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
440 #define LL_RCC_MCO2_DIV_10 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
441 #define LL_RCC_MCO2_DIV_11 ((RCC_CFGR_MCO2PRE>>16U) |\
442 RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
443 #define LL_RCC_MCO2_DIV_12 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
444 #define LL_RCC_MCO2_DIV_13 ((RCC_CFGR_MCO2PRE>>16U) |\
445 RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
446 #define LL_RCC_MCO2_DIV_14 ((RCC_CFGR_MCO2PRE>>16U) |\
447 RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
448 #define LL_RCC_MCO2_DIV_15 ((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
449
450 /**
451 * @}
452 */
453
454 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
455 * @{
456 */
457 #define LL_RCC_RTC_NOCLOCK 0U
458 #define LL_RCC_RTC_HSE_DIV_2 (RCC_CFGR_RTCPRE_1)
459 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
460 #define LL_RCC_RTC_HSE_DIV_4 (RCC_CFGR_RTCPRE_2)
461 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
462 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
463 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
464 #define LL_RCC_RTC_HSE_DIV_8 (RCC_CFGR_RTCPRE_3)
465 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0)
466 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1)
467 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
468 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2)
469 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
470 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
471 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3 |\
472 RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
473 #define LL_RCC_RTC_HSE_DIV_16 (RCC_CFGR_RTCPRE_4)
474 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_0)
475 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1)
476 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
477 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2)
478 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
479 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
480 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4 |\
481 RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
482 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3)
483 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0)
484 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1)
485 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4 |\
486 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
487 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2)
488 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4 |\
489 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
490 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4 |\
491 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
492 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4 |\
493 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
494 #define LL_RCC_RTC_HSE_DIV_32 (RCC_CFGR_RTCPRE_5)
495 #define LL_RCC_RTC_HSE_DIV_33 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_0)
496 #define LL_RCC_RTC_HSE_DIV_34 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_1)
497 #define LL_RCC_RTC_HSE_DIV_35 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
498 #define LL_RCC_RTC_HSE_DIV_36 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_2)
499 #define LL_RCC_RTC_HSE_DIV_37 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
500 #define LL_RCC_RTC_HSE_DIV_38 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
501 #define LL_RCC_RTC_HSE_DIV_39 (RCC_CFGR_RTCPRE_5 |\
502 RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
503 #define LL_RCC_RTC_HSE_DIV_40 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3)
504 #define LL_RCC_RTC_HSE_DIV_41 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0)
505 #define LL_RCC_RTC_HSE_DIV_42 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1)
506 #define LL_RCC_RTC_HSE_DIV_43 (RCC_CFGR_RTCPRE_5 |\
507 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
508 #define LL_RCC_RTC_HSE_DIV_44 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2)
509 #define LL_RCC_RTC_HSE_DIV_45 (RCC_CFGR_RTCPRE_5 |\
510 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
511 #define LL_RCC_RTC_HSE_DIV_46 (RCC_CFGR_RTCPRE_5 |\
512 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
513 #define LL_RCC_RTC_HSE_DIV_47 (RCC_CFGR_RTCPRE_5 |\
514 RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
515 #define LL_RCC_RTC_HSE_DIV_48 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4)
516 #define LL_RCC_RTC_HSE_DIV_49 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_0)
517 #define LL_RCC_RTC_HSE_DIV_50 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1)
518 #define LL_RCC_RTC_HSE_DIV_51 (RCC_CFGR_RTCPRE_5 |\
519 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
520 #define LL_RCC_RTC_HSE_DIV_52 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2)
521 #define LL_RCC_RTC_HSE_DIV_53 (RCC_CFGR_RTCPRE_5 |\
522 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
523 #define LL_RCC_RTC_HSE_DIV_54 (RCC_CFGR_RTCPRE_5 |\
524 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
525 #define LL_RCC_RTC_HSE_DIV_55 (RCC_CFGR_RTCPRE_5 |\
526 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
527 #define LL_RCC_RTC_HSE_DIV_56 (RCC_CFGR_RTCPRE_5 | RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3)
528 #define LL_RCC_RTC_HSE_DIV_57 (RCC_CFGR_RTCPRE_5 |\
529 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_0)
530 #define LL_RCC_RTC_HSE_DIV_58 (RCC_CFGR_RTCPRE_5 |\
531 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1)
532 #define LL_RCC_RTC_HSE_DIV_59 (RCC_CFGR_RTCPRE_5 |\
533 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
534 #define LL_RCC_RTC_HSE_DIV_60 (RCC_CFGR_RTCPRE_5 |\
535 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2)
536 #define LL_RCC_RTC_HSE_DIV_61 (RCC_CFGR_RTCPRE_5 |\
537 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_0)
538 #define LL_RCC_RTC_HSE_DIV_62 (RCC_CFGR_RTCPRE_5 |\
539 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1)
540 #define LL_RCC_RTC_HSE_DIV_63 (RCC_CFGR_RTCPRE_5 |\
541 RCC_CFGR_RTCPRE_4 | RCC_CFGR_RTCPRE_3 | RCC_CFGR_RTCPRE_2 | RCC_CFGR_RTCPRE_1 | RCC_CFGR_RTCPRE_0)
542 /**
543 * @}
544 */
545
546 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
547 * @{
548 */
549 #define LL_RCC_ADC_CLKSOURCE_PLL2P 0U
550 #define LL_RCC_ADC_CLKSOURCE_PLL3R RCC_CCIPR1_ADCSEL_0
551 #define LL_RCC_ADC_CLKSOURCE_CLKP RCC_CCIPR1_ADCSEL_1
552 /**
553 * @}
554 */
555
556 /** @defgroup RCC_LL_EC_ADFx_CLKSOURCE Peripheral ADF clock source selection
557 * @{
558 */
559 #define LL_RCC_ADF1_CLKSOURCE_HCLK 0U
560 #define LL_RCC_ADF1_CLKSOURCE_PLL2P RCC_CCIPR1_ADF1SEL_0
561 #define LL_RCC_ADF1_CLKSOURCE_PLL3P RCC_CCIPR1_ADF1SEL_1
562 #define LL_RCC_ADF1_CLKSOURCE_I2S_CKIN (RCC_CCIPR1_ADF1SEL_1 | RCC_CCIPR1_ADF1SEL_0)
563 #define LL_RCC_ADF1_CLKSOURCE_CSI RCC_CCIPR1_ADF1SEL_2
564 #define LL_RCC_ADF1_CLKSOURCE_HSI (RCC_CCIPR1_ADF1SEL_2 | RCC_CCIPR1_ADF1SEL_0)
565 /**
566 * @}
567 */
568
569 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
570 * @{
571 */
572 #define LL_RCC_CEC_CLKSOURCE_LSE 0U
573 #define LL_RCC_CEC_CLKSOURCE_LSI RCC_CCIPR2_CECSEL_0
574 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV_122 RCC_CCIPR2_CECSEL_1
575 /**
576 * @}
577 */
578
579 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
580 * @{
581 */
582 #define LL_RCC_CLKP_CLKSOURCE_HSI 0U
583 #define LL_RCC_CLKP_CLKSOURCE_CSI RCC_CCIPR1_CKPERSEL_0
584 #define LL_RCC_CLKP_CLKSOURCE_HSE RCC_CCIPR1_CKPERSEL_1
585 /**
586 * @}
587 */
588
589 /** @defgroup RCC_LL_EC_ETHxPHY_CLKSOURCE Peripheral ETHPHY clock source selection
590 * @{
591 */
592 #define LL_RCC_ETH1PHY_CLKSOURCE_HSE 0U
593 #define LL_RCC_ETH1PHY_CLKSOURCE_PLL3S RCC_CCIPR1_ETH1PHYCKSEL
594 /**
595 * @}
596 */
597
598 /** @defgroup RCC_LL_EC_ETHxREF_CLKSOURCE Peripheral ETHREF clock source selection
599 * @{
600 */
601 #define LL_RCC_ETH1REF_CLKSOURCE_RMII 0U
602 #define LL_RCC_ETH1REF_CLKSOURCE_HSE RCC_CCIPR1_ETH1REFCKSEL_0
603 #define LL_RCC_ETH1REF_CLKSOURCE_FB RCC_CCIPR1_ETH1REFCKSEL_1
604 /**
605 * @}
606 */
607
608 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
609 * @{
610 */
611 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0U
612 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q RCC_CCIPR2_FDCANSEL_0
613 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q RCC_CCIPR2_FDCANSEL_1
614 /**
615 * @}
616 */
617
618 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
619 * @{
620 */
621 #define LL_RCC_FMC_CLKSOURCE_HCLK 0U
622 #define LL_RCC_FMC_CLKSOURCE_PLL1Q RCC_CCIPR1_FMCSEL_0
623 #define LL_RCC_FMC_CLKSOURCE_PLL2R RCC_CCIPR1_FMCSEL_1
624 #define LL_RCC_FMC_CLKSOURCE_HSI (RCC_CCIPR1_FMCSEL_1 | RCC_CCIPR1_FMCSEL_0)
625 #define LL_RCC_FMC_CLKSOURCE_HCLK_DIV4 LL_RCC_SWP_FMC_HCLK_DIV4 /* Recovery: Read-only */
626 /**
627 * @}
628 */
629
630 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
631 * @{
632 */
633 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, 0U)
634 #define LL_RCC_I2C1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, RCC_CCIPR2_I2C1_I3C1SEL_0)
635 #define LL_RCC_I2C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, RCC_CCIPR2_I2C1_I3C1SEL_1)
636 #define LL_RCC_I2C1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, RCC_CCIPR2_I2C1_I3C1SEL_1 |\
637 RCC_CCIPR2_I2C1_I3C1SEL_0)
638
639 #define LL_RCC_I2C23_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, 0U)
640 #define LL_RCC_I2C23_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, RCC_CCIPR2_I2C23SEL_0)
641 #define LL_RCC_I2C23_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, RCC_CCIPR2_I2C23SEL_1)
642 #define LL_RCC_I2C23_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, RCC_CCIPR2_I2C23SEL_1 |\
643 RCC_CCIPR2_I2C23SEL_0)
644 /**
645 * @}
646 */
647
648 /** @defgroup RCC_LL_EC_I3Cx_CLKSOURCE Peripheral I3C clock source selection
649 * @{
650 */
651 #define LL_RCC_I3C1_CLKSOURCE_PCLK1 0U
652 #define LL_RCC_I3C1_CLKSOURCE_PLL3R RCC_CCIPR2_I2C1_I3C1SEL_0
653 #define LL_RCC_I3C1_CLKSOURCE_HSI RCC_CCIPR2_I2C1_I3C1SEL_1
654 #define LL_RCC_I3C1_CLKSOURCE_CSI (RCC_CCIPR2_I2C1_I3C1SEL_1 | RCC_CCIPR2_I2C1_I3C1SEL_0)
655 /**
656 * @}
657 */
658
659 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
660 * @{
661 */
662 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0U)
663 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_0)
664 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1)
665 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_1 |\
666 RCC_CCIPR2_LPTIM1SEL_0)
667 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2)
668 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIPR2_LPTIM1SEL_2 |\
669 RCC_CCIPR2_LPTIM1SEL_0)
670
671 #define LL_RCC_LPTIM23_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, 0U)
672 #define LL_RCC_LPTIM23_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_0)
673 #define LL_RCC_LPTIM23_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_1)
674 #define LL_RCC_LPTIM23_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_1 |\
675 RCC_CCIPR4_LPTIM23SEL_0)
676 #define LL_RCC_LPTIM23_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_2)
677 #define LL_RCC_LPTIM23_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, RCC_CCIPR4_LPTIM23SEL_2 |\
678 RCC_CCIPR4_LPTIM23SEL_0)
679
680 #define LL_RCC_LPTIM45_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, 0U)
681 #define LL_RCC_LPTIM45_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_0)
682 #define LL_RCC_LPTIM45_CLKSOURCE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_1)
683 #define LL_RCC_LPTIM45_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_1 |\
684 RCC_CCIPR4_LPTIM45SEL_0)
685 #define LL_RCC_LPTIM45_CLKSOURCE_LSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_2)
686 #define LL_RCC_LPTIM45_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, RCC_CCIPR4_LPTIM45SEL_2 |\
687 RCC_CCIPR4_LPTIM45SEL_0)
688 /**
689 * @}
690 */
691
692 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
693 * @{
694 */
695 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 0U
696 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q RCC_CCIPR4_LPUART1SEL_0
697 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q RCC_CCIPR4_LPUART1SEL_1
698 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_CCIPR4_LPUART1SEL_1 | RCC_CCIPR4_LPUART1SEL_0)
699 #define LL_RCC_LPUART1_CLKSOURCE_CSI RCC_CCIPR4_LPUART1SEL_2
700 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR4_LPUART1SEL_2 | RCC_CCIPR4_LPUART1SEL_0)
701 /**
702 * @}
703 */
704
705 /** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
706 * @{
707 */
708 #define LL_RCC_LTDC_CLKSOURCE_PLL3R 0U
709 /**
710 * @}
711 */
712
713 /** @defgroup RCC_LL_EC_PSSI_CLKSOURCE Peripheral PSSI clock source selection
714 * @{
715 */
716 #define LL_RCC_PSSI_CLKSOURCE_PLL3R 0U
717 #define LL_RCC_PSSI_CLKSOURCE_CLKP RCC_CCIPR1_PSSISEL
718 /**
719 * @}
720 */
721
722 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
723 * @{
724 */
725 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, 0U)
726 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_0)
727 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_1)
728 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_0 |\
729 RCC_CCIPR3_SAI1SEL_1)
730 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, RCC_CCIPR3_SAI1SEL_2)
731
732 #define LL_RCC_SAI2_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, 0U)
733 #define LL_RCC_SAI2_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_0)
734 #define LL_RCC_SAI2_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_1)
735 #define LL_RCC_SAI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_1 |\
736 RCC_CCIPR3_SAI2SEL_0)
737 #define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI2SEL_2)
738 #define LL_RCC_SAI2_CLKSOURCE_SPDIFRX LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, RCC_CCIPR3_SAI1SEL_2 |\
739 RCC_CCIPR3_SAI2SEL_0)
740 /**
741 * @}
742 */
743
744 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection
745 * @{
746 */
747 #define LL_RCC_SDMMC_CLKSOURCE_PLL2S 0U
748 #define LL_RCC_SDMMC_CLKSOURCE_PLL2T RCC_CCIPR1_SDMMC12SEL
749 /**
750 * @}
751 */
752
753 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection
754 * @{
755 */
756 #define LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q 0U
757 #define LL_RCC_SPDIFRX_CLKSOURCE_PLL2R RCC_CCIPR2_SPDIFRXSEL_0
758 #define LL_RCC_SPDIFRX_CLKSOURCE_PLL3R RCC_CCIPR2_SPDIFRXSEL_1
759 #define LL_RCC_SPDIFRX_CLKSOURCE_HSI (RCC_CCIPR2_SPDIFRXSEL_0 | RCC_CCIPR2_SPDIFRXSEL_1)
760 /**
761 * @}
762 */
763
764 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection
765 * @{
766 */
767 #define LL_RCC_SPI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0U)
768 #define LL_RCC_SPI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_0)
769 #define LL_RCC_SPI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1)
770 #define LL_RCC_SPI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_1 |\
771 RCC_CCIPR3_SPI1SEL_0)
772 #define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR3_SPI1SEL_2)
773
774 #define LL_RCC_SPI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, 0U)
775 #define LL_RCC_SPI23_CLKSOURCE_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_0)
776 #define LL_RCC_SPI23_CLKSOURCE_PLL3P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_1)
777 #define LL_RCC_SPI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_1 |\
778 RCC_CCIPR2_SPI23SEL_0)
779 #define LL_RCC_SPI23_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, RCC_CCIPR2_SPI23SEL_2)
780
781 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, 0U)
782 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_0)
783 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_1)
784 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_1 |\
785 RCC_CCIPR3_SPI45SEL_0)
786 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_2)
787 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, RCC_CCIPR3_SPI45SEL_2 |\
788 RCC_CCIPR3_SPI45SEL_0)
789
790 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, 0U)
791 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_0)
792 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_1)
793 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_1 |\
794 RCC_CCIPR4_SPI6SEL_0)
795 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_2)
796 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, RCC_CCIPR4_SPI6SEL_2 |\
797 RCC_CCIPR4_SPI6SEL_0)
798 /**
799 * @}
800 */
801
802 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
803 * @{
804 */
805 #define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, 0U)
806 #define LL_RCC_USART1_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_0)
807 #define LL_RCC_USART1_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_1)
808 #define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_1 |\
809 RCC_CCIPR3_USART1SEL_0)
810 #define LL_RCC_USART1_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_2)
811 #define LL_RCC_USART1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, RCC_CCIPR3_USART1SEL_2 |\
812 RCC_CCIPR3_USART1SEL_0)
813
814 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, 0U)
815 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_0)
816 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_1)
817 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_1 |\
818 RCC_CCIPR2_UART234578SEL_0)
819 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_2)
820 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, RCC_CCIPR2_UART234578SEL_2 |\
821 RCC_CCIPR2_UART234578SEL_0)
822 /**
823 * @}
824 */
825
826 /** @defgroup RCC_LL_EC_OTGFS_CLKSOURCE Peripheral OTGFS kernel clock source selection
827 * @{
828 */
829 #define LL_RCC_OTGFS_CLKSOURCE_HSI48 0U
830 #define LL_RCC_OTGFS_CLKSOURCE_PLL3Q RCC_CCIPR1_OTGFSSEL_0
831 #define LL_RCC_OTGFS_CLKSOURCE_HSE RCC_CCIPR1_OTGFSSEL_1
832 #define LL_RCC_OTGFS_CLKSOURCE_CLK48 (RCC_CCIPR1_OTGFSSEL_1 | RCC_CCIPR1_OTGFSSEL_0)
833 /**
834 * @}
835 */
836
837 /** @defgroup RCC_LL_EC_USBPHYC_CLKSOURCE Peripheral USBPHYC kernel clock source selection
838 * @{
839 */
840 #define LL_RCC_USBPHYC_CLKSOURCE_HSE 0U
841 #define LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2 RCC_CCIPR1_USBPHYCSEL_0
842 #define LL_RCC_USBPHYC_CLKSOURCE_PLL3Q RCC_CCIPR1_USBPHYCSEL_1
843 #define LL_RCC_USBPHYC_CLKSOURCE_DISABLE (RCC_CCIPR1_USBPHYCSEL_1 | RCC_CCIPR1_USBPHYCSEL_0)
844 /**
845 * @}
846 */
847
848 /** @defgroup RCC_LL_EC_USBREF_CLKSOURCE Peripheral USBREF clock source selection
849 * @{
850 */
851 #define LL_RCC_USBREF_CLKSOURCE_16M (RCC_CCIPR1_USBREFCKSEL_1 | RCC_CCIPR1_USBREFCKSEL_0)
852 #define LL_RCC_USBREF_CLKSOURCE_19_2M RCC_CCIPR1_USBREFCKSEL_3
853 #define LL_RCC_USBREF_CLKSOURCE_20M (RCC_CCIPR1_USBREFCKSEL_3 | RCC_CCIPR1_USBREFCKSEL_0)
854 #define LL_RCC_USBREF_CLKSOURCE_24M (RCC_CCIPR1_USBREFCKSEL_3 | RCC_CCIPR1_USBREFCKSEL_1)
855 #define LL_RCC_USBREF_CLKSOURCE_26M (RCC_CCIPR1_USBREFCKSEL_3 |\
856 RCC_CCIPR1_USBREFCKSEL_2 | RCC_CCIPR1_USBREFCKSEL_1)
857 #define LL_RCC_USBREF_CLKSOURCE_32M (RCC_CCIPR1_USBREFCKSEL_3 |\
858 RCC_CCIPR1_USBREFCKSEL_1 | RCC_CCIPR1_USBREFCKSEL_0)
859 /**
860 * @}
861 */
862
863 /** @defgroup RCC_LL_EC_XSPI_CLKSOURCE Peripheral XSPI clock source selection
864 * @{
865 */
866 #define LL_RCC_XSPI1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, 0U)
867 #define LL_RCC_XSPI1_CLKSOURCE_PLL2S LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, RCC_CCIPR1_XSPI1SEL_0)
868 #define LL_RCC_XSPI1_CLKSOURCE_PLL2T LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, RCC_CCIPR1_XSPI1SEL_1)
869 #define LL_RCC_XSPI1_CLKSOURCE_HCLK_DIV4 LL_RCC_SWP_XSPI1_HCLK_DIV4 /* Recovery: Read-only */
870
871 #define LL_RCC_XSPI2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, 0U)
872 #define LL_RCC_XSPI2_CLKSOURCE_PLL2S LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, RCC_CCIPR1_XSPI2SEL_0)
873 #define LL_RCC_XSPI2_CLKSOURCE_PLL2T LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, RCC_CCIPR1_XSPI2SEL_1)
874 #define LL_RCC_XSPI2_CLKSOURCE_HCLK_DIV4 LL_RCC_SWP_XSPI2_HCLK_DIV4 /* Recovery: Read-only */
875 /**
876 * @}
877 */
878
879 /** @addtogroup RCC_LL_EC_ADC_CLKSOURCE
880 * @{
881 */
882 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR1_ADCSEL
883 /**
884 * @}
885 */
886
887 /** @addtogroup RCC_LL_EC_ADFx_CLKSOURCE
888 * @{
889 */
890 #define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR1_ADF1SEL
891 /**
892 * @}
893 */
894
895
896 /** @addtogroup RCC_LL_EC_CEC_CLKSOURCE
897 * @{
898 */
899 #define LL_RCC_CEC_CLKSOURCE RCC_CCIPR2_CECSEL
900 /**
901 * @}
902 */
903
904 /** @addtogroup RCC_LL_EC_CLKP_CLKSOURCE
905 * @{
906 */
907 #define LL_RCC_CLKP_CLKSOURCE RCC_CCIPR1_CKPERSEL
908 /**
909 * @}
910 */
911
912 /** @addtogroup RCC_LL_EC_ETHxPHY_CLKSOURCE
913 * @{
914 */
915 #define LL_RCC_ETH1PHY_CLKSOURCE RCC_CCIPR1_ETH1PHYCKSEL
916 /**
917 * @}
918 */
919
920 /** @addtogroup RCC_LL_EC_ETHxREF_CLKSOURCE
921 * @{
922 */
923 #define LL_RCC_ETH1REF_CLKSOURCE RCC_CCIPR1_ETH1REFCKSEL
924 /**
925 * @}
926 */
927
928 /** @addtogroup RCC_LL_EC_FDCAN_CLKSOURCE
929 * @{
930 */
931 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL
932 /**
933 * @}
934 */
935
936 /** @addtogroup RCC_LL_EC_FMC_CLKSOURCE
937 * @{
938 */
939 #define LL_RCC_FMC_CLKSOURCE RCC_CCIPR1_FMCSEL
940 /**
941 * @}
942 */
943
944 /** @addtogroup RCC_LL_EC_I2Cx_CLKSOURCE
945 * @{
946 */
947 #define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C1_I3C1SEL, RCC_CCIPR2_I2C1_I3C1SEL_Pos, 0U)
948 #define LL_RCC_I2C23_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_I2C23SEL, RCC_CCIPR2_I2C23SEL_Pos, 0U)
949 /**
950 * @}
951 */
952
953 /** @addtogroup RCC_LL_EC_I3Cx_CLKSOURCE
954 * @{
955 */
956 #define LL_RCC_I3C1_CLKSOURCE RCC_CCIPR2_I2C1_I3C1SEL
957 /**
958 * @}
959 */
960
961 /** @addtogroup RCC_LL_EC_LPTIMx_CLKSOURCE
962 * @{
963 */
964 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0U)
965 #define LL_RCC_LPTIM23_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM23SEL, RCC_CCIPR4_LPTIM23SEL_Pos, 0U)
966 #define LL_RCC_LPTIM45_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_LPTIM45SEL, RCC_CCIPR4_LPTIM45SEL_Pos, 0U)
967 /**
968 * @}
969 */
970
971 /** @addtogroup RCC_LL_EC_LPUARTx_CLKSOURCE
972 * @{
973 */
974 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR4_LPUART1SEL
975 /**
976 * @}
977 */
978
979 /** @addtogroup RCC_LL_EC_OTGFS_CLKSOURCE
980 * @{
981 */
982 #define LL_RCC_OTGFS_CLKSOURCE RCC_CCIPR1_OTGFSSEL
983 /**
984 * @}
985 */
986
987 /** @addtogroup RCC_LL_EC_PSSI_CLKSOURCE
988 * @{
989 */
990 #define LL_RCC_PSSI_CLKSOURCE RCC_CCIPR1_PSSISEL
991 /**
992 * @}
993 */
994
995 /** @addtogroup RCC_LL_EC_SAIx_CLKSOURCE
996 * @{
997 */
998 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI1SEL, RCC_CCIPR3_SAI1SEL_Pos, 0U)
999 #define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SAI2SEL, RCC_CCIPR3_SAI2SEL_Pos, 0U)
1000 /**
1001 * @}
1002 */
1003
1004 /** @addtogroup RCC_LL_EC_SDMMC_CLKSOURCE
1005 * @{
1006 */
1007 #define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_SDMMC12SEL
1008 /**
1009 * @}
1010 */
1011
1012 /** @addtogroup RCC_LL_EC_SPDIFRX_CLKSOURCE
1013 * @{
1014 */
1015 #define LL_RCC_SPDIFRX_CLKSOURCE RCC_CCIPR2_SPDIFRXSEL
1016 /**
1017 * @}
1018 */
1019
1020 /** @addtogroup RCC_LL_EC_SPIx_CLKSOURCE
1021 * @{
1022 */
1023 #define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0U)
1024 #define LL_RCC_SPI23_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_SPI23SEL, RCC_CCIPR2_SPI23SEL_Pos, 0U)
1025 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI45SEL, RCC_CCIPR3_SPI45SEL_Pos, 0U)
1026 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_SPI6SEL, RCC_CCIPR4_SPI6SEL_Pos, 0U)
1027 /**
1028 * @}
1029 */
1030
1031 /** @addtogroup RCC_LL_EC_USARTx_CLKSOURCE
1032 * @{
1033 */
1034 #define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_USART1SEL, RCC_CCIPR3_USART1SEL_Pos, 0U)
1035 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_UART234578SEL, RCC_CCIPR2_UART234578SEL_Pos, 0U)
1036 /**
1037 * @}
1038 */
1039
1040 /** @addtogroup RCC_LL_EC_USBPHYC_CLKSOURCE
1041 * @{
1042 */
1043 #define LL_RCC_USBPHYC_CLKSOURCE RCC_CCIPR1_USBPHYCSEL
1044 /**
1045 * @}
1046 */
1047
1048 /** @addtogroup RCC_LL_EC_USBREF_CLKSOURCE
1049 * @{
1050 */
1051 #define LL_RCC_USBREF_CLKSOURCE RCC_CCIPR1_USBREFCKSEL
1052 /**
1053 * @}
1054 */
1055
1056
1057 /** @addtogroup RCC_LL_EC_XSPIx_CLKSOURCE
1058 * @{
1059 */
1060 #define LL_RCC_XSPI1_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI1SEL, RCC_CCIPR1_XSPI1SEL_Pos, 0U)
1061 #define LL_RCC_XSPI2_CLKSOURCE LL_CLKSOURCE(CCIPR1_OFFSET, RCC_CCIPR1_XSPI2SEL, RCC_CCIPR1_XSPI2SEL_Pos, 0U)
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
1067 * @{
1068 */
1069 #define LL_RCC_RTC_CLKSOURCE_NONE 0U
1070 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
1071 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
1072 #define LL_RCC_RTC_CLKSOURCE_HSE (RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
1073 /**
1074 * @}
1075 */
1076
1077 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
1078 * @{
1079 */
1080 #define LL_RCC_TIM_PRESCALER_DISABLE 0U
1081 #define LL_RCC_TIM_PRESCALER_ENABLE RCC_CFGR_TIMPRE
1082 /**
1083 * @}
1084 */
1085
1086 /** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source
1087 * @{
1088 */
1089 #define LL_RCC_PLLSOURCE_HSI 0U
1090 #define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_0
1091 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_1
1092 #define LL_RCC_PLLSOURCE_NONE (RCC_PLLCKSELR_PLLSRC_1 | RCC_PLLCKSELR_PLLSRC_0)
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range
1098 * @{
1099 */
1100 #define LL_RCC_PLLINPUTRANGE_1_2 0U
1101 #define LL_RCC_PLLINPUTRANGE_2_4 RCC_PLLCFGR_PLL1RGE_0
1102 #define LL_RCC_PLLINPUTRANGE_4_8 RCC_PLLCFGR_PLL1RGE_1
1103 #define LL_RCC_PLLINPUTRANGE_8_16 (RCC_PLLCFGR_PLL1RGE_1 | RCC_PLLCFGR_PLL1RGE_0)
1104 /**
1105 * @}
1106 */
1107
1108 /** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range
1109 * @{
1110 */
1111 #define LL_RCC_PLLVCORANGE_WIDE 0U /*!< VCO output range: 400 to 1600 MHz */
1112 #define LL_RCC_PLLVCORANGE_MEDIUM RCC_PLLCFGR_PLL1VCOSEL /*!< VCO output range: 150 to 420 MHz */
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup RCC_LL_EC_PLL_SPREAD_SEL PLL Spread Spectrum Selection
1118 * @{
1119 */
1120 #define LL_RCC_PLL_SPREAD_CENTER 0U /*!< PLL center spread spectrum selection */
1121 #define LL_RCC_PLL_SPREAD_DOWN RCC_PLL1SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup RCC_LL_EC_PLL_DITHERING_TPDFN PLL Dithering TPDF Noise Control
1127 * @{
1128 */
1129 #define LL_RCC_PLL_DITHERING_TPDFN_ENABLE 0U /*!< PLL Dithering TPDF Noise injection enabled */
1130 #define LL_RCC_PLL_DITHERING_TPDFN_DISABLE RCC_PLL1SSCGR_TPDFNDIS /*!< PLL Dithering TPDF Noise injection disabled */
1131 /**
1132 * @}
1133 */
1134
1135 /** @defgroup RCC_LL_EC_PLL_DITHERING_RPDFN PLL Dithering RPDF Noise Control
1136 * @{
1137 */
1138 #define LL_RCC_PLL_DITHERING_RPDFN_ENABLE 0U /*!< PLL Dithering RPDF Noise injection enabled */
1139 #define LL_RCC_PLL_DITHERING_RPDFN_DISABLE RCC_PLL1SSCGR_RPDFNDIS /*!< PLL Dithering RPDF Noise injection disabled */
1140 /**
1141 * @}
1142 */
1143
1144 /**
1145 * @}
1146 */
1147
1148 /* Exported macros -----------------------------------------------------------*/
1149 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1150 * @{
1151 */
1152
1153 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1154 * @{
1155 */
1156
1157 /**
1158 * @brief Write a value in RCC register
1159 * @param __REG__ Register to be written
1160 * @param __VALUE__ Value to be written in the register
1161 * @retval None
1162 */
1163 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1164
1165 /**
1166 * @brief Read a value in RCC register
1167 * @param __REG__ Register to be read
1168 * @retval Register value
1169 */
1170 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1171 /**
1172 * @}
1173 */
1174
1175 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1176 * @{
1177 */
1178
1179 /**
1180 * @brief Helper macro to calculate the SYSCLK frequency
1181 * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
1182 * @param __SYSPRESCALER__ This parameter can be one of the following values:
1183 * @arg @ref LL_RCC_SYSCLK_DIV_1
1184 * @arg @ref LL_RCC_SYSCLK_DIV_2
1185 * @arg @ref LL_RCC_SYSCLK_DIV_4
1186 * @arg @ref LL_RCC_SYSCLK_DIV_8
1187 * @arg @ref LL_RCC_SYSCLK_DIV_16
1188 * @arg @ref LL_RCC_SYSCLK_DIV_64
1189 * @arg @ref LL_RCC_SYSCLK_DIV_128
1190 * @arg @ref LL_RCC_SYSCLK_DIV_256
1191 * @arg @ref LL_RCC_SYSCLK_DIV_512
1192 * @retval SYSCLK clock frequency (in Hz)
1193 */
1194 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) &\
1195 RCC_CDCFGR_CPRE) >> RCC_CDCFGR_CPRE_Pos]) & 0x1FU))
1196
1197 /**
1198 * @brief Helper macro to calculate the HCLK frequency
1199 * @param __SYSCLKFREQ__ SYSCLK frequency.
1200 * @param __HPRESCALER__ This parameter can be one of the following values:
1201 * @arg @ref LL_RCC_AHB_DIV_1
1202 * @arg @ref LL_RCC_AHB_DIV_2
1203 * @arg @ref LL_RCC_AHB_DIV_4
1204 * @arg @ref LL_RCC_AHB_DIV_8
1205 * @arg @ref LL_RCC_AHB_DIV_16
1206 * @arg @ref LL_RCC_AHB_DIV_64
1207 * @arg @ref LL_RCC_AHB_DIV_128
1208 * @arg @ref LL_RCC_AHB_DIV_256
1209 * @arg @ref LL_RCC_AHB_DIV_512
1210 * @retval HCLK clock frequency (in Hz)
1211 */
1212 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) &\
1213 RCC_BMCFGR_BMPRE) >> RCC_BMCFGR_BMPRE_Pos]) & 0x1FU))
1214
1215 /**
1216 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1217 * @param __HCLKFREQ__ HCLK frequency
1218 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1219 * @arg @ref LL_RCC_APB1_DIV_1
1220 * @arg @ref LL_RCC_APB1_DIV_2
1221 * @arg @ref LL_RCC_APB1_DIV_4
1222 * @arg @ref LL_RCC_APB1_DIV_8
1223 * @arg @ref LL_RCC_APB1_DIV_16
1224 * @retval PCLK1 clock frequency (in Hz)
1225 */
1226 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) &\
1227 RCC_APBCFGR_PPRE1) >> RCC_APBCFGR_PPRE1_Pos]) & 0x1FU))
1228
1229 /**
1230 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1231 * @param __HCLKFREQ__ HCLK frequency
1232 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1233 * @arg @ref LL_RCC_APB2_DIV_1
1234 * @arg @ref LL_RCC_APB2_DIV_2
1235 * @arg @ref LL_RCC_APB2_DIV_4
1236 * @arg @ref LL_RCC_APB2_DIV_8
1237 * @arg @ref LL_RCC_APB2_DIV_16
1238 * @retval PCLK2 clock frequency (in Hz)
1239 */
1240 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) &\
1241 RCC_APBCFGR_PPRE2) >> RCC_APBCFGR_PPRE2_Pos]) & 0x1FU))
1242
1243 /**
1244 * @brief Helper macro to calculate the PCLK4 frequency (ABP4)
1245 * @param __HCLKFREQ__ HCLK frequency
1246 * @param __APB4PRESCALER__ This parameter can be one of the following values:
1247 * @arg @ref LL_RCC_APB4_DIV_1
1248 * @arg @ref LL_RCC_APB4_DIV_2
1249 * @arg @ref LL_RCC_APB4_DIV_4
1250 * @arg @ref LL_RCC_APB4_DIV_8
1251 * @arg @ref LL_RCC_APB4_DIV_16
1252 * @retval PCLK1 clock frequency (in Hz)
1253 */
1254 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) &\
1255 RCC_APBCFGR_PPRE4) >> RCC_APBCFGR_PPRE4_Pos]) & 0x1FU))
1256
1257 /**
1258 * @brief Helper macro to calculate the PCLK5 frequency (APB5)
1259 * @param __HCLKFREQ__ HCLK frequency
1260 * @param __APB5PRESCALER__ This parameter can be one of the following values:
1261 * @arg @ref LL_RCC_APB5_DIV_1
1262 * @arg @ref LL_RCC_APB5_DIV_2
1263 * @arg @ref LL_RCC_APB5_DIV_4
1264 * @arg @ref LL_RCC_APB5_DIV_8
1265 * @arg @ref LL_RCC_APB5_DIV_16
1266 * @retval PCLK1 clock frequency (in Hz)
1267 */
1268 #define LL_RCC_CALC_PCLK5_FREQ(__HCLKFREQ__, __APB5PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB5PRESCALER__) &\
1269 RCC_APBCFGR_PPRE5) >> RCC_APBCFGR_PPRE5_Pos]) & 0x1FU))
1270
1271 /**
1272 * @}
1273 */
1274
1275 #if defined(USE_FULL_LL_DRIVER)
1276 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
1277 * @{
1278 */
1279 #define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */
1280 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
1281 /**
1282 * @}
1283 */
1284 #endif /* USE_FULL_LL_DRIVER */
1285
1286 /**
1287 * @}
1288 */
1289
1290 /* Exported functions --------------------------------------------------------*/
1291 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1292 * @{
1293 */
1294
1295 /** @defgroup RCC_LL_EF_HSE HSE
1296 * @{
1297 */
1298
1299 /**
1300 * @brief Enable the Clock Security System.
1301 * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1302 * a reset occurs or system enter in standby mode.
1303 * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS
1304 * @retval None
1305 */
LL_RCC_HSE_EnableCSS(void)1306 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1307 {
1308 SET_BIT(RCC->CR, RCC_CR_HSECSSON);
1309 }
1310
1311 /**
1312 * @brief Enable HSE external oscillator (HSE Bypass)
1313 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1314 * @retval None
1315 */
LL_RCC_HSE_EnableBypass(void)1316 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1317 {
1318 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1319 }
1320
1321 /**
1322 * @brief Disable HSE external oscillator (HSE Bypass)
1323 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1324 * @retval None
1325 */
LL_RCC_HSE_DisableBypass(void)1326 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1327 {
1328 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1329 }
1330
1331 /**
1332 * @brief Select the Analog HSE external clock type in Bypass mode
1333 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock
1334 * @retval None
1335 */
LL_RCC_HSE_SelectAnalogClock(void)1336 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
1337 {
1338 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
1339 }
1340
1341 /**
1342 * @brief Select the Digital HSE external clock type in Bypass mode
1343 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock
1344 * @retval None
1345 */
LL_RCC_HSE_SelectDigitalClock(void)1346 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
1347 {
1348 SET_BIT(RCC->CR, RCC_CR_HSEEXT);
1349 }
1350
1351 /**
1352 * @brief Enable HSE crystal oscillator (HSE ON)
1353 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1354 * @retval None
1355 */
LL_RCC_HSE_Enable(void)1356 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1357 {
1358 SET_BIT(RCC->CR, RCC_CR_HSEON);
1359 }
1360
1361 /**
1362 * @brief Disable HSE crystal oscillator (HSE ON)
1363 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1364 * @retval None
1365 */
LL_RCC_HSE_Disable(void)1366 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1367 {
1368 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1369 }
1370
1371 /**
1372 * @brief Check if HSE oscillator Ready
1373 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1374 * @retval State of bit (1 or 0).
1375 */
LL_RCC_HSE_IsReady(void)1376 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1377 {
1378 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL);
1379 }
1380
1381 /**
1382 * @}
1383 */
1384
1385 /** @defgroup RCC_LL_EF_HSI HSI
1386 * @{
1387 */
1388
1389 /**
1390 * @brief Enable HSI oscillator
1391 * @rmtoll CR HSION LL_RCC_HSI_Enable
1392 * @retval None
1393 */
LL_RCC_HSI_Enable(void)1394 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1395 {
1396 SET_BIT(RCC->CR, RCC_CR_HSION);
1397 }
1398
1399 /**
1400 * @brief Disable HSI oscillator
1401 * @rmtoll CR HSION LL_RCC_HSI_Disable
1402 * @retval None
1403 */
LL_RCC_HSI_Disable(void)1404 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1405 {
1406 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1407 }
1408
1409 /**
1410 * @brief Check if HSI clock is ready
1411 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1412 * @retval State of bit (1 or 0).
1413 */
LL_RCC_HSI_IsReady(void)1414 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1415 {
1416 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
1417 }
1418
1419 /**
1420 * @brief Check if HSI new divider applied and ready
1421 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
1422 * @retval State of bit (1 or 0).
1423 */
LL_RCC_HSI_IsDividerReady(void)1424 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1425 {
1426 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL);
1427 }
1428
1429 /**
1430 * @brief Set HSI divider
1431 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
1432 * @param Divider This parameter can be one of the following values:
1433 * @arg @ref LL_RCC_HSI_DIV_1
1434 * @arg @ref LL_RCC_HSI_DIV_2
1435 * @arg @ref LL_RCC_HSI_DIV_4
1436 * @arg @ref LL_RCC_HSI_DIV_8
1437 * @retval None.
1438 */
LL_RCC_HSI_SetDivider(uint32_t Divider)1439 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1440 {
1441 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1442 }
1443
1444 /**
1445 * @brief Get HSI divider
1446 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
1447 * @retval can be one of the following values:
1448 * @arg @ref LL_RCC_HSI_DIV_1
1449 * @arg @ref LL_RCC_HSI_DIV_2
1450 * @arg @ref LL_RCC_HSI_DIV_4
1451 * @arg @ref LL_RCC_HSI_DIV_8
1452 */
LL_RCC_HSI_GetDivider(void)1453 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1454 {
1455 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1456 }
1457
1458 /**
1459 * @brief Enable HSI oscillator in Stop mode
1460 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode
1461 * @retval None
1462 */
LL_RCC_HSI_EnableStopMode(void)1463 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
1464 {
1465 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1466 }
1467
1468 /**
1469 * @brief Disable HSI oscillator in Stop mode
1470 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableStopMode
1471 * @retval None
1472 */
LL_RCC_HSI_DisableStopMode(void)1473 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
1474 {
1475 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1476 }
1477
1478 /**
1479 * @brief Check if HSI oscillator in Stop mode has been enabled or not
1480 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledStopMode
1481 * @retval State of bit (1 or 0).
1482 */
LL_RCC_HSI_IsEnabledStopMode(void)1483 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledStopMode(void)
1484 {
1485 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1486 }
1487
1488 /**
1489 * @brief Enable XSPI clock protection
1490 * @rmtoll CKPROTR XSPICKP LL_RCC_EnableXSPIClockProtection
1491 * @retval None
1492 */
LL_RCC_EnableXSPIClockProtection(void)1493 __STATIC_INLINE void LL_RCC_EnableXSPIClockProtection(void)
1494 {
1495 SET_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPICKP);
1496 }
1497
1498 /**
1499 * @brief Disable XSPI clock protection
1500 * @rmtoll CKPROTR XSPICKP LL_RCC_DisableXSPIClockProtection
1501 * @retval None
1502 */
LL_RCC_DisableXSPIClockProtection(void)1503 __STATIC_INLINE void LL_RCC_DisableXSPIClockProtection(void)
1504 {
1505 CLEAR_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPICKP);
1506 }
1507
1508 /**
1509 * @brief Check if XSPI clock protection has been enabled or not
1510 * @rmtoll CKPROTR XSPICKP LL_RCC_IsEnabledXSPIClockProtection
1511 * @retval State of bit (1 or 0).
1512 */
LL_RCC_IsEnabledXSPIClockProtection(void)1513 __STATIC_INLINE uint32_t LL_RCC_IsEnabledXSPIClockProtection(void)
1514 {
1515 return ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPICKP) == (RCC_CKPROTR_XSPICKP)) ? 1UL : 0UL);
1516 }
1517
1518 /**
1519 * @brief Enable FMC clock protection
1520 * @rmtoll CKPROTR FMCCKP LL_RCC_EnableFMCClockProtection
1521 * @retval None
1522 */
LL_RCC_EnableFMCClockProtection(void)1523 __STATIC_INLINE void LL_RCC_EnableFMCClockProtection(void)
1524 {
1525 SET_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCCKP);
1526 }
1527
1528 /**
1529 * @brief Disable FMC clock protection
1530 * @rmtoll CKPROTR FMCCKP LL_RCC_DisableFMCClockProtection
1531 * @retval None
1532 */
LL_RCC_DisableFMCClockProtection(void)1533 __STATIC_INLINE void LL_RCC_DisableFMCClockProtection(void)
1534 {
1535 CLEAR_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCCKP);
1536 }
1537
1538 /**
1539 * @brief Check if FMC clock protection has been enabled or not
1540 * @rmtoll CKPROTR FMCCKP LL_RCC_IsEnabledFMCClockProtection
1541 * @retval State of bit (1 or 0).
1542 */
LL_RCC_IsEnabledFMCClockProtection(void)1543 __STATIC_INLINE uint32_t LL_RCC_IsEnabledFMCClockProtection(void)
1544 {
1545 return ((READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCCKP) == (RCC_CKPROTR_FMCCKP)) ? 1UL : 0UL);
1546 }
1547
1548 /**
1549 * @brief Get XSPI2 kernel clock switch position
1550 * @rmtoll CKPROTR XSPI2SWP LL_RCC_GetXSPI2SwitchPosition
1551 * @retval Returned value can be one of the following values:
1552 * @arg @ref LL_RCC_SWP_XSPI2_NEUTRAL
1553 @arg @ref LL_RCC_SWP_XSPI2_HCLK5
1554 @arg @ref LL_RCC_SWP_XSPI2_PLL2S
1555 @arg @ref LL_RCC_SWP_XSPI2_PLL2T
1556 @arg @ref LL_RCC_SWP_XSPI2_HCLK_DIV4
1557 */
LL_RCC_GetXSPI2SwitchPosition(void)1558 __STATIC_INLINE uint32_t LL_RCC_GetXSPI2SwitchPosition(void)
1559 {
1560 return (READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI2SWP));
1561 }
1562
1563 /**
1564 * @brief Get XSPI1 kernel clock switch position
1565 * @rmtoll CKPROTR XSPI1SWP LL_RCC_GetXSPI1SwitchPosition
1566 * @retval Returned value can be one of the following values:
1567 * @arg @ref LL_RCC_SWP_XSPI1_NEUTRAL
1568 @arg @ref LL_RCC_SWP_XSPI1_HCLK5
1569 @arg @ref LL_RCC_SWP_XSPI1_PLL2S
1570 @arg @ref LL_RCC_SWP_XSPI1_PLL2T
1571 @arg @ref LL_RCC_SWP_XSPI1_HCLK_DIV4
1572 */
LL_RCC_GetXSPI1SwitchPosition(void)1573 __STATIC_INLINE uint32_t LL_RCC_GetXSPI1SwitchPosition(void)
1574 {
1575 return (READ_BIT(RCC->CKPROTR, RCC_CKPROTR_XSPI1SWP));
1576 }
1577
1578 /**
1579 * @brief Get FMC kernel clock switch position
1580 * @rmtoll CKPROTR FMCSWP LL_RCC_GetFMCSwitchPosition
1581 * @retval Returned value can be one of the following values:
1582 * @arg @ref LL_RCC_SWP_FMC_NEUTRAL
1583 @arg @ref LL_RCC_SWP_FMC_HCLK5
1584 @arg @ref LL_RCC_SWP_FMC_PLL1Q
1585 @arg @ref LL_RCC_SWP_FMC_PLL2R
1586 @arg @ref LL_RCC_SWP_FMC_HSI
1587 @arg @ref LL_RCC_SWP_FMC_HCLK_DIV4
1588 */
LL_RCC_GetFMCSwitchPosition(void)1589 __STATIC_INLINE uint32_t LL_RCC_GetFMCSwitchPosition(void)
1590 {
1591 return (READ_BIT(RCC->CKPROTR, RCC_CKPROTR_FMCSWP));
1592 }
1593
1594 /**
1595 * @brief Get HSI Calibration value
1596 * @note When HSITRIM is written, HSICAL is updated with the sum of
1597 * HSITRIM and the factory trim value
1598 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1599 * @retval A value between 0 and 4095 (0xFFF)
1600 */
LL_RCC_HSI_GetCalibration(void)1601 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1602 {
1603 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1604 }
1605
1606 /**
1607 * @brief Set HSI Calibration trimming
1608 * @note user-programmable trimming value that is added to the HSICAL
1609 * @note Default value is 64, which, when added to the HSICAL value,
1610 * should trim the HSI to 64 MHz +/- 1 %
1611 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1612 * @param Value Parameter can be a value between 0 and 127
1613 * @retval None
1614 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1615 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1616 {
1617 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1618 }
1619
1620 /**
1621 * @brief Get HSI Calibration trimming
1622 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming
1623 * @retval A value between 0 and 127
1624 */
LL_RCC_HSI_GetCalibTrimming(void)1625 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1626 {
1627 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1628 }
1629
1630 /**
1631 * @}
1632 */
1633
1634 /** @defgroup RCC_LL_EF_CSI CSI
1635 * @{
1636 */
1637
1638 /**
1639 * @brief Enable CSI oscillator
1640 * @rmtoll CR CSION LL_RCC_CSI_Enable
1641 * @retval None
1642 */
LL_RCC_CSI_Enable(void)1643 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1644 {
1645 SET_BIT(RCC->CR, RCC_CR_CSION);
1646 }
1647
1648 /**
1649 * @brief Disable CSI oscillator
1650 * @rmtoll CR CSION LL_RCC_CSI_Disable
1651 * @retval None
1652 */
LL_RCC_CSI_Disable(void)1653 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1654 {
1655 CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1656 }
1657
1658 /**
1659 * @brief Check if CSI clock is ready
1660 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
1661 * @retval State of bit (1 or 0).
1662 */
LL_RCC_CSI_IsReady(void)1663 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1664 {
1665 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == RCC_CR_CSIRDY) ? 1UL : 0UL);
1666 }
1667
1668 /**
1669 * @brief Enable CSI oscillator in Stop mode
1670 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode
1671 * @retval None
1672 */
LL_RCC_CSI_EnableStopMode(void)1673 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
1674 {
1675 SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1676 }
1677
1678 /**
1679 * @brief Disable CSI oscillator in Stop mode
1680 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode
1681 * @retval None
1682 */
LL_RCC_CSI_DisableStopMode(void)1683 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
1684 {
1685 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1686 }
1687
1688 /**
1689 * @brief Check if CSI oscillator in Stop mode has been enabled or not
1690 * @rmtoll CR CSIKERON LL_RCC_CSI_IsEnabledStopMode
1691 * @retval State of bit (1 or 0).
1692 */
LL_RCC_CSI_IsEnabledStopMode(void)1693 __STATIC_INLINE uint32_t LL_RCC_CSI_IsEnabledStopMode(void)
1694 {
1695 return ((READ_BIT(RCC->CR, RCC_CR_CSIKERON) == (RCC_CR_CSIKERON)) ? 1UL : 0UL);
1696 }
1697
1698 /**
1699 * @brief Get CSI Calibration value
1700 * @note When CSITRIM is written, CSICAL is updated with the sum of
1701 * CSITRIM and the factory trim value
1702 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration
1703 * @retval A value between 0 and 255 (0xFF)
1704 */
LL_RCC_CSI_GetCalibration(void)1705 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1706 {
1707 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1708 }
1709
1710 /**
1711 * @brief Set CSI Calibration trimming
1712 * @note user-programmable trimming value that is added to the CSICAL
1713 * @note Default value is 16, which, when added to the CSICAL value,
1714 * should trim the CSI to 4 MHz +/- 1 %
1715 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
1716 * @param Value can be a value between 0 and 31
1717 * @retval None
1718 */
LL_RCC_CSI_SetCalibTrimming(uint32_t Value)1719 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1720 {
1721 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1722 }
1723
1724 /**
1725 * @brief Get CSI Calibration trimming
1726 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
1727 * @retval A value between 0 and 31
1728 */
LL_RCC_CSI_GetCalibTrimming(void)1729 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1730 {
1731 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1732 }
1733
1734 /**
1735 * @}
1736 */
1737
1738 /** @defgroup RCC_LL_EF_HSI48 HSI48
1739 * @{
1740 */
1741
1742 /**
1743 * @brief Enable HSI48 oscillator
1744 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1745 * @retval None
1746 */
LL_RCC_HSI48_Enable(void)1747 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1748 {
1749 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1750 }
1751
1752 /**
1753 * @brief Disable HSI48 oscillator
1754 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
1755 * @retval None
1756 */
LL_RCC_HSI48_Disable(void)1757 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1758 {
1759 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
1760 }
1761
1762 /**
1763 * @brief Check if HSI48 clock is ready
1764 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
1765 * @retval State of bit (1 or 0).
1766 */
LL_RCC_HSI48_IsReady(void)1767 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1768 {
1769 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL);
1770 }
1771
1772 /**
1773 * @brief Get HSI48 Calibration value
1774 * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
1775 * HSI48TRIM and the factory trim value
1776 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1777 * @retval A value between 0 and 1023 (0x3FF)
1778 */
LL_RCC_HSI48_GetCalibration(void)1779 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1780 {
1781 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1782 }
1783 /**
1784 * @}
1785 */
1786
1787 /** @defgroup RCC_LL_EF_LSE LSE
1788 * @{
1789 */
1790
1791 /**
1792 * @brief Enable the Clock Security System on LSE.
1793 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
1794 * a clock failure is detected.
1795 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1796 * @retval None
1797 */
LL_RCC_LSE_EnableCSS(void)1798 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1799 {
1800 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1801 }
1802
1803 /**
1804 * @brief Disable the Clock Security System on LSE.
1805 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
1806 * a clock failure is detected.
1807 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1808 * @retval None
1809 */
LL_RCC_LSE_DisableCSS(void)1810 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1811 {
1812 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1813 }
1814
1815 /**
1816 * @brief Check if LSE failure is detected by Clock Security System
1817 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected
1818 * @retval State of bit (1 or 0).
1819 */
LL_RCC_LSE_IsFailureDetected(void)1820 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
1821 {
1822 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL);
1823 }
1824
1825 /**
1826 * @brief Re-arm the Clock Security System on LSE.
1827 * @note Once a clock failure is detected, the LSE Clock Security System can be re-armed providing that
1828 * LSECSSON is disabled.
1829 * @rmtoll BDCR LSECSSRA LL_RCC_LSE_ReArmCSS
1830 * @retval None
1831 */
LL_RCC_LSE_ReArmCSS(void)1832 __STATIC_INLINE void LL_RCC_LSE_ReArmCSS(void)
1833 {
1834 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSRA);
1835 }
1836
1837 /**
1838 * @brief Enable Low Speed External (LSE) crystal.
1839 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1840 * @retval None
1841 */
LL_RCC_LSE_Enable(void)1842 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1843 {
1844 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1845 }
1846
1847 /**
1848 * @brief Disable Low Speed External (LSE) crystal.
1849 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1850 * @retval None
1851 */
LL_RCC_LSE_Disable(void)1852 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1853 {
1854 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1855 }
1856
1857 /**
1858 * @brief Enable external clock source (LSE bypass).
1859 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1860 * @retval None
1861 */
LL_RCC_LSE_EnableBypass(void)1862 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1863 {
1864 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1865 }
1866
1867 /**
1868 * @brief Disable external clock source (LSE bypass).
1869 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1870 * @retval None
1871 */
LL_RCC_LSE_DisableBypass(void)1872 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1873 {
1874 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1875 }
1876
1877 /**
1878 * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
1879 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
1880 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
1881 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock
1882 * @retval None
1883 */
LL_RCC_LSE_SelectDigitalClock(void)1884 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
1885 {
1886 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
1887 }
1888
1889 /**
1890 * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
1891 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
1892 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
1893 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock
1894 * @retval None
1895 */
LL_RCC_LSE_SelectAnalogClock(void)1896 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
1897 {
1898 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
1899 }
1900
1901 /**
1902 * @brief Set LSE oscillator drive capability
1903 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1904 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1905 * @param LSEDrive This parameter can be one of the following values:
1906 * @arg @ref LL_RCC_LSEDRIVE_LOW
1907 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1908 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1909 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1910 * @retval None
1911 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1912 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1913 {
1914 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1915 }
1916
1917 /**
1918 * @brief Get LSE oscillator drive capability
1919 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1920 * @retval Returned value can be one of the following values:
1921 * @arg @ref LL_RCC_LSEDRIVE_LOW
1922 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1923 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1924 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1925 */
LL_RCC_LSE_GetDriveCapability(void)1926 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1927 {
1928 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1929 }
1930
1931 /**
1932 * @brief Check if LSE oscillator Ready
1933 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1934 * @retval State of bit (1 or 0).
1935 */
LL_RCC_LSE_IsReady(void)1936 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1937 {
1938 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL);
1939 }
1940
1941 /**
1942 * @}
1943 */
1944
1945 /** @defgroup RCC_LL_EF_LSI LSI
1946 * @{
1947 */
1948
1949 /**
1950 * @brief Enable LSI Oscillator
1951 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1952 * @retval None
1953 */
LL_RCC_LSI_Enable(void)1954 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1955 {
1956 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1957 }
1958
1959 /**
1960 * @brief Disable LSI Oscillator
1961 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1962 * @retval None
1963 */
LL_RCC_LSI_Disable(void)1964 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1965 {
1966 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1967 }
1968
1969 /**
1970 * @brief Check if LSI is Ready
1971 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1972 * @retval State of bit (1 or 0).
1973 */
LL_RCC_LSI_IsReady(void)1974 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1975 {
1976 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL);
1977 }
1978
1979 /**
1980 * @}
1981 */
1982
1983 /** @defgroup RCC_LL_EF_System System
1984 * @{
1985 */
1986
1987 /**
1988 * @brief Configure the system clock source
1989 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1990 * @param Source This parameter can be one of the following values:
1991 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1992 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
1993 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1994 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
1995 * @retval None
1996 */
LL_RCC_SetSysClkSource(uint32_t Source)1997 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1998 {
1999 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2000 }
2001
2002 /**
2003 * @brief Get the system clock source
2004 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2005 * @retval Returned value can be one of the following values:
2006 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2007 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2008 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2009 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2010 */
LL_RCC_GetSysClkSource(void)2011 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2012 {
2013 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2014 }
2015
2016 /**
2017 * @brief Configure the system wakeup clock source
2018 * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource
2019 * @param Source This parameter can be one of the following values:
2020 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2021 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2022 * @retval None
2023 */
LL_RCC_SetSysWakeUpClkSource(uint32_t Source)2024 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
2025 {
2026 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
2027 }
2028
2029 /**
2030 * @brief Get the system wakeup clock source
2031 * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource
2032 * @retval Returned value can be one of the following values:
2033 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2034 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2035 */
LL_RCC_GetSysWakeUpClkSource(void)2036 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
2037 {
2038 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2039 }
2040
2041 /**
2042 * @brief Configure the kernel wakeup clock source
2043 * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
2044 * @param Source This parameter can be one of the following values:
2045 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2046 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2047 * @retval None
2048 */
LL_RCC_SetKerWakeUpClkSource(uint32_t Source)2049 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
2050 {
2051 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
2052 }
2053
2054 /**
2055 * @brief Get the kernel wakeup clock source
2056 * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
2057 * @retval Returned value can be one of the following values:
2058 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2059 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2060 */
LL_RCC_GetKerWakeUpClkSource(void)2061 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
2062 {
2063 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
2064 }
2065
2066 /**
2067 * @brief Set System prescaler
2068 * @rmtoll CDCFGR CPRE LL_RCC_SetSysPrescaler
2069 * @param Prescaler This parameter can be one of the following values:
2070 * @arg @ref LL_RCC_SYSCLK_DIV_1
2071 * @arg @ref LL_RCC_SYSCLK_DIV_2
2072 * @arg @ref LL_RCC_SYSCLK_DIV_4
2073 * @arg @ref LL_RCC_SYSCLK_DIV_8
2074 * @arg @ref LL_RCC_SYSCLK_DIV_16
2075 * @arg @ref LL_RCC_SYSCLK_DIV_64
2076 * @arg @ref LL_RCC_SYSCLK_DIV_128
2077 * @arg @ref LL_RCC_SYSCLK_DIV_256
2078 * @arg @ref LL_RCC_SYSCLK_DIV_512
2079 * @retval None
2080 */
LL_RCC_SetSysPrescaler(uint32_t Prescaler)2081 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
2082 {
2083 MODIFY_REG(RCC->CDCFGR, RCC_CDCFGR_CPRE, Prescaler);
2084 }
2085
2086 /**
2087 * @brief Set AHB prescaler
2088 * @rmtoll BMCFGR BMPRE LL_RCC_SetAHBPrescaler
2089 * @param Prescaler This parameter can be one of the following values:
2090 * @arg @ref LL_RCC_AHB_DIV_1
2091 * @arg @ref LL_RCC_AHB_DIV_2
2092 * @arg @ref LL_RCC_AHB_DIV_4
2093 * @arg @ref LL_RCC_AHB_DIV_8
2094 * @arg @ref LL_RCC_AHB_DIV_16
2095 * @arg @ref LL_RCC_AHB_DIV_64
2096 * @arg @ref LL_RCC_AHB_DIV_128
2097 * @arg @ref LL_RCC_AHB_DIV_256
2098 * @arg @ref LL_RCC_AHB_DIV_512
2099 * @retval None
2100 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)2101 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2102 {
2103 MODIFY_REG(RCC->BMCFGR, RCC_BMCFGR_BMPRE, Prescaler);
2104 }
2105
2106 /**
2107 * @brief Set APB1 prescaler
2108 * @rmtoll APBCFGR PPRE1 LL_RCC_SetAPB1Prescaler
2109 * @param Prescaler This parameter can be one of the following values:
2110 * @arg @ref LL_RCC_APB1_DIV_1
2111 * @arg @ref LL_RCC_APB1_DIV_2
2112 * @arg @ref LL_RCC_APB1_DIV_4
2113 * @arg @ref LL_RCC_APB1_DIV_8
2114 * @arg @ref LL_RCC_APB1_DIV_16
2115 * @retval None
2116 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)2117 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2118 {
2119 MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE1, Prescaler);
2120 }
2121
2122 /**
2123 * @brief Set APB2 prescaler
2124 * @rmtoll APBCFGR PPRE2 LL_RCC_SetAPB2Prescaler
2125 * @param Prescaler This parameter can be one of the following values:
2126 * @arg @ref LL_RCC_APB2_DIV_1
2127 * @arg @ref LL_RCC_APB2_DIV_2
2128 * @arg @ref LL_RCC_APB2_DIV_4
2129 * @arg @ref LL_RCC_APB2_DIV_8
2130 * @arg @ref LL_RCC_APB2_DIV_16
2131 * @retval None
2132 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)2133 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2134 {
2135 MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE2, Prescaler);
2136 }
2137
2138 /**
2139 * @brief Set APB4 prescaler
2140 * @rmtoll APBCFGR PPRE4 LL_RCC_SetAPB4Prescaler
2141 * @param Prescaler This parameter can be one of the following values:
2142 * @arg @ref LL_RCC_APB4_DIV_1
2143 * @arg @ref LL_RCC_APB4_DIV_2
2144 * @arg @ref LL_RCC_APB4_DIV_4
2145 * @arg @ref LL_RCC_APB4_DIV_8
2146 * @arg @ref LL_RCC_APB4_DIV_16
2147 * @retval None
2148 */
LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)2149 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2150 {
2151 MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE4, Prescaler);
2152 }
2153
2154 /**
2155 * @brief Set APB5 prescaler
2156 * @rmtoll APBCFGR PPRE5 LL_RCC_SetAPB5Prescaler
2157 * @param Prescaler This parameter can be one of the following values:
2158 * @arg @ref LL_RCC_APB5_DIV_1
2159 * @arg @ref LL_RCC_APB5_DIV_2
2160 * @arg @ref LL_RCC_APB5_DIV_4
2161 * @arg @ref LL_RCC_APB5_DIV_8
2162 * @arg @ref LL_RCC_APB5_DIV_16
2163 * @retval None
2164 */
LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)2165 __STATIC_INLINE void LL_RCC_SetAPB5Prescaler(uint32_t Prescaler)
2166 {
2167 MODIFY_REG(RCC->APBCFGR, RCC_APBCFGR_PPRE5, Prescaler);
2168 }
2169
2170 /**
2171 * @brief Get System prescaler
2172 * @rmtoll CDCFGR CPRE LL_RCC_GetSysPrescaler
2173 * @retval Returned value can be one of the following values:
2174 * @arg @ref LL_RCC_SYSCLK_DIV_1
2175 * @arg @ref LL_RCC_SYSCLK_DIV_2
2176 * @arg @ref LL_RCC_SYSCLK_DIV_4
2177 * @arg @ref LL_RCC_SYSCLK_DIV_8
2178 * @arg @ref LL_RCC_SYSCLK_DIV_16
2179 * @arg @ref LL_RCC_SYSCLK_DIV_64
2180 * @arg @ref LL_RCC_SYSCLK_DIV_128
2181 * @arg @ref LL_RCC_SYSCLK_DIV_256
2182 * @arg @ref LL_RCC_SYSCLK_DIV_512
2183 */
LL_RCC_GetSysPrescaler(void)2184 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
2185 {
2186 return (uint32_t)(READ_BIT(RCC->CDCFGR, RCC_CDCFGR_CPRE));
2187 }
2188
2189 /**
2190 * @brief Get AHB prescaler
2191 * @rmtoll BMCFGR BMPRE LL_RCC_GetAHBPrescaler
2192 * @retval Returned value can be one of the following values:
2193 * @arg @ref LL_RCC_AHB_DIV_1
2194 * @arg @ref LL_RCC_AHB_DIV_2
2195 * @arg @ref LL_RCC_AHB_DIV_4
2196 * @arg @ref LL_RCC_AHB_DIV_8
2197 * @arg @ref LL_RCC_AHB_DIV_16
2198 * @arg @ref LL_RCC_AHB_DIV_64
2199 * @arg @ref LL_RCC_AHB_DIV_128
2200 * @arg @ref LL_RCC_AHB_DIV_256
2201 * @arg @ref LL_RCC_AHB_DIV_512
2202 */
LL_RCC_GetAHBPrescaler(void)2203 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2204 {
2205 return (uint32_t)(READ_BIT(RCC->BMCFGR, RCC_BMCFGR_BMPRE));
2206 }
2207
2208 /**
2209 * @brief Get APB1 prescaler
2210 * @rmtoll APBCFGR PPRE1 LL_RCC_GetAPB1Prescaler
2211 * @retval Returned value can be one of the following values:
2212 * @arg @ref LL_RCC_APB1_DIV_1
2213 * @arg @ref LL_RCC_APB1_DIV_2
2214 * @arg @ref LL_RCC_APB1_DIV_4
2215 * @arg @ref LL_RCC_APB1_DIV_8
2216 * @arg @ref LL_RCC_APB1_DIV_16
2217 */
LL_RCC_GetAPB1Prescaler(void)2218 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2219 {
2220 return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE1));
2221 }
2222
2223 /**
2224 * @brief Get APB2 prescaler
2225 * @rmtoll APBCFGR PPRE2 LL_RCC_GetAPB2Prescaler
2226 * @retval Returned value can be one of the following values:
2227 * @arg @ref LL_RCC_APB2_DIV_1
2228 * @arg @ref LL_RCC_APB2_DIV_2
2229 * @arg @ref LL_RCC_APB2_DIV_4
2230 * @arg @ref LL_RCC_APB2_DIV_8
2231 * @arg @ref LL_RCC_APB2_DIV_16
2232 */
LL_RCC_GetAPB2Prescaler(void)2233 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2234 {
2235 return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE2));
2236 }
2237
2238 /**
2239 * @brief Get APB4 prescaler
2240 * @rmtoll APBCFGR PPRE4 LL_RCC_GetAPB4Prescaler
2241 * @retval Returned value can be one of the following values:
2242 * @arg @ref LL_RCC_APB4_DIV_1
2243 * @arg @ref LL_RCC_APB4_DIV_2
2244 * @arg @ref LL_RCC_APB4_DIV_4
2245 * @arg @ref LL_RCC_APB4_DIV_8
2246 * @arg @ref LL_RCC_APB4_DIV_16
2247 */
LL_RCC_GetAPB4Prescaler(void)2248 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2249 {
2250 return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE4));
2251 }
2252
2253 /**
2254 * @brief Get APB5 prescaler
2255 * @rmtoll APBCFGR PPRE5 LL_RCC_GetAPB5Prescaler
2256 * @retval Returned value can be one of the following values:
2257 * @arg @ref LL_RCC_APB5_DIV_1
2258 * @arg @ref LL_RCC_APB5_DIV_2
2259 * @arg @ref LL_RCC_APB5_DIV_4
2260 * @arg @ref LL_RCC_APB5_DIV_8
2261 * @arg @ref LL_RCC_APB5_DIV_16
2262 */
LL_RCC_GetAPB5Prescaler(void)2263 __STATIC_INLINE uint32_t LL_RCC_GetAPB5Prescaler(void)
2264 {
2265 return (uint32_t)(READ_BIT(RCC->APBCFGR, RCC_APBCFGR_PPRE5));
2266 }
2267
2268 /**
2269 * @}
2270 */
2271
2272 /** @defgroup RCC_LL_EF_MCO MCO
2273 * @{
2274 */
2275
2276 /**
2277 * @brief Configure MCOx
2278 * @rmtoll CFGR MCO1SEL LL_RCC_ConfigMCO\n
2279 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2280 * CFGR MCO2SEL LL_RCC_ConfigMCO\n
2281 * CFGR MCO2PRE LL_RCC_ConfigMCO
2282 * @param MCOxSource This parameter can be one of the following values:
2283 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2284 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2285 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2286 * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q
2287 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2288 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2289 * @arg @ref LL_RCC_MCO2SOURCE_PLL2P
2290 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2291 * @arg @ref LL_RCC_MCO2SOURCE_PLL1P
2292 * @arg @ref LL_RCC_MCO2SOURCE_CSI
2293 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2294 * @param MCOxPrescaler This parameter can be one of the following values:
2295 * @arg @ref LL_RCC_MCO1_DIV_1
2296 * @arg @ref LL_RCC_MCO1_DIV_2
2297 * @arg @ref LL_RCC_MCO1_DIV_3
2298 * @arg @ref LL_RCC_MCO1_DIV_4
2299 * @arg @ref LL_RCC_MCO1_DIV_5
2300 * @arg @ref LL_RCC_MCO1_DIV_6
2301 * @arg @ref LL_RCC_MCO1_DIV_7
2302 * @arg @ref LL_RCC_MCO1_DIV_8
2303 * @arg @ref LL_RCC_MCO1_DIV_9
2304 * @arg @ref LL_RCC_MCO1_DIV_10
2305 * @arg @ref LL_RCC_MCO1_DIV_11
2306 * @arg @ref LL_RCC_MCO1_DIV_12
2307 * @arg @ref LL_RCC_MCO1_DIV_13
2308 * @arg @ref LL_RCC_MCO1_DIV_14
2309 * @arg @ref LL_RCC_MCO1_DIV_15
2310 * @arg @ref LL_RCC_MCO2_DIV_1
2311 * @arg @ref LL_RCC_MCO2_DIV_2
2312 * @arg @ref LL_RCC_MCO2_DIV_3
2313 * @arg @ref LL_RCC_MCO2_DIV_4
2314 * @arg @ref LL_RCC_MCO2_DIV_5
2315 * @arg @ref LL_RCC_MCO2_DIV_6
2316 * @arg @ref LL_RCC_MCO2_DIV_7
2317 * @arg @ref LL_RCC_MCO2_DIV_8
2318 * @arg @ref LL_RCC_MCO2_DIV_9
2319 * @arg @ref LL_RCC_MCO2_DIV_10
2320 * @arg @ref LL_RCC_MCO2_DIV_11
2321 * @arg @ref LL_RCC_MCO2_DIV_12
2322 * @arg @ref LL_RCC_MCO2_DIV_13
2323 * @arg @ref LL_RCC_MCO2_DIV_14
2324 * @arg @ref LL_RCC_MCO2_DIV_15
2325 * @retval None
2326 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2327 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2328 {
2329 MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2330 }
2331
2332 /**
2333 * @}
2334 */
2335
2336 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2337 * @{
2338 */
2339
2340 /**
2341 * @brief Configure periph clock source
2342 * @rmtoll CCIPR1 * LL_RCC_SetClockSource\n
2343 * CCIPR2 * LL_RCC_SetClockSource\n
2344 * CCIPR3 * LL_RCC_SetClockSource\n
2345 * CCIPR4 * LL_RCC_SetClockSource
2346 * @param ClkSource This parameter can be one of the following values:
2347 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2348 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R
2349 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2350 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2351 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1
2352 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R
2353 * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI
2354 * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI
2355 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2356 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2357 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2358 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2359 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2360 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2361 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4
2362 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P
2363 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R
2364 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
2365 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
2366 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP
2367 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4
2368 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P
2369 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R
2370 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
2371 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
2372 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP
2373 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2374 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2375 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2376 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2377 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2378 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
2379 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
2380 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
2381 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
2382 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
2383 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX
2384 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2385 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2386 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
2387 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
2388 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2389 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q
2390 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P
2391 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P
2392 * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN
2393 * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP
2394 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2395 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2396 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2397 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2398 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2399 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2400 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2401 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2402 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2403 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2404 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2405 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2406 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2407 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2408 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
2409 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2410 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2411 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2412 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2413 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2414 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2415 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2416 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2417 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2418 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
2419 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S
2420 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T
2421 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
2422 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S
2423 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T
2424 * @retval None
2425 */
LL_RCC_SetClockSource(uint32_t ClkSource)2426 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2427 {
2428 volatile uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CCIPR1 + LL_CLKSOURCE_REG(ClkSource));
2429 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2430 }
2431
2432 /**
2433 * @brief Configure ADCx Kernel clock source
2434 * @rmtoll CCIPR1 ADCSEL LL_RCC_SetADCClockSource
2435 * @param ClkSource This parameter can be one of the following values:
2436 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
2437 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
2438 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
2439 * @retval None
2440 */
LL_RCC_SetADCClockSource(uint32_t ClkSource)2441 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
2442 {
2443 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, ClkSource);
2444 }
2445
2446 /**
2447 * @brief Configure ADFx Kernel clock source
2448 * @rmtoll CCIPR1 ADF1SEL LL_RCC_SetADFClockSource
2449 * @param ClkSource This parameter can be one of the following values:
2450 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
2451 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P
2452 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P
2453 * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
2454 * @arg @ref LL_RCC_ADF1_CLKSOURCE_CSI
2455 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI
2456 * @retval None
2457 */
LL_RCC_SetADFClockSource(uint32_t ClkSource)2458 __STATIC_INLINE void LL_RCC_SetADFClockSource(uint32_t ClkSource)
2459 {
2460 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL, ClkSource);
2461 }
2462
2463 /**
2464 * @brief Configure CECx clock source
2465 * @rmtoll CCIPR2 CECSEL LL_RCC_SetCECClockSource
2466 * @param ClkSource This parameter can be one of the following values:
2467 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2468 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
2469 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV_122
2470 * @retval None
2471 */
LL_RCC_SetCECClockSource(uint32_t ClkSource)2472 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
2473 {
2474 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_CECSEL, ClkSource);
2475 }
2476
2477 /**
2478 * @brief Configure CLKP Kernel clock source
2479 * @rmtoll CCIPR1 CKPERSEL LL_RCC_SetCLKPClockSource
2480 * @param ClkSource This parameter can be one of the following values:
2481 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
2482 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
2483 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
2484 * @retval None
2485 */
LL_RCC_SetCLKPClockSource(uint32_t ClkSource)2486 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
2487 {
2488 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL, ClkSource);
2489 }
2490
2491 /**
2492 * @brief Configure ETHx PHY clock source
2493 * @rmtoll CCIPR1 ETH1PHYCKSEL LL_RCC_SetETHPHYClockSource
2494 * @param ClkSource This parameter can be one of the following values:
2495 * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_HSE
2496 * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_PLL3S
2497 * @retval None
2498 */
LL_RCC_SetETHPHYClockSource(uint32_t ClkSource)2499 __STATIC_INLINE void LL_RCC_SetETHPHYClockSource(uint32_t ClkSource)
2500 {
2501 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL, ClkSource);
2502 }
2503
2504 /**
2505 * @brief Configure ETHx REF clock source
2506 * @rmtoll CCIPR1 ETH1REFCKSEL LL_RCC_SetETHREFClockSource
2507 * @param ClkSource This parameter can be one of the following values:
2508 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII
2509 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_HSE
2510 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB
2511 * @retval None
2512 */
LL_RCC_SetETHREFClockSource(uint32_t ClkSource)2513 __STATIC_INLINE void LL_RCC_SetETHREFClockSource(uint32_t ClkSource)
2514 {
2515 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL, ClkSource);
2516 }
2517
2518 /**
2519 * @brief Configure FDCANx Kernel clock source
2520 * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource
2521 * @param ClkSource This parameter can be one of the following values:
2522 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
2523 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
2524 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
2525 * @retval None
2526 */
LL_RCC_SetFDCANClockSource(uint32_t ClkSource)2527 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
2528 {
2529 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, ClkSource);
2530 }
2531
2532 /**
2533 * @brief Configure FMCx Kernel clock source
2534 * @rmtoll CCIPR1 FMCSEL LL_RCC_SetFMCClockSource
2535 * @param ClkSource This parameter can be one of the following values:
2536 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
2537 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
2538 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
2539 * @arg @ref LL_RCC_FMC_CLKSOURCE_HSI
2540 * @retval None
2541 */
LL_RCC_SetFMCClockSource(uint32_t ClkSource)2542 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
2543 {
2544 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FMCSEL, ClkSource);
2545 }
2546
2547 /**
2548 * @brief Configure I2Cx clock source
2549 * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_SetI2CClockSource
2550 * @rmtoll CCIPR2 I2C23SEL LL_RCC_SetI2CClockSource
2551 * @param ClkSource This parameter can be one of the following values:
2552 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2553 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R
2554 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2555 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2556 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1
2557 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R
2558 * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI
2559 * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI
2560 * @retval None
2561 */
LL_RCC_SetI2CClockSource(uint32_t ClkSource)2562 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
2563 {
2564 LL_RCC_SetClockSource(ClkSource);
2565 }
2566
2567 /**
2568 * @brief Configure I3Cx clock source
2569 * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_SetI3CClockSource
2570 * @param ClkSource This parameter can be one of the following values:
2571 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
2572 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R
2573 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
2574 * @arg @ref LL_RCC_I3C1_CLKSOURCE_CSI
2575 * @retval None
2576 */
LL_RCC_SetI3CClockSource(uint32_t ClkSource)2577 __STATIC_INLINE void LL_RCC_SetI3CClockSource(uint32_t ClkSource)
2578 {
2579 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL, ClkSource);
2580 }
2581
2582 /**
2583 * @brief Configure LPTIMx clock source
2584 * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n
2585 * CCIPR4 LPTIM23SEL LL_RCC_SetLPTIMClockSource\n
2586 * CCIPR4 LPTIM45SEL LL_RCC_SetLPTIMClockSource
2587 * @param ClkSource This parameter can be one of the following values:
2588 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2589 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2590 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2591 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2592 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2593 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2594 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4
2595 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P
2596 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R
2597 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
2598 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
2599 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP
2600 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4
2601 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P
2602 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R
2603 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
2604 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
2605 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP
2606 * @retval None
2607 */
LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)2608 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
2609 {
2610 LL_RCC_SetClockSource(ClkSource);
2611 }
2612
2613 /**
2614 * @brief Configure LPUARTx clock source
2615 * @rmtoll CCIPR4 LPUART1SEL LL_RCC_SetLPUARTClockSource
2616 * @param ClkSource This parameter can be one of the following values:
2617 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
2618 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2619 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
2620 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2621 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2622 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2623 * @retval None
2624 */
LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)2625 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
2626 {
2627 MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL, ClkSource);
2628 }
2629
2630 /**
2631 * @brief Configure OTGFSx clock source
2632 * @rmtoll CCIPR1 OTGFSSEL LL_RCC_SetOTGFSClockSource
2633 * @param ClkSource This parameter can be one of the following values:
2634 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48
2635 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48
2636 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSE
2637 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q
2638 * @retval None
2639 */
LL_RCC_SetOTGFSClockSource(uint32_t ClkSource)2640 __STATIC_INLINE void LL_RCC_SetOTGFSClockSource(uint32_t ClkSource)
2641 {
2642 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL, ClkSource);
2643 }
2644
2645 /**
2646 * @brief Configure XSPIx Kernel clock source
2647 * @rmtoll CCIPR1 XSPI1SEL LL_RCC_SetXSPIClockSource\n
2648 * CCIPR1 XSPI2SEL LL_RCC_SetXSPIClockSource
2649 * @param ClkSource This parameter can be one of the following values:
2650 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
2651 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S
2652 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T
2653 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
2654 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S
2655 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T
2656 * @retval None
2657 */
LL_RCC_SetXSPIClockSource(uint32_t ClkSource)2658 __STATIC_INLINE void LL_RCC_SetXSPIClockSource(uint32_t ClkSource)
2659 {
2660 LL_RCC_SetClockSource(ClkSource);
2661 }
2662
2663 /**
2664 * @brief Configure PSSI clock source
2665 * @rmtoll CCIPR1 PSSISEL LL_RCC_SetPSSIClockSource
2666 * @param ClkSource This parameter can be one of the following values:
2667 * @arg @ref LL_RCC_PSSI_CLKSOURCE_PLL3R
2668 * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP
2669 * @retval None
2670 */
LL_RCC_SetPSSIClockSource(uint32_t ClkSource)2671 __STATIC_INLINE void LL_RCC_SetPSSIClockSource(uint32_t ClkSource)
2672 {
2673 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_PSSISEL, ClkSource);
2674 }
2675
2676 /**
2677 * @brief Configure SAIx clock source
2678 * @rmtoll CCIPR3 SAI1SEL LL_RCC_SetSAIClockSource\n
2679 * CCIPR3 SAI2SEL LL_RCC_SetSAIClockSource
2680 * @param ClkSource This parameter can be one of the following values:
2681 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2682 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2683 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2684 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2685 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2686 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
2687 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
2688 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
2689 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
2690 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
2691 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX
2692 * @retval None
2693 */
LL_RCC_SetSAIClockSource(uint32_t ClkSource)2694 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
2695 {
2696 LL_RCC_SetClockSource(ClkSource);
2697 }
2698
2699 /**
2700 * @brief Configure SDMMCx clock source
2701 * @rmtoll CCIPR1 SDMMCSEL LL_RCC_SetSDMMCClockSource
2702 * @param ClkSource This parameter can be one of the following values:
2703 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2S
2704 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2T
2705 * @retval None
2706 */
LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)2707 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
2708 {
2709 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL, ClkSource);
2710 }
2711
2712 /**
2713 * @brief Configure SPDIFRX Kernel clock source
2714 * @rmtoll CCIPR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
2715 * @param ClkSource This parameter can be one of the following values:
2716 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q
2717 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL2R
2718 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL3R
2719 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_HSI
2720 * @retval None
2721 */
LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)2722 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t ClkSource)
2723 {
2724 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL, ClkSource);
2725 }
2726
2727 /**
2728 * @brief Configure SPIx Kernel clock source
2729 * @rmtoll CCIPR3 SPI1SEL LL_RCC_SetSPIClockSource\n
2730 * CCIPR2 SPI23SEL LL_RCC_SetSPIClockSource\n
2731 * CCIPR3 SPI45SEL LL_RCC_SetSPIClockSource\n
2732 * CCIPR4 SPI6SEL LL_RCC_SetSPIClockSource
2733 * @param ClkSource This parameter can be one of the following values:
2734 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2735 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2736 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
2737 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
2738 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2739 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q
2740 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P
2741 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P
2742 * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN
2743 * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP
2744 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2745 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2746 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2747 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2748 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2749 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2750 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2751 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2752 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2753 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2754 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2755 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2756 * @retval None
2757 */
LL_RCC_SetSPIClockSource(uint32_t ClkSource)2758 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
2759 {
2760 LL_RCC_SetClockSource(ClkSource);
2761 }
2762
2763 /**
2764 * @brief Configure USARTx clock source
2765 * @rmtoll CCIPR3 USART1SEL LL_RCC_SetUSARTClockSource\n
2766 * CCIPR2 UART234578SEL LL_RCC_SetUSARTClockSource
2767 * @param ClkSource This parameter can be one of the following values:
2768 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2769 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2770 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
2771 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2772 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2773 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2774 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2775 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2776 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2777 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2778 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2779 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2780 * @retval None
2781 */
LL_RCC_SetUSARTClockSource(uint32_t ClkSource)2782 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
2783 {
2784 LL_RCC_SetClockSource(ClkSource);
2785 }
2786
2787 /**
2788 * @brief Configure USBPHYC clock source
2789 * @rmtoll CCIPR1 USBPHYCSEL LL_RCC_SetUSBPHYCClockSource
2790 * @param ClkSource This parameter can be one of the following values:
2791 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_DISABLE
2792 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE
2793 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2
2794 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_PLL3Q
2795 * @retval None
2796 */
LL_RCC_SetUSBPHYCClockSource(uint32_t ClkSource)2797 __STATIC_INLINE void LL_RCC_SetUSBPHYCClockSource(uint32_t ClkSource)
2798 {
2799 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL, ClkSource);
2800 }
2801
2802 /**
2803 * @brief Configure USBREF clock source
2804 * @rmtoll CCIPR1 USBREFCKSEL LL_RCC_SetUSBREFClockSource
2805 * @param ClkSource This parameter can be one of the following values:
2806 * @arg @ref LL_RCC_USBREF_CLKSOURCE_16M
2807 * @arg @ref LL_RCC_USBREF_CLKSOURCE_19_2M
2808 * @arg @ref LL_RCC_USBREF_CLKSOURCE_20M
2809 * @arg @ref LL_RCC_USBREF_CLKSOURCE_24M
2810 * @arg @ref LL_RCC_USBREF_CLKSOURCE_26M
2811 * @arg @ref LL_RCC_USBREF_CLKSOURCE_32M
2812 * @retval None
2813 */
LL_RCC_SetUSBREFClockSource(uint32_t ClkSource)2814 __STATIC_INLINE void LL_RCC_SetUSBREFClockSource(uint32_t ClkSource)
2815 {
2816 MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USBREFCKSEL, ClkSource);
2817 }
2818
2819 /**
2820 * @brief Get periph clock source
2821 * @rmtoll CCIPR1 * LL_RCC_GetClockSource\n
2822 * CCIPR2 * LL_RCC_GetClockSource\n
2823 * CCIPR3 * LL_RCC_GetClockSource\n
2824 * CCIPR4 * LL_RCC_GetClockSource
2825 * @param Periph This parameter can be one of the following values:
2826 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2827 * @arg @ref LL_RCC_I2C23_CLKSOURCE
2828 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2829 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE
2830 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE
2831 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2832 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2833 * @arg @ref LL_RCC_SPI1_CLKSOURCE
2834 * @arg @ref LL_RCC_SPI23_CLKSOURCE
2835 * @arg @ref LL_RCC_SPI45_CLKSOURCE
2836 * @arg @ref LL_RCC_SPI6_CLKSOURCE
2837 * @arg @ref LL_RCC_USART1_CLKSOURCE
2838 * @arg @ref LL_RCC_USART234578_CLKSOURCE
2839 * @arg @ref LL_RCC_XSPI1_CLKSOURCE
2840 * @arg @ref LL_RCC_XSPI2_CLKSOURCE
2841 * @retval Returned value can be one of the following values:
2842 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2843 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R
2844 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2845 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
2846 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1
2847 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R
2848 * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI
2849 * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI
2850 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2851 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2852 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2853 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2854 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2855 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2856 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4
2857 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P
2858 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R
2859 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
2860 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
2861 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP
2862 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4
2863 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P
2864 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R
2865 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
2866 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
2867 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP
2868 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2869 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2870 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2871 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2872 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2873 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
2874 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
2875 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
2876 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
2877 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
2878 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX
2879 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
2880 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
2881 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
2882 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
2883 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
2884 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q
2885 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P
2886 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P
2887 * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN
2888 * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP
2889 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2890 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2891 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2892 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2893 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2894 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2895 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2896 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2897 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2898 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2899 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2900 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2901 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2902 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
2903 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
2904 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2905 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
2906 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2907 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2908 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2909 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2910 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2911 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2912 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2913 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
2914 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S
2915 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T
2916 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
2917 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S
2918 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T
2919 * @retval None
2920 */
LL_RCC_GetClockSource(uint32_t Periph)2921 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
2922 {
2923 const volatile uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CCIPR1) + LL_CLKSOURCE_REG(Periph)));
2924 return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
2925 }
2926
2927 /**
2928 * @brief Get ADC Kernel clock source
2929 * @rmtoll CCIPR1 ADCSEL LL_RCC_GetADCClockSource
2930 * @param Periph This parameter can be one of the following values:
2931 * @arg @ref LL_RCC_ADC_CLKSOURCE
2932 * @retval Returned value can be one of the following values:
2933 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
2934 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
2935 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
2936 */
LL_RCC_GetADCClockSource(uint32_t Periph)2937 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
2938 {
2939 UNUSED(Periph);
2940 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADCSEL));
2941 }
2942
2943 /**
2944 * @brief Get ADF clock source
2945 * @rmtoll CCIPR1 ADF1SEL LL_RCC_GetADFClockSource
2946 * @param Periph This parameter can be one of the following values:
2947 * @arg @ref LL_RCC_ADF1_CLKSOURCE
2948 * @retval Returned value can be one of the following values:
2949 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK
2950 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P
2951 * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P
2952 * @arg @ref LL_RCC_ADF1_CLKSOURCE_I2S_CKIN
2953 * @arg @ref LL_RCC_ADF1_CLKSOURCE_CSI
2954 * @arg @ref LL_RCC_ADF1_CLKSOURCE_HSI
2955 */
LL_RCC_GetADFClockSource(uint32_t Periph)2956 __STATIC_INLINE uint32_t LL_RCC_GetADFClockSource(uint32_t Periph)
2957 {
2958 UNUSED(Periph);
2959 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ADF1SEL));
2960 }
2961
2962 /**
2963 * @brief Get CEC clock source
2964 * @rmtoll CCIPR2 CECSEL LL_RCC_GetCECClockSource
2965 * @param Periph This parameter can be one of the following values:
2966 * @arg @ref LL_RCC_CEC_CLKSOURCE
2967 * @retval Returned value can be one of the following values:
2968 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2969 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
2970 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV_122
2971 */
LL_RCC_GetCECClockSource(uint32_t Periph)2972 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
2973 {
2974 UNUSED(Periph);
2975 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_CECSEL));
2976 }
2977
2978 /**
2979 * @brief Get CLKP Kernel clock source
2980 * @rmtoll CCIPR1 CKPERSEL LL_RCC_GetCLKPClockSource
2981 * @param Periph This parameter can be one of the following values:
2982 * @arg @ref LL_RCC_CLKP_CLKSOURCE
2983 * @retval Returned value can be one of the following values:
2984 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
2985 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
2986 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
2987 */
LL_RCC_GetCLKPClockSource(uint32_t Periph)2988 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
2989 {
2990 UNUSED(Periph);
2991 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CKPERSEL));
2992 }
2993
2994 /**
2995 * @brief Get ETH PHY clock source
2996 * @rmtoll CCIPR1 ETH1PHYCKSEL LL_RCC_GetETHPHYClockSource
2997 * @param Periph This parameter can be one of the following values:
2998 * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE
2999 * @retval Returned value can be one of the following values:
3000 * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_HSE
3001 * @arg @ref LL_RCC_ETH1PHY_CLKSOURCE_PLL3S
3002 */
LL_RCC_GetETHPHYClockSource(uint32_t Periph)3003 __STATIC_INLINE uint32_t LL_RCC_GetETHPHYClockSource(uint32_t Periph)
3004 {
3005 UNUSED(Periph);
3006 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1PHYCKSEL));
3007 }
3008
3009 /**
3010 * @brief Get ETH REF clock source
3011 * @rmtoll CCIPR1 ETH1REFCKSEL LL_RCC_GetETHREFClockSource
3012 * @param Periph This parameter can be one of the following values:
3013 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE
3014 * @retval Returned value can be one of the following values:
3015 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_RMII
3016 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_HSE
3017 * @arg @ref LL_RCC_ETH1REF_CLKSOURCE_FB
3018 */
LL_RCC_GetETHREFClockSource(uint32_t Periph)3019 __STATIC_INLINE uint32_t LL_RCC_GetETHREFClockSource(uint32_t Periph)
3020 {
3021 UNUSED(Periph);
3022 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ETH1REFCKSEL));
3023 }
3024
3025 /**
3026 * @brief Get FDCAN Kernel clock source
3027 * @rmtoll CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource
3028 * @param Periph This parameter can be one of the following values:
3029 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3030 * @retval Returned value can be one of the following values:
3031 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3032 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3033 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3034 */
LL_RCC_GetFDCANClockSource(uint32_t Periph)3035 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
3036 {
3037 UNUSED(Periph);
3038 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL));
3039 }
3040
3041 /**
3042 * @brief Get FMC Kernel clock source
3043 * @rmtoll CCIPR1 FMCSEL LL_RCC_GetFMCClockSource
3044 * @param Periph This parameter can be one of the following values:
3045 * @arg @ref LL_RCC_FMC_CLKSOURCE
3046 * @retval Returned value can be one of the following values:
3047 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3048 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3049 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3050 * @arg @ref LL_RCC_FMC_CLKSOURCE_HSI
3051 */
LL_RCC_GetFMCClockSource(uint32_t Periph)3052 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
3053 {
3054 UNUSED(Periph);
3055 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FMCSEL));
3056 }
3057
3058 /**
3059 * @brief Get I2Cx clock source
3060 * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_GetI2CClockSource
3061 * @rmtoll CCIPR2 I2C23SEL LL_RCC_GetI2CClockSource
3062 * @param Periph This parameter can be one of the following values:
3063 * @arg @ref LL_RCC_I2C1_CLKSOURCE
3064 * @arg @ref LL_RCC_I2C23_CLKSOURCE
3065 * @retval Returned value can be one of the following values:
3066 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
3067 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PLL3R
3068 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
3069 * @arg @ref LL_RCC_I2C1_CLKSOURCE_CSI
3070 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PCLK1
3071 * @arg @ref LL_RCC_I2C23_CLKSOURCE_PLL3R
3072 * @arg @ref LL_RCC_I2C23_CLKSOURCE_HSI
3073 * @arg @ref LL_RCC_I2C23_CLKSOURCE_CSI
3074 */
LL_RCC_GetI2CClockSource(uint32_t Periph)3075 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
3076 {
3077 return LL_RCC_GetClockSource(Periph);
3078 }
3079
3080 /**
3081 * @brief Get I3Cx clock source
3082 * @rmtoll CCIPR2 I2C1_I3C1SEL LL_RCC_GetI3CClockSource
3083 * @param Periph This parameter can be one of the following values:
3084 * @arg @ref LL_RCC_I3C1_CLKSOURCE
3085 * @retval Returned value can be one of the following values:
3086 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1
3087 * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R
3088 * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI
3089 * @arg @ref LL_RCC_I3C1_CLKSOURCE_CSI
3090 */
LL_RCC_GetI3CClockSource(uint32_t Periph)3091 __STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t Periph)
3092 {
3093 UNUSED(Periph);
3094 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C1_I3C1SEL));
3095 }
3096
3097 /**
3098 * @brief Get LPTIM clock source
3099 * @rmtoll CCIPR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
3100 * CCIPR4 LPTIM23SEL LL_RCC_GetLPTIMClockSource\n
3101 * CCIPR4 LPTIM45SEL LL_RCC_GetLPTIMClockSource
3102 * @param Periph This parameter can be one of the following values:
3103 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3104 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE
3105 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE
3106 * @retval Returned value can be one of the following values:
3107 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3108 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3109 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3110 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3111 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3112 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3113 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PCLK4
3114 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL2P
3115 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_PLL3R
3116 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSE
3117 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_LSI
3118 * @arg @ref LL_RCC_LPTIM23_CLKSOURCE_CLKP
3119 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PCLK4
3120 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL2P
3121 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_PLL3R
3122 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSE
3123 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_LSI
3124 * @arg @ref LL_RCC_LPTIM45_CLKSOURCE_CLKP
3125 * @retval None
3126 */
LL_RCC_GetLPTIMClockSource(uint32_t Periph)3127 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
3128 {
3129 return LL_RCC_GetClockSource(Periph);
3130 }
3131
3132 /**
3133 * @brief Get LPUART clock source
3134 * @rmtoll CCIPR4 LPUART1SEL LL_RCC_GetLPUARTClockSource
3135 * @param Periph This parameter can be one of the following values:
3136 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3137 * @retval Returned value can be one of the following values:
3138 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3139 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3140 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
3141 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3142 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3143 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3144 */
LL_RCC_GetLPUARTClockSource(uint32_t Periph)3145 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
3146 {
3147 UNUSED(Periph);
3148 return (uint32_t)(READ_BIT(RCC->CCIPR4, RCC_CCIPR4_LPUART1SEL));
3149 }
3150
3151 /**
3152 * @brief Get OTGFS clock source
3153 * @rmtoll CCIPR1 OTGFSSEL LL_RCC_GetOTGFSClockSource
3154 * @param Periph This parameter can be one of the following values:
3155 * @arg @ref LL_RCC_OTGFS_CLKSOURCE
3156 * @retval Returned value can be one of the following values:
3157 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSE
3158 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48
3159 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q
3160 * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48
3161 */
LL_RCC_GetOTGFSClockSource(uint32_t Periph)3162 __STATIC_INLINE uint32_t LL_RCC_GetOTGFSClockSource(uint32_t Periph)
3163 {
3164 UNUSED(Periph);
3165 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_OTGFSSEL));
3166 }
3167
3168 /**
3169 * @brief Get XSPI Kernel clock source
3170 * @rmtoll CCIPR1 XSPI1SEL LL_RCC_GetXSPIClockSource\n
3171 * CCIPR1 XSPI2SEL LL_RCC_GetXSPIClockSource
3172 * @param Periph This parameter can be one of the following values:
3173 * @arg @ref LL_RCC_XSPI1_CLKSOURCE
3174 * @arg @ref LL_RCC_XSPI2_CLKSOURCE
3175 * @retval Returned value can be one of the following values:
3176 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_HCLK
3177 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2S
3178 * @arg @ref LL_RCC_XSPI1_CLKSOURCE_PLL2T
3179 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_HCLK
3180 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2S
3181 * @arg @ref LL_RCC_XSPI2_CLKSOURCE_PLL2T
3182 */
LL_RCC_GetXSPIClockSource(uint32_t Periph)3183 __STATIC_INLINE uint32_t LL_RCC_GetXSPIClockSource(uint32_t Periph)
3184 {
3185 return LL_RCC_GetClockSource(Periph);
3186 }
3187
3188 /**
3189 * @brief Get PSSI clock source
3190 * @rmtoll CCIPR1 PSSISEL LL_RCC_GetPSSIClockSource
3191 * @param Periph This parameter can be one of the following values:
3192 * @arg @ref LL_RCC_PSSI_CLKSOURCE
3193 * @retval Returned value can be one of the following values:
3194 * @arg @ref LL_RCC_PSSI_CLKSOURCE_PLL3R
3195 * @arg @ref LL_RCC_PSSI_CLKSOURCE_CLKP
3196 */
LL_RCC_GetPSSIClockSource(uint32_t Periph)3197 __STATIC_INLINE uint32_t LL_RCC_GetPSSIClockSource(uint32_t Periph)
3198 {
3199 UNUSED(Periph);
3200 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_PSSISEL));
3201 }
3202
3203 /**
3204 * @brief Get SAIx clock source
3205 * @rmtoll CCIPR3 SAI1SEL LL_RCC_GetSAIClockSource\n
3206 * CCIPR3 SAI2SEL LL_RCC_GetSAIClockSource
3207 * @param Periph This parameter can be one of the following values:
3208 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3209 * @arg @ref LL_RCC_SAI2_CLKSOURCE
3210 * @retval Returned value can be one of the following values:
3211 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3212 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3213 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3214 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3215 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3216 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1Q
3217 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2P
3218 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3P
3219 * @arg @ref LL_RCC_SAI2_CLKSOURCE_I2S_CKIN
3220 * @arg @ref LL_RCC_SAI2_CLKSOURCE_CLKP
3221 * @arg @ref LL_RCC_SAI2_CLKSOURCE_SPDIFRX
3222 */
LL_RCC_GetSAIClockSource(uint32_t Periph)3223 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
3224 {
3225 UNUSED(Periph);
3226 return LL_RCC_GetClockSource(Periph);
3227 }
3228
3229 /**
3230 * @brief Get SDMMC clock source
3231 * @rmtoll CCIPR1 SDMMCSEL LL_RCC_GetSDMMCClockSource
3232 * @param Periph This parameter can be one of the following values:
3233 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
3234 * @retval Returned value can be one of the following values:
3235 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2S
3236 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2T
3237 */
LL_RCC_GetSDMMCClockSource(uint32_t Periph)3238 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
3239 {
3240 UNUSED(Periph);
3241 return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SDMMC12SEL));
3242 }
3243
3244 /**
3245 * @brief Get SPDIFRX Kernel clock source
3246 * @rmtoll CCIPR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
3247 * @param Periph This parameter can be one of the following values:
3248 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE
3249 * @retval Returned value can be one of the following values:
3250 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL1Q
3251 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL2R
3252 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_PLL3R
3253 * @arg @ref LL_RCC_SPDIFRX_CLKSOURCE_HSI
3254 */
LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)3255 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t Periph)
3256 {
3257 UNUSED(Periph);
3258 return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SPDIFRXSEL));
3259 }
3260
3261 /**
3262 * @brief Get SPIx Kernel clock source
3263 * @rmtoll CCIPR3 SPI1SEL LL_RCC_GetSPIClockSource\n
3264 * CCIPR2 SPI23SEL LL_RCC_GetSPIClockSource\n
3265 * CCIPR3 SPI45SEL LL_RCC_GetSPIClockSource\n
3266 * CCIPR4 SPI6SEL LL_RCC_GetSPIClockSource
3267 * @param Periph This parameter can be one of the following values:
3268 * @arg @ref LL_RCC_SPI1_CLKSOURCE
3269 * @arg @ref LL_RCC_SPI23_CLKSOURCE
3270 * @arg @ref LL_RCC_SPI45_CLKSOURCE
3271 * @arg @ref LL_RCC_SPI6_CLKSOURCE
3272 * @retval Returned value can be one of the following values:
3273 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q
3274 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P
3275 * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL3P
3276 * @arg @ref LL_RCC_SPI1_CLKSOURCE_I2S_CKIN
3277 * @arg @ref LL_RCC_SPI1_CLKSOURCE_CLKP
3278 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL1Q
3279 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL2P
3280 * @arg @ref LL_RCC_SPI23_CLKSOURCE_PLL3P
3281 * @arg @ref LL_RCC_SPI23_CLKSOURCE_I2S_CKIN
3282 * @arg @ref LL_RCC_SPI23_CLKSOURCE_CLKP
3283 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3284 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3285 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3286 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3287 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3288 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3289 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3290 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3291 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3292 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3293 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3294 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3295 */
LL_RCC_GetSPIClockSource(uint32_t Periph)3296 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
3297 {
3298 return LL_RCC_GetClockSource(Periph);
3299 }
3300
3301 /**
3302 * @brief Get USARTx clock source
3303 * @rmtoll CCIPR3 USART1SEL LL_RCC_GetUSARTClockSource\n
3304 * CCIPR2 UART234578SEL LL_RCC_GetUSARTClockSource
3305 * @param Periph This parameter can be one of the following values:
3306 * @arg @ref LL_RCC_USART1_CLKSOURCE
3307 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3308 * @retval Returned value can be one of the following values:
3309 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
3310 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL2Q
3311 * @arg @ref LL_RCC_USART1_CLKSOURCE_PLL3Q
3312 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
3313 * @arg @ref LL_RCC_USART1_CLKSOURCE_CSI
3314 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
3315 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3316 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3317 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3318 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3319 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3320 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3321 */
LL_RCC_GetUSARTClockSource(uint32_t Periph)3322 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
3323 {
3324 UNUSED(Periph);
3325 return LL_RCC_GetClockSource(Periph);
3326 }
3327
3328 /**
3329 * @brief Get USBPHYC clock source
3330 * @rmtoll CCIPR1 USBPHYCSEL LL_RCC_GetUSBPHYCClockSource
3331 * @param Periph This parameter can be one of the following values:
3332 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE
3333 * @retval Returned value can be one of the following values:
3334 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_DISABLE
3335 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE
3336 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_HSE_DIV_2
3337 * @arg @ref LL_RCC_USBPHYC_CLKSOURCE_PLL3Q
3338 */
LL_RCC_GetUSBPHYCClockSource(uint32_t Periph)3339 __STATIC_INLINE uint32_t LL_RCC_GetUSBPHYCClockSource(uint32_t Periph)
3340 {
3341 UNUSED(Periph);
3342 return (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USBPHYCSEL));
3343 }
3344
3345 /**
3346 * @brief Configure USBREF clock frequency
3347 * @rmtoll CCIPR1 USBREFCKSEL LL_RCC_GetUSBREFClockSource
3348 * @param Periph This parameter can be one of the following values:
3349 * @arg @ref LL_RCC_USBREF_CLKSOURCE
3350 * @retval Returned value can be one of the following values:
3351 * @arg @ref LL_RCC_USBREF_CLKSOURCE_16M
3352 * @arg @ref LL_RCC_USBREF_CLKSOURCE_19_2M
3353 * @arg @ref LL_RCC_USBREF_CLKSOURCE_20M
3354 * @arg @ref LL_RCC_USBREF_CLKSOURCE_24M
3355 * @arg @ref LL_RCC_USBREF_CLKSOURCE_26M
3356 * @arg @ref LL_RCC_USBREF_CLKSOURCE_32M
3357 * @retval None
3358 */
LL_RCC_GetUSBREFClockSource(uint32_t Periph)3359 __STATIC_INLINE uint32_t LL_RCC_GetUSBREFClockSource(uint32_t Periph)
3360 {
3361 UNUSED(Periph);
3362 return (READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USBREFCKSEL));
3363 }
3364
3365 /**
3366 * @}
3367 */
3368
3369 /** @defgroup RCC_LL_EF_RTC RTC
3370 * @{
3371 */
3372
3373 /**
3374 * @brief Set RTC Clock Source
3375 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3376 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3377 * set). The BDRST bit can be used to reset them.
3378 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3379 * @param Source This parameter can be one of the following values:
3380 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3381 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3382 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3383 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3384 * @retval None
3385 */
LL_RCC_SetRTCClockSource(uint32_t Source)3386 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3387 {
3388 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3389 }
3390
3391 /**
3392 * @brief Get RTC Clock Source
3393 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3394 * @retval Returned value can be one of the following values:
3395 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3396 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3397 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3398 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3399 */
LL_RCC_GetRTCClockSource(void)3400 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
3401 {
3402 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
3403 }
3404
3405 /**
3406 * @brief Enable RTC
3407 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
3408 * @retval None
3409 */
LL_RCC_EnableRTC(void)3410 __STATIC_INLINE void LL_RCC_EnableRTC(void)
3411 {
3412 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3413 }
3414
3415 /**
3416 * @brief Disable RTC
3417 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
3418 * @retval None
3419 */
LL_RCC_DisableRTC(void)3420 __STATIC_INLINE void LL_RCC_DisableRTC(void)
3421 {
3422 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
3423 }
3424
3425 /**
3426 * @brief Check if RTC has been enabled or not
3427 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
3428 * @retval State of bit (1 or 0).
3429 */
LL_RCC_IsEnabledRTC(void)3430 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
3431 {
3432 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
3433 }
3434
3435 /**
3436 * @brief Force the Backup domain reset
3437 * @rmtoll BDCR VSWRST LL_RCC_ForceBackupDomainReset
3438 * @retval None
3439 */
LL_RCC_ForceBackupDomainReset(void)3440 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3441 {
3442 SET_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3443 }
3444
3445 /**
3446 * @brief Release the Backup domain reset
3447 * @rmtoll BDCR VSWRST LL_RCC_ReleaseBackupDomainReset
3448 * @retval None
3449 */
LL_RCC_ReleaseBackupDomainReset(void)3450 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3451 {
3452 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
3453 }
3454
3455 /**
3456 * @brief Set HSE Prescalers for RTC Clock
3457 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
3458 * @param Prescaler This parameter can be one of the following values:
3459 * @arg @ref LL_RCC_RTC_NOCLOCK
3460 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3461 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3462 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3463 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3464 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3465 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3466 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3467 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3468 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3469 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3470 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3471 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3472 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3473 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3474 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3475 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3476 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3477 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3478 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3479 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3480 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3481 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3482 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3483 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3484 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3485 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3486 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3487 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3488 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3489 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3490 * @arg @ref LL_RCC_RTC_HSE_DIV_32
3491 * @arg @ref LL_RCC_RTC_HSE_DIV_33
3492 * @arg @ref LL_RCC_RTC_HSE_DIV_34
3493 * @arg @ref LL_RCC_RTC_HSE_DIV_35
3494 * @arg @ref LL_RCC_RTC_HSE_DIV_36
3495 * @arg @ref LL_RCC_RTC_HSE_DIV_37
3496 * @arg @ref LL_RCC_RTC_HSE_DIV_38
3497 * @arg @ref LL_RCC_RTC_HSE_DIV_39
3498 * @arg @ref LL_RCC_RTC_HSE_DIV_40
3499 * @arg @ref LL_RCC_RTC_HSE_DIV_41
3500 * @arg @ref LL_RCC_RTC_HSE_DIV_42
3501 * @arg @ref LL_RCC_RTC_HSE_DIV_43
3502 * @arg @ref LL_RCC_RTC_HSE_DIV_44
3503 * @arg @ref LL_RCC_RTC_HSE_DIV_45
3504 * @arg @ref LL_RCC_RTC_HSE_DIV_46
3505 * @arg @ref LL_RCC_RTC_HSE_DIV_47
3506 * @arg @ref LL_RCC_RTC_HSE_DIV_48
3507 * @arg @ref LL_RCC_RTC_HSE_DIV_49
3508 * @arg @ref LL_RCC_RTC_HSE_DIV_50
3509 * @arg @ref LL_RCC_RTC_HSE_DIV_51
3510 * @arg @ref LL_RCC_RTC_HSE_DIV_52
3511 * @arg @ref LL_RCC_RTC_HSE_DIV_53
3512 * @arg @ref LL_RCC_RTC_HSE_DIV_54
3513 * @arg @ref LL_RCC_RTC_HSE_DIV_55
3514 * @arg @ref LL_RCC_RTC_HSE_DIV_56
3515 * @arg @ref LL_RCC_RTC_HSE_DIV_57
3516 * @arg @ref LL_RCC_RTC_HSE_DIV_58
3517 * @arg @ref LL_RCC_RTC_HSE_DIV_59
3518 * @arg @ref LL_RCC_RTC_HSE_DIV_60
3519 * @arg @ref LL_RCC_RTC_HSE_DIV_61
3520 * @arg @ref LL_RCC_RTC_HSE_DIV_62
3521 * @arg @ref LL_RCC_RTC_HSE_DIV_63
3522 * @retval None
3523 */
LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)3524 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
3525 {
3526 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
3527 }
3528
3529 /**
3530 * @brief Get HSE Prescalers for RTC Clock
3531 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
3532 * @retval Returned value can be one of the following values:
3533 * @arg @ref LL_RCC_RTC_NOCLOCK
3534 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3535 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3536 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3537 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3538 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3539 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3540 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3541 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3542 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3543 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3544 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3545 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3546 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3547 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3548 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3549 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3550 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3551 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3552 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3553 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3554 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3555 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3556 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3557 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3558 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3559 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3560 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3561 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3562 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3563 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3564 * @arg @ref LL_RCC_RTC_HSE_DIV_32
3565 * @arg @ref LL_RCC_RTC_HSE_DIV_33
3566 * @arg @ref LL_RCC_RTC_HSE_DIV_34
3567 * @arg @ref LL_RCC_RTC_HSE_DIV_35
3568 * @arg @ref LL_RCC_RTC_HSE_DIV_36
3569 * @arg @ref LL_RCC_RTC_HSE_DIV_37
3570 * @arg @ref LL_RCC_RTC_HSE_DIV_38
3571 * @arg @ref LL_RCC_RTC_HSE_DIV_39
3572 * @arg @ref LL_RCC_RTC_HSE_DIV_40
3573 * @arg @ref LL_RCC_RTC_HSE_DIV_41
3574 * @arg @ref LL_RCC_RTC_HSE_DIV_42
3575 * @arg @ref LL_RCC_RTC_HSE_DIV_43
3576 * @arg @ref LL_RCC_RTC_HSE_DIV_44
3577 * @arg @ref LL_RCC_RTC_HSE_DIV_45
3578 * @arg @ref LL_RCC_RTC_HSE_DIV_46
3579 * @arg @ref LL_RCC_RTC_HSE_DIV_47
3580 * @arg @ref LL_RCC_RTC_HSE_DIV_48
3581 * @arg @ref LL_RCC_RTC_HSE_DIV_49
3582 * @arg @ref LL_RCC_RTC_HSE_DIV_50
3583 * @arg @ref LL_RCC_RTC_HSE_DIV_51
3584 * @arg @ref LL_RCC_RTC_HSE_DIV_52
3585 * @arg @ref LL_RCC_RTC_HSE_DIV_53
3586 * @arg @ref LL_RCC_RTC_HSE_DIV_54
3587 * @arg @ref LL_RCC_RTC_HSE_DIV_55
3588 * @arg @ref LL_RCC_RTC_HSE_DIV_56
3589 * @arg @ref LL_RCC_RTC_HSE_DIV_57
3590 * @arg @ref LL_RCC_RTC_HSE_DIV_58
3591 * @arg @ref LL_RCC_RTC_HSE_DIV_59
3592 * @arg @ref LL_RCC_RTC_HSE_DIV_60
3593 * @arg @ref LL_RCC_RTC_HSE_DIV_61
3594 * @arg @ref LL_RCC_RTC_HSE_DIV_62
3595 * @arg @ref LL_RCC_RTC_HSE_DIV_63
3596 */
LL_RCC_GetRTC_HSEPrescaler(void)3597 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
3598 {
3599 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
3600 }
3601
3602 /**
3603 * @}
3604 */
3605
3606 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
3607 * @{
3608 */
3609
3610 /**
3611 * @brief Set Timers Clock Prescalers
3612 * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler
3613 * @param Prescaler This parameter can be one of the following values:
3614 * @arg @ref LL_RCC_TIM_PRESCALER_DISABLE
3615 * @arg @ref LL_RCC_TIM_PRESCALER_ENABLE
3616 * @retval None
3617 */
LL_RCC_SetTIMPrescaler(uint32_t Prescaler)3618 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
3619 {
3620 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
3621 }
3622
3623 /**
3624 * @brief Get Timers Clock Prescalers
3625 * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler
3626 * @retval Returned value can be one of the following values:
3627 * @arg @ref LL_RCC_TIM_PRESCALER_DISABLE
3628 * @arg @ref LL_RCC_TIM_PRESCALER_ENABLE
3629 */
LL_RCC_GetTIMPrescaler(void)3630 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
3631 {
3632 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
3633 }
3634
3635 /**
3636 * @}
3637 */
3638
3639 /** @defgroup RCC_LL_EF_USBPHYC USBPHYC
3640 * @{
3641 */
3642
3643 /**
3644 * @brief Enable USBPHYC power-down
3645 * @rmtoll AHB1LPENR UCPDCTRL LL_RCC_USBPHYC_EnablePowerDown
3646 * @retval None
3647 */
LL_RCC_USBPHYC_EnablePowerDown(void)3648 __STATIC_INLINE void LL_RCC_USBPHYC_EnablePowerDown(void)
3649 {
3650 SET_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_UCPDCTRL);
3651 }
3652
3653 /**
3654 * @brief Disable USBPHYC power-down
3655 * @rmtoll AHB1LPENR UCPDCTRL LL_RCC_USBPHYC_DisablePowerDown
3656 * @retval None
3657 */
LL_RCC_USBPHYC_DisablePowerDown(void)3658 __STATIC_INLINE void LL_RCC_USBPHYC_DisablePowerDown(void)
3659 {
3660 CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_UCPDCTRL);
3661 }
3662
3663 /**
3664 * @brief Check if USBPHYC is powered-down
3665 * @rmtoll AHB1LPENR UCPDCTRL LL_RCC_USBPHYC_IsEnabledPowerDown
3666 * @retval State of bit (1 or 0).
3667 */
LL_RCC_USBPHYC_IsEnabledPowerDown(void)3668 __STATIC_INLINE uint32_t LL_RCC_USBPHYC_IsEnabledPowerDown(void)
3669 {
3670 return ((READ_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_UCPDCTRL) == (RCC_AHB1LPENR_UCPDCTRL)) ? 1UL : 0UL);
3671 }
3672
3673 /**
3674 * @}
3675 */
3676
3677 /** @defgroup RCC_LL_EF_PLL PLL
3678 * @{
3679 */
3680
3681 /**
3682 * @brief Set the oscillator used as PLL clock source.
3683 * @note PLL clock source is common to all PLLs.
3684 * @note PLLSRC can be written only when all PLLs are disabled.
3685 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource
3686 * @param PLLSource parameter can be one of the following values:
3687 * @arg @ref LL_RCC_PLLSOURCE_HSI
3688 * @arg @ref LL_RCC_PLLSOURCE_CSI
3689 * @arg @ref LL_RCC_PLLSOURCE_HSE
3690 * @arg @ref LL_RCC_PLLSOURCE_NONE
3691 * @retval None
3692 */
LL_RCC_PLL_SetSource(uint32_t PLLSource)3693 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
3694 {
3695 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
3696 }
3697
3698 /**
3699 * @brief Get the oscillator used as PLL clock source.
3700 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource
3701 * @retval Returned value can be one of the following values:
3702 * @arg @ref LL_RCC_PLLSOURCE_HSI
3703 * @arg @ref LL_RCC_PLLSOURCE_CSI
3704 * @arg @ref LL_RCC_PLLSOURCE_HSE
3705 * @arg @ref LL_RCC_PLLSOURCE_NONE
3706 */
LL_RCC_PLL_GetSource(void)3707 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
3708 {
3709 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
3710 }
3711
3712 /**
3713 * @brief Enable PLL1
3714 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
3715 * @retval None
3716 */
LL_RCC_PLL1_Enable(void)3717 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
3718 {
3719 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
3720 }
3721
3722 /**
3723 * @brief Disable PLL1
3724 * @note Cannot be disabled if the PLL1 clock is used as the system clock
3725 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
3726 * @retval None
3727 */
LL_RCC_PLL1_Disable(void)3728 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
3729 {
3730 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
3731 }
3732
3733 /**
3734 * @brief Check if PLL1 Ready
3735 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
3736 * @retval State of bit (1 or 0).
3737 */
LL_RCC_PLL1_IsReady(void)3738 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
3739 {
3740 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL);
3741 }
3742
3743 /**
3744 * @brief Configure PLL1 used for SYSCLK Domain
3745 * @note PLL Source, DIVM1, DIVN and DIVP can be written only when PLL is disabled.
3746 * @note PLLN/PLLR can be written only when PLL is disabled.
3747 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL1_ConfigDomain_SYS\n
3748 * PLLCKSELR DIVM1 LL_RCC_PLL1_ConfigDomain_SYS\n
3749 * PLL1DIVR1 DIVN LL_RCC_PLL1_ConfigDomain_SYS\n
3750 * PLL1DIVR1 DIVP LL_RCC_PLL1_ConfigDomain_SYS
3751 * @param Source This parameter can be one of the following values:
3752 * @arg @ref LL_RCC_PLLSOURCE_HSI
3753 * @arg @ref LL_RCC_PLLSOURCE_CSI
3754 * @arg @ref LL_RCC_PLLSOURCE_HSE
3755 * @arg @ref LL_RCC_PLLSOURCE_NONE
3756 * @param M parameter can be a value between 1 and 64
3757 * @param N parameter can be a value between 8 to 420
3758 * @param P parameter can be a value between 2 and 128 (odd division factor not supported)
3759 *
3760 * @retval None
3761 */
LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source,uint32_t M,uint32_t N,uint32_t P)3762 __STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t M, uint32_t N, uint32_t P)
3763 {
3764 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1 | RCC_PLLCKSELR_PLLSRC,
3765 (M << RCC_PLLCKSELR_DIVM1_Pos) | Source);
3766 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP | RCC_PLL1DIVR1_DIVN,
3767 ((P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos) | ((N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos));
3768 }
3769
3770 /**
3771 * @brief Enable PLL1P
3772 * @note This API shall be called only when PLL1 is disabled.
3773 * @rmtoll PLLCFGR PLL1PEN LL_RCC_PLL1P_Enable
3774 * @retval None
3775 */
LL_RCC_PLL1P_Enable(void)3776 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
3777 {
3778 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN);
3779 }
3780
3781 /**
3782 * @brief Enable PLL1Q
3783 * @note This API shall be called only when PLL1 is disabled.
3784 * @rmtoll PLLCFGR PLL1QEN LL_RCC_PLL1Q_Enable
3785 * @retval None
3786 */
LL_RCC_PLL1Q_Enable(void)3787 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
3788 {
3789 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN);
3790 }
3791
3792 /**
3793 * @brief Enable PLL1R
3794 * @note This API shall be called only when PLL1 is disabled.
3795 * @rmtoll PLLCFGR PLL1REN LL_RCC_PLL1R_Enable
3796 * @retval None
3797 */
LL_RCC_PLL1R_Enable(void)3798 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
3799 {
3800 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN);
3801 }
3802
3803 /**
3804 * @brief Enable PLL1S
3805 * @note This API shall be called only when PLL1 is disabled.
3806 * @rmtoll PLLCFGR PLL1SEN LL_RCC_PLL1S_Enable
3807 * @retval None
3808 */
LL_RCC_PLL1S_Enable(void)3809 __STATIC_INLINE void LL_RCC_PLL1S_Enable(void)
3810 {
3811 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN);
3812 }
3813
3814 /**
3815 * @brief Enable PLL1 FRACN
3816 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
3817 * @retval None
3818 */
LL_RCC_PLL1FRACN_Enable(void)3819 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
3820 {
3821 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
3822 }
3823
3824 /**
3825 * @brief Check if PLL1 P is enabled
3826 * @rmtoll PLLCFGR PLL1PEN LL_RCC_PLL1P_IsEnabled
3827 * @retval State of bit (1 or 0).
3828 */
LL_RCC_PLL1P_IsEnabled(void)3829 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
3830 {
3831 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN) == RCC_PLLCFGR_PLL1PEN) ? 1UL : 0UL);
3832 }
3833
3834 /**
3835 * @brief Check if PLL1 Q is enabled
3836 * @rmtoll PLLCFGR PLL1QEN LL_RCC_PLL1Q_IsEnabled
3837 * @retval State of bit (1 or 0).
3838 */
LL_RCC_PLL1Q_IsEnabled(void)3839 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
3840 {
3841 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN) == RCC_PLLCFGR_PLL1QEN) ? 1UL : 0UL);
3842 }
3843
3844 /**
3845 * @brief Check if PLL1 R is enabled
3846 * @rmtoll PLLCFGR PLL1REN LL_RCC_PLL1R_IsEnabled
3847 * @retval State of bit (1 or 0).
3848 */
LL_RCC_PLL1R_IsEnabled(void)3849 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
3850 {
3851 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN) == RCC_PLLCFGR_PLL1REN) ? 1UL : 0UL);
3852 }
3853
3854 /**
3855 * @brief Check if PLL1 S is enabled
3856 * @rmtoll PLLCFGR PLL1SEN LL_RCC_PLL1S_IsEnabled
3857 * @retval State of bit (1 or 0).
3858 */
LL_RCC_PLL1S_IsEnabled(void)3859 __STATIC_INLINE uint32_t LL_RCC_PLL1S_IsEnabled(void)
3860 {
3861 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN) == RCC_PLLCFGR_PLL1SEN) ? 1UL : 0UL);
3862 }
3863
3864 /**
3865 * @brief Check if PLL1 FRACN is enabled
3866 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
3867 * @retval State of bit (1 or 0).
3868 */
LL_RCC_PLL1FRACN_IsEnabled(void)3869 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
3870 {
3871 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL);
3872 }
3873
3874 /**
3875 * @brief Disable PLL1P
3876 * @note This API shall be called only when PLL1 is disabled.
3877 * @rmtoll PLLCFGR PLL1PEN LL_RCC_PLL1P_Disable
3878 * @retval None
3879 */
LL_RCC_PLL1P_Disable(void)3880 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
3881 {
3882 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1PEN);
3883 }
3884
3885 /**
3886 * @brief Disable PLL1Q
3887 * @note This API shall be called only when PLL1 is disabled.
3888 * @rmtoll PLLCFGR PLL1QEN LL_RCC_PLL1Q_Disable
3889 * @retval None
3890 */
LL_RCC_PLL1Q_Disable(void)3891 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
3892 {
3893 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1QEN);
3894 }
3895
3896 /**
3897 * @brief Disable PLL1R
3898 * @note This API shall be called only when PLL1 is disabled.
3899 * @rmtoll PLLCFGR PLL1REN LL_RCC_PLL1R_Disable
3900 * @retval None
3901 */
LL_RCC_PLL1R_Disable(void)3902 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
3903 {
3904 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1REN);
3905 }
3906
3907 /**
3908 * @brief Disable PLL1S
3909 * @note This API shall be called only when PLL1 is disabled.
3910 * @rmtoll PLLCFGR PLL1SEN LL_RCC_PLL1S_Disable
3911 * @retval None
3912 */
LL_RCC_PLL1S_Disable(void)3913 __STATIC_INLINE void LL_RCC_PLL1S_Disable(void)
3914 {
3915 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SEN);
3916 }
3917
3918 /**
3919 * @brief Disable PLL1 FRACN
3920 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable
3921 * @retval None
3922 */
LL_RCC_PLL1FRACN_Disable(void)3923 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
3924 {
3925 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
3926 }
3927
3928 /**
3929 * @brief Get PLL1 VCO Input Range
3930 * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_GetVCOInputRange
3931 * @retval Returned value can be one of the following values:
3932 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
3933 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
3934 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
3935 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
3936 */
LL_RCC_PLL1_GetVCOInputRange(void)3937 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetVCOInputRange(void)
3938 {
3939 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE));
3940 }
3941
3942 /**
3943 * @brief Get PLL1 VCO OutputRange
3944 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_GetVCOOutputRange
3945 * @retval Returned value can be one of the following values:
3946 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
3947 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
3948 */
LL_RCC_PLL1_GetVCOOutputRange(void)3949 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetVCOOutputRange(void)
3950 {
3951 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL));
3952 }
3953
3954 /**
3955 * @brief Set PLL1 VCO Input Range
3956 * @note This API shall be called only when PLL1 is disabled.
3957 * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
3958 * @param InputRange This parameter can be one of the following values:
3959 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
3960 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
3961 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
3962 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
3963 * @retval None
3964 */
LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)3965 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
3966 {
3967 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange);
3968 }
3969
3970 /**
3971 * @brief Set PLL1 VCO OutputRange
3972 * @note This API shall be called only when PLL1 is disabled.
3973 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOutputRange
3974 * @param VCORange This parameter can be one of the following values:
3975 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
3976 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
3977 * @retval None
3978 */
LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)3979 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
3980 {
3981 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange);
3982 }
3983
3984 /**
3985 * @brief Get PLL1 N Coefficient
3986 * @rmtoll PLL1DIVR1 DIVN LL_RCC_PLL1_GetN
3987 * @retval A value between 8 and 420
3988 */
LL_RCC_PLL1_GetN(void)3989 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
3990 {
3991 return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVN) >> RCC_PLL1DIVR1_DIVN_Pos) + 1UL);
3992 }
3993
3994 /**
3995 * @brief Get PLL1 M Coefficient
3996 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM
3997 * @retval A value between 0 and 63
3998 */
LL_RCC_PLL1_GetM(void)3999 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4000 {
4001 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
4002 }
4003
4004 /**
4005 * @brief Get PLL1 P Coefficient
4006 * @rmtoll PLL1DIVR1 DIVP LL_RCC_PLL1_GetP
4007 * @retval A value between 2 and 128
4008 */
LL_RCC_PLL1_GetP(void)4009 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4010 {
4011 return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP) >> RCC_PLL1DIVR1_DIVP_Pos) + 1UL);
4012 }
4013
4014 /**
4015 * @brief Get PLL1 Q Coefficient
4016 * @rmtoll PLL1DIVR1 DIVQ LL_RCC_PLL1_GetQ
4017 * @retval A value between 1 and 128
4018 */
LL_RCC_PLL1_GetQ(void)4019 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4020 {
4021 return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ) >> RCC_PLL1DIVR1_DIVQ_Pos) + 1UL);
4022 }
4023
4024 /**
4025 * @brief Get PLL1 R Coefficient
4026 * @rmtoll PLL1DIVR1 DIVR LL_RCC_PLL1_GetR
4027 * @retval A value between 1 and 128
4028 */
LL_RCC_PLL1_GetR(void)4029 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4030 {
4031 return (uint32_t)((READ_BIT(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVR) >> RCC_PLL1DIVR1_DIVR_Pos) + 1UL);
4032 }
4033
4034 /**
4035 * @brief Get PLL1 S Coefficient
4036 * @rmtoll PLL1DIVR2 DIVS LL_RCC_PLL1_GetS
4037 * @retval A value between 1 and 8
4038 */
LL_RCC_PLL1_GetS(void)4039 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetS(void)
4040 {
4041 return (uint32_t)((READ_BIT(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS) >> RCC_PLL1DIVR2_DIVS_Pos) + 1UL);
4042 }
4043
4044 /**
4045 * @brief Get PLL1 FRACN Coefficient
4046 * @rmtoll PLL1FRACR FRACN LL_RCC_PLL1_GetFRACN
4047 * @retval A value between 0 and 8191 (0x1FFF)
4048 */
LL_RCC_PLL1_GetFRACN(void)4049 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4050 {
4051 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN) >> RCC_PLL1FRACR_FRACN_Pos);
4052 }
4053
4054 /**
4055 * @brief Set PLL1 N Coefficient
4056 * @note This API shall be called only when PLL1 is disabled.
4057 * @rmtoll PLL1DIVR1 DIVN LL_RCC_PLL1_SetN
4058 * @param N parameter can be a value between 8 and 420
4059 */
LL_RCC_PLL1_SetN(uint32_t N)4060 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
4061 {
4062 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVN, (N - 1UL) << RCC_PLL1DIVR1_DIVN_Pos);
4063 }
4064
4065 /**
4066 * @brief Set PLL1 M Coefficient
4067 * @note This API shall be called only when PLL1 is disabled.
4068 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM
4069 * @param M parameter can be a value between 1 and 64
4070 */
LL_RCC_PLL1_SetM(uint32_t M)4071 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
4072 {
4073 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
4074 }
4075
4076 /**
4077 * @brief Set PLL1 P Coefficient
4078 * @note This API shall be called only when PLL1 is disabled.
4079 * @rmtoll PLL1DIVR1 DIVP LL_RCC_PLL1_SetP
4080 * @param P parameter can be a value between 2 and 128 (odd division factor not supported)
4081 */
LL_RCC_PLL1_SetP(uint32_t P)4082 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
4083 {
4084 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVP, (P - 1UL) << RCC_PLL1DIVR1_DIVP_Pos);
4085 }
4086
4087 /**
4088 * @brief Set PLL1 Q Coefficient
4089 * @note This API shall be called only when PLL1 is disabled.
4090 * @rmtoll PLL1DIVR1 DIVQ LL_RCC_PLL1_SetQ
4091 * @param Q parameter can be a value between 1 and 128
4092 */
LL_RCC_PLL1_SetQ(uint32_t Q)4093 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
4094 {
4095 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVQ, (Q - 1UL) << RCC_PLL1DIVR1_DIVQ_Pos);
4096 }
4097
4098 /**
4099 * @brief Set PLL1 R Coefficient
4100 * @note This API shall be called only when PLL1 is disabled.
4101 * @rmtoll PLL1DIVR1 DIVR LL_RCC_PLL1_SetR
4102 * @param R parameter can be a value between 1 and 128
4103 */
LL_RCC_PLL1_SetR(uint32_t R)4104 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
4105 {
4106 MODIFY_REG(RCC->PLL1DIVR1, RCC_PLL1DIVR1_DIVR, (R - 1UL) << RCC_PLL1DIVR1_DIVR_Pos);
4107 }
4108
4109 /**
4110 * @brief Set PLL1 S Coefficient
4111 * @note This API shall be called only when PLL1 is disabled.
4112 * @rmtoll PLL1DIVR2 DIVS LL_RCC_PLL1_SetS
4113 * @param S parameter can be a value between 1 and 8
4114 */
LL_RCC_PLL1_SetS(uint32_t S)4115 __STATIC_INLINE void LL_RCC_PLL1_SetS(uint32_t S)
4116 {
4117 MODIFY_REG(RCC->PLL1DIVR2, RCC_PLL1DIVR2_DIVS, (S - 1UL) << RCC_PLL1DIVR2_DIVS_Pos);
4118 }
4119
4120 /**
4121 * @brief Set PLL1 FRACN Coefficient
4122 * @rmtoll PLL1FRACR FRACN LL_RCC_PLL1_SetFRACN
4123 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4124 */
LL_RCC_PLL1_SetFRACN(uint32_t FRACN)4125 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4126 {
4127 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN, FRACN << RCC_PLL1FRACR_FRACN_Pos);
4128 }
4129
4130 /**
4131 * @brief Enable Spread Spectrum for PLL1.
4132 * @note Configuration to be done with LL_RCC_PLL1_ConfigSpreadSpectrum
4133 * @rmtoll PLLCFGR PLL1SSCGEN LL_RCC_PLL1_EnableSpreadSpectrum
4134 * @retval None
4135 */
LL_RCC_PLL1_EnableSpreadSpectrum(void)4136 __STATIC_INLINE void LL_RCC_PLL1_EnableSpreadSpectrum(void)
4137 {
4138 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SSCGEN);
4139 }
4140
4141 /**
4142 * @brief Disable Spread Spectrum for PLL1.
4143 * @rmtoll PLLCFGR PLL1SSCGEN LL_RCC_PLL1_DisableSpreadSpectrum
4144 * @retval None
4145 */
LL_RCC_PLL1_DisableSpreadSpectrum(void)4146 __STATIC_INLINE void LL_RCC_PLL1_DisableSpreadSpectrum(void)
4147 {
4148 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SSCGEN);
4149 }
4150
4151 /**
4152 * @brief Check if Spread Spectrum for PLL1 is enabled
4153 * @rmtoll PLLCFGR PLL1SSCGEN LL_RCC_PLL1_IsEnabledSpreadSpectrum
4154 * @retval State of bit (1 or 0).
4155 */
LL_RCC_PLL1_IsEnabledSpreadSpectrum(void)4156 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledSpreadSpectrum(void)
4157 {
4158 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1SSCGEN) == RCC_PLLCFGR_PLL1SSCGEN) ? 1UL : 0UL);
4159 }
4160
4161 /**
4162 * @brief Get Spread Spectrum Modulation Period for PLL1
4163 * @rmtoll PLL1SSCGR MODPER LL_RCC_PLL1_GetModulationPeriod
4164 * @retval Between Min_Data=0 and Max_Data=8191
4165 */
LL_RCC_PLL1_GetModulationPeriod(void)4166 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetModulationPeriod(void)
4167 {
4168 return (uint32_t)(READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_MODPER));
4169 }
4170
4171 /**
4172 * @brief Get Spread Spectrum Increment Step for PLL1
4173 * @rmtoll PLL1SSCGR INCSTEP LL_RCC_PLL1_GetIncrementStep
4174 * @retval Between Min_Data=0 and Max_Data=32767
4175 */
LL_RCC_PLL1_GetIncrementStep(void)4176 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetIncrementStep(void)
4177 {
4178 return (uint32_t)(READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_INCSTEP) >> RCC_PLL1SSCGR_INCSTEP_Pos);
4179 }
4180
4181 /**
4182 * @brief Get Spread Spectrum Selection for PLL1
4183 * @rmtoll PLL1SSCGR SPREADSEL LL_RCC_PLL1_GetSpreadSelection
4184 * @retval Returned value can be one of the following values:
4185 * @arg @ref LL_RCC_PLL_SPREAD_CENTER
4186 * @arg @ref LL_RCC_PLL_SPREAD_DOWN
4187 */
LL_RCC_PLL1_GetSpreadSelection(void)4188 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetSpreadSelection(void)
4189 {
4190 return (uint32_t)(READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_SPREADSEL));
4191 }
4192
4193 /**
4194 * @brief Check if Dithering RPDF Noise for PLL1 is enabled
4195 * @rmtoll PLL1SSCGR RPDFNDIS LL_RCC_PLL1_IsEnabledRPDFNDithering
4196 * @retval State of bit (1 or 0).
4197 */
LL_RCC_PLL1_IsEnabledRPDFNDithering(void)4198 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledRPDFNDithering(void)
4199 {
4200 return ((READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_RPDFNDIS) == 0U) ? 1UL : 0UL);
4201 }
4202
4203 /**
4204 * @brief Check if Dithering TPDF Noise for PLL1 is enabled
4205 * @rmtoll PLL1SSCGR TPDFNDIS LL_RCC_PLL1_IsEnabledTPDFNDithering
4206 * @retval State of bit (1 or 0).
4207 */
LL_RCC_PLL1_IsEnabledTPDFNDithering(void)4208 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledTPDFNDithering(void)
4209 {
4210 return ((READ_BIT(RCC->PLL1SSCGR, RCC_PLL1SSCGR_TPDFNDIS) == 0U) ? 1UL : 0UL);
4211 }
4212
4213 /**
4214 * @brief Enable PLL2
4215 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
4216 * @retval None
4217 */
LL_RCC_PLL2_Enable(void)4218 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4219 {
4220 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4221 }
4222
4223 /**
4224 * @brief Disable PLL2
4225 * @note Cannot be disabled if the PLL2 clock is used as the system clock
4226 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
4227 * @retval None
4228 */
LL_RCC_PLL2_Disable(void)4229 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4230 {
4231 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4232 }
4233
4234 /**
4235 * @brief Check if PLL2 Ready
4236 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
4237 * @retval State of bit (1 or 0).
4238 */
LL_RCC_PLL2_IsReady(void)4239 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4240 {
4241 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL);
4242 }
4243
4244 /**
4245 * @brief Enable PLL2P
4246 * @note This API shall be called only when PLL2 is disabled.
4247 * @rmtoll PLLCFGR PLL2PEN LL_RCC_PLL2P_Enable
4248 * @retval None
4249 */
LL_RCC_PLL2P_Enable(void)4250 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4251 {
4252 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2PEN);
4253 }
4254
4255 /**
4256 * @brief Enable PLL2Q
4257 * @note This API shall be called only when PLL2 is disabled.
4258 * @rmtoll PLLCFGR PLL2QEN LL_RCC_PLL2Q_Enable
4259 * @retval None
4260 */
LL_RCC_PLL2Q_Enable(void)4261 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4262 {
4263 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2QEN);
4264 }
4265
4266 /**
4267 * @brief Enable PLL2R
4268 * @note This API shall be called only when PLL2 is disabled.
4269 * @rmtoll PLLCFGR PLL2REN LL_RCC_PLL2R_Enable
4270 * @retval None
4271 */
LL_RCC_PLL2R_Enable(void)4272 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4273 {
4274 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2REN);
4275 }
4276
4277 /**
4278 * @brief Enable PLL2S
4279 * @note This API shall be called only when PLL2 is disabled.
4280 * @rmtoll PLLCFGR PLL2SEN LL_RCC_PLL2S_Enable
4281 * @retval None
4282 */
LL_RCC_PLL2S_Enable(void)4283 __STATIC_INLINE void LL_RCC_PLL2S_Enable(void)
4284 {
4285 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SEN);
4286 }
4287
4288 /**
4289 * @brief Enable PLL2T
4290 * @note This API shall be called only when PLL2 is disabled.
4291 * @rmtoll PLLCFGR PLL2TEN LL_RCC_PLL2T_Enable
4292 * @retval None
4293 */
LL_RCC_PLL2T_Enable(void)4294 __STATIC_INLINE void LL_RCC_PLL2T_Enable(void)
4295 {
4296 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2TEN);
4297 }
4298
4299 /**
4300 * @brief Enable PLL2 FRACN
4301 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4302 * @retval None
4303 */
LL_RCC_PLL2FRACN_Enable(void)4304 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4305 {
4306 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4307 }
4308
4309 /**
4310 * @brief Check if PLL2 P is enabled
4311 * @rmtoll PLLCFGR PLL2PEN LL_RCC_PLL2P_IsEnabled
4312 * @retval State of bit (1 or 0).
4313 */
LL_RCC_PLL2P_IsEnabled(void)4314 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4315 {
4316 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2PEN) == RCC_PLLCFGR_PLL2PEN) ? 1UL : 0UL);
4317 }
4318
4319 /**
4320 * @brief Check if PLL2 Q is enabled
4321 * @rmtoll PLLCFGR PLL2QEN LL_RCC_PLL2Q_IsEnabled
4322 * @retval State of bit (1 or 0).
4323 */
LL_RCC_PLL2Q_IsEnabled(void)4324 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4325 {
4326 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2QEN) == RCC_PLLCFGR_PLL2QEN) ? 1UL : 0UL);
4327 }
4328
4329 /**
4330 * @brief Check if PLL2 R is enabled
4331 * @rmtoll PLLCFGR PLL2REN LL_RCC_PLL2R_IsEnabled
4332 * @retval State of bit (1 or 0).
4333 */
LL_RCC_PLL2R_IsEnabled(void)4334 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4335 {
4336 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2REN) == RCC_PLLCFGR_PLL2REN) ? 1UL : 0UL);
4337 }
4338
4339 /**
4340 * @brief Check if PLL2 S is enabled
4341 * @rmtoll PLLCFGR PLL2SEN LL_RCC_PLL2S_IsEnabled
4342 * @retval State of bit (1 or 0).
4343 */
LL_RCC_PLL2S_IsEnabled(void)4344 __STATIC_INLINE uint32_t LL_RCC_PLL2S_IsEnabled(void)
4345 {
4346 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SEN) == RCC_PLLCFGR_PLL2SEN) ? 1UL : 0UL);
4347 }
4348
4349 /**
4350 * @brief Check if PLL2 T is enabled
4351 * @rmtoll PLLCFGR PLL2TEN LL_RCC_PLL2T_IsEnabled
4352 * @retval State of bit (1 or 0).
4353 */
LL_RCC_PLL2T_IsEnabled(void)4354 __STATIC_INLINE uint32_t LL_RCC_PLL2T_IsEnabled(void)
4355 {
4356 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2TEN) == RCC_PLLCFGR_PLL2TEN) ? 1UL : 0UL);
4357 }
4358
4359 /**
4360 * @brief Check if PLL2 FRACN is enabled
4361 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
4362 * @retval State of bit (1 or 0).
4363 */
LL_RCC_PLL2FRACN_IsEnabled(void)4364 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4365 {
4366 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL);
4367 }
4368
4369 /**
4370 * @brief Disable PLL2P
4371 * @note This API shall be called only when PLL2 is disabled.
4372 * @rmtoll PLLCFGR PLL2PEN LL_RCC_PLL2P_Disable
4373 * @retval None
4374 */
LL_RCC_PLL2P_Disable(void)4375 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4376 {
4377 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2PEN);
4378 }
4379
4380 /**
4381 * @brief Disable PLL2Q
4382 * @note This API shall be called only when PLL2 is disabled.
4383 * @rmtoll PLLCFGR PLL2QEN LL_RCC_PLL2Q_Disable
4384 * @retval None
4385 */
LL_RCC_PLL2Q_Disable(void)4386 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4387 {
4388 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2QEN);
4389 }
4390
4391 /**
4392 * @brief Disable PLL2R
4393 * @note This API shall be called only when PLL2 is disabled.
4394 * @rmtoll PLLCFGR PLL2REN LL_RCC_PLL2R_Disable
4395 * @retval None
4396 */
LL_RCC_PLL2R_Disable(void)4397 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4398 {
4399 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2REN);
4400 }
4401
4402 /**
4403 * @brief Disable PLL2S
4404 * @note This API shall be called only when PLL2 is disabled.
4405 * @rmtoll PLLCFGR PLL2SEN LL_RCC_PLL2S_Disable
4406 * @retval None
4407 */
LL_RCC_PLL2S_Disable(void)4408 __STATIC_INLINE void LL_RCC_PLL2S_Disable(void)
4409 {
4410 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SEN);
4411 }
4412
4413 /**
4414 * @brief Disable PLL2T
4415 * @note This API shall be called only when PLL2 is disabled.
4416 * @rmtoll PLLCFGR PLL2TEN LL_RCC_PLL2T_Disable
4417 * @retval None
4418 */
LL_RCC_PLL2T_Disable(void)4419 __STATIC_INLINE void LL_RCC_PLL2T_Disable(void)
4420 {
4421 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2TEN);
4422 }
4423
4424 /**
4425 * @brief Disable PLL2 FRACN
4426 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable
4427 * @retval None
4428 */
LL_RCC_PLL2FRACN_Disable(void)4429 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4430 {
4431 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4432 }
4433
4434 /**
4435 * @brief Get PLL2 VCO Input Range
4436 * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_GetVCOInputRange
4437 * @retval Returned value can be one of the following values:
4438 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4439 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4440 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4441 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4442 */
LL_RCC_PLL2_GetVCOInputRange(void)4443 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetVCOInputRange(void)
4444 {
4445 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE) >> 11U);
4446 }
4447
4448 /**
4449 * @brief Get PLL2 VCO OutputRange
4450 * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_GetVCOOutputRange
4451 * @retval Returned value can be one of the following values:
4452 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4453 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4454 */
LL_RCC_PLL2_GetVCOOutputRange(void)4455 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetVCOOutputRange(void)
4456 {
4457 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL) >> 11U);
4458 }
4459
4460 /**
4461 * @brief Set PLL2 VCO Input Range
4462 * @note This API shall be called only when PLL2 is disabled.
4463 * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
4464 * @param InputRange This parameter can be one of the following values:
4465 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4466 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4467 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4468 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4469 * @retval None
4470 */
LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)4471 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4472 {
4473 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (InputRange << 11U));
4474 }
4475
4476 /**
4477 * @brief Set PLL2 VCO OutputRange
4478 * @note This API shall be called only when PLL2 is disabled.
4479 * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOutputRange
4480 * @param VCORange This parameter can be one of the following values:
4481 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4482 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4483 * @retval None
4484 */
LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)4485 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4486 {
4487 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (VCORange << 11U));
4488 }
4489
4490 /**
4491 * @brief Get PLL2 N Coefficient
4492 * @rmtoll PLL2DIVR1 DIVN LL_RCC_PLL2_GetN
4493 * @retval A value between 8 and 420
4494 */
LL_RCC_PLL2_GetN(void)4495 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4496 {
4497 return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVN) >> RCC_PLL2DIVR1_DIVN_Pos) + 1UL);
4498 }
4499
4500 /**
4501 * @brief Get PLL2 M Coefficient
4502 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM
4503 * @retval A value between 0 and 63
4504 */
LL_RCC_PLL2_GetM(void)4505 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4506 {
4507 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
4508 }
4509
4510 /**
4511 * @brief Get PLL2 P Coefficient
4512 * @rmtoll PLL2DIVR1 DIVP LL_RCC_PLL2_GetP
4513 * @retval A value between 1 and 128
4514 */
LL_RCC_PLL2_GetP(void)4515 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4516 {
4517 return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVP) >> RCC_PLL2DIVR1_DIVP_Pos) + 1UL);
4518 }
4519
4520 /**
4521 * @brief Get PLL2 Q Coefficient
4522 * @rmtoll PLL2DIVR1 DIVQ LL_RCC_PLL2_GetQ
4523 * @retval A value between 1 and 128
4524 */
LL_RCC_PLL2_GetQ(void)4525 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4526 {
4527 return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVQ) >> RCC_PLL2DIVR1_DIVQ_Pos) + 1UL);
4528 }
4529
4530 /**
4531 * @brief Get PLL2 R Coefficient
4532 * @rmtoll PLL2DIVR1 DIVR LL_RCC_PLL2_GetR
4533 * @retval A value between 1 and 128
4534 */
LL_RCC_PLL2_GetR(void)4535 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4536 {
4537 return (uint32_t)((READ_BIT(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVR) >> RCC_PLL2DIVR1_DIVR_Pos) + 1UL);
4538 }
4539
4540 /**
4541 * @brief Get PLL2 S Coefficient
4542 * @rmtoll PLL2DIVR2 DIVS LL_RCC_PLL2_GetS
4543 * @retval A value between 1 and 8
4544 */
LL_RCC_PLL2_GetS(void)4545 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetS(void)
4546 {
4547 return (uint32_t)((READ_BIT(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVS) >> RCC_PLL2DIVR2_DIVS_Pos) + 1UL);
4548 }
4549
4550 /**
4551 * @brief Get PLL2 T Coefficient
4552 * @rmtoll PLL2DIVR2 DIVT LL_RCC_PLL2_GetT
4553 * @retval A value between 1 and 8
4554 */
LL_RCC_PLL2_GetT(void)4555 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetT(void)
4556 {
4557 return (uint32_t)((READ_BIT(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVT) >> RCC_PLL2DIVR2_DIVT_Pos) + 1UL);
4558 }
4559
4560 /**
4561 * @brief Get PLL2 FRACN Coefficient
4562 * @rmtoll PLL2FRACR FRACN LL_RCC_PLL2_GetFRACN
4563 * @retval A value between 0 and 8191 (0x1FFF)
4564 */
LL_RCC_PLL2_GetFRACN(void)4565 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4566 {
4567 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN) >> RCC_PLL2FRACR_FRACN_Pos);
4568 }
4569
4570 /**
4571 * @brief Set PLL2 N Coefficient
4572 * @note This API shall be called only when PLL2 is disabled.
4573 * @rmtoll PLL2DIVR1 DIVN LL_RCC_PLL2_SetN
4574 * @param N parameter can be a value between 8 and 420
4575 */
LL_RCC_PLL2_SetN(uint32_t N)4576 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
4577 {
4578 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVN, (N - 1UL) << RCC_PLL2DIVR1_DIVN_Pos);
4579 }
4580
4581 /**
4582 * @brief Set PLL2 M Coefficient
4583 * @note This API shall be called only when PLL2 is disabled.
4584 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM
4585 * @param M parameter can be a value between 1 and 64
4586 */
LL_RCC_PLL2_SetM(uint32_t M)4587 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
4588 {
4589 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
4590 }
4591
4592 /**
4593 * @brief Set PLL2 P Coefficient
4594 * @note This API shall be called only when PLL2 is disabled.
4595 * @rmtoll PLL2DIVR1 DIVP LL_RCC_PLL2_SetP
4596 * @param P parameter can be a value between 1 and 128
4597 */
LL_RCC_PLL2_SetP(uint32_t P)4598 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
4599 {
4600 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVP, (P - 1UL) << RCC_PLL2DIVR1_DIVP_Pos);
4601 }
4602
4603 /**
4604 * @brief Set PLL2 Q Coefficient
4605 * @note This API shall be called only when PLL2 is disabled.
4606 * @rmtoll PLL2DIVR1 DIVQ LL_RCC_PLL2_SetQ
4607 * @param Q parameter can be a value between 1 and 128
4608 */
LL_RCC_PLL2_SetQ(uint32_t Q)4609 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
4610 {
4611 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVQ, (Q - 1UL) << RCC_PLL2DIVR1_DIVQ_Pos);
4612 }
4613
4614 /**
4615 * @brief Set PLL2 R Coefficient
4616 * @note This API shall be called only when PLL2 is disabled.
4617 * @rmtoll PLL2DIVR1 DIVR LL_RCC_PLL2_SetR
4618 * @param R parameter can be a value between 1 and 128
4619 */
LL_RCC_PLL2_SetR(uint32_t R)4620 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
4621 {
4622 MODIFY_REG(RCC->PLL2DIVR1, RCC_PLL2DIVR1_DIVR, (R - 1UL) << RCC_PLL2DIVR1_DIVR_Pos);
4623 }
4624
4625 /**
4626 * @brief Set PLL2 S Coefficient
4627 * @note This API shall be called only when PLL2 is disabled.
4628 * @rmtoll PLL2DIVR2 DIVS LL_RCC_PLL2_SetS
4629 * @param S parameter can be a value between 1 and 8
4630 */
LL_RCC_PLL2_SetS(uint32_t S)4631 __STATIC_INLINE void LL_RCC_PLL2_SetS(uint32_t S)
4632 {
4633 MODIFY_REG(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVS, (S - 1UL) << RCC_PLL2DIVR2_DIVS_Pos);
4634 }
4635
4636 /**
4637 * @brief Set PLL2 T Coefficient
4638 * @note This API shall be called only when PLL2 is disabled.
4639 * @rmtoll PLL2DIVR2 DIVT LL_RCC_PLL2_SetT
4640 * @param T parameter can be a value between 1 and 8
4641 */
LL_RCC_PLL2_SetT(uint32_t T)4642 __STATIC_INLINE void LL_RCC_PLL2_SetT(uint32_t T)
4643 {
4644 MODIFY_REG(RCC->PLL2DIVR2, RCC_PLL2DIVR2_DIVT, (T - 1UL) << RCC_PLL2DIVR2_DIVT_Pos);
4645 }
4646
4647 /**
4648 * @brief Set PLL2 FRACN Coefficient
4649 * @rmtoll PLL2FRACR FRACN LL_RCC_PLL2_SetFRACN
4650 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4651 */
LL_RCC_PLL2_SetFRACN(uint32_t FRACN)4652 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
4653 {
4654 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN, FRACN << RCC_PLL2FRACR_FRACN_Pos);
4655 }
4656
4657 /**
4658 * @brief Enable Spread Spectrum for PLL2.
4659 * @note Configuration to be done with LL_RCC_PLL2_ConfigSpreadSpectrum
4660 * @rmtoll PLLCFGR PLL2SSCGEN LL_RCC_PLL2_EnableSpreadSpectrum
4661 * @retval None
4662 */
LL_RCC_PLL2_EnableSpreadSpectrum(void)4663 __STATIC_INLINE void LL_RCC_PLL2_EnableSpreadSpectrum(void)
4664 {
4665 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SSCGEN);
4666 }
4667
4668 /**
4669 * @brief Disable Spread Spectrum for PLL2.
4670 * @rmtoll PLLCFGR PLL2SSCGEN LL_RCC_PLL2_DisableSpreadSpectrum
4671 * @retval None
4672 */
LL_RCC_PLL2_DisableSpreadSpectrum(void)4673 __STATIC_INLINE void LL_RCC_PLL2_DisableSpreadSpectrum(void)
4674 {
4675 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SSCGEN);
4676 }
4677
4678 /**
4679 * @brief Check if Spread Spectrum for PLL2 is enabled
4680 * @rmtoll PLLCFGR PLL2SSCGEN LL_RCC_PLL2_IsEnabledSpreadSpectrum
4681 * @retval State of bit (1 or 0).
4682 */
LL_RCC_PLL2_IsEnabledSpreadSpectrum(void)4683 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledSpreadSpectrum(void)
4684 {
4685 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2SSCGEN) == RCC_PLLCFGR_PLL2SSCGEN) ? 1UL : 0UL);
4686 }
4687
4688 /**
4689 * @brief Get Spread Spectrum Modulation Period for PLL2
4690 * @rmtoll PLL2SSCGR MODPER LL_RCC_PLL2_GetModulationPeriod
4691 * @retval Between Min_Data=0 and Max_Data=8191
4692 */
LL_RCC_PLL2_GetModulationPeriod(void)4693 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetModulationPeriod(void)
4694 {
4695 return (uint32_t)(READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_MODPER));
4696 }
4697
4698 /**
4699 * @brief Get Spread Spectrum Increment Step for PLL2
4700 * @rmtoll PLL2SSCGR INCSTEP LL_RCC_PLL2_GetIncrementStep
4701 * @retval Between Min_Data=0 and Max_Data=32767
4702 */
LL_RCC_PLL2_GetIncrementStep(void)4703 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetIncrementStep(void)
4704 {
4705 return (uint32_t)(READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_INCSTEP) >> RCC_PLL2SSCGR_INCSTEP_Pos);
4706 }
4707
4708 /**
4709 * @brief Get Spread Spectrum Selection for PLL2
4710 * @rmtoll PLL2SSCGR SPREADSEL LL_RCC_PLL2_GetSpreadSelection
4711 * @retval Returned value can be one of the following values:
4712 * @arg @ref LL_RCC_PLL_SPREAD_CENTER
4713 * @arg @ref LL_RCC_PLL_SPREAD_DOWN
4714 */
LL_RCC_PLL2_GetSpreadSelection(void)4715 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetSpreadSelection(void)
4716 {
4717 return (uint32_t)(READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_SPREADSEL));
4718 }
4719
4720
4721 /**
4722 * @brief Check if Dithering RPDF Noise for PLL2 is enabled
4723 * @rmtoll PLL2SSCGR RPDFNDIS LL_RCC_PLL2_IsEnabledRPDFNDithering
4724 * @retval State of bit (1 or 0).
4725 */
LL_RCC_PLL2_IsEnabledRPDFNDithering(void)4726 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledRPDFNDithering(void)
4727 {
4728 return ((READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_RPDFNDIS) == 0U) ? 1UL : 0UL);
4729 }
4730
4731 /**
4732 * @brief Check if Dithering TPDF Noise for PLL2 is enabled
4733 * @rmtoll PLL2SSCGR TPDFNDIS LL_RCC_PLL2_IsEnabledTPDFNDithering
4734 * @retval State of bit (1 or 0).
4735 */
LL_RCC_PLL2_IsEnabledTPDFNDithering(void)4736 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledTPDFNDithering(void)
4737 {
4738 return ((READ_BIT(RCC->PLL2SSCGR, RCC_PLL2SSCGR_TPDFNDIS) == 0U) ? 1UL : 0UL);
4739 }
4740 /**
4741 * @brief Enable PLL3
4742 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
4743 * @retval None
4744 */
LL_RCC_PLL3_Enable(void)4745 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4746 {
4747 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
4748 }
4749
4750 /**
4751 * @brief Disable PLL3
4752 * @note Cannot be disabled if the PLL3 clock is used as the system clock
4753 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
4754 * @retval None
4755 */
LL_RCC_PLL3_Disable(void)4756 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4757 {
4758 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
4759 }
4760
4761 /**
4762 * @brief Check if PLL3 Ready
4763 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
4764 * @retval State of bit (1 or 0).
4765 */
LL_RCC_PLL3_IsReady(void)4766 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4767 {
4768 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL);
4769 }
4770
4771 /**
4772 * @brief Enable PLL3P
4773 * @note This API shall be called only when PLL3 is disabled.
4774 * @rmtoll PLLCFGR PLL3PEN LL_RCC_PLL3P_Enable
4775 * @retval None
4776 */
LL_RCC_PLL3P_Enable(void)4777 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
4778 {
4779 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3PEN);
4780 }
4781
4782 /**
4783 * @brief Enable PLL3Q
4784 * @note This API shall be called only when PLL3 is disabled.
4785 * @rmtoll PLLCFGR PLL3QEN LL_RCC_PLL3Q_Enable
4786 * @retval None
4787 */
LL_RCC_PLL3Q_Enable(void)4788 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
4789 {
4790 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3QEN);
4791 }
4792
4793 /**
4794 * @brief Enable PLL3R
4795 * @note This API shall be called only when PLL3 is disabled.
4796 * @rmtoll PLLCFGR PLL3REN LL_RCC_PLL3R_Enable
4797 * @retval None
4798 */
LL_RCC_PLL3R_Enable(void)4799 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
4800 {
4801 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3REN);
4802 }
4803
4804 /**
4805 * @brief Enable PLL3S
4806 * @note This API shall be called only when PLL3 is disabled.
4807 * @rmtoll PLLCFGR PLL3SEN LL_RCC_PLL3S_Enable
4808 * @retval None
4809 */
LL_RCC_PLL3S_Enable(void)4810 __STATIC_INLINE void LL_RCC_PLL3S_Enable(void)
4811 {
4812 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SEN);
4813 }
4814
4815 /**
4816 * @brief Enable PLL3 FRACN
4817 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
4818 * @retval None
4819 */
LL_RCC_PLL3FRACN_Enable(void)4820 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
4821 {
4822 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
4823 }
4824
4825 /**
4826 * @brief Check if PLL3 P is enabled
4827 * @rmtoll PLLCFGR PLL3PEN LL_RCC_PLL3P_IsEnabled
4828 * @retval State of bit (1 or 0).
4829 */
LL_RCC_PLL3P_IsEnabled(void)4830 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
4831 {
4832 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3PEN) == RCC_PLLCFGR_PLL3PEN) ? 1UL : 0UL);
4833 }
4834
4835 /**
4836 * @brief Check if PLL3 Q is enabled
4837 * @rmtoll PLLCFGR PLL3QEN LL_RCC_PLL3Q_IsEnabled
4838 * @retval State of bit (1 or 0).
4839 */
LL_RCC_PLL3Q_IsEnabled(void)4840 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
4841 {
4842 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3QEN) == RCC_PLLCFGR_PLL3QEN) ? 1UL : 0UL);
4843 }
4844
4845 /**
4846 * @brief Check if PLL3 R is enabled
4847 * @rmtoll PLLCFGR PLL3REN LL_RCC_PLL3R_IsEnabled
4848 * @retval State of bit (1 or 0).
4849 */
LL_RCC_PLL3R_IsEnabled(void)4850 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
4851 {
4852 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3REN) == RCC_PLLCFGR_PLL3REN) ? 1UL : 0UL);
4853 }
4854
4855 /**
4856 * @brief Check if PLL3 S is enabled
4857 * @rmtoll PLLCFGR PLL3SEN LL_RCC_PLL3S_IsEnabled
4858 * @retval State of bit (1 or 0).
4859 */
LL_RCC_PLL3S_IsEnabled(void)4860 __STATIC_INLINE uint32_t LL_RCC_PLL3S_IsEnabled(void)
4861 {
4862 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SEN) == RCC_PLLCFGR_PLL3SEN) ? 1UL : 0UL);
4863 }
4864
4865 /**
4866 * @brief Check if PLL3 FRACN is enabled
4867 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
4868 * @retval State of bit (1 or 0).
4869 */
LL_RCC_PLL3FRACN_IsEnabled(void)4870 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
4871 {
4872 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL);
4873 }
4874
4875 /**
4876 * @brief Disable PLL3P
4877 * @note This API shall be called only when PLL3 is disabled.
4878 * @rmtoll PLLCFGR PLL3PEN LL_RCC_PLL3P_Disable
4879 * @retval None
4880 */
LL_RCC_PLL3P_Disable(void)4881 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
4882 {
4883 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3PEN);
4884 }
4885
4886 /**
4887 * @brief Disable PLL3Q
4888 * @note This API shall be called only when PLL3 is disabled.
4889 * @rmtoll PLLCFGR PLL3QEN LL_RCC_PLL3Q_Disable
4890 * @retval None
4891 */
LL_RCC_PLL3Q_Disable(void)4892 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
4893 {
4894 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3QEN);
4895 }
4896
4897 /**
4898 * @brief Disable PLL3R
4899 * @note This API shall be called only when PLL3 is disabled.
4900 * @rmtoll PLLCFGR PLL3REN LL_RCC_PLL3R_Disable
4901 * @retval None
4902 */
LL_RCC_PLL3R_Disable(void)4903 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
4904 {
4905 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3REN);
4906 }
4907
4908 /**
4909 * @brief Disable PLL3S
4910 * @note This API shall be called only when PLL3 is disabled.
4911 * @rmtoll PLLCFGR PLL3SEN LL_RCC_PLL3S_Disable
4912 * @retval None
4913 */
LL_RCC_PLL3S_Disable(void)4914 __STATIC_INLINE void LL_RCC_PLL3S_Disable(void)
4915 {
4916 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SEN);
4917 }
4918
4919 /**
4920 * @brief Disable PLL3 FRACN
4921 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable
4922 * @retval None
4923 */
LL_RCC_PLL3FRACN_Disable(void)4924 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
4925 {
4926 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
4927 }
4928
4929 /**
4930 * @brief Get PLL3 VCO Input Range
4931 * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_GetVCOInputRange
4932 * @retval Returned value can be one of the following values:
4933 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4934 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4935 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4936 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4937 */
LL_RCC_PLL3_GetVCOInputRange(void)4938 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetVCOInputRange(void)
4939 {
4940 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE) >> 22U);
4941 }
4942
4943 /**
4944 * @brief Get PLL3 VCO OutputRange
4945 * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_GetVCOOutputRange
4946 * @retval Returned value can be one of the following values:
4947 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4948 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4949 */
LL_RCC_PLL3_GetVCOOutputRange(void)4950 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetVCOOutputRange(void)
4951 {
4952 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL) >> 22U);
4953 }
4954
4955 /**
4956 * @brief Set PLL3 VCO Input Range
4957 * @note This API shall be called only when PLL3 is disabled.
4958 * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
4959 * @param InputRange This parameter can be one of the following values:
4960 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4961 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4962 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4963 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4964 * @retval None
4965 */
LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)4966 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
4967 {
4968 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (InputRange << 22U));
4969 }
4970
4971 /**
4972 * @brief Set PLL3 VCO OutputRange
4973 * @note This API shall be called only when PLL3 is disabled.
4974 * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOutputRange
4975 * @param VCORange This parameter can be one of the following values:
4976 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4977 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4978 * @retval None
4979 */
LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)4980 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
4981 {
4982 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (VCORange << 22U));
4983 }
4984
4985 /**
4986 * @brief Get PLL3 N Coefficient
4987 * @rmtoll PLL3DIVR1 DIVN LL_RCC_PLL3_GetN
4988 * @retval A value between 8 and 420
4989 */
LL_RCC_PLL3_GetN(void)4990 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
4991 {
4992 return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVN) >> RCC_PLL3DIVR1_DIVN_Pos) + 1UL);
4993 }
4994
4995 /**
4996 * @brief Get PLL3 M Coefficient
4997 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM
4998 * @retval A value between 0 and 63
4999 */
LL_RCC_PLL3_GetM(void)5000 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5001 {
5002 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
5003 }
5004
5005 /**
5006 * @brief Get PLL3 P Coefficient
5007 * @rmtoll PLL3DIVR1 DIVP LL_RCC_PLL3_GetP
5008 * @retval A value between 1 and 128
5009 */
LL_RCC_PLL3_GetP(void)5010 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
5011 {
5012 return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVP) >> RCC_PLL3DIVR1_DIVP_Pos) + 1UL);
5013 }
5014
5015 /**
5016 * @brief Get PLL3 Q Coefficient
5017 * @rmtoll PLL3DIVR1 DIVQ LL_RCC_PLL3_GetQ
5018 * @retval A value between 1 and 128
5019 */
LL_RCC_PLL3_GetQ(void)5020 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5021 {
5022 return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVQ) >> RCC_PLL3DIVR1_DIVQ_Pos) + 1UL);
5023 }
5024
5025 /**
5026 * @brief Get PLL3 R Coefficient
5027 * @rmtoll PLL3DIVR1 DIVR LL_RCC_PLL3_GetR
5028 * @retval A value between 1 and 128
5029 */
LL_RCC_PLL3_GetR(void)5030 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5031 {
5032 return (uint32_t)((READ_BIT(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVR) >> RCC_PLL3DIVR1_DIVR_Pos) + 1UL);
5033 }
5034
5035 /**
5036 * @brief Get PLL3 S Coefficient
5037 * @rmtoll PLL3DIVR2 DIVS LL_RCC_PLL3_GetS
5038 * @retval A value between 1 and 8
5039 */
LL_RCC_PLL3_GetS(void)5040 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetS(void)
5041 {
5042 return (uint32_t)((READ_BIT(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS) >> RCC_PLL3DIVR2_DIVS_Pos) + 1UL);
5043 }
5044
5045 /**
5046 * @brief Get PLL3 FRACN Coefficient
5047 * @rmtoll PLL3FRACR FRACN LL_RCC_PLL3_GetFRACN
5048 * @retval A value between 0 and 8191 (0x1FFF)
5049 */
LL_RCC_PLL3_GetFRACN(void)5050 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5051 {
5052 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN) >> RCC_PLL3FRACR_FRACN_Pos);
5053 }
5054
5055 /**
5056 * @brief Set PLL3 N Coefficient
5057 * @note This API shall be called only when PLL3 is disabled.
5058 * @rmtoll PLL3DIVR1 DIVN LL_RCC_PLL3_SetN
5059 * @param N parameter can be a value between 8 and 420
5060 */
LL_RCC_PLL3_SetN(uint32_t N)5061 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
5062 {
5063 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVN, (N - 1UL) << RCC_PLL3DIVR1_DIVN_Pos);
5064 }
5065
5066 /**
5067 * @brief Set PLL3 M Coefficient
5068 * @note This API shall be called only when PLL3 is disabled.
5069 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM
5070 * @param M parameter can be a value between 1 and 64
5071 */
LL_RCC_PLL3_SetM(uint32_t M)5072 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
5073 {
5074 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
5075 }
5076
5077 /**
5078 * @brief Set PLL3 P Coefficient
5079 * @note This API shall be called only when PLL3 is disabled.
5080 * @rmtoll PLL3DIVR1 DIVP LL_RCC_PLL3_SetP
5081 * @param P parameter can be a value between 1 and 128
5082 */
LL_RCC_PLL3_SetP(uint32_t P)5083 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
5084 {
5085 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVP, (P - 1UL) << RCC_PLL3DIVR1_DIVP_Pos);
5086 }
5087
5088 /**
5089 * @brief Set PLL3 Q Coefficient
5090 * @note This API shall be called only when PLL3 is disabled.
5091 * @rmtoll PLL3DIVR1 DIVQ LL_RCC_PLL3_SetQ
5092 * @param Q parameter can be a value between 1 and 128
5093 */
LL_RCC_PLL3_SetQ(uint32_t Q)5094 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
5095 {
5096 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVQ, (Q - 1UL) << RCC_PLL3DIVR1_DIVQ_Pos);
5097 }
5098
5099 /**
5100 * @brief Set PLL3 R Coefficient
5101 * @note This API shall be called only when PLL3 is disabled.
5102 * @rmtoll PLL3DIVR1 DIVR LL_RCC_PLL3_SetR
5103 * @param R parameter can be a value between 1 and 128
5104 */
LL_RCC_PLL3_SetR(uint32_t R)5105 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
5106 {
5107 MODIFY_REG(RCC->PLL3DIVR1, RCC_PLL3DIVR1_DIVR, (R - 1UL) << RCC_PLL3DIVR1_DIVR_Pos);
5108 }
5109
5110 /**
5111 * @brief Set PLL3 S Coefficient
5112 * @note This API shall be called only when PLL3 is disabled.
5113 * @rmtoll PLL3DIVR2 DIVS LL_RCC_PLL3_SetS
5114 * @param S parameter can be a value between 1 and 8
5115 */
LL_RCC_PLL3_SetS(uint32_t S)5116 __STATIC_INLINE void LL_RCC_PLL3_SetS(uint32_t S)
5117 {
5118 MODIFY_REG(RCC->PLL3DIVR2, RCC_PLL3DIVR2_DIVS, (S - 1UL) << RCC_PLL3DIVR2_DIVS_Pos);
5119 }
5120
5121 /**
5122 * @brief Set PLL3 FRACN Coefficient
5123 * @rmtoll PLL3FRACR FRACN LL_RCC_PLL3_SetFRACN
5124 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5125 */
LL_RCC_PLL3_SetFRACN(uint32_t FRACN)5126 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5127 {
5128 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN, FRACN << RCC_PLL3FRACR_FRACN_Pos);
5129 }
5130
5131
5132 /**
5133 * @brief Enable Spread Spectrum for PLL3.
5134 * @note Configuration to be done with LL_RCC_PLL3_ConfigSpreadSpectrum
5135 * @rmtoll PLLCFGR PLL3SSCGEN LL_RCC_PLL3_EnableSpreadSpectrum
5136 * @retval None
5137 */
LL_RCC_PLL3_EnableSpreadSpectrum(void)5138 __STATIC_INLINE void LL_RCC_PLL3_EnableSpreadSpectrum(void)
5139 {
5140 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SSCGEN);
5141 }
5142
5143 /**
5144 * @brief Disable Spread Spectrum for PLL3.
5145 * @rmtoll PLLCFGR PLL3SSCGEN LL_RCC_PLL3_DisableSpreadSpectrum
5146 * @retval None
5147 */
LL_RCC_PLL3_DisableSpreadSpectrum(void)5148 __STATIC_INLINE void LL_RCC_PLL3_DisableSpreadSpectrum(void)
5149 {
5150 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SSCGEN);
5151 }
5152
5153 /**
5154 * @brief Check if Spread Spectrum for PLL3 is enabled
5155 * @rmtoll PLLCFGR PLL3SSCGEN LL_RCC_PLL3_IsEnabledSpreadSpectrum
5156 * @retval State of bit (1 or 0).
5157 */
LL_RCC_PLL3_IsEnabledSpreadSpectrum(void)5158 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledSpreadSpectrum(void)
5159 {
5160 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3SSCGEN) == RCC_PLLCFGR_PLL3SSCGEN) ? 1UL : 0UL);
5161 }
5162
5163 /**
5164 * @brief Get Spread Spectrum Modulation Period for PLL3
5165 * @rmtoll PLL3SSCGR MODPER LL_RCC_PLL3_GetModulationPeriod
5166 * @retval Between Min_Data=0 and Max_Data=8191
5167 */
LL_RCC_PLL3_GetModulationPeriod(void)5168 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetModulationPeriod(void)
5169 {
5170 return (uint32_t)(READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_MODPER));
5171 }
5172
5173 /**
5174 * @brief Get Spread Spectrum Increment Step for PLL3
5175 * @rmtoll PLL3SSCGR INCSTEP LL_RCC_PLL3_GetIncrementStep
5176 * @retval Between Min_Data=0 and Max_Data=32767
5177 */
LL_RCC_PLL3_GetIncrementStep(void)5178 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetIncrementStep(void)
5179 {
5180 return (uint32_t)(READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_INCSTEP) >> RCC_PLL3SSCGR_INCSTEP_Pos);
5181 }
5182
5183 /**
5184 * @brief Get Spread Spectrum Selection for PLL3
5185 * @rmtoll PLL3SSCGR SPREADSEL LL_RCC_PLL3_GetSpreadSelection
5186 * @retval Returned value can be one of the following values:
5187 * @arg @ref LL_RCC_PLL_SPREAD_CENTER
5188 * @arg @ref LL_RCC_PLL_SPREAD_DOWN
5189 */
LL_RCC_PLL3_GetSpreadSelection(void)5190 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetSpreadSelection(void)
5191 {
5192 return (uint32_t)(READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_SPREADSEL));
5193 }
5194
5195
5196 /**
5197 * @brief Check if Dithering RPDF Noise for PLL3 is enabled
5198 * @rmtoll PLL3SSCGR RPDFNDIS LL_RCC_PLL3_IsEnabledRPDFNDithering
5199 * @retval State of bit (1 or 0).
5200 */
LL_RCC_PLL3_IsEnabledRPDFNDithering(void)5201 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledRPDFNDithering(void)
5202 {
5203 return ((READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_RPDFNDIS) == 0U) ? 1UL : 0UL);
5204 }
5205
5206 /**
5207 * @brief Check if Dithering TPDF Noise for PLL3 is enabled
5208 * @rmtoll PLL3SSCGR TPDFNDIS LL_RCC_PLL3_IsEnabledTPDFNDithering
5209 * @retval State of bit (1 or 0).
5210 */
LL_RCC_PLL3_IsEnabledTPDFNDithering(void)5211 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledTPDFNDithering(void)
5212 {
5213 return ((READ_BIT(RCC->PLL3SSCGR, RCC_PLL3SSCGR_TPDFNDIS) == 0U) ? 1UL : 0UL);
5214 }
5215 /**
5216 * @}
5217 */
5218
5219
5220 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5221 * @{
5222 */
5223
5224 /**
5225 * @brief Clear LSI ready interrupt flag
5226 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5227 * @retval None
5228 */
LL_RCC_ClearFlag_LSIRDY(void)5229 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5230 {
5231 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5232 }
5233
5234 /**
5235 * @brief Clear LSE ready interrupt flag
5236 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5237 * @retval None
5238 */
LL_RCC_ClearFlag_LSERDY(void)5239 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5240 {
5241 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5242 }
5243
5244 /**
5245 * @brief Clear HSI ready interrupt flag
5246 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5247 * @retval None
5248 */
LL_RCC_ClearFlag_HSIRDY(void)5249 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5250 {
5251 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5252 }
5253
5254 /**
5255 * @brief Clear HSE ready interrupt flag
5256 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5257 * @retval None
5258 */
LL_RCC_ClearFlag_HSERDY(void)5259 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5260 {
5261 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5262 }
5263
5264 /**
5265 * @brief Clear CSI ready interrupt flag
5266 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
5267 * @retval None
5268 */
LL_RCC_ClearFlag_CSIRDY(void)5269 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5270 {
5271 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5272 }
5273
5274 /**
5275 * @brief Clear HSI48 ready interrupt flag
5276 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5277 * @retval None
5278 */
LL_RCC_ClearFlag_HSI48RDY(void)5279 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5280 {
5281 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5282 }
5283
5284 /**
5285 * @brief Clear PLL1 ready interrupt flag
5286 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
5287 * @retval None
5288 */
LL_RCC_ClearFlag_PLL1RDY(void)5289 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5290 {
5291 SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC);
5292 }
5293
5294 /**
5295 * @brief Clear PLL2 ready interrupt flag
5296 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
5297 * @retval None
5298 */
LL_RCC_ClearFlag_PLL2RDY(void)5299 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5300 {
5301 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5302 }
5303
5304 /**
5305 * @brief Clear PLL3 ready interrupt flag
5306 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
5307 * @retval None
5308 */
LL_RCC_ClearFlag_PLL3RDY(void)5309 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5310 {
5311 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5312 }
5313
5314 /**
5315 * @brief Clear LSE Clock security system interrupt flag
5316 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
5317 * @retval None
5318 */
LL_RCC_ClearFlag_LSECSS(void)5319 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5320 {
5321 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5322 }
5323
5324 /**
5325 * @brief Clear HSE Clock security system interrupt flag
5326 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
5327 * @retval None
5328 */
LL_RCC_ClearFlag_HSECSS(void)5329 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5330 {
5331 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5332 }
5333
5334 /**
5335 * @brief Check if LSI ready interrupt occurred or not
5336 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5337 * @retval State of bit (1 or 0).
5338 */
LL_RCC_IsActiveFlag_LSIRDY(void)5339 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5340 {
5341 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL);
5342 }
5343
5344 /**
5345 * @brief Check if LSE ready interrupt occurred or not
5346 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5347 * @retval State of bit (1 or 0).
5348 */
LL_RCC_IsActiveFlag_LSERDY(void)5349 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5350 {
5351 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL);
5352 }
5353
5354 /**
5355 * @brief Check if HSI ready interrupt occurred or not
5356 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5357 * @retval State of bit (1 or 0).
5358 */
LL_RCC_IsActiveFlag_HSIRDY(void)5359 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5360 {
5361 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL);
5362 }
5363
5364 /**
5365 * @brief Check if HSE ready interrupt occurred or not
5366 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5367 * @retval State of bit (1 or 0).
5368 */
LL_RCC_IsActiveFlag_HSERDY(void)5369 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5370 {
5371 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL);
5372 }
5373
5374 /**
5375 * @brief Check if CSI ready interrupt occurred or not
5376 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
5377 * @retval State of bit (1 or 0).
5378 */
LL_RCC_IsActiveFlag_CSIRDY(void)5379 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5380 {
5381 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == RCC_CIFR_CSIRDYF) ? 1UL : 0UL);
5382 }
5383
5384 /**
5385 * @brief Check if HSI48 ready interrupt occurred or not
5386 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5387 * @retval State of bit (1 or 0).
5388 */
LL_RCC_IsActiveFlag_HSI48RDY(void)5389 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5390 {
5391 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL);
5392 }
5393
5394 /**
5395 * @brief Check if PLL1 ready interrupt occurred or not
5396 * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY
5397 * @retval State of bit (1 or 0).
5398 */
LL_RCC_IsActiveFlag_PLL1RDY(void)5399 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5400 {
5401 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL);
5402 }
5403
5404 /**
5405 * @brief Check if PLL2 ready interrupt occurred or not
5406 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
5407 * @retval State of bit (1 or 0).
5408 */
LL_RCC_IsActiveFlag_PLL2RDY(void)5409 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5410 {
5411 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL);
5412 }
5413
5414 /**
5415 * @brief Check if PLL3 ready interrupt occurred or not
5416 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
5417 * @retval State of bit (1 or 0).
5418 */
LL_RCC_IsActiveFlag_PLL3RDY(void)5419 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5420 {
5421 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL);
5422 }
5423
5424 /**
5425 * @brief Check if LSE Clock security system interrupt occurred or not
5426 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
5427 * @retval State of bit (1 or 0).
5428 */
LL_RCC_IsActiveFlag_LSECSS(void)5429 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5430 {
5431 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL);
5432 }
5433
5434 /**
5435 * @brief Check if HSE Clock security system interrupt occurred or not
5436 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
5437 * @retval State of bit (1 or 0).
5438 */
LL_RCC_IsActiveFlag_HSECSS(void)5439 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5440 {
5441 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL);
5442 }
5443
5444 /**
5445 * @brief Check if RCC flag Low Power D1 reset is set or not.
5446 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
5447 * @retval State of bit (1 or 0).
5448 */
LL_RCC_IsActiveFlag_LPWRRST(void)5449 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5450 {
5451 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == RCC_RSR_LPWRRSTF) ? 1UL : 0UL);
5452 }
5453
5454 /**
5455 * @brief Check if RCC flag Window Watchdog reset is set or not.
5456 * @rmtoll RSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
5457 * @retval State of bit (1 or 0).
5458 */
LL_RCC_IsActiveFlag_WWDGRST(void)5459 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
5460 {
5461 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDGRSTF) == RCC_RSR_WWDGRSTF) ? 1UL : 0UL);
5462 }
5463
5464 /**
5465 * @brief Check if RCC flag Independent Watchdog reset is set or not.
5466 * @rmtoll RSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
5467 * @retval State of bit (1 or 0).
5468 */
LL_RCC_IsActiveFlag_IWDGRST(void)5469 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
5470 {
5471 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDGRSTF) == RCC_RSR_IWDGRSTF) ? 1UL : 0UL);
5472 }
5473
5474 /**
5475 * @brief Check if RCC flag Software reset is set or not.
5476 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
5477 * @retval State of bit (1 or 0).
5478 */
LL_RCC_IsActiveFlag_SFTRST(void)5479 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5480 {
5481 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == RCC_RSR_SFTRSTF) ? 1UL : 0UL);
5482 }
5483
5484 /**
5485 * @brief Check if RCC flag POR/PDR reset is set or not.
5486 * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
5487 * @retval State of bit (1 or 0).
5488 */
LL_RCC_IsActiveFlag_PORRST(void)5489 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
5490 {
5491 return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == RCC_RSR_PORRSTF) ? 1UL : 0UL);
5492 }
5493
5494 /**
5495 * @brief Check if RCC flag Pin reset is set or not.
5496 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5497 * @retval State of bit (1 or 0).
5498 */
LL_RCC_IsActiveFlag_PINRST(void)5499 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5500 {
5501 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == RCC_RSR_PINRSTF) ? 1UL : 0UL);
5502 }
5503
5504 /**
5505 * @brief Check if RCC flag BOR reset is set or not.
5506 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5507 * @retval State of bit (1 or 0).
5508 */
LL_RCC_IsActiveFlag_BORRST(void)5509 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5510 {
5511 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
5512 }
5513
5514 /**
5515 * @brief Set RMVF bit to clear all reset flags.
5516 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
5517 * @retval None
5518 */
LL_RCC_ClearResetFlags(void)5519 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5520 {
5521 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5522 }
5523
5524 /**
5525 * @}
5526 */
5527
5528 /** @defgroup RCC_LL_EF_IT_Management IT Management
5529 * @{
5530 */
5531
5532 /**
5533 * @brief Enable LSI ready interrupt
5534 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
5535 * @retval None
5536 */
LL_RCC_EnableIT_LSIRDY(void)5537 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
5538 {
5539 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5540 }
5541
5542 /**
5543 * @brief Enable LSE ready interrupt
5544 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
5545 * @retval None
5546 */
LL_RCC_EnableIT_LSERDY(void)5547 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
5548 {
5549 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5550 }
5551
5552 /**
5553 * @brief Enable HSI ready interrupt
5554 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
5555 * @retval None
5556 */
LL_RCC_EnableIT_HSIRDY(void)5557 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
5558 {
5559 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5560 }
5561
5562 /**
5563 * @brief Enable HSE ready interrupt
5564 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
5565 * @retval None
5566 */
LL_RCC_EnableIT_HSERDY(void)5567 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
5568 {
5569 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5570 }
5571
5572 /**
5573 * @brief Enable CSI ready interrupt
5574 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
5575 * @retval None
5576 */
LL_RCC_EnableIT_CSIRDY(void)5577 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
5578 {
5579 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5580 }
5581
5582 /**
5583 * @brief Enable HSI48 ready interrupt
5584 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
5585 * @retval None
5586 */
LL_RCC_EnableIT_HSI48RDY(void)5587 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
5588 {
5589 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5590 }
5591
5592 /**
5593 * @brief Enable PLL1 ready interrupt
5594 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
5595 * @retval None
5596 */
LL_RCC_EnableIT_PLL1RDY(void)5597 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
5598 {
5599 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
5600 }
5601
5602 /**
5603 * @brief Enable PLL2 ready interrupt
5604 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
5605 * @retval None
5606 */
LL_RCC_EnableIT_PLL2RDY(void)5607 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
5608 {
5609 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
5610 }
5611
5612 /**
5613 * @brief Enable PLL3 ready interrupt
5614 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
5615 * @retval None
5616 */
LL_RCC_EnableIT_PLL3RDY(void)5617 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
5618 {
5619 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
5620 }
5621
5622 /**
5623 * @brief Enable LSECSS interrupt
5624 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
5625 * @retval None
5626 */
LL_RCC_EnableIT_LSECSS(void)5627 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
5628 {
5629 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5630 }
5631
5632 /**
5633 * @brief Disable LSI ready interrupt
5634 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
5635 * @retval None
5636 */
LL_RCC_DisableIT_LSIRDY(void)5637 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
5638 {
5639 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
5640 }
5641
5642 /**
5643 * @brief Disable LSE ready interrupt
5644 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
5645 * @retval None
5646 */
LL_RCC_DisableIT_LSERDY(void)5647 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
5648 {
5649 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
5650 }
5651
5652 /**
5653 * @brief Disable HSI ready interrupt
5654 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
5655 * @retval None
5656 */
LL_RCC_DisableIT_HSIRDY(void)5657 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
5658 {
5659 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
5660 }
5661
5662 /**
5663 * @brief Disable HSE ready interrupt
5664 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
5665 * @retval None
5666 */
LL_RCC_DisableIT_HSERDY(void)5667 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5668 {
5669 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
5670 }
5671
5672 /**
5673 * @brief Disable CSI ready interrupt
5674 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
5675 * @retval None
5676 */
LL_RCC_DisableIT_CSIRDY(void)5677 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
5678 {
5679 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
5680 }
5681
5682 /**
5683 * @brief Disable HSI48 ready interrupt
5684 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
5685 * @retval None
5686 */
LL_RCC_DisableIT_HSI48RDY(void)5687 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
5688 {
5689 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
5690 }
5691
5692 /**
5693 * @brief Disable PLL1 ready interrupt
5694 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
5695 * @retval None
5696 */
LL_RCC_DisableIT_PLL1RDY(void)5697 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
5698 {
5699 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
5700 }
5701
5702 /**
5703 * @brief Disable PLL2 ready interrupt
5704 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
5705 * @retval None
5706 */
LL_RCC_DisableIT_PLL2RDY(void)5707 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
5708 {
5709 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
5710 }
5711
5712 /**
5713 * @brief Disable PLL3 ready interrupt
5714 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
5715 * @retval None
5716 */
LL_RCC_DisableIT_PLL3RDY(void)5717 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
5718 {
5719 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
5720 }
5721
5722 /**
5723 * @brief Disable LSECSS interrupt
5724 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
5725 * @retval None
5726 */
LL_RCC_DisableIT_LSECSS(void)5727 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
5728 {
5729 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
5730 }
5731
5732 /**
5733 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5734 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY
5735 * @retval State of bit (1 or 0).
5736 */
LL_RCC_IsEnableIT_LSIRDY(void)5737 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
5738 {
5739 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
5740 }
5741
5742 /**
5743 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5744 * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY
5745 * @retval State of bit (1 or 0).
5746 */
LL_RCC_IsEnableIT_LSERDY(void)5747 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
5748 {
5749 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
5750 }
5751
5752 /**
5753 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5754 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY
5755 * @retval State of bit (1 or 0).
5756 */
LL_RCC_IsEnableIT_HSIRDY(void)5757 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
5758 {
5759 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
5760 }
5761
5762 /**
5763 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5764 * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY
5765 * @retval State of bit (1 or 0).
5766 */
LL_RCC_IsEnableIT_HSERDY(void)5767 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
5768 {
5769 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
5770 }
5771
5772 /**
5773 * @brief Checks if CSI ready interrupt source is enabled or disabled.
5774 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY
5775 * @retval State of bit (1 or 0).
5776 */
LL_RCC_IsEnableIT_CSIRDY(void)5777 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
5778 {
5779 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);
5780 }
5781
5782 /**
5783 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
5784 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY
5785 * @retval State of bit (1 or 0).
5786 */
LL_RCC_IsEnableIT_HSI48RDY(void)5787 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
5788 {
5789 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
5790 }
5791
5792 /**
5793 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
5794 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY
5795 * @retval State of bit (1 or 0).
5796 */
LL_RCC_IsEnableIT_PLL1RDY(void)5797 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
5798 {
5799 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
5800 }
5801
5802 /**
5803 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
5804 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY
5805 * @retval State of bit (1 or 0).
5806 */
LL_RCC_IsEnableIT_PLL2RDY(void)5807 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
5808 {
5809 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
5810 }
5811
5812 /**
5813 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
5814 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY
5815 * @retval State of bit (1 or 0).
5816 */
LL_RCC_IsEnableIT_PLL3RDY(void)5817 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
5818 {
5819 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
5820 }
5821
5822 /**
5823 * @brief Checks if LSECSS interrupt source is enabled or disabled.
5824 * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS
5825 * @retval State of bit (1 or 0).
5826 */
LL_RCC_IsEnableIT_LSECSS(void)5827 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
5828 {
5829 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
5830 }
5831 /**
5832 * @}
5833 */
5834
5835 /** @defgroup RCC_LL_EF_CALC_FREQ Calculate frequencies
5836 * @{
5837 */
5838 /**
5839 * @brief Helper function to calculate the PLL frequency output
5840 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (),
5841 * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ());
5842 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
5843 * @param M Between 1 and 63
5844 * @param N Between 4 and 512
5845 * @param FRACN Between 0 and 0x1FFF
5846 * @param PQR VCO output divider (P, Q or R)
5847 * Between 1 and 128, except for PLL1P Odd value not allowed
5848 * @retval PLL1 clock frequency (in Hz)
5849 */
LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACN,uint32_t PQR)5850 __STATIC_INLINE uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN,
5851 uint32_t PQR)
5852 {
5853 float_t freq;
5854
5855 freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
5856
5857 freq = freq / (float_t)PQR;
5858
5859 return (uint32_t)freq;
5860 }
5861 /**
5862 * @}
5863 */
5864
5865 #if defined(USE_FULL_LL_DRIVER)
5866 /** @defgroup RCC_LL_EF_Init De-initialization function
5867 * @{
5868 */
5869 void LL_RCC_DeInit(void);
5870 /**
5871 * @}
5872 */
5873
5874 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
5875 * @{
5876 */
5877 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5878 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5879 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
5880 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
5881
5882 void LL_RCC_PLL1_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig);
5883 void LL_RCC_PLL2_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig);
5884 void LL_RCC_PLL3_ConfigSpreadSpectrum(const LL_PLL_SpreadSpectrumTypeDef *pConfig);
5885
5886 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
5887 uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource);
5888 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
5889 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
5890 uint32_t LL_RCC_GetETHPHYClockFreq(uint32_t ETHxSource);
5891 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
5892 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
5893 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
5894 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource);
5895 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
5896 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
5897 uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource);
5898 uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource);
5899 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
5900 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
5901 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
5902 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
5903 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
5904 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
5905 uint32_t LL_RCC_GetUSBPHYCClockFreq(uint32_t USBPHYCxSource);
5906
5907 /**
5908 * @}
5909 */
5910
5911 #endif /* USE_FULL_LL_DRIVER */
5912
5913 /**
5914 * @}
5915 */
5916
5917 /**
5918 * @}
5919 */
5920
5921 #endif /* defined(RCC) */
5922
5923 /**
5924 * @}
5925 */
5926
5927 #ifdef __cplusplus
5928 }
5929 #endif
5930
5931 #endif /* STM32H7RSxx_LL_RCC_H */
5932
