1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7RSxx_LL_CRS_H
21 #define STM32H7RSxx_LL_CRS_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined(CRS)
35
36 /** @defgroup CRS_LL CRS
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
48 * @{
49 */
50
51 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
52 * @brief Flags defines which can be used with LL_CRS_ReadReg function
53 * @{
54 */
55 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
56 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
57 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
58 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
59 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
60 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
61 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
62 /**
63 * @}
64 */
65
66 /** @defgroup CRS_LL_EC_IT IT Defines
67 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
68 * @{
69 */
70 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
71 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
72 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
73 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
74 /**
75 * @}
76 */
77
78 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
79 * @{
80 */
81 #define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
82 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
83 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
84 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
85 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
86 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
87 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
88 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
89 /**
90 * @}
91 */
92
93 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
94 * @{
95 */
96 #define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
97 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
98 #define LL_CRS_SYNC_SOURCE_OTG_FS CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source OTG_FS SOF (default) */
99 #define LL_CRS_SYNC_SOURCE_OTG_HS (CRS_CFGR_SYNCSRC_1 | CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source OTG_HS SOF */
100 /**
101 * @}
102 */
103
104 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
105 * @{
106 */
107 #define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
108 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
109 /**
110 * @}
111 */
112
113 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
114 * @{
115 */
116 #define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
117 #define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
118 /**
119 * @}
120 */
121
122 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
123 * @{
124 */
125 /**
126 * @brief Reset value of the RELOAD field
127 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
128 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
129 */
130 #define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
131
132 /**
133 * @brief Reset value of Frequency error limit.
134 */
135 #define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
136
137 /**
138 * @brief Reset value of the HSI48 Calibration field
139 * @note The default value is 32, which corresponds to the middle of the trimming interval.
140 * The trimming step is specified in the product datasheet.
141 * A higher TRIM value corresponds to a higher output frequency.
142 */
143 #define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
144 /**
145 * @}
146 */
147
148 /**
149 * @}
150 */
151
152 /* Exported macro ------------------------------------------------------------*/
153 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
154 * @{
155 */
156
157 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
158 * @{
159 */
160
161 /**
162 * @brief Write a value in CRS register
163 * @param __INSTANCE__ CRS Instance
164 * @param __REG__ Register to be written
165 * @param __VALUE__ Value to be written in the register
166 * @retval None
167 */
168 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
169
170 /**
171 * @brief Read a value in CRS register
172 * @param __INSTANCE__ CRS Instance
173 * @param __REG__ Register to be read
174 * @retval Register value
175 */
176 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
177 /**
178 * @}
179 */
180
181 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
182 * @{
183 */
184
185 /**
186 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
187 * @note The RELOAD value should be selected according to the ratio between
188 * the target frequency and the frequency of the synchronization source after
189 * prescaling. It is then decreased by one in order to reach the expected
190 * synchronization on the zero value. The formula is the following:
191 * RELOAD = (fTARGET / fSYNC) -1
192 * @param __FTARGET__ Target frequency (value in Hz)
193 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
194 * @retval Reload value (in Hz)
195 */
196 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
197
198 /**
199 * @}
200 */
201
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
208 * @{
209 */
210
211 /** @defgroup CRS_LL_EF_Configuration Configuration
212 * @{
213 */
214
215 /**
216 * @brief Enable Frequency error counter
217 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
218 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
219 * @retval None
220 */
LL_CRS_EnableFreqErrorCounter(void)221 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
222 {
223 SET_BIT(CRS->CR, CRS_CR_CEN);
224 }
225
226 /**
227 * @brief Disable Frequency error counter
228 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
229 * @retval None
230 */
LL_CRS_DisableFreqErrorCounter(void)231 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
232 {
233 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
234 }
235
236 /**
237 * @brief Check if Frequency error counter is enabled or not
238 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
239 * @retval State of bit (1 or 0).
240 */
LL_CRS_IsEnabledFreqErrorCounter(void)241 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
242 {
243 return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
244 }
245
246 /**
247 * @brief Enable Automatic trimming counter
248 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
249 * @retval None
250 */
LL_CRS_EnableAutoTrimming(void)251 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
252 {
253 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
254 }
255
256 /**
257 * @brief Disable Automatic trimming counter
258 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
259 * @retval None
260 */
LL_CRS_DisableAutoTrimming(void)261 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
262 {
263 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
264 }
265
266 /**
267 * @brief Check if Automatic trimming is enabled or not
268 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
269 * @retval State of bit (1 or 0).
270 */
LL_CRS_IsEnabledAutoTrimming(void)271 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
272 {
273 return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
274 }
275
276 /**
277 * @brief Set HSI48 oscillator smooth trimming
278 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
279 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
280 * @param Value a number between Min_Data = 0 and Max_Data = 63
281 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
282 * @retval None
283 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)284 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
285 {
286 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
287 }
288
289 /**
290 * @brief Get HSI48 oscillator smooth trimming
291 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
292 * @retval a number between Min_Data = 0 and Max_Data = 63
293 */
LL_CRS_GetHSI48SmoothTrimming(void)294 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
295 {
296 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
297 }
298
299 /**
300 * @brief Set counter reload value
301 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
302 * @param Value a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
303 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
304 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
305 * @retval None
306 */
LL_CRS_SetReloadCounter(uint32_t Value)307 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
308 {
309 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
310 }
311
312 /**
313 * @brief Get counter reload value
314 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
315 * @retval a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
316 */
LL_CRS_GetReloadCounter(void)317 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
318 {
319 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
320 }
321
322 /**
323 * @brief Set frequency error limit
324 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
325 * @param Value a number between Min_Data = 0 and Max_Data = 255
326 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
327 * @retval None
328 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)329 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
330 {
331 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
332 }
333
334 /**
335 * @brief Get frequency error limit
336 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
337 * @retval A number between Min_Data = 0 and Max_Data = 255
338 */
LL_CRS_GetFreqErrorLimit(void)339 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
340 {
341 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
342 }
343
344 /**
345 * @brief Set division factor for SYNC signal
346 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
347 * @param Divider This parameter can be one of the following values:
348 * @arg @ref LL_CRS_SYNC_DIV_1
349 * @arg @ref LL_CRS_SYNC_DIV_2
350 * @arg @ref LL_CRS_SYNC_DIV_4
351 * @arg @ref LL_CRS_SYNC_DIV_8
352 * @arg @ref LL_CRS_SYNC_DIV_16
353 * @arg @ref LL_CRS_SYNC_DIV_32
354 * @arg @ref LL_CRS_SYNC_DIV_64
355 * @arg @ref LL_CRS_SYNC_DIV_128
356 * @retval None
357 */
LL_CRS_SetSyncDivider(uint32_t Divider)358 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
359 {
360 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
361 }
362
363 /**
364 * @brief Get division factor for SYNC signal
365 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
366 * @retval Returned value can be one of the following values:
367 * @arg @ref LL_CRS_SYNC_DIV_1
368 * @arg @ref LL_CRS_SYNC_DIV_2
369 * @arg @ref LL_CRS_SYNC_DIV_4
370 * @arg @ref LL_CRS_SYNC_DIV_8
371 * @arg @ref LL_CRS_SYNC_DIV_16
372 * @arg @ref LL_CRS_SYNC_DIV_32
373 * @arg @ref LL_CRS_SYNC_DIV_64
374 * @arg @ref LL_CRS_SYNC_DIV_128
375 */
LL_CRS_GetSyncDivider(void)376 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
377 {
378 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
379 }
380
381 /**
382 * @brief Set SYNC signal source
383 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
384 * @param Source This parameter can be one of the following values:
385 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
386 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
387 * @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS
388 * @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS
389 * @retval None
390 */
LL_CRS_SetSyncSignalSource(uint32_t Source)391 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
392 {
393 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
394 }
395
396 /**
397 * @brief Get SYNC signal source
398 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
399 * @retval Returned value can be one of the following values:
400 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
401 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
402 * @arg @ref LL_CRS_SYNC_SOURCE_OTG_FS
403 * @arg @ref LL_CRS_SYNC_SOURCE_OTG_HS
404 */
LL_CRS_GetSyncSignalSource(void)405 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
406 {
407 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
408 }
409
410 /**
411 * @brief Set input polarity for the SYNC signal source
412 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
413 * @param Polarity This parameter can be one of the following values:
414 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
415 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
416 * @retval None
417 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)418 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
419 {
420 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
421 }
422
423 /**
424 * @brief Get input polarity for the SYNC signal source
425 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
426 * @retval Returned value can be one of the following values:
427 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
428 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
429 */
LL_CRS_GetSyncPolarity(void)430 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
431 {
432 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
433 }
434
435 /**
436 * @brief Configure CRS for the synchronization
437 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
438 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
439 * CFGR FELIM LL_CRS_ConfigSynchronization\n
440 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
441 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
442 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
443 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
444 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 255
445 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 65535 (0xFFFF)
446 * @param Settings This parameter can be a combination of the following values:
447 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4
448 * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32
449 * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
450 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE
451 * or @ref LL_CRS_SYNC_SOURCE_OTG_FS or @ref LL_CRS_SYNC_SOURCE_OTG_HS
452 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
453 * @retval None
454 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)455 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
456 uint32_t ReloadValue, uint32_t Settings)
457 {
458 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
459 MODIFY_REG(CRS->CFGR,
460 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
461 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
462 }
463
464 /**
465 * @}
466 */
467
468 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
469 * @{
470 */
471
472 /**
473 * @brief Generate software SYNC event
474 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
475 * @retval None
476 */
LL_CRS_GenerateEvent_SWSYNC(void)477 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
478 {
479 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
480 }
481
482 /**
483 * @brief Get the frequency error direction latched in the time of the last
484 * SYNC event
485 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
486 * @retval Returned value can be one of the following values:
487 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
488 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
489 */
LL_CRS_GetFreqErrorDirection(void)490 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
491 {
492 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
493 }
494
495 /**
496 * @brief Get the frequency error counter value latched in the time of the last SYNC event
497 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
498 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
499 */
LL_CRS_GetFreqErrorCapture(void)500 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
501 {
502 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
503 }
504
505 /**
506 * @}
507 */
508
509 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
510 * @{
511 */
512
513 /**
514 * @brief Check if SYNC event OK signal occurred or not
515 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
516 * @retval State of bit (1 or 0).
517 */
LL_CRS_IsActiveFlag_SYNCOK(void)518 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
519 {
520 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
521 }
522
523 /**
524 * @brief Check if SYNC warning signal occurred or not
525 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
526 * @retval State of bit (1 or 0).
527 */
LL_CRS_IsActiveFlag_SYNCWARN(void)528 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
529 {
530 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
531 }
532
533 /**
534 * @brief Check if Synchronization or trimming error signal occurred or not
535 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
536 * @retval State of bit (1 or 0).
537 */
LL_CRS_IsActiveFlag_ERR(void)538 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
539 {
540 return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
541 }
542
543 /**
544 * @brief Check if Expected SYNC signal occurred or not
545 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
546 * @retval State of bit (1 or 0).
547 */
LL_CRS_IsActiveFlag_ESYNC(void)548 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
549 {
550 return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
551 }
552
553 /**
554 * @brief Check if SYNC error signal occurred or not
555 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
556 * @retval State of bit (1 or 0).
557 */
LL_CRS_IsActiveFlag_SYNCERR(void)558 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
559 {
560 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Check if SYNC missed error signal occurred or not
565 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
566 * @retval State of bit (1 or 0).
567 */
LL_CRS_IsActiveFlag_SYNCMISS(void)568 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
569 {
570 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
571 }
572
573 /**
574 * @brief Check if Trimming overflow or underflow occurred or not
575 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
576 * @retval State of bit (1 or 0).
577 */
LL_CRS_IsActiveFlag_TRIMOVF(void)578 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
579 {
580 return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Clear the SYNC event OK flag
585 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
586 * @retval None
587 */
LL_CRS_ClearFlag_SYNCOK(void)588 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
589 {
590 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
591 }
592
593 /**
594 * @brief Clear the SYNC warning flag
595 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
596 * @retval None
597 */
LL_CRS_ClearFlag_SYNCWARN(void)598 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
599 {
600 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
601 }
602
603 /**
604 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
605 * the ERR flag
606 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
607 * @retval None
608 */
LL_CRS_ClearFlag_ERR(void)609 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
610 {
611 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
612 }
613
614 /**
615 * @brief Clear Expected SYNC flag
616 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
617 * @retval None
618 */
LL_CRS_ClearFlag_ESYNC(void)619 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
620 {
621 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
622 }
623
624 /**
625 * @}
626 */
627
628 /** @defgroup CRS_LL_EF_IT_Management IT_Management
629 * @{
630 */
631
632 /**
633 * @brief Enable SYNC event OK interrupt
634 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
635 * @retval None
636 */
LL_CRS_EnableIT_SYNCOK(void)637 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
638 {
639 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
640 }
641
642 /**
643 * @brief Disable SYNC event OK interrupt
644 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
645 * @retval None
646 */
LL_CRS_DisableIT_SYNCOK(void)647 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
648 {
649 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
650 }
651
652 /**
653 * @brief Check if SYNC event OK interrupt is enabled or not
654 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
655 * @retval State of bit (1 or 0).
656 */
LL_CRS_IsEnabledIT_SYNCOK(void)657 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
658 {
659 return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
660 }
661
662 /**
663 * @brief Enable SYNC warning interrupt
664 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
665 * @retval None
666 */
LL_CRS_EnableIT_SYNCWARN(void)667 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
668 {
669 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
670 }
671
672 /**
673 * @brief Disable SYNC warning interrupt
674 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
675 * @retval None
676 */
LL_CRS_DisableIT_SYNCWARN(void)677 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
678 {
679 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
680 }
681
682 /**
683 * @brief Check if SYNC warning interrupt is enabled or not
684 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
685 * @retval State of bit (1 or 0).
686 */
LL_CRS_IsEnabledIT_SYNCWARN(void)687 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
688 {
689 return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
690 }
691
692 /**
693 * @brief Enable Synchronization or trimming error interrupt
694 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
695 * @retval None
696 */
LL_CRS_EnableIT_ERR(void)697 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
698 {
699 SET_BIT(CRS->CR, CRS_CR_ERRIE);
700 }
701
702 /**
703 * @brief Disable Synchronization or trimming error interrupt
704 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
705 * @retval None
706 */
LL_CRS_DisableIT_ERR(void)707 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
708 {
709 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
710 }
711
712 /**
713 * @brief Check if Synchronization or trimming error interrupt is enabled or not
714 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
715 * @retval State of bit (1 or 0).
716 */
LL_CRS_IsEnabledIT_ERR(void)717 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
718 {
719 return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
720 }
721
722 /**
723 * @brief Enable Expected SYNC interrupt
724 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
725 * @retval None
726 */
LL_CRS_EnableIT_ESYNC(void)727 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
728 {
729 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
730 }
731
732 /**
733 * @brief Disable Expected SYNC interrupt
734 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
735 * @retval None
736 */
LL_CRS_DisableIT_ESYNC(void)737 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
738 {
739 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
740 }
741
742 /**
743 * @brief Check if Expected SYNC interrupt is enabled or not
744 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
745 * @retval State of bit (1 or 0).
746 */
LL_CRS_IsEnabledIT_ESYNC(void)747 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
748 {
749 return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
750 }
751
752 /**
753 * @}
754 */
755
756 #if defined(USE_FULL_LL_DRIVER)
757 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
758 * @{
759 */
760
761 ErrorStatus LL_CRS_DeInit(void);
762
763 /**
764 * @}
765 */
766 #endif /* USE_FULL_LL_DRIVER */
767
768 /**
769 * @}
770 */
771
772 /**
773 * @}
774 */
775
776 #endif /* defined(CRS) */
777
778 /**
779 * @}
780 */
781
782 #ifdef __cplusplus
783 }
784 #endif
785
786 #endif /* STM32H7RSxx_LL_CRS_H */
787
