1 /** 2 ****************************************************************************** 3 * @file stm32h7rsxx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7RSxx_HAL_ADC_H 21 #define STM32H7RSxx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32h7rsxx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32h7rsxx_ll_adc.h" 32 33 /** @addtogroup STM32H7RSxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this 64 parameter is discarded and forced to setting 65 "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed 66 during injection sequence). 67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 68 69 } ADC_OversamplingTypeDef; 70 71 /** 72 * @brief Structure definition of ADC instance and ADC group regular. 73 * @note Parameters of this structure are shared within 2 scopes: 74 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 75 * ScanConvMode, EOCSelection, LowPowerAutoWait. 76 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 77 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, 78 * SamplingMode. 79 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 80 * ADC state can be either: 81 * - For all parameters: ADC disabled 82 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled 83 * without conversion on going on group regular. 84 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going 85 * on groups regular and injected. 86 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 87 * without error reporting (as it can be the expected behavior in case of intended action to update another 88 * parameter (which fulfills the ADC state condition) on the fly). 89 */ 90 typedef struct 91 { 92 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous 93 clock derived from system clock or PLL (Refer to reference manual for list of 94 clocks available)) and clock prescaler. 95 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 96 Note: The ADC clock configuration is common to all ADC instances. 97 Note: In case of usage of channels on injected group, ADC frequency should be 98 lower than AHB clock frequency /4 for resolution 12 or 10 bits, 99 AHB clock frequency /3 for resolution 8 bits, 100 AHB clock frequency /2 for resolution 6 bits. 101 Note: In case of synchronous clock mode based on HCLK/1, the configuration must 102 be enabled only if the system clock has a 50% duty clock cycle (APB 103 prescaler configured inside RCC must be bypassed and PCLK clock must have 104 50% duty cycle). Refer to reference manual for details. 105 Note: In case of usage of asynchronous clock, the selected clock must be 106 preliminarily enabled at RCC top level. 107 Note: This parameter can be modified only if all ADC instances are disabled. */ 108 109 uint32_t Resolution; /*!< Configure the ADC resolution. 110 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 111 112 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 113 Refer to reference manual for alignments formats versus resolutions. 114 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 115 116 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 117 This parameter can be associated to parameter 'DiscontinuousConvMode' to have 118 main sequence subdivided in successive parts. 119 If disabled: Conversion is performed in single mode (one channel converted, the 120 one defined in rank 1). Parameters 'NbrOfConversion' and 121 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 122 If enabled: Conversions are performed in sequence mode (multiple ranks defined 123 by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each 124 channel in sequencer). Scan direction is upward: from rank 1 to 125 rank 'n'. 126 This parameter can be a value of @ref ADC_Scan_mode */ 127 128 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and 129 interruption: end of unitary conversion or end of sequence conversions. 130 This parameter can be a value of @ref ADC_EOCSelection. */ 131 132 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the 133 previous conversion (for ADC group regular) or previous sequence (for ADC group 134 injected) has been retrieved by user software, using function HAL_ADC_GetValue() 135 or HAL_ADCEx_InjectedGetValue(). 136 This feature automatically adapts the frequency of ADC conversions triggers to 137 the speed of the system that reads the data. Moreover, this avoids risk of 138 overrun for low frequency applications. 139 This parameter can be set to ENABLE or DISABLE. 140 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), 141 HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC 142 flag (by CPU to free the IRQ pending event or by DMA). 143 Auto wait will work but fort a very short time, discarding its intended 144 benefit (except specific case of high load of CPU or DMA transfers which 145 can justify usage of auto wait). 146 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, 147 when ADC conversion data is needed: 148 use HAL_ADC_PollForConversion() to ensure that conversion is completed and 149 HAL_ADC_GetValue() to retrieve conversion result and trig another 150 conversion start. (in case of usage of ADC group injected, use the 151 equivalent functions HAL_ADCExInjected_Start(), 152 HAL_ADCEx_InjectedGetValue(), ...). */ 153 154 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) 155 or continuous mode for ADC group regular, after the first ADC conversion 156 start trigger occurred (software start or external trigger). This parameter 157 can be set to ENABLE or DISABLE. */ 158 159 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group 160 sequencer. 161 This parameter is dependent on ScanConvMode: 162 - sequencer configured to fully configurable: 163 Number of ranks in the scan sequence is configurable using this parameter. 164 Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to 165 parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. 166 Afterwards, when all needed sequencer ranks are set, parameter 167 'NbrOfConversion' can be updated without modifying configuration of 168 sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). 169 - sequencer configured to not fully configurable: 170 Number of ranks in the scan sequence is defined by number of channels set in 171 the sequence. This parameter is discarded. 172 This parameter must be a number between Min_Data = 1 and Max_Data = 8. 173 Note: This parameter must be modified when no conversion is on going on regular 174 group (ADC disabled, or ADC enabled without continuous mode or external 175 trigger that could launch a conversion). */ 176 177 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed 178 in Complete-sequence/Discontinuous-sequence (main sequence subdivided in 179 successive parts). 180 Discontinuous mode is used only if sequencer is enabled (parameter 181 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 182 Discontinuous mode can be enabled only if continuous mode is disabled. 183 If continuous mode is enabled, this parameter setting is discarded. 184 This parameter can be set to ENABLE or DISABLE. 185 Note: On this STM32 series, ADC group regular number of discontinuous 186 ranks increment is fixed to one-by-one. */ 187 188 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence 189 of ADC group regular (parameter NbrOfConversion) will be subdivided. 190 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 191 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 192 193 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion 194 start. 195 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger 196 is used instead. 197 This parameter can be a value of @ref ADC_regular_external_trigger_source. 198 Caution: external trigger source is common to all ADC instances. */ 199 200 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start 201 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 202 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 203 204 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 205 This parameter can be a value of @ref ADC_regular_sampling_mode */ 206 207 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (one shot 208 or circular), or stored in the DR register or transferred to ADF register. 209 Note: In continuous mode, DMA must be configured in circular mode. Otherwise 210 an overrun will be triggered when DMA buffer maximum pointer is reached. 211 This parameter can be a value of @ref ADC_ConversionDataManagement. 212 Note: This parameter must be modified when no conversion is on going on both 213 regular and injected groups (ADC disabled, or ADC enabled without continuous mode 214 or external trigger that could launch a conversion). */ 215 216 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 217 This parameter applies to ADC group regular only. 218 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 219 Note: In case of overrun set to data preserved and usage with programming model 220 with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of 221 conversion flags, this induces the release of the preserved data. If 222 needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), 223 placed in user program code (called before end of conversion flags clear) 224 Note: Error reporting with respect to the conversion mode: 225 - Usage with ADC conversion by polling for event or interruption: Error is 226 reported only if overrun is set to data preserved. If overrun is set to 227 data overwritten, user can willingly not read all the converted data, 228 this is not considered as an erroneous case. 229 - Usage with ADC conversion by DMA: Error is reported whatever overrun 230 setting (DMA is expected to process all data from data register). */ 231 232 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 233 This parameter can be set to ENABLE or DISABLE. 234 Note: This parameter can be modified only if there is no conversion is 235 ongoing on ADC groups regular and injected */ 236 237 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 238 Caution: this setting overwrites the previous oversampling configuration 239 if oversampling is already enabled. */ 240 241 } ADC_InitTypeDef; 242 243 /** 244 * @brief Structure definition of ADC channel for regular group 245 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 246 * ADC state can be either: 247 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 248 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion 249 * on going on regular group. 250 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on 251 * regular and injected groups. 252 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 253 * without error reporting (as it can be the expected behavior in case of intended action to update another 254 * parameter (which fulfills the ADC state condition) on the fly). 255 */ 256 typedef struct 257 { 258 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 259 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 260 Note: Depending on devices and ADC instances, some channels may not be available 261 on device package pins. Refer to device datasheet for channels 262 availability. */ 263 264 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 265 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 266 Note: to disable a channel or change order of conversion sequencer, rank 267 containing a previous channel setting can be overwritten by the new channel 268 setting (or parameter number of conversions adjusted) */ 269 270 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 271 Unit: ADC clock cycles 272 Conversion time is the addition of sampling time and processing time 273 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 274 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 275 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 276 Caution: This parameter applies to a channel that can be used into regular 277 and/or injected group. It overwrites the last setting. 278 Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), 279 sampling time constraints must be respected (sampling time can be adjusted 280 in function of ADC clock frequency and sampling time setting). 281 Refer to device datasheet for timings values. */ 282 283 uint32_t SingleDiff; /*!< Select single-ended or differential input. 284 In differential mode: Differential measurement is carried out between the 285 selected channel 'i' (positive input) and channel 'i+1' (negative input). 286 Only channel 'i' has to be configured, channel 'i+1' is configured automatically 287 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 288 Caution: This parameter applies to a channel that can be used in a regular 289 and/or injected group. 290 It overwrites the last setting. 291 Note: Refer to Reference Manual to ensure the selected channel is available in 292 differential mode. 293 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is 294 not usable separately. 295 Note: This parameter must be modified when ADC is disabled (before ADC start 296 conversion or after ADC stop conversion). 297 If ADC is enabled, this parameter setting is bypassed without error 298 reporting (as it can be the expected behavior in case of another parameter 299 update on the fly) */ 300 301 uint32_t OffsetNumber; /*!< Select the offset number 302 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 303 Caution: Only one offset is allowed per channel. This parameter overwrites the 304 last setting. */ 305 306 uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. 307 Offset value must be a positive number. 308 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter 309 must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 310 0x3FF, 0xFF or 0x3F respectively. 311 Note: This parameter must be modified when no conversion is on going on both 312 regular and injected groups (ADC disabled, or ADC enabled without 313 continuous mode or external trigger that could launch a conversion). */ 314 315 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive 316 sign) from or to the raw converted data. 317 This parameter can be a value of @ref ADCEx_OffsetSign. 318 Note: This parameter must be modified when no conversion is on going on both 319 regular and injected groups (ADC disabled, or ADC enabled without 320 continuous mode or external trigger that could launch a conversion).*/ 321 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 322 This parameter value can be ENABLE or DISABLE. 323 Note: This parameter must be modified when no conversion is on going on both 324 regular and injected groups (ADC disabled, or ADC enabled without 325 continuous mode or external trigger that could launch a conversion). */ 326 327 } ADC_ChannelConfTypeDef; 328 329 /** 330 * @brief Structure definition of ADC analog watchdog 331 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 332 * ADC state can be either: 333 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion 334 on going on ADC groups regular and injected. 335 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and 336 injected groups. 337 */ 338 typedef struct 339 { 340 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 341 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels 342 by setting parameter 'WatchdogMode') 343 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls 344 of 'HAL_ADC_AnalogWDGConfig()' for each channel) 345 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 346 347 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 348 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all 349 channels, ADC groups regular and-or injected. 350 For Analog Watchdog 2 and 3: Several channels can be monitored by applying 351 successively the AWD init structure. Channels on ADC 352 group regular and injected are not differentiated: Set 353 value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 354 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor 355 all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no 356 channel. 357 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 358 359 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 360 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' 361 is configured on single channel (only 1 channel can be 362 monitored). 363 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, 364 call successively the function HAL_ADC_AnalogWDGConfig() 365 for each channel to be added (or removed with value 366 'ADC_ANALOGWATCHDOG_NONE'). 367 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 368 369 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 370 This parameter can be set to ENABLE or DISABLE */ 371 372 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 373 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 374 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 375 respectively. 376 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 377 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 378 LSB are ignored. 379 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 380 impacted: the comparison of analog watchdog thresholds is done on 381 oversampling final computation (after ratio and shift application): 382 ADC data register bitfield [15:4] (12 most significant bits). */ 383 384 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 385 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a 386 number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F 387 respectively. 388 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC 389 resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 390 LSB are ignored. 391 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 392 impacted: the comparison of analog watchdog thresholds is done on 393 oversampling final computation (after ratio and shift application): 394 ADC data register bitfield [15:4] (12 most significant bits).*/ 395 396 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 397 Before setting flag or raising interrupt, analog watchdog can wait to have several 398 consecutive out-of-window samples. This parameter allows to configure this number. 399 This parameter only applies to Analog watchdog 1. For others, use value 400 ADC_AWD_FILTERING_NONE. 401 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ 402 } ADC_AnalogWDGConfTypeDef; 403 404 /** 405 * @brief ADC group injected contexts queue configuration 406 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 407 */ 408 typedef struct 409 { 410 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 411 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 412 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 413 414 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 415 } ADC_InjectionConfigTypeDef; 416 417 /** @defgroup ADC_States ADC States 418 * @{ 419 */ 420 421 /** 422 * @brief HAL ADC state machine: ADC states definition (bitfields) 423 * @note ADC state machine is managed by bitfields, state must be compared 424 * with bit by bit. 425 * For example: 426 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 427 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 428 */ 429 /* States of ADC global scope */ 430 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 431 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 432 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, 433 calibration, ...) */ 434 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 435 436 /* States of ADC errors */ 437 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 438 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 439 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 440 441 /* States of ADC group regular */ 442 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur 443 (either by continuous mode, external trigger, low power 444 auto power-on (if feature available), multimode ADC master 445 control (if feature available)) */ 446 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 447 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 448 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag 449 raised */ 450 451 /* States of ADC group injected */ 452 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur 453 (either by auto-injection mode, external trigger, low 454 power auto power-on (if feature available), multimode 455 ADC master control (if feature available)) */ 456 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 457 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 458 459 /* States of ADC analog watchdogs */ 460 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 461 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 462 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 463 464 /* States of ADC multi-mode */ 465 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC 466 master (when feature available) */ 467 468 /** 469 * @} 470 */ 471 472 /** 473 * @brief ADC handle Structure definition 474 */ 475 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 476 typedef struct __ADC_HandleTypeDef 477 #else 478 typedef struct 479 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 480 { 481 ADC_TypeDef *Instance; /*!< Register base address */ 482 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular 483 conversions setting */ 484 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 485 HAL_LockTypeDef Lock; /*!< ADC locking object */ 486 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 487 __IO uint32_t ErrorCode; /*!< ADC Error code */ 488 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up 489 structure */ 490 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 491 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 492 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer 493 callback */ 494 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 495 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 496 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete 497 callback */ 498 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue 499 overflow callback */ 500 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 501 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 502 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 503 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 504 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 505 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 506 } ADC_HandleTypeDef; 507 508 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 509 /** 510 * @brief HAL ADC Callback ID enumeration definition 511 */ 512 typedef enum 513 { 514 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 515 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 516 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 517 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 518 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 519 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 520 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 521 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 522 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 523 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 524 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 525 } HAL_ADC_CallbackIDTypeDef; 526 527 /** 528 * @brief HAL ADC Callback pointer definition 529 */ 530 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 531 532 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 533 534 /** 535 * @} 536 */ 537 538 539 /* Exported constants --------------------------------------------------------*/ 540 541 /** @defgroup ADC_Exported_Constants ADC Exported Constants 542 * @{ 543 */ 544 545 /** @defgroup ADC_Error_Code ADC Error Code 546 * @{ 547 */ 548 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 549 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 550 enable/disable, erroneous state, ...) */ 551 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 552 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 553 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 554 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 555 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 556 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 557 /** 558 * @} 559 */ 560 561 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 562 * @{ 563 */ 564 565 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock 566 without prescaler */ 567 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock 568 with prescaler division by 2 */ 569 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock 570 with prescaler division by 4 */ 571 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without 572 prescaler */ 573 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler 574 division by 2 */ 575 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler 576 division by 4 */ 577 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler 578 division by 6 */ 579 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler 580 division by 8 */ 581 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler 582 division by 10 */ 583 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler 584 division by 12 */ 585 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler 586 division by 16 */ 587 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler 588 division by 32 */ 589 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler 590 division by 64 */ 591 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler 592 division by 128 */ 593 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler 594 division by 256 */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 600 * @{ 601 */ 602 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 603 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 604 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 605 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 606 /** 607 * @} 608 */ 609 610 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 611 * @{ 612 */ 613 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned 614 (alignment on data register LSB bit 0)*/ 615 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned 616 (alignment on data register MSB bit 15)*/ 617 /** 618 * @} 619 */ 620 621 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 622 * @{ 623 */ 624 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 625 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 626 /** 627 * @} 628 */ 629 630 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 631 * @{ 632 */ 633 /* ADC group regular trigger sources for all ADC instances */ 634 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion 635 trigger software start */ 636 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion 637 trigger from external peripheral: TIM1 channel 1 event (capture compare). */ 638 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion 639 trigger from external peripheral: TIM1 channel 2 event (capture compare). */ 640 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion 641 trigger from external peripheral: TIM1 channel 3 event (capture compare). */ 642 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion 643 trigger from external peripheral: TIM2 channel 2 event (capture compare). */ 644 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion 645 trigger from external peripheral: TIM3 TRGO event. */ 646 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion 647 trigger from external peripheral: TIM4 channel 4 event (capture compare). */ 648 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion 649 trigger from external peripheral: external interrupt line 11 event. */ 650 #define ADC_EXTERNALTRIG_T12_TRGO (LL_ADC_REG_TRIG_EXT_TIM12_TRGO) /*!< ADC group regular conversion 651 trigger from external peripheral: TIM12 TRGO event. */ 652 #define ADC_EXTERNALTRIG_T9_TRGO (LL_ADC_REG_TRIG_EXT_TIM9_TRGO) /*!< ADC group regular conversion 653 trigger from external peripheral: TIM9 TRGO event. */ 654 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion 655 trigger from external peripheral: TIM1 TRGO event. */ 656 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion 657 trigger from external peripheral: TIM1 TRGO2 event. */ 658 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion 659 trigger from external peripheral: TIM2 TRGO event. */ 660 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion 661 trigger from external peripheral: TIM4 TRGO event. */ 662 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion 663 trigger from external peripheral: TIM6 TRGO event. */ 664 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion 665 trigger from external peripheral: TIM15 TRGO event. */ 666 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion 667 trigger from external peripheral: TIM3 channel 4 event (capture compare). */ 668 #define ADC_EXTERNALTRIG_LPTIM1_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion 669 trigger from external peripheral: LPTIM1 channel 1 event (capture compare). */ 670 #define ADC_EXTERNALTRIG_LPTIM2_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM2_CH1) /*!< ADC group regular conversion 671 trigger from external peripheral: LPTIM2 channel 1 event (capture compare). */ 672 #define ADC_EXTERNALTRIG_LPTIM3_CH1 (LL_ADC_REG_TRIG_EXT_LPTIM3_CH1) /*!< ADC group regular conversion 673 trigger from external peripheral: LPTIM3 channel 1 event (capture compare). */ 674 /** 675 * @} 676 */ 677 678 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 679 * @{ 680 */ 681 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger 682 disabled (SW start)*/ 683 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion 684 trigger polarity set to rising edge */ 685 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion 686 trigger polarity set to falling edge */ 687 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion 688 trigger polarity set to both rising and falling edges */ 689 /** 690 * @} 691 */ 692 693 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 694 * @{ 695 */ 696 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is 697 defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 698 #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts 699 immediately after end of conversion, and stops upon trigger event. 700 Note: First conversion is using minimal sampling time 701 (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */ 702 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled 703 by trigger events: 704 Trigger rising edge = start sampling 705 Trigger falling edge = stop sampling and start conversion */ 706 /** 707 * @} 708 */ 709 710 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 711 * @{ 712 */ 713 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 714 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 715 /** 716 * @} 717 */ 718 719 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 720 * @{ 721 */ 722 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case 723 of overrun: data preserved */ 724 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case 725 of overrun: data overwritten */ 726 /** 727 * @} 728 */ 729 730 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 731 * @{ 732 */ 733 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 734 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 735 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 736 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 737 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 738 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 739 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 740 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 741 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 742 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 743 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 744 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 745 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 746 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 747 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 748 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 749 /** 750 * @} 751 */ 752 753 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 754 * @{ 755 */ 756 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 757 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 758 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 759 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 760 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 761 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 762 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 763 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 764 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 765 ADC clock cycles. If selected, this sampling time replaces sampling time 766 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 767 /** 768 * @} 769 */ 770 771 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 772 * @{ 773 */ 774 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 775 /* all ADC instances (refer to Reference Manual). */ 776 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ 777 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ 778 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ 779 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ 780 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ 781 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ 782 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ 783 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ 784 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ 785 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ 786 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ 787 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ 788 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ 789 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ 790 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ 791 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ 792 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ 793 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ 794 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ 795 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal 796 voltage reference, channel specific to ADC1. */ 797 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor, 798 channel specific to ADC1. */ 799 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/4: Vbat voltage 800 through a divider ladder of factor 1/4 to have channel voltage always below 801 Vdda, channel specific to ADC2. */ 802 #define ADC_CHANNEL_VDDCORE (LL_ADC_CHANNEL_VDDCORE) /*!< Internal channel Vddcore, channel 803 specific to ADC2. */ 804 /** 805 * @} 806 */ 807 808 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 809 * @{ 810 */ 811 #define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register 812 only */ 813 #define ADC_CONVERSIONDATA_DMA_ONESHOT (0x00000000UL) /*!< DMA one shot mode selected. 814 Note: DMA access is enabled in function HAL_ADC_Start_DMA. */ 815 #define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMACFG) /*!< DMA circular mode selected. 816 Note: DMA access is enabled in function HAL_ADC_Start_DMA. */ 817 #define ADC_CONVERSIONDATA_MDF (ADC_CFGR_ADFCFG) /*!< MDF (ADF) mode selected */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number 823 * @{ 824 */ 825 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 826 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 827 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 828 /** 829 * @} 830 */ 831 832 /** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration 833 * @{ 834 */ 835 #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one 836 out-of-window sample to raise flag or interrupt */ 837 #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives 838 out-of-window samples to raise flag or interrupt */ 839 #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives 840 out-of-window samples to raise flag or interrupt */ 841 #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives 842 out-of-window samples to raise flag or interrupt */ 843 #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives 844 out-of-window samples to raise flag or interrupt */ 845 #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives 846 out-of-window samples to raise flag or interrupt */ 847 #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives 848 out-of-window samples to raise flag or interrupt */ 849 #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \ 850 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives 851 out-of-window samples to raise flag or interrupt */ 852 /** 853 * @} 854 */ 855 856 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode 857 * @{ 858 */ 859 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ 860 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< ADC AWD applied to a regular 861 group single channel */ 862 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to an 863 injected group single channel */ 864 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\ 865 | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to a regular 866 and injected groups single channel */ 867 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< ADC AWD applied to regular 868 group all channels */ 869 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to injected 870 group all channels */ 871 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< ADC AWD applied to regular 872 and injected groups all channels */ 873 /** 874 * @} 875 */ 876 877 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 878 * @{ 879 */ 880 /** 881 * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed 882 * to result as the ADC oversampling conversion data (before potential shift) 883 */ 884 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ 885 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ 886 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ 887 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ 888 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ 889 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ 890 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ 891 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ 892 /** 893 * @} 894 */ 895 896 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 897 * @{ 898 */ 899 /** 900 * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling 901 * conversion data) 902 */ 903 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ 904 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ 905 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ 906 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ 907 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ 908 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ 909 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ 910 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ 911 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ 912 /** 913 * @} 914 */ 915 916 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 917 * @{ 918 */ 919 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: 920 continuous mode (all conversions of OVS ratio are done from 1 trigger) */ 921 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: 922 discontinuous mode (each conversion of OVS ratio needs a trigger) */ 923 /** 924 * @} 925 */ 926 927 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 928 * @{ 929 */ 930 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained 931 during injection sequence */ 932 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during 933 injection sequence */ 934 /** 935 * @} 936 */ 937 938 /** @defgroup ADC_Event_type ADC Event type 939 * @{ 940 */ 941 /** 942 * @note Analog watchdog 1 is available on all stm32 series 943 * Analog watchdog 2 and 3 are not available on all series 944 */ 945 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 946 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 947 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 948 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 949 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 950 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 951 /** 952 * @} 953 */ 954 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility 955 with other STM32 devices having only one analog watchdog */ 956 957 /** @defgroup ADC_interrupts_definition ADC interrupts definition 958 * @{ 959 */ 960 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 961 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 962 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 963 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 964 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 965 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 966 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 967 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 968 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog 969 watchdog) */ 970 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog 971 watchdog) */ 972 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 973 974 /** 975 * @} 976 */ 977 978 /** @defgroup ADC_flags_definition ADC flags definition 979 * @{ 980 */ 981 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 982 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 983 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 984 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 985 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 986 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 987 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 988 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 989 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 990 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 991 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 992 993 /** 994 * @} 995 */ 996 997 /** 998 * @} 999 */ 1000 1001 /* Private macro -------------------------------------------------------------*/ 1002 1003 /** @defgroup ADC_Private_Macros ADC Private Macros 1004 * @{ 1005 */ 1006 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 1007 /* code of final user. */ 1008 1009 /** 1010 * @brief Verify the ADC data conversion setting. 1011 * @param DATA : programmed DATA conversion mode. 1012 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 1013 */ 1014 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 1015 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 1016 (((DATA) == ADC_CONVERSIONDATA_MDF)) || \ 1017 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 1018 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 1019 1020 /** 1021 * @brief Return resolution bits in CFGR register RES[1:0] field. 1022 * @param __HANDLE__ ADC handle 1023 * @retval Value of bitfield RES in CFGR register. 1024 */ 1025 #define ADC_GET_RESOLUTION(__HANDLE__) \ 1026 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 1027 1028 /** 1029 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 1030 * @param __HANDLE__ ADC handle 1031 * @retval None 1032 */ 1033 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 1034 1035 /** 1036 * @brief Simultaneously clear and set specific bits of the handle State. 1037 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 1038 * the first parameter is the ADC handle State, the second parameter is the 1039 * bit field to clear, the third and last parameter is the bit field to set. 1040 * @retval None 1041 */ 1042 #define ADC_STATE_CLR_SET MODIFY_REG 1043 1044 /** 1045 * @brief Verify that a given value is aligned with the ADC resolution range. 1046 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1047 * @param __ADC_VALUE__ value checked against the resolution. 1048 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1049 */ 1050 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1051 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1052 1053 /** 1054 * @brief Verify the length of the scheduled regular conversions group. 1055 * @param __LENGTH__ number of programmed conversions. 1056 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) 1057 * or RESET (__LENGTH__ is null or too large) 1058 */ 1059 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 1060 1061 1062 /** 1063 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 1064 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 1065 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) 1066 * or RESET (NUMBER is null or too large) 1067 */ 1068 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 1069 1070 1071 /** 1072 * @brief Verify the ADC clock setting. 1073 * @param __ADC_CLOCK__ programmed ADC clock. 1074 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 1075 */ 1076 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 1077 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 1078 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 1079 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 1080 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 1081 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 1082 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 1083 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 1084 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 1085 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 1086 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 1087 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 1088 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 1089 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 1090 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 1091 1092 /** 1093 * @brief Verify the ADC resolution setting. 1094 * @param __RESOLUTION__ programmed ADC resolution. 1095 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1096 */ 1097 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1098 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1099 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1100 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1101 1102 /** 1103 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 1104 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 1105 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1106 */ 1107 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1108 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1109 1110 /** 1111 * @brief Verify the ADC converted data alignment. 1112 * @param __ALIGN__ programmed ADC converted data alignment. 1113 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 1114 */ 1115 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 1116 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 1117 1118 /** 1119 * @brief Verify the ADC scan mode. 1120 * @param __SCAN_MODE__ programmed ADC scan mode. 1121 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1122 */ 1123 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1124 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1125 1126 /** 1127 * @brief Verify the ADC edge trigger setting for regular group. 1128 * @param __EDGE__ programmed ADC edge trigger setting. 1129 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1130 */ 1131 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1132 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1133 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1134 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1135 1136 /** 1137 * @brief Verify the ADC regular conversions external trigger. 1138 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1139 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1140 */ 1141 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1142 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1143 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1144 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1145 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1146 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1147 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1148 ((__REGTRIG__) == ADC_EXTERNALTRIG_T12_TRGO) || \ 1149 ((__REGTRIG__) == ADC_EXTERNALTRIG_T9_TRGO) || \ 1150 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1151 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1152 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1153 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1154 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1155 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1156 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1157 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_CH1) || \ 1158 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_CH1) || \ 1159 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_CH1) || \ 1160 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1161 1162 /** 1163 * @brief Verify the ADC regular conversions external trigger. 1164 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 1165 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 1166 */ 1167 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 1168 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 1169 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 1170 1171 /** 1172 * @brief Verify the ADC regular conversions check for converted data availability. 1173 * @param __EOC_SELECTION__ converted data availability check. 1174 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1175 */ 1176 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1177 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1178 1179 /** 1180 * @brief Verify the ADC regular conversions overrun handling. 1181 * @param __OVR__ ADC regular conversions overrun handling. 1182 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1183 */ 1184 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1185 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1186 1187 /** 1188 * @brief Verify the ADC conversions sampling time. 1189 * @param __TIME__ ADC conversions sampling time. 1190 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1191 */ 1192 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1193 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 1194 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 1195 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 1196 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 1197 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 1198 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 1199 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 1200 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 1201 1202 /** 1203 * @brief Verify the ADC regular channel setting. 1204 * @param __CHANNEL__ programmed ADC regular channel. 1205 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1206 */ 1207 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1208 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1209 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1210 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1211 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1212 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1213 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1214 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1215 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1216 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1217 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1218 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1219 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1220 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1221 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1222 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1223 1224 /** 1225 * @} 1226 */ 1227 1228 1229 /* Private constants ---------------------------------------------------------*/ 1230 1231 /** @defgroup ADC_Private_Constants ADC Private Constants 1232 * @{ 1233 */ 1234 1235 /* Fixed timeout values for ADC conversion (including sampling time) */ 1236 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1237 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1238 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1239 /* Minimum ADC Clock frequency is 0.14 MHz */ 1240 /* Maximum conversion time is */ 1241 /* 653 / 0.14 MHz = 4.66 ms */ 1242 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1243 1244 /* Delay for temperature sensor stabilization time. */ 1245 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1246 /* Unit: us */ 1247 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1248 1249 /** 1250 * @} 1251 */ 1252 1253 /* Exported macro ------------------------------------------------------------*/ 1254 1255 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1256 * @{ 1257 */ 1258 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1259 /* final user. */ 1260 1261 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1262 * @{ 1263 */ 1264 1265 /** @brief Reset ADC handle state. 1266 * @param __HANDLE__ ADC handle 1267 * @retval None 1268 */ 1269 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1270 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1271 do{ \ 1272 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1273 (__HANDLE__)->MspInitCallback = NULL; \ 1274 (__HANDLE__)->MspDeInitCallback = NULL; \ 1275 } while(0) 1276 #else 1277 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1278 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1279 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1280 1281 /** 1282 * @brief Enable ADC interrupt. 1283 * @param __HANDLE__ ADC handle 1284 * @param __INTERRUPT__ ADC Interrupt 1285 * This parameter can be one of the following values: 1286 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1287 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1288 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1289 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1290 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1291 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1292 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1293 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1294 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1295 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1296 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1297 * @retval None 1298 */ 1299 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1300 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1301 1302 /** 1303 * @brief Disable ADC interrupt. 1304 * @param __HANDLE__ ADC handle 1305 * @param __INTERRUPT__ ADC Interrupt 1306 * This parameter can be one of the following values: 1307 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1308 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1309 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1310 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1311 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1312 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1313 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1314 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1315 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1316 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1317 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1318 * @retval None 1319 */ 1320 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1321 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1322 1323 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1324 * @param __HANDLE__ ADC handle 1325 * @param __INTERRUPT__ ADC interrupt source to check 1326 * This parameter can be one of the following values: 1327 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1328 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1329 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1330 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1331 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1332 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1333 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1334 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1335 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1336 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1337 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1338 * @retval State of interruption (SET or RESET) 1339 */ 1340 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1341 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1342 1343 /** 1344 * @brief Check whether the specified ADC flag is set or not. 1345 * @param __HANDLE__ ADC handle 1346 * @param __FLAG__ ADC flag 1347 * This parameter can be one of the following values: 1348 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1349 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1350 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1351 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1352 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1353 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1354 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1355 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1356 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1357 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1358 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1359 * @retval State of flag (TRUE or FALSE). 1360 */ 1361 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1362 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1363 1364 /** 1365 * @brief Clear the specified ADC flag. 1366 * @param __HANDLE__ ADC handle 1367 * @param __FLAG__ ADC flag 1368 * This parameter can be one of the following values: 1369 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1370 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1371 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1372 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1373 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1374 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1375 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1376 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1377 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1378 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1379 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1380 * @retval None 1381 */ 1382 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1383 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1384 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1385 1386 /** 1387 * @} 1388 */ 1389 1390 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1391 * @{ 1392 */ 1393 1394 /** 1395 * @brief Helper macro to get ADC channel number in decimal format 1396 * from literals ADC_CHANNEL_x. 1397 * @note Example: 1398 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1399 * will return decimal number "4". 1400 * @note The input can be a value from functions where a channel 1401 * number is returned, either defined with number 1402 * or with bitfield (only one bit must be set). 1403 * @param __CHANNEL__ This parameter can be one of the following values: 1404 * @arg @ref ADC_CHANNEL_0 (3) 1405 * @arg @ref ADC_CHANNEL_1 (3) 1406 * @arg @ref ADC_CHANNEL_2 (3) 1407 * @arg @ref ADC_CHANNEL_3 (3) 1408 * @arg @ref ADC_CHANNEL_4 (3) 1409 * @arg @ref ADC_CHANNEL_5 (3) 1410 * @arg @ref ADC_CHANNEL_6 1411 * @arg @ref ADC_CHANNEL_7 1412 * @arg @ref ADC_CHANNEL_8 1413 * @arg @ref ADC_CHANNEL_9 1414 * @arg @ref ADC_CHANNEL_10 1415 * @arg @ref ADC_CHANNEL_11 1416 * @arg @ref ADC_CHANNEL_12 1417 * @arg @ref ADC_CHANNEL_13 1418 * @arg @ref ADC_CHANNEL_14 1419 * @arg @ref ADC_CHANNEL_15 1420 * @arg @ref ADC_CHANNEL_16 1421 * @arg @ref ADC_CHANNEL_17 1422 * @arg @ref ADC_CHANNEL_18 1423 * @arg @ref ADC_CHANNEL_VREFINT (1) 1424 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1425 * @arg @ref ADC_CHANNEL_VBAT (1) 1426 * 1427 * (1) On STM32H7RS, parameter available only on ADC instance: ADC3.\n 1428 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1429 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1430 * @retval Value between Min_Data=0 and Max_Data=18 1431 */ 1432 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1433 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1434 1435 /** 1436 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1437 * from number in decimal format. 1438 * @note Example: 1439 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1440 * will return a data equivalent to "ADC_CHANNEL_4". 1441 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1442 * @retval Returned value can be one of the following values: 1443 * @arg @ref ADC_CHANNEL_0 (3) 1444 * @arg @ref ADC_CHANNEL_1 (3) 1445 * @arg @ref ADC_CHANNEL_2 (3) 1446 * @arg @ref ADC_CHANNEL_3 (3) 1447 * @arg @ref ADC_CHANNEL_4 (3) 1448 * @arg @ref ADC_CHANNEL_5 (3) 1449 * @arg @ref ADC_CHANNEL_6 1450 * @arg @ref ADC_CHANNEL_7 1451 * @arg @ref ADC_CHANNEL_8 1452 * @arg @ref ADC_CHANNEL_9 1453 * @arg @ref ADC_CHANNEL_10 1454 * @arg @ref ADC_CHANNEL_11 1455 * @arg @ref ADC_CHANNEL_12 1456 * @arg @ref ADC_CHANNEL_13 1457 * @arg @ref ADC_CHANNEL_14 1458 * @arg @ref ADC_CHANNEL_15 1459 * @arg @ref ADC_CHANNEL_16 1460 * @arg @ref ADC_CHANNEL_17 1461 * @arg @ref ADC_CHANNEL_18 1462 * @arg @ref ADC_CHANNEL_VREFINT (1) 1463 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1464 * @arg @ref ADC_CHANNEL_VBAT (1) 1465 * 1466 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1.\n 1467 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1468 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1469 * (1, 3) For ADC channel read back from ADC register, 1470 * comparison with internal channel parameter to be done 1471 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1472 */ 1473 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1474 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1475 1476 /** 1477 * @brief Helper macro to determine whether the selected channel 1478 * corresponds to literal definitions of driver. 1479 * @note The different literal definitions of ADC channels are: 1480 * - ADC internal channel: 1481 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1482 * - ADC external channel (channel connected to a GPIO pin): 1483 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1484 * @note The channel parameter must be a value defined from literal 1485 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1486 * ADC_CHANNEL_TEMPSENSOR, ...), 1487 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1488 * must not be a value from functions where a channel number is 1489 * returned from ADC registers, 1490 * because internal and external channels share the same channel 1491 * number in ADC registers. The differentiation is made only with 1492 * parameters definitions of driver. 1493 * @param __CHANNEL__ This parameter can be one of the following values: 1494 * @arg @ref ADC_CHANNEL_0 (3) 1495 * @arg @ref ADC_CHANNEL_1 (3) 1496 * @arg @ref ADC_CHANNEL_2 (3) 1497 * @arg @ref ADC_CHANNEL_3 (3) 1498 * @arg @ref ADC_CHANNEL_4 (3) 1499 * @arg @ref ADC_CHANNEL_5 (3) 1500 * @arg @ref ADC_CHANNEL_6 1501 * @arg @ref ADC_CHANNEL_7 1502 * @arg @ref ADC_CHANNEL_8 1503 * @arg @ref ADC_CHANNEL_9 1504 * @arg @ref ADC_CHANNEL_10 1505 * @arg @ref ADC_CHANNEL_11 1506 * @arg @ref ADC_CHANNEL_12 1507 * @arg @ref ADC_CHANNEL_13 1508 * @arg @ref ADC_CHANNEL_14 1509 * @arg @ref ADC_CHANNEL_15 1510 * @arg @ref ADC_CHANNEL_16 1511 * @arg @ref ADC_CHANNEL_17 1512 * @arg @ref ADC_CHANNEL_18 1513 * @arg @ref ADC_CHANNEL_VREFINT (1) 1514 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1515 * @arg @ref ADC_CHANNEL_VBAT (1) 1516 * 1517 * (1) On STM32H7RS, parameter available only on ADC instance: ADC3.\n 1518 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1519 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1520 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel 1521 * connected to a GPIO pin). 1522 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1523 */ 1524 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1525 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1526 1527 /** 1528 * @brief Helper macro to convert a channel defined from parameter 1529 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1530 * ADC_CHANNEL_TEMPSENSOR, ...), 1531 * to its equivalent parameter definition of a ADC external channel 1532 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1533 * @note The channel parameter can be, additionally to a value 1534 * defined from parameter definition of a ADC internal channel 1535 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1536 * a value defined from parameter definition of 1537 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1538 * or a value from functions where a channel number is returned 1539 * from ADC registers. 1540 * @param __CHANNEL__ This parameter can be one of the following values: 1541 * @arg @ref ADC_CHANNEL_0 (3) 1542 * @arg @ref ADC_CHANNEL_1 (3) 1543 * @arg @ref ADC_CHANNEL_2 (3) 1544 * @arg @ref ADC_CHANNEL_3 (3) 1545 * @arg @ref ADC_CHANNEL_4 (3) 1546 * @arg @ref ADC_CHANNEL_5 (3) 1547 * @arg @ref ADC_CHANNEL_6 1548 * @arg @ref ADC_CHANNEL_7 1549 * @arg @ref ADC_CHANNEL_8 1550 * @arg @ref ADC_CHANNEL_9 1551 * @arg @ref ADC_CHANNEL_10 1552 * @arg @ref ADC_CHANNEL_11 1553 * @arg @ref ADC_CHANNEL_12 1554 * @arg @ref ADC_CHANNEL_13 1555 * @arg @ref ADC_CHANNEL_14 1556 * @arg @ref ADC_CHANNEL_15 1557 * @arg @ref ADC_CHANNEL_16 1558 * @arg @ref ADC_CHANNEL_17 1559 * @arg @ref ADC_CHANNEL_18 1560 * @arg @ref ADC_CHANNEL_VREFINT (1) 1561 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1562 * @arg @ref ADC_CHANNEL_VBAT (1) 1563 * 1564 * (1) On STM32H7RS, parameter available only on ADC instance: ADC3.\n 1565 * (3) On STM32H7RS, fast channel allows: 2.5 (sampling) + 12.5 (conversion 12b) = 15 ADC clock cycles (fADC) 1566 * Other channels are slow channels: 6.5 (sampling) + 12.5 (conversion 12b) = 19 ADC clock cycles (fADC) 1567 * @retval Returned value can be one of the following values: 1568 * @arg @ref ADC_CHANNEL_0 1569 * @arg @ref ADC_CHANNEL_1 1570 * @arg @ref ADC_CHANNEL_2 1571 * @arg @ref ADC_CHANNEL_3 1572 * @arg @ref ADC_CHANNEL_4 1573 * @arg @ref ADC_CHANNEL_5 1574 * @arg @ref ADC_CHANNEL_6 1575 * @arg @ref ADC_CHANNEL_7 1576 * @arg @ref ADC_CHANNEL_8 1577 * @arg @ref ADC_CHANNEL_9 1578 * @arg @ref ADC_CHANNEL_10 1579 * @arg @ref ADC_CHANNEL_11 1580 * @arg @ref ADC_CHANNEL_12 1581 * @arg @ref ADC_CHANNEL_13 1582 * @arg @ref ADC_CHANNEL_14 1583 * @arg @ref ADC_CHANNEL_15 1584 * @arg @ref ADC_CHANNEL_16 1585 * @arg @ref ADC_CHANNEL_17 1586 * @arg @ref ADC_CHANNEL_18 1587 */ 1588 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1589 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1590 1591 /** 1592 * @brief Helper macro to determine whether the internal channel 1593 * selected is available on the ADC instance selected. 1594 * @note The channel parameter must be a value defined from parameter 1595 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1596 * ADC_CHANNEL_TEMPSENSOR, ...), 1597 * must not be a value defined from parameter definition of 1598 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1599 * or a value from functions where a channel number is 1600 * returned from ADC registers, 1601 * because internal and external channels share the same channel 1602 * number in ADC registers. The differentiation is made only with 1603 * parameters definitions of driver. 1604 * @param __ADC_INSTANCE__ ADC instance 1605 * @param __CHANNEL__ This parameter can be one of the following values: 1606 * @arg @ref ADC_CHANNEL_VREFINT (1) 1607 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1608 * @arg @ref ADC_CHANNEL_VBAT (1) 1609 * 1610 * (1) On STM32H7RS, parameter available only on ADC instance: ADC1. 1611 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1612 * Value "1" if the internal channel selected is available on the ADC instance selected. 1613 */ 1614 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1615 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1616 1617 #if defined(ADC_MULTIMODE_SUPPORT) 1618 /** 1619 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1620 * or ADC slave from raw value with both ADC conversion data concatenated. 1621 * @note This macro is intended to be used when multimode transfer by DMA 1622 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1623 * In this case the transferred data need to processed with this macro 1624 * to separate the conversion data of ADC master and ADC slave. 1625 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1626 * @arg @ref LL_ADC_MULTI_MASTER 1627 * @arg @ref LL_ADC_MULTI_SLAVE 1628 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1629 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1630 */ 1631 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1632 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1633 #endif /* ADC_MULTIMODE_SUPPORT */ 1634 1635 /** 1636 * @brief Helper macro to select the ADC common instance 1637 * to which is belonging the selected ADC instance. 1638 * @note ADC common register instance can be used for: 1639 * - Set parameters common to several ADC instances 1640 * - Multimode (for devices with several ADC instances) 1641 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1642 * @param __ADCx__ ADC instance 1643 * @retval ADC common register instance 1644 */ 1645 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1646 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1647 1648 /** 1649 * @brief Helper macro to check if all ADC instances sharing the same 1650 * ADC common instance are disabled. 1651 * @note This check is required by functions with setting conditioned to 1652 * ADC state: 1653 * All ADC instances of the ADC common group must be disabled. 1654 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1655 * @note On devices with only 1 ADC common instance, parameter of this macro 1656 * is useless and can be ignored (parameter kept for compatibility 1657 * with devices featuring several ADC common instances). 1658 * @param __ADCXY_COMMON__ ADC common instance 1659 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1660 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1661 * are disabled. 1662 * Value "1" if at least one ADC instance sharing the same ADC common instance 1663 * is enabled. 1664 */ 1665 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1666 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1667 1668 /** 1669 * @brief Helper macro to define the ADC conversion data full-scale digital 1670 * value corresponding to the selected ADC resolution. 1671 * @note ADC conversion data full-scale corresponds to voltage range 1672 * determined by analog voltage references Vref+ and Vref- 1673 * (refer to reference manual). 1674 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1675 * @arg @ref ADC_RESOLUTION_12B 1676 * @arg @ref ADC_RESOLUTION_10B 1677 * @arg @ref ADC_RESOLUTION_8B 1678 * @arg @ref ADC_RESOLUTION_6B 1679 * @retval ADC conversion data full-scale digital value 1680 */ 1681 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1682 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1683 1684 /** 1685 * @brief Helper macro to convert the ADC conversion data from 1686 * a resolution to another resolution. 1687 * @param __DATA__ ADC conversion data to be converted 1688 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1689 * This parameter can be one of the following values: 1690 * @arg @ref ADC_RESOLUTION_12B 1691 * @arg @ref ADC_RESOLUTION_10B 1692 * @arg @ref ADC_RESOLUTION_8B 1693 * @arg @ref ADC_RESOLUTION_6B 1694 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1695 * This parameter can be one of the following values: 1696 * @arg @ref ADC_RESOLUTION_12B 1697 * @arg @ref ADC_RESOLUTION_10B 1698 * @arg @ref ADC_RESOLUTION_8B 1699 * @arg @ref ADC_RESOLUTION_6B 1700 * @retval ADC conversion data to the requested resolution 1701 */ 1702 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1703 __ADC_RESOLUTION_CURRENT__,\ 1704 __ADC_RESOLUTION_TARGET__) \ 1705 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1706 (__ADC_RESOLUTION_CURRENT__),\ 1707 (__ADC_RESOLUTION_TARGET__)) 1708 1709 /** 1710 * @brief Helper macro to calculate the voltage (unit: mVolt) 1711 * corresponding to a ADC conversion data (unit: digital value). 1712 * @note Analog reference voltage (Vref+) must be either known from 1713 * user board environment or can be calculated using ADC measurement 1714 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1715 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1716 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1717 * (unit: digital value). 1718 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1719 * @arg @ref ADC_RESOLUTION_12B 1720 * @arg @ref ADC_RESOLUTION_10B 1721 * @arg @ref ADC_RESOLUTION_8B 1722 * @arg @ref ADC_RESOLUTION_6B 1723 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1724 */ 1725 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1726 __ADC_DATA__,\ 1727 __ADC_RESOLUTION__) \ 1728 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1729 (__ADC_DATA__),\ 1730 (__ADC_RESOLUTION__)) 1731 1732 /** 1733 * @brief Helper macro to calculate the voltage (unit: mVolt) 1734 * corresponding to a ADC conversion data (unit: digital value) 1735 * in differential ended mode. 1736 * @note Analog reference voltage (Vref+) must be either known from 1737 * user board environment or can be calculated using ADC measurement 1738 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1739 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1740 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1741 * (unit: digital value). 1742 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1743 * @arg @ref ADC_RESOLUTION_12B 1744 * @arg @ref ADC_RESOLUTION_10B 1745 * @arg @ref ADC_RESOLUTION_8B 1746 * @arg @ref ADC_RESOLUTION_6B 1747 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1748 */ 1749 #define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1750 __ADC_DATA__,\ 1751 __ADC_RESOLUTION__) \ 1752 __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1753 (__ADC_DATA__),\ 1754 (__ADC_RESOLUTION__)) 1755 1756 /** 1757 * @brief Helper macro to calculate analog reference voltage (Vref+) 1758 * (unit: mVolt) from ADC conversion data of internal voltage 1759 * reference VrefInt. 1760 * @note Computation is using VrefInt calibration value 1761 * stored in system memory for each device during production. 1762 * @note This voltage depends on user board environment: voltage level 1763 * connected to pin Vref+. 1764 * On devices with small package, the pin Vref+ is not present 1765 * and internally bonded to pin Vdda. 1766 * @note On this STM32 series, calibration data of internal voltage reference 1767 * VrefInt corresponds to a resolution of 12 bits, 1768 * this is the recommended ADC resolution to convert voltage of 1769 * internal voltage reference VrefInt. 1770 * Otherwise, this macro performs the processing to scale 1771 * ADC conversion data to 12 bits. 1772 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1773 * of internal voltage reference VrefInt (unit: digital value). 1774 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1775 * @arg @ref ADC_RESOLUTION_12B 1776 * @arg @ref ADC_RESOLUTION_10B 1777 * @arg @ref ADC_RESOLUTION_8B 1778 * @arg @ref ADC_RESOLUTION_6B 1779 * @retval Analog reference voltage (unit: mV) 1780 */ 1781 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1782 __ADC_RESOLUTION__) \ 1783 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1784 (__ADC_RESOLUTION__)) 1785 1786 /** 1787 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1788 * from ADC conversion data of internal temperature sensor. 1789 * @note Computation is using temperature sensor calibration values 1790 * stored in system memory for each device during production. 1791 * @note Calculation formula: 1792 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1793 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1794 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1795 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1796 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1797 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1798 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1799 * TEMP_DEGC_CAL1 (calibrated in factory) 1800 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1801 * TEMP_DEGC_CAL2 (calibrated in factory) 1802 * Caution: Calculation relevancy under reserve that calibration 1803 * parameters are correct (address and data). 1804 * To calculate temperature using temperature sensor 1805 * datasheet typical values (generic values less, therefore 1806 * less accurate than calibrated values), 1807 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1808 * @note As calculation input, the analog reference voltage (Vref+) must be 1809 * defined as it impacts the ADC LSB equivalent voltage. 1810 * @note Analog reference voltage (Vref+) must be either known from 1811 * user board environment or can be calculated using ADC measurement 1812 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1813 * @note On this STM32 series, calibration data of temperature sensor 1814 * corresponds to a resolution of 12 bits, 1815 * this is the recommended ADC resolution to convert voltage of 1816 * temperature sensor. 1817 * Otherwise, this macro performs the processing to scale 1818 * ADC conversion data to 12 bits. 1819 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1820 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1821 * temperature sensor (unit: digital value). 1822 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1823 * sensor voltage has been measured. 1824 * This parameter can be one of the following values: 1825 * @arg @ref ADC_RESOLUTION_12B 1826 * @arg @ref ADC_RESOLUTION_10B 1827 * @arg @ref ADC_RESOLUTION_8B 1828 * @arg @ref ADC_RESOLUTION_6B 1829 * @retval Temperature (unit: degree Celsius) 1830 */ 1831 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1832 __TEMPSENSOR_ADC_DATA__,\ 1833 __ADC_RESOLUTION__) \ 1834 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1835 (__TEMPSENSOR_ADC_DATA__),\ 1836 (__ADC_RESOLUTION__)) 1837 1838 /** 1839 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1840 * from ADC conversion data of internal temperature sensor. 1841 * @note Computation is using temperature sensor typical values 1842 * (refer to device datasheet). 1843 * @note Calculation formula: 1844 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1845 * / Avg_Slope + CALx_TEMP 1846 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1847 * (unit: digital value) 1848 * Avg_Slope = temperature sensor slope 1849 * (unit: uV/Degree Celsius) 1850 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1851 * temperature CALx_TEMP (unit: mV) 1852 * Caution: Calculation relevancy under reserve the temperature sensor 1853 * of the current device has characteristics in line with 1854 * datasheet typical values. 1855 * If temperature sensor calibration values are available on 1856 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1857 * temperature calculation will be more accurate using 1858 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1859 * @note As calculation input, the analog reference voltage (Vref+) must be 1860 * defined as it impacts the ADC LSB equivalent voltage. 1861 * @note Analog reference voltage (Vref+) must be either known from 1862 * user board environment or can be calculated using ADC measurement 1863 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1864 * @note ADC measurement data must correspond to a resolution of 12bits 1865 * (full scale digital value 4095). If not the case, the data must be 1866 * preliminarily rescaled to an equivalent resolution of 12 bits. 1867 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value 1868 (unit: uV/DegCelsius). 1869 * On this STM32 series, refer to device datasheet parameter "Avg_Slope". 1870 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at 1871 temperature and Vref+ defined in parameters below) (unit: mV). 1872 * On this STM32 series, refer to device datasheet parameter "V30" 1873 * (corresponding to TS_CAL1). 1874 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see 1875 parameter above) is corresponding (unit: mV) 1876 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1877 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1878 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1879 * This parameter can be one of the following values: 1880 * @arg @ref ADC_RESOLUTION_12B 1881 * @arg @ref ADC_RESOLUTION_10B 1882 * @arg @ref ADC_RESOLUTION_8B 1883 * @arg @ref ADC_RESOLUTION_6B 1884 * @retval Temperature (unit: degree Celsius) 1885 */ 1886 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1887 __TEMPSENSOR_TYP_CALX_V__,\ 1888 __TEMPSENSOR_CALX_TEMP__,\ 1889 __VREFANALOG_VOLTAGE__,\ 1890 __TEMPSENSOR_ADC_DATA__,\ 1891 __ADC_RESOLUTION__) \ 1892 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1893 (__TEMPSENSOR_TYP_CALX_V__),\ 1894 (__TEMPSENSOR_CALX_TEMP__),\ 1895 (__VREFANALOG_VOLTAGE__),\ 1896 (__TEMPSENSOR_ADC_DATA__),\ 1897 (__ADC_RESOLUTION__)) 1898 1899 /** 1900 * @} 1901 */ 1902 1903 /** 1904 * @} 1905 */ 1906 1907 /* Include ADC HAL Extended module */ 1908 #include "stm32h7rsxx_hal_adc_ex.h" 1909 1910 /* Exported functions --------------------------------------------------------*/ 1911 /** @addtogroup ADC_Exported_Functions 1912 * @{ 1913 */ 1914 1915 /** @addtogroup ADC_Exported_Functions_Group1 1916 * @brief Initialization and Configuration functions 1917 * @{ 1918 */ 1919 /* Initialization and de-initialization functions ****************************/ 1920 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1921 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1922 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1923 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1924 1925 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1926 /* Callbacks Register/UnRegister functions ***********************************/ 1927 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1928 pADC_CallbackTypeDef pCallback); 1929 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1930 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1931 /** 1932 * @} 1933 */ 1934 1935 /** @addtogroup ADC_Exported_Functions_Group2 1936 * @brief IO operation functions 1937 * @{ 1938 */ 1939 /* IO operation functions *****************************************************/ 1940 1941 /* Blocking mode: Polling */ 1942 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1943 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1944 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1945 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1946 1947 /* Non-blocking mode: Interruption */ 1948 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1949 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1950 1951 /* Non-blocking mode: DMA */ 1952 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1953 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1954 1955 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1956 uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); 1957 1958 /* ADC sampling control */ 1959 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc); 1960 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc); 1961 1962 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1963 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1964 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1965 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1966 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1967 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1968 /** 1969 * @} 1970 */ 1971 1972 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1973 * @brief Peripheral Control functions 1974 * @{ 1975 */ 1976 /* Peripheral Control functions ***********************************************/ 1977 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); 1978 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, 1979 const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 1980 1981 /** 1982 * @} 1983 */ 1984 1985 /* Peripheral State functions *************************************************/ 1986 /** @addtogroup ADC_Exported_Functions_Group4 1987 * @{ 1988 */ 1989 uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); 1990 uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); 1991 1992 /** 1993 * @} 1994 */ 1995 1996 /** 1997 * @} 1998 */ 1999 2000 /* Private functions ---------------------------------------------------------*/ 2001 /** @addtogroup ADC_Private_Functions ADC Private Functions 2002 * @{ 2003 */ 2004 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 2005 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 2006 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 2007 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 2008 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 2009 void ADC_DMAError(DMA_HandleTypeDef *hdma); 2010 2011 /** 2012 * @} 2013 */ 2014 2015 /** 2016 * @} 2017 */ 2018 2019 /** 2020 * @} 2021 */ 2022 2023 #ifdef __cplusplus 2024 } 2025 #endif 2026 2027 2028 #endif /* STM32H7RSxx_HAL_ADC_H */ 2029
