1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32h5xx_ll_tim.h"
22 #include "stm32h5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM12) \
43 || defined (TIM13) \
44 || defined (TIM14) \
45 || defined (TIM15) \
46 || defined (TIM16) \
47 || defined (TIM17)
48
49 /** @addtogroup TIM_LL
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55 /* Private constants ---------------------------------------------------------*/
56 /* Private macros ------------------------------------------------------------*/
57 /** @addtogroup TIM_LL_Private_Macros
58 * @{
59 */
60 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
61 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
62 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
63 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
64 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
65
66 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
67 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
68 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
69
70 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
71 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
72 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
73 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
74 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
75 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
76 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
77 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
78 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
79 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
80 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
81 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
82 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
83 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
84 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
85 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
86
87 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
88 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
89
90 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
91 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
92
93 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
94 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
95
96 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
97 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
98 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
99
100 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
101 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
102 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
103 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
104
105 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
117 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
118 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
119 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
120 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
121
122 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
123 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
124 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
125
126 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
127 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
128 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
129 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
130 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
131 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
132 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
133 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
134 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
135
136 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
137 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
138
139 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
140 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
141
142 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
143 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
144
145 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
146 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
147 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
148 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
149
150 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
151 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
152
153 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
154 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
155
156 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
159 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
160 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
161 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
162 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
163 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
164 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
165 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
166 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
167 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
170 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
171 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
172
173 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
174 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
175
176 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
177 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
178
179 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
180 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
181
182 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
185 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
186 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
187 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
188 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
189 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
190 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
191 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
192 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
193 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
194 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
195 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
196 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
197 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
198
199 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
200 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
201
202 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
203 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
204 /**
205 * @}
206 */
207
208
209 /* Private function prototypes -----------------------------------------------*/
210 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
211 * @{
212 */
213 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
214 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
215 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
216 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
217 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
218 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
219 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
220 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
221 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
222 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
223 /**
224 * @}
225 */
226
227 /* Exported functions --------------------------------------------------------*/
228 /** @addtogroup TIM_LL_Exported_Functions
229 * @{
230 */
231
232 /** @addtogroup TIM_LL_EF_Init
233 * @{
234 */
235
236 /**
237 * @brief Set TIMx registers to their reset values.
238 * @param TIMx Timer instance
239 * @retval An ErrorStatus enumeration value:
240 * - SUCCESS: TIMx registers are de-initialized
241 * - ERROR: invalid TIMx instance
242 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)243 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
244 {
245 ErrorStatus result = SUCCESS;
246
247 /* Check the parameters */
248 assert_param(IS_TIM_INSTANCE(TIMx));
249
250 if (TIMx == TIM1)
251 {
252 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
253 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
254 }
255 else if (TIMx == TIM2)
256 {
257 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
258 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
259 }
260 else if (TIMx == TIM3)
261 {
262 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
263 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
264 }
265 #if defined (TIM4)
266 else if (TIMx == TIM4)
267 {
268 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
269 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
270 }
271 #endif /* TIM4 */
272 #if defined (TIM5)
273 else if (TIMx == TIM5)
274 {
275 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
276 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
277 }
278 #endif /* TIM5 */
279 else if (TIMx == TIM6)
280 {
281 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
282 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
283 }
284 else if (TIMx == TIM7)
285 {
286 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
287 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
288 }
289 #if defined (TIM8)
290 else if (TIMx == TIM8)
291 {
292 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
293 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
294 }
295 #endif /* TIM8 */
296 #if defined (TIM12)
297 else if (TIMx == TIM12)
298 {
299 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
300 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
301 }
302 #endif /* TIM12 */
303 #if defined (TIM13)
304 else if (TIMx == TIM13)
305 {
306 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
307 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
308 }
309 #endif /* TIM13 */
310 #if defined (TIM14)
311 else if (TIMx == TIM14)
312 {
313 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
314 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
315 }
316 #endif /* TIM14 */
317 #if defined (TIM15)
318 else if (TIMx == TIM15)
319 {
320 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
321 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
322 }
323 #endif /* TIM15 */
324 #if defined (TIM16)
325 else if (TIMx == TIM16)
326 {
327 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
328 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
329 }
330 #endif /* TIM16 */
331 #if defined (TIM17)
332 else if (TIMx == TIM17)
333 {
334 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
335 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
336 }
337 #endif /* TIM17 */
338 else
339 {
340 result = ERROR;
341 }
342
343 return result;
344 }
345
346 /**
347 * @brief Set the fields of the time base unit configuration data structure
348 * to their default values.
349 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
350 * @retval None
351 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)352 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
353 {
354 /* Set the default configuration */
355 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
356 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
357 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
358 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
359 TIM_InitStruct->RepetitionCounter = 0x00000000U;
360 }
361
362 /**
363 * @brief Configure the TIMx time base unit.
364 * @param TIMx Timer Instance
365 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
366 * (TIMx time base unit configuration data structure)
367 * @retval An ErrorStatus enumeration value:
368 * - SUCCESS: TIMx registers are de-initialized
369 * - ERROR: not applicable
370 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)371 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
372 {
373 uint32_t tmpcr1;
374
375 /* Check the parameters */
376 assert_param(IS_TIM_INSTANCE(TIMx));
377 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
378 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
379
380 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
381
382 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
383 {
384 /* Select the Counter Mode */
385 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
386 }
387
388 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
389 {
390 /* Set the clock division */
391 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
392 }
393
394 /* Write to TIMx CR1 */
395 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
396
397 /* Set the Autoreload value */
398 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
399
400 /* Set the Prescaler value */
401 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
402
403 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
404 {
405 /* Set the Repetition Counter value */
406 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
407 }
408
409 /* Generate an update event to reload the Prescaler
410 and the repetition counter value (if applicable) immediately */
411 LL_TIM_GenerateEvent_UPDATE(TIMx);
412
413 return SUCCESS;
414 }
415
416 /**
417 * @brief Set the fields of the TIMx output channel configuration data
418 * structure to their default values.
419 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
420 * (the output channel configuration data structure)
421 * @retval None
422 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)423 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
424 {
425 /* Set the default configuration */
426 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
427 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
428 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
429 TIM_OC_InitStruct->CompareValue = 0x00000000U;
430 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
431 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
432 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
433 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
434 }
435
436 /**
437 * @brief Configure the TIMx output channel.
438 * @param TIMx Timer Instance
439 * @param Channel This parameter can be one of the following values:
440 * @arg @ref LL_TIM_CHANNEL_CH1
441 * @arg @ref LL_TIM_CHANNEL_CH2
442 * @arg @ref LL_TIM_CHANNEL_CH3
443 * @arg @ref LL_TIM_CHANNEL_CH4
444 * @arg @ref LL_TIM_CHANNEL_CH5
445 * @arg @ref LL_TIM_CHANNEL_CH6
446 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
447 * data structure)
448 * @retval An ErrorStatus enumeration value:
449 * - SUCCESS: TIMx output channel is initialized
450 * - ERROR: TIMx output channel is not initialized
451 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)452 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
453 {
454 ErrorStatus result = ERROR;
455
456 switch (Channel)
457 {
458 case LL_TIM_CHANNEL_CH1:
459 result = OC1Config(TIMx, TIM_OC_InitStruct);
460 break;
461 case LL_TIM_CHANNEL_CH2:
462 result = OC2Config(TIMx, TIM_OC_InitStruct);
463 break;
464 case LL_TIM_CHANNEL_CH3:
465 result = OC3Config(TIMx, TIM_OC_InitStruct);
466 break;
467 case LL_TIM_CHANNEL_CH4:
468 result = OC4Config(TIMx, TIM_OC_InitStruct);
469 break;
470 case LL_TIM_CHANNEL_CH5:
471 result = OC5Config(TIMx, TIM_OC_InitStruct);
472 break;
473 case LL_TIM_CHANNEL_CH6:
474 result = OC6Config(TIMx, TIM_OC_InitStruct);
475 break;
476 default:
477 break;
478 }
479
480 return result;
481 }
482
483 /**
484 * @brief Set the fields of the TIMx input channel configuration data
485 * structure to their default values.
486 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
487 * data structure)
488 * @retval None
489 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)490 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
491 {
492 /* Set the default configuration */
493 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
494 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
495 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
496 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
497 }
498
499 /**
500 * @brief Configure the TIMx input channel.
501 * @param TIMx Timer Instance
502 * @param Channel This parameter can be one of the following values:
503 * @arg @ref LL_TIM_CHANNEL_CH1
504 * @arg @ref LL_TIM_CHANNEL_CH2
505 * @arg @ref LL_TIM_CHANNEL_CH3
506 * @arg @ref LL_TIM_CHANNEL_CH4
507 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
508 * structure)
509 * @retval An ErrorStatus enumeration value:
510 * - SUCCESS: TIMx output channel is initialized
511 * - ERROR: TIMx output channel is not initialized
512 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)513 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
514 {
515 ErrorStatus result = ERROR;
516
517 switch (Channel)
518 {
519 case LL_TIM_CHANNEL_CH1:
520 result = IC1Config(TIMx, TIM_IC_InitStruct);
521 break;
522 case LL_TIM_CHANNEL_CH2:
523 result = IC2Config(TIMx, TIM_IC_InitStruct);
524 break;
525 case LL_TIM_CHANNEL_CH3:
526 result = IC3Config(TIMx, TIM_IC_InitStruct);
527 break;
528 case LL_TIM_CHANNEL_CH4:
529 result = IC4Config(TIMx, TIM_IC_InitStruct);
530 break;
531 default:
532 break;
533 }
534
535 return result;
536 }
537
538 /**
539 * @brief Fills each TIM_EncoderInitStruct field with its default value
540 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
541 * configuration data structure)
542 * @retval None
543 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)544 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
545 {
546 /* Set the default configuration */
547 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
548 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
549 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
550 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
551 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
552 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
553 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
554 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
555 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
556 }
557
558 /**
559 * @brief Configure the encoder interface of the timer instance.
560 * @param TIMx Timer Instance
561 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
562 * configuration data structure)
563 * @retval An ErrorStatus enumeration value:
564 * - SUCCESS: TIMx registers are de-initialized
565 * - ERROR: not applicable
566 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)567 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
568 {
569 uint32_t tmpccmr1;
570 uint32_t tmpccer;
571
572 /* Check the parameters */
573 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
574 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
575 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
576 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
577 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
578 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
579 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
580 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
581 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
582 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
583
584 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
585 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
586
587 /* Get the TIMx CCMR1 register value */
588 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
589
590 /* Get the TIMx CCER register value */
591 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
592
593 /* Configure TI1 */
594 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
595 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
596 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
597 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
598
599 /* Configure TI2 */
600 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
601 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
602 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
603 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
604
605 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
606 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
607 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
608 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
609 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
610
611 /* Set encoder mode */
612 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
613
614 /* Write to TIMx CCMR1 */
615 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
616
617 /* Write to TIMx CCER */
618 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
619
620 return SUCCESS;
621 }
622
623 /**
624 * @brief Set the fields of the TIMx Hall sensor interface configuration data
625 * structure to their default values.
626 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
627 * configuration data structure)
628 * @retval None
629 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)630 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
631 {
632 /* Set the default configuration */
633 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
634 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
635 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
636 TIM_HallSensorInitStruct->CommutationDelay = 0U;
637 }
638
639 /**
640 * @brief Configure the Hall sensor interface of the timer instance.
641 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
642 * to the TI1 input channel
643 * @note TIMx slave mode controller is configured in reset mode.
644 Selected internal trigger is TI1F_ED.
645 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
646 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
647 * between 2 changes on the inputs. It gives information about motor speed.
648 * @note Channel 2 is configured in output PWM 2 mode.
649 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
650 * @note OC2REF is selected as trigger output on TRGO.
651 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
652 * when TIMx operates in Hall sensor interface mode.
653 * @param TIMx Timer Instance
654 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
655 * interface configuration data structure)
656 * @retval An ErrorStatus enumeration value:
657 * - SUCCESS: TIMx registers are de-initialized
658 * - ERROR: not applicable
659 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)660 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
661 {
662 uint32_t tmpcr2;
663 uint32_t tmpccmr1;
664 uint32_t tmpccer;
665 uint32_t tmpsmcr;
666
667 /* Check the parameters */
668 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
669 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
670 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
671 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
672
673 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
674 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
675
676 /* Get the TIMx CR2 register value */
677 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
678
679 /* Get the TIMx CCMR1 register value */
680 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
681
682 /* Get the TIMx CCER register value */
683 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
684
685 /* Get the TIMx SMCR register value */
686 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
687
688 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
689 tmpcr2 |= TIM_CR2_TI1S;
690
691 /* OC2REF signal is used as trigger output (TRGO) */
692 tmpcr2 |= LL_TIM_TRGO_OC2REF;
693
694 /* Configure the slave mode controller */
695 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
696 tmpsmcr |= LL_TIM_TS_TI1F_ED;
697 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
698
699 /* Configure input channel 1 */
700 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
701 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
702 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
703 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
704
705 /* Configure input channel 2 */
706 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
707 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
708
709 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
710 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
711 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
712 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
713
714 /* Write to TIMx CR2 */
715 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
716
717 /* Write to TIMx SMCR */
718 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
719
720 /* Write to TIMx CCMR1 */
721 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
722
723 /* Write to TIMx CCER */
724 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
725
726 /* Write to TIMx CCR2 */
727 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
728
729 return SUCCESS;
730 }
731
732 /**
733 * @brief Set the fields of the Break and Dead Time configuration data structure
734 * to their default values.
735 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
736 * data structure)
737 * @retval None
738 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)739 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
740 {
741 /* Set the default configuration */
742 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
743 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
744 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
745 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
746 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
747 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
748 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
749 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
750 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
751 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
752 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
753 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
754 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
755 }
756
757 /**
758 * @brief Configure the Break and Dead Time feature of the timer instance.
759 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
760 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
761 * can be necessary to configure all of them during the first write access to
762 * the TIMx_BDTR register.
763 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
764 * a timer instance provides a break input.
765 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
766 * a timer instance provides a second break input.
767 * @param TIMx Timer Instance
768 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
769 * data structure)
770 * @retval An ErrorStatus enumeration value:
771 * - SUCCESS: Break and Dead Time is initialized
772 * - ERROR: not applicable
773 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)774 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
775 {
776 uint32_t tmpbdtr = 0;
777
778 /* Check the parameters */
779 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
780 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
781 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
782 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
783 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
784 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
785 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
786 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
787 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
788
789 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
790 the OSSI State, the dead time value and the Automatic Output Enable Bit */
791
792 /* Set the BDTR bits */
793 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
794 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
795 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
796 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
797 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
798 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
799 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
800 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
801 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
802
803 if (IS_TIM_BKIN2_INSTANCE(TIMx))
804 {
805 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
806 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
807 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
808 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
809
810 /* Set the BREAK2 input related BDTR bit-fields */
811 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
812 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
813 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
814 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
815 }
816
817 /* Set TIMx_BDTR */
818 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
819
820 return SUCCESS;
821 }
822 /**
823 * @}
824 */
825
826 /**
827 * @}
828 */
829
830 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
831 * @brief Private functions
832 * @{
833 */
834 /**
835 * @brief Configure the TIMx output channel 1.
836 * @param TIMx Timer Instance
837 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
838 * @retval An ErrorStatus enumeration value:
839 * - SUCCESS: TIMx registers are de-initialized
840 * - ERROR: not applicable
841 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)842 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
843 {
844 uint32_t tmpccmr1;
845 uint32_t tmpccer;
846 uint32_t tmpcr2;
847
848 /* Check the parameters */
849 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
850 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
851 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
852 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
853
854 /* Disable the Channel 1: Reset the CC1E Bit */
855 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
856
857 /* Get the TIMx CCER register value */
858 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
859
860 /* Get the TIMx CR2 register value */
861 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
862
863 /* Get the TIMx CCMR1 register value */
864 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
865
866 /* Reset Capture/Compare selection Bits */
867 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
868
869 /* Set the Output Compare Mode */
870 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
871
872 /* Set the Output Compare Polarity */
873 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
874
875 /* Set the Output State */
876 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
877
878 if (IS_TIM_BREAK_INSTANCE(TIMx))
879 {
880 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
881 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
882 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
883 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
884
885 /* Set the complementary output Polarity */
886 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
887
888 /* Set the complementary output State */
889 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
890
891 /* Set the Output Idle state */
892 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
893
894 /* Set the complementary output Idle state */
895 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
896 }
897
898 /* Write to TIMx CR2 */
899 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
900
901 /* Write to TIMx CCMR1 */
902 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
903
904 /* Set the Capture Compare Register value */
905 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
906
907 /* Write to TIMx CCER */
908 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
909
910 return SUCCESS;
911 }
912
913 /**
914 * @brief Configure the TIMx output channel 2.
915 * @param TIMx Timer Instance
916 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
917 * @retval An ErrorStatus enumeration value:
918 * - SUCCESS: TIMx registers are de-initialized
919 * - ERROR: not applicable
920 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)921 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
922 {
923 uint32_t tmpccmr1;
924 uint32_t tmpccer;
925 uint32_t tmpcr2;
926
927 /* Check the parameters */
928 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
929 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
930 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
931 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
932
933 /* Disable the Channel 2: Reset the CC2E Bit */
934 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
935
936 /* Get the TIMx CCER register value */
937 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
938
939 /* Get the TIMx CR2 register value */
940 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
941
942 /* Get the TIMx CCMR1 register value */
943 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
944
945 /* Reset Capture/Compare selection Bits */
946 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
947
948 /* Select the Output Compare Mode */
949 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
950
951 /* Set the Output Compare Polarity */
952 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
953
954 /* Set the Output State */
955 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
956
957 if (IS_TIM_BREAK_INSTANCE(TIMx))
958 {
959 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
960 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
961 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
962 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
963
964 /* Set the complementary output Polarity */
965 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
966
967 /* Set the complementary output State */
968 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
969
970 /* Set the Output Idle state */
971 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
972
973 /* Set the complementary output Idle state */
974 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
975 }
976
977 /* Write to TIMx CR2 */
978 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
979
980 /* Write to TIMx CCMR1 */
981 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
982
983 /* Set the Capture Compare Register value */
984 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
985
986 /* Write to TIMx CCER */
987 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
988
989 return SUCCESS;
990 }
991
992 /**
993 * @brief Configure the TIMx output channel 3.
994 * @param TIMx Timer Instance
995 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
996 * @retval An ErrorStatus enumeration value:
997 * - SUCCESS: TIMx registers are de-initialized
998 * - ERROR: not applicable
999 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1000 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1001 {
1002 uint32_t tmpccmr2;
1003 uint32_t tmpccer;
1004 uint32_t tmpcr2;
1005
1006 /* Check the parameters */
1007 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1008 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1009 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1010 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1011
1012 /* Disable the Channel 3: Reset the CC3E Bit */
1013 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1014
1015 /* Get the TIMx CCER register value */
1016 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1017
1018 /* Get the TIMx CR2 register value */
1019 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1020
1021 /* Get the TIMx CCMR2 register value */
1022 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1023
1024 /* Reset Capture/Compare selection Bits */
1025 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1026
1027 /* Select the Output Compare Mode */
1028 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1029
1030 /* Set the Output Compare Polarity */
1031 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1032
1033 /* Set the Output State */
1034 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1035
1036 if (IS_TIM_BREAK_INSTANCE(TIMx))
1037 {
1038 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1039 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1040 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1041 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1042
1043 /* Set the complementary output Polarity */
1044 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1045
1046 /* Set the complementary output State */
1047 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1048
1049 /* Set the Output Idle state */
1050 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1051
1052 /* Set the complementary output Idle state */
1053 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1054 }
1055
1056 /* Write to TIMx CR2 */
1057 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1058
1059 /* Write to TIMx CCMR2 */
1060 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1061
1062 /* Set the Capture Compare Register value */
1063 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1064
1065 /* Write to TIMx CCER */
1066 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1067
1068 return SUCCESS;
1069 }
1070
1071 /**
1072 * @brief Configure the TIMx output channel 4.
1073 * @param TIMx Timer Instance
1074 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1075 * @retval An ErrorStatus enumeration value:
1076 * - SUCCESS: TIMx registers are de-initialized
1077 * - ERROR: not applicable
1078 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1079 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1080 {
1081 uint32_t tmpccmr2;
1082 uint32_t tmpccer;
1083 uint32_t tmpcr2;
1084
1085 /* Check the parameters */
1086 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1087 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1088 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1089 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1090
1091 /* Disable the Channel 4: Reset the CC4E Bit */
1092 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1093
1094 /* Get the TIMx CCER register value */
1095 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1096
1097 /* Get the TIMx CR2 register value */
1098 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1099
1100 /* Get the TIMx CCMR2 register value */
1101 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1102
1103 /* Reset Capture/Compare selection Bits */
1104 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1105
1106 /* Select the Output Compare Mode */
1107 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1108
1109 /* Set the Output Compare Polarity */
1110 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1111
1112 /* Set the Output State */
1113 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1114
1115 if (IS_TIM_BREAK_INSTANCE(TIMx))
1116 {
1117 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1118 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1119 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1120 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1121
1122 /* Set the complementary output Polarity */
1123 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1124
1125 /* Set the complementary output State */
1126 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1127
1128 /* Set the Output Idle state */
1129 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1130
1131 /* Set the complementary output Idle state */
1132 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1133 }
1134
1135 /* Write to TIMx CR2 */
1136 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1137
1138 /* Write to TIMx CCMR2 */
1139 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1140
1141 /* Set the Capture Compare Register value */
1142 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1143
1144 /* Write to TIMx CCER */
1145 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1146
1147 return SUCCESS;
1148 }
1149
1150 /**
1151 * @brief Configure the TIMx output channel 5.
1152 * @param TIMx Timer Instance
1153 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1154 * @retval An ErrorStatus enumeration value:
1155 * - SUCCESS: TIMx registers are de-initialized
1156 * - ERROR: not applicable
1157 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1158 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1159 {
1160 uint32_t tmpccmr3;
1161 uint32_t tmpccer;
1162
1163 /* Check the parameters */
1164 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1165 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1166 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1167 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1168 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1169 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1170
1171 /* Disable the Channel 5: Reset the CC5E Bit */
1172 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1173
1174 /* Get the TIMx CCER register value */
1175 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1176
1177 /* Get the TIMx CCMR3 register value */
1178 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1179
1180 /* Select the Output Compare Mode */
1181 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1182
1183 /* Set the Output Compare Polarity */
1184 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1185
1186 /* Set the Output State */
1187 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1188
1189 if (IS_TIM_BREAK_INSTANCE(TIMx))
1190 {
1191 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1192 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1193
1194 /* Set the Output Idle state */
1195 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1196
1197 }
1198
1199 /* Write to TIMx CCMR3 */
1200 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1201
1202 /* Set the Capture Compare Register value */
1203 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1204
1205 /* Write to TIMx CCER */
1206 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1207
1208 return SUCCESS;
1209 }
1210
1211 /**
1212 * @brief Configure the TIMx output channel 6.
1213 * @param TIMx Timer Instance
1214 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1215 * @retval An ErrorStatus enumeration value:
1216 * - SUCCESS: TIMx registers are de-initialized
1217 * - ERROR: not applicable
1218 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1219 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1220 {
1221 uint32_t tmpccmr3;
1222 uint32_t tmpccer;
1223
1224 /* Check the parameters */
1225 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1226 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1227 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1228 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1229 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1230 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1231
1232 /* Disable the Channel 5: Reset the CC6E Bit */
1233 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1234
1235 /* Get the TIMx CCER register value */
1236 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1237
1238 /* Get the TIMx CCMR3 register value */
1239 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1240
1241 /* Select the Output Compare Mode */
1242 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1243
1244 /* Set the Output Compare Polarity */
1245 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1246
1247 /* Set the Output State */
1248 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1249
1250 if (IS_TIM_BREAK_INSTANCE(TIMx))
1251 {
1252 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1253 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1254
1255 /* Set the Output Idle state */
1256 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1257 }
1258
1259 /* Write to TIMx CCMR3 */
1260 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1261
1262 /* Set the Capture Compare Register value */
1263 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1264
1265 /* Write to TIMx CCER */
1266 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1267
1268 return SUCCESS;
1269 }
1270
1271 /**
1272 * @brief Configure the TIMx input channel 1.
1273 * @param TIMx Timer Instance
1274 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1275 * @retval An ErrorStatus enumeration value:
1276 * - SUCCESS: TIMx registers are de-initialized
1277 * - ERROR: not applicable
1278 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1279 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1280 {
1281 /* Check the parameters */
1282 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1283 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1284 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1285 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1286 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1287
1288 /* Disable the Channel 1: Reset the CC1E Bit */
1289 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1290
1291 /* Select the Input and set the filter and the prescaler value */
1292 MODIFY_REG(TIMx->CCMR1,
1293 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1294 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1295
1296 /* Select the Polarity and set the CC1E Bit */
1297 MODIFY_REG(TIMx->CCER,
1298 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1299 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1300
1301 return SUCCESS;
1302 }
1303
1304 /**
1305 * @brief Configure the TIMx input channel 2.
1306 * @param TIMx Timer Instance
1307 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1308 * @retval An ErrorStatus enumeration value:
1309 * - SUCCESS: TIMx registers are de-initialized
1310 * - ERROR: not applicable
1311 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1312 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1313 {
1314 /* Check the parameters */
1315 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1316 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1317 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1318 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1319 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1320
1321 /* Disable the Channel 2: Reset the CC2E Bit */
1322 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1323
1324 /* Select the Input and set the filter and the prescaler value */
1325 MODIFY_REG(TIMx->CCMR1,
1326 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1327 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1328
1329 /* Select the Polarity and set the CC2E Bit */
1330 MODIFY_REG(TIMx->CCER,
1331 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1332 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1333
1334 return SUCCESS;
1335 }
1336
1337 /**
1338 * @brief Configure the TIMx input channel 3.
1339 * @param TIMx Timer Instance
1340 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1341 * @retval An ErrorStatus enumeration value:
1342 * - SUCCESS: TIMx registers are de-initialized
1343 * - ERROR: not applicable
1344 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1345 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1346 {
1347 /* Check the parameters */
1348 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1349 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1350 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1351 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1352 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1353
1354 /* Disable the Channel 3: Reset the CC3E Bit */
1355 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1356
1357 /* Select the Input and set the filter and the prescaler value */
1358 MODIFY_REG(TIMx->CCMR2,
1359 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1360 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1361
1362 /* Select the Polarity and set the CC3E Bit */
1363 MODIFY_REG(TIMx->CCER,
1364 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1365 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1366
1367 return SUCCESS;
1368 }
1369
1370 /**
1371 * @brief Configure the TIMx input channel 4.
1372 * @param TIMx Timer Instance
1373 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1374 * @retval An ErrorStatus enumeration value:
1375 * - SUCCESS: TIMx registers are de-initialized
1376 * - ERROR: not applicable
1377 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1378 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1379 {
1380 /* Check the parameters */
1381 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1382 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1383 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1384 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1385 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1386
1387 /* Disable the Channel 4: Reset the CC4E Bit */
1388 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1389
1390 /* Select the Input and set the filter and the prescaler value */
1391 MODIFY_REG(TIMx->CCMR2,
1392 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1393 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1394
1395 /* Select the Polarity and set the CC4E Bit */
1396 MODIFY_REG(TIMx->CCER,
1397 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1398 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1399
1400 return SUCCESS;
1401 }
1402
1403
1404 /**
1405 * @}
1406 */
1407
1408 /**
1409 * @}
1410 */
1411
1412 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
1413
1414 /**
1415 * @}
1416 */
1417
1418 #endif /* USE_FULL_LL_DRIVER */
1419
