1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32g4xx_ll_tim.h"
22 #include "stm32g4xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2) \
71 || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
72 || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
73
74 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
75 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
76
77 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
78 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
79
80 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
81 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
82
83 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
84 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
85 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
86
87 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
89 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
90 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
91
92 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
108
109 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
111 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
112
113 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
114 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
115 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
116 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
117 || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
118 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
119 || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
120 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
121 || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
122
123 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
124 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
125
126 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
127 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
128
129 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
131
132 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
133 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
134 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
135 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
136
137 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
138 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
139
140 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
141 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
142
143 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
159
160 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
161 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
162
163 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
164 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
165
166 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
167 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
168
169 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
185
186 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
187 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
188
189 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
190 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
191 /**
192 * @}
193 */
194
195
196 /* Private function prototypes -----------------------------------------------*/
197 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
198 * @{
199 */
200 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
201 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
205 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
206 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
207 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
208 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
209 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
210 /**
211 * @}
212 */
213
214 /* Exported functions --------------------------------------------------------*/
215 /** @addtogroup TIM_LL_Exported_Functions
216 * @{
217 */
218
219 /** @addtogroup TIM_LL_EF_Init
220 * @{
221 */
222
223 /**
224 * @brief Set TIMx registers to their reset values.
225 * @param TIMx Timer instance
226 * @retval An ErrorStatus enumeration value:
227 * - SUCCESS: TIMx registers are de-initialized
228 * - ERROR: invalid TIMx instance
229 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)230 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
231 {
232 ErrorStatus result = SUCCESS;
233
234 /* Check the parameters */
235 assert_param(IS_TIM_INSTANCE(TIMx));
236
237 if (TIMx == TIM1)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
241 }
242 else if (TIMx == TIM2)
243 {
244 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
245 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
246 }
247 else if (TIMx == TIM3)
248 {
249 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
250 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
251 }
252 else if (TIMx == TIM4)
253 {
254 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
255 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
256 }
257 #if defined(TIM5)
258 else if (TIMx == TIM5)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
262 }
263 #endif /* TIM5 */
264 else if (TIMx == TIM6)
265 {
266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
267 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
268 }
269 else if (TIMx == TIM7)
270 {
271 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
272 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
273 }
274 else if (TIMx == TIM8)
275 {
276 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
277 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
278 }
279 else if (TIMx == TIM15)
280 {
281 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
282 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
283 }
284 else if (TIMx == TIM16)
285 {
286 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
287 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
288 }
289 else if (TIMx == TIM17)
290 {
291 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
292 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
293 }
294 #if defined(TIM20)
295 else if (TIMx == TIM20)
296 {
297 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
298 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
299 }
300 #endif /* TIM20 */
301 else
302 {
303 result = ERROR;
304 }
305
306 return result;
307 }
308
309 /**
310 * @brief Set the fields of the time base unit configuration data structure
311 * to their default values.
312 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
313 * @retval None
314 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)315 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
316 {
317 /* Set the default configuration */
318 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
319 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
320 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
321 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
322 TIM_InitStruct->RepetitionCounter = 0x00000000U;
323 }
324
325 /**
326 * @brief Configure the TIMx time base unit.
327 * @param TIMx Timer Instance
328 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
329 * (TIMx time base unit configuration data structure)
330 * @retval An ErrorStatus enumeration value:
331 * - SUCCESS: TIMx registers are de-initialized
332 * - ERROR: not applicable
333 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)334 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
335 {
336 uint32_t tmpcr1;
337
338 /* Check the parameters */
339 assert_param(IS_TIM_INSTANCE(TIMx));
340 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
341 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
342
343 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
344
345 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
346 {
347 /* Select the Counter Mode */
348 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
349 }
350
351 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
352 {
353 /* Set the clock division */
354 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
355 }
356
357 /* Write to TIMx CR1 */
358 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
359
360 /* Set the Autoreload value */
361 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
362
363 /* Set the Prescaler value */
364 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
365
366 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
367 {
368 /* Set the Repetition Counter value */
369 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
370 }
371
372 /* Generate an update event to reload the Prescaler
373 and the repetition counter value (if applicable) immediately */
374 LL_TIM_GenerateEvent_UPDATE(TIMx);
375
376 return SUCCESS;
377 }
378
379 /**
380 * @brief Set the fields of the TIMx output channel configuration data
381 * structure to their default values.
382 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
383 * (the output channel configuration data structure)
384 * @retval None
385 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)386 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
387 {
388 /* Set the default configuration */
389 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
390 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
391 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
392 TIM_OC_InitStruct->CompareValue = 0x00000000U;
393 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
394 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
395 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
396 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
397 }
398
399 /**
400 * @brief Configure the TIMx output channel.
401 * @param TIMx Timer Instance
402 * @param Channel This parameter can be one of the following values:
403 * @arg @ref LL_TIM_CHANNEL_CH1
404 * @arg @ref LL_TIM_CHANNEL_CH2
405 * @arg @ref LL_TIM_CHANNEL_CH3
406 * @arg @ref LL_TIM_CHANNEL_CH4
407 * @arg @ref LL_TIM_CHANNEL_CH5
408 * @arg @ref LL_TIM_CHANNEL_CH6
409 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
410 * data structure)
411 * @retval An ErrorStatus enumeration value:
412 * - SUCCESS: TIMx output channel is initialized
413 * - ERROR: TIMx output channel is not initialized
414 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)415 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
416 {
417 ErrorStatus result = ERROR;
418
419 switch (Channel)
420 {
421 case LL_TIM_CHANNEL_CH1:
422 result = OC1Config(TIMx, TIM_OC_InitStruct);
423 break;
424 case LL_TIM_CHANNEL_CH2:
425 result = OC2Config(TIMx, TIM_OC_InitStruct);
426 break;
427 case LL_TIM_CHANNEL_CH3:
428 result = OC3Config(TIMx, TIM_OC_InitStruct);
429 break;
430 case LL_TIM_CHANNEL_CH4:
431 result = OC4Config(TIMx, TIM_OC_InitStruct);
432 break;
433 case LL_TIM_CHANNEL_CH5:
434 result = OC5Config(TIMx, TIM_OC_InitStruct);
435 break;
436 case LL_TIM_CHANNEL_CH6:
437 result = OC6Config(TIMx, TIM_OC_InitStruct);
438 break;
439 default:
440 break;
441 }
442
443 return result;
444 }
445
446 /**
447 * @brief Set the fields of the TIMx input channel configuration data
448 * structure to their default values.
449 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
450 * data structure)
451 * @retval None
452 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)453 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
454 {
455 /* Set the default configuration */
456 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
457 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
458 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
459 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
460 }
461
462 /**
463 * @brief Configure the TIMx input channel.
464 * @param TIMx Timer Instance
465 * @param Channel This parameter can be one of the following values:
466 * @arg @ref LL_TIM_CHANNEL_CH1
467 * @arg @ref LL_TIM_CHANNEL_CH2
468 * @arg @ref LL_TIM_CHANNEL_CH3
469 * @arg @ref LL_TIM_CHANNEL_CH4
470 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
471 * structure)
472 * @retval An ErrorStatus enumeration value:
473 * - SUCCESS: TIMx output channel is initialized
474 * - ERROR: TIMx output channel is not initialized
475 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)476 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
477 {
478 ErrorStatus result = ERROR;
479
480 switch (Channel)
481 {
482 case LL_TIM_CHANNEL_CH1:
483 result = IC1Config(TIMx, TIM_IC_InitStruct);
484 break;
485 case LL_TIM_CHANNEL_CH2:
486 result = IC2Config(TIMx, TIM_IC_InitStruct);
487 break;
488 case LL_TIM_CHANNEL_CH3:
489 result = IC3Config(TIMx, TIM_IC_InitStruct);
490 break;
491 case LL_TIM_CHANNEL_CH4:
492 result = IC4Config(TIMx, TIM_IC_InitStruct);
493 break;
494 default:
495 break;
496 }
497
498 return result;
499 }
500
501 /**
502 * @brief Fills each TIM_EncoderInitStruct field with its default value
503 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
504 * configuration data structure)
505 * @retval None
506 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)507 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
508 {
509 /* Set the default configuration */
510 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
511 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
512 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
513 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
514 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
515 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
516 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
517 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
518 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
519 }
520
521 /**
522 * @brief Configure the encoder interface of the timer instance.
523 * @param TIMx Timer Instance
524 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
525 * configuration data structure)
526 * @retval An ErrorStatus enumeration value:
527 * - SUCCESS: TIMx registers are de-initialized
528 * - ERROR: not applicable
529 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)530 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
531 {
532 uint32_t tmpccmr1;
533 uint32_t tmpccer;
534
535 /* Check the parameters */
536 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
537 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
538 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
539 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
540 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
541 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
542 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
543 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
544 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
545 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
546
547 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
548 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
549
550 /* Get the TIMx CCMR1 register value */
551 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
552
553 /* Get the TIMx CCER register value */
554 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
555
556 /* Configure TI1 */
557 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
558 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
559 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
560 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
561
562 /* Configure TI2 */
563 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
564 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
565 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
566 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
567
568 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
569 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
570 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
571 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
572 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
573
574 /* Set encoder mode */
575 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
576
577 /* Write to TIMx CCMR1 */
578 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
579
580 /* Write to TIMx CCER */
581 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
582
583 return SUCCESS;
584 }
585
586 /**
587 * @brief Set the fields of the TIMx Hall sensor interface configuration data
588 * structure to their default values.
589 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
590 * configuration data structure)
591 * @retval None
592 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)593 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
594 {
595 /* Set the default configuration */
596 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
597 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
598 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
599 TIM_HallSensorInitStruct->CommutationDelay = 0U;
600 }
601
602 /**
603 * @brief Configure the Hall sensor interface of the timer instance.
604 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
605 * to the TI1 input channel
606 * @note TIMx slave mode controller is configured in reset mode.
607 Selected internal trigger is TI1F_ED.
608 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
609 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
610 * between 2 changes on the inputs. It gives information about motor speed.
611 * @note Channel 2 is configured in output PWM 2 mode.
612 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
613 * @note OC2REF is selected as trigger output on TRGO.
614 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
615 * when TIMx operates in Hall sensor interface mode.
616 * @param TIMx Timer Instance
617 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
618 * interface configuration data structure)
619 * @retval An ErrorStatus enumeration value:
620 * - SUCCESS: TIMx registers are de-initialized
621 * - ERROR: not applicable
622 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)623 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
624 {
625 uint32_t tmpcr2;
626 uint32_t tmpccmr1;
627 uint32_t tmpccer;
628 uint32_t tmpsmcr;
629
630 /* Check the parameters */
631 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
632 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
633 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
634 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
635
636 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
637 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
638
639 /* Get the TIMx CR2 register value */
640 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
641
642 /* Get the TIMx CCMR1 register value */
643 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
644
645 /* Get the TIMx CCER register value */
646 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
647
648 /* Get the TIMx SMCR register value */
649 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
650
651 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
652 tmpcr2 |= TIM_CR2_TI1S;
653
654 /* OC2REF signal is used as trigger output (TRGO) */
655 tmpcr2 |= LL_TIM_TRGO_OC2REF;
656
657 /* Configure the slave mode controller */
658 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
659 tmpsmcr |= LL_TIM_TS_TI1F_ED;
660 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
661
662 /* Configure input channel 1 */
663 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
664 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
665 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
666 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
667
668 /* Configure input channel 2 */
669 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
670 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
671
672 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
673 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
674 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
675 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
676
677 /* Write to TIMx CR2 */
678 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
679
680 /* Write to TIMx SMCR */
681 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
682
683 /* Write to TIMx CCMR1 */
684 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
685
686 /* Write to TIMx CCER */
687 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
688
689 /* Write to TIMx CCR2 */
690 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
691
692 return SUCCESS;
693 }
694
695 /**
696 * @brief Set the fields of the Break and Dead Time configuration data structure
697 * to their default values.
698 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
699 * data structure)
700 * @retval None
701 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)702 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
703 {
704 /* Set the default configuration */
705 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
706 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
707 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
708 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
709 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
710 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
711 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
712 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
713 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
714 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
715 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
716 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
717 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
718 }
719
720 /**
721 * @brief Configure the Break and Dead Time feature of the timer instance.
722 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
723 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
724 * can be necessary to configure all of them during the first write access to
725 * the TIMx_BDTR register.
726 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
727 * a timer instance provides a break input.
728 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
729 * a timer instance provides a second break input.
730 * @param TIMx Timer Instance
731 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
732 * data structure)
733 * @retval An ErrorStatus enumeration value:
734 * - SUCCESS: Break and Dead Time is initialized
735 * - ERROR: not applicable
736 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)737 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
738 {
739 uint32_t tmpbdtr = 0;
740
741 /* Check the parameters */
742 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
743 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
744 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
745 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
746 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
747 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
748 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
749 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
750 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
751
752 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
753 the OSSI State, the dead time value and the Automatic Output Enable Bit */
754
755 /* Set the BDTR bits */
756 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
757 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
758 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
759 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
760 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
761 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
762 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
763 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
764 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
765
766 if (IS_TIM_BKIN2_INSTANCE(TIMx))
767 {
768 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
769 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
770 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
771 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
772
773 /* Set the BREAK2 input related BDTR bit-fields */
774 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
775 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
776 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
777 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
778 }
779
780 /* Set TIMx_BDTR */
781 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
782
783 return SUCCESS;
784 }
785 /**
786 * @}
787 */
788
789 /**
790 * @}
791 */
792
793 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
794 * @brief Private functions
795 * @{
796 */
797 /**
798 * @brief Configure the TIMx output channel 1.
799 * @param TIMx Timer Instance
800 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
801 * @retval An ErrorStatus enumeration value:
802 * - SUCCESS: TIMx registers are de-initialized
803 * - ERROR: not applicable
804 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)805 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
806 {
807 uint32_t tmpccmr1;
808 uint32_t tmpccer;
809 uint32_t tmpcr2;
810
811 /* Check the parameters */
812 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
813 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
814 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
815 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
816
817 /* Disable the Channel 1: Reset the CC1E Bit */
818 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
819
820 /* Get the TIMx CCER register value */
821 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
822
823 /* Get the TIMx CR2 register value */
824 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
825
826 /* Get the TIMx CCMR1 register value */
827 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
828
829 /* Reset Capture/Compare selection Bits */
830 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
831
832 /* Set the Output Compare Mode */
833 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
834
835 /* Set the Output Compare Polarity */
836 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
837
838 /* Set the Output State */
839 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
840
841 if (IS_TIM_BREAK_INSTANCE(TIMx))
842 {
843 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
844 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
845 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
846 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
847
848 /* Set the complementary output Polarity */
849 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
850
851 /* Set the complementary output State */
852 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
853
854 /* Set the Output Idle state */
855 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
856
857 /* Set the complementary output Idle state */
858 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
859 }
860
861 /* Write to TIMx CR2 */
862 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
863
864 /* Write to TIMx CCMR1 */
865 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
866
867 /* Set the Capture Compare Register value */
868 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
869
870 /* Write to TIMx CCER */
871 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
872
873 return SUCCESS;
874 }
875
876 /**
877 * @brief Configure the TIMx output channel 2.
878 * @param TIMx Timer Instance
879 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
880 * @retval An ErrorStatus enumeration value:
881 * - SUCCESS: TIMx registers are de-initialized
882 * - ERROR: not applicable
883 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)884 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
885 {
886 uint32_t tmpccmr1;
887 uint32_t tmpccer;
888 uint32_t tmpcr2;
889
890 /* Check the parameters */
891 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
892 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
893 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
894 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
895
896 /* Disable the Channel 2: Reset the CC2E Bit */
897 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
898
899 /* Get the TIMx CCER register value */
900 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
901
902 /* Get the TIMx CR2 register value */
903 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
904
905 /* Get the TIMx CCMR1 register value */
906 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
907
908 /* Reset Capture/Compare selection Bits */
909 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
910
911 /* Select the Output Compare Mode */
912 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
913
914 /* Set the Output Compare Polarity */
915 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
916
917 /* Set the Output State */
918 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
919
920 if (IS_TIM_BREAK_INSTANCE(TIMx))
921 {
922 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
923 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
924 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
925 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
926
927 /* Set the complementary output Polarity */
928 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
929
930 /* Set the complementary output State */
931 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
932
933 /* Set the Output Idle state */
934 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
935
936 /* Set the complementary output Idle state */
937 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
938 }
939
940 /* Write to TIMx CR2 */
941 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
942
943 /* Write to TIMx CCMR1 */
944 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
945
946 /* Set the Capture Compare Register value */
947 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
948
949 /* Write to TIMx CCER */
950 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
951
952 return SUCCESS;
953 }
954
955 /**
956 * @brief Configure the TIMx output channel 3.
957 * @param TIMx Timer Instance
958 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
959 * @retval An ErrorStatus enumeration value:
960 * - SUCCESS: TIMx registers are de-initialized
961 * - ERROR: not applicable
962 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)963 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
964 {
965 uint32_t tmpccmr2;
966 uint32_t tmpccer;
967 uint32_t tmpcr2;
968
969 /* Check the parameters */
970 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
971 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
972 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
973 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
974
975 /* Disable the Channel 3: Reset the CC3E Bit */
976 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
977
978 /* Get the TIMx CCER register value */
979 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
980
981 /* Get the TIMx CR2 register value */
982 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
983
984 /* Get the TIMx CCMR2 register value */
985 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
986
987 /* Reset Capture/Compare selection Bits */
988 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
989
990 /* Select the Output Compare Mode */
991 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
992
993 /* Set the Output Compare Polarity */
994 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
995
996 /* Set the Output State */
997 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
998
999 if (IS_TIM_BREAK_INSTANCE(TIMx))
1000 {
1001 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1002 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1003 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1004 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1005
1006 /* Set the complementary output Polarity */
1007 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1008
1009 /* Set the complementary output State */
1010 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1011
1012 /* Set the Output Idle state */
1013 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1014
1015 /* Set the complementary output Idle state */
1016 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1017 }
1018
1019 /* Write to TIMx CR2 */
1020 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1021
1022 /* Write to TIMx CCMR2 */
1023 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1024
1025 /* Set the Capture Compare Register value */
1026 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1027
1028 /* Write to TIMx CCER */
1029 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1030
1031 return SUCCESS;
1032 }
1033
1034 /**
1035 * @brief Configure the TIMx output channel 4.
1036 * @param TIMx Timer Instance
1037 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1038 * @retval An ErrorStatus enumeration value:
1039 * - SUCCESS: TIMx registers are de-initialized
1040 * - ERROR: not applicable
1041 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1042 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1043 {
1044 uint32_t tmpccmr2;
1045 uint32_t tmpccer;
1046 uint32_t tmpcr2;
1047
1048 /* Check the parameters */
1049 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1050 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1051 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1052 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1053
1054 /* Disable the Channel 4: Reset the CC4E Bit */
1055 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1056
1057 /* Get the TIMx CCER register value */
1058 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1059
1060 /* Get the TIMx CR2 register value */
1061 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1062
1063 /* Get the TIMx CCMR2 register value */
1064 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1065
1066 /* Reset Capture/Compare selection Bits */
1067 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1068
1069 /* Select the Output Compare Mode */
1070 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1071
1072 /* Set the Output Compare Polarity */
1073 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1074
1075 /* Set the Output State */
1076 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1077
1078 if (IS_TIM_BREAK_INSTANCE(TIMx))
1079 {
1080 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1081 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1082 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1083 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1084
1085 /* Set the complementary output Polarity */
1086 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1087
1088 /* Set the complementary output State */
1089 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1090
1091 /* Set the Output Idle state */
1092 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1093
1094 /* Set the complementary output Idle state */
1095 MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1096 }
1097
1098 /* Write to TIMx CR2 */
1099 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1100
1101 /* Write to TIMx CCMR2 */
1102 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1103
1104 /* Set the Capture Compare Register value */
1105 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1106
1107 /* Write to TIMx CCER */
1108 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1109
1110 return SUCCESS;
1111 }
1112
1113 /**
1114 * @brief Configure the TIMx output channel 5.
1115 * @param TIMx Timer Instance
1116 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1117 * @retval An ErrorStatus enumeration value:
1118 * - SUCCESS: TIMx registers are de-initialized
1119 * - ERROR: not applicable
1120 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1121 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1122 {
1123 uint32_t tmpccmr3;
1124 uint32_t tmpccer;
1125
1126 /* Check the parameters */
1127 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1128 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1129 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1130 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1131 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1132 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1133
1134 /* Disable the Channel 5: Reset the CC5E Bit */
1135 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1136
1137 /* Get the TIMx CCER register value */
1138 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1139
1140 /* Get the TIMx CCMR3 register value */
1141 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1142
1143 /* Select the Output Compare Mode */
1144 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1145
1146 /* Set the Output Compare Polarity */
1147 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1148
1149 /* Set the Output State */
1150 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1151
1152 if (IS_TIM_BREAK_INSTANCE(TIMx))
1153 {
1154 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1155 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1156
1157 /* Set the Output Idle state */
1158 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1159
1160 }
1161
1162 /* Write to TIMx CCMR3 */
1163 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1164
1165 /* Set the Capture Compare Register value */
1166 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1167
1168 /* Write to TIMx CCER */
1169 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1170
1171 return SUCCESS;
1172 }
1173
1174 /**
1175 * @brief Configure the TIMx output channel 6.
1176 * @param TIMx Timer Instance
1177 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1178 * @retval An ErrorStatus enumeration value:
1179 * - SUCCESS: TIMx registers are de-initialized
1180 * - ERROR: not applicable
1181 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1182 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1183 {
1184 uint32_t tmpccmr3;
1185 uint32_t tmpccer;
1186
1187 /* Check the parameters */
1188 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1189 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1190 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1191 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1192 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1193 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1194
1195 /* Disable the Channel 5: Reset the CC6E Bit */
1196 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1197
1198 /* Get the TIMx CCER register value */
1199 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1200
1201 /* Get the TIMx CCMR3 register value */
1202 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1203
1204 /* Select the Output Compare Mode */
1205 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1206
1207 /* Set the Output Compare Polarity */
1208 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1209
1210 /* Set the Output State */
1211 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1212
1213 if (IS_TIM_BREAK_INSTANCE(TIMx))
1214 {
1215 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1216 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1217
1218 /* Set the Output Idle state */
1219 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1220 }
1221
1222 /* Write to TIMx CCMR3 */
1223 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1224
1225 /* Set the Capture Compare Register value */
1226 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1227
1228 /* Write to TIMx CCER */
1229 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1230
1231 return SUCCESS;
1232 }
1233
1234 /**
1235 * @brief Configure the TIMx input channel 1.
1236 * @param TIMx Timer Instance
1237 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1238 * @retval An ErrorStatus enumeration value:
1239 * - SUCCESS: TIMx registers are de-initialized
1240 * - ERROR: not applicable
1241 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1242 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1243 {
1244 /* Check the parameters */
1245 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1246 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1247 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1248 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1249 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1250
1251 /* Disable the Channel 1: Reset the CC1E Bit */
1252 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1253
1254 /* Select the Input and set the filter and the prescaler value */
1255 MODIFY_REG(TIMx->CCMR1,
1256 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1257 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1258
1259 /* Select the Polarity and set the CC1E Bit */
1260 MODIFY_REG(TIMx->CCER,
1261 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1262 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1263
1264 return SUCCESS;
1265 }
1266
1267 /**
1268 * @brief Configure the TIMx input channel 2.
1269 * @param TIMx Timer Instance
1270 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1271 * @retval An ErrorStatus enumeration value:
1272 * - SUCCESS: TIMx registers are de-initialized
1273 * - ERROR: not applicable
1274 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1275 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1276 {
1277 /* Check the parameters */
1278 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1279 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1280 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1281 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1282 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1283
1284 /* Disable the Channel 2: Reset the CC2E Bit */
1285 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1286
1287 /* Select the Input and set the filter and the prescaler value */
1288 MODIFY_REG(TIMx->CCMR1,
1289 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1290 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1291
1292 /* Select the Polarity and set the CC2E Bit */
1293 MODIFY_REG(TIMx->CCER,
1294 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1295 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1296
1297 return SUCCESS;
1298 }
1299
1300 /**
1301 * @brief Configure the TIMx input channel 3.
1302 * @param TIMx Timer Instance
1303 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1304 * @retval An ErrorStatus enumeration value:
1305 * - SUCCESS: TIMx registers are de-initialized
1306 * - ERROR: not applicable
1307 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1308 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1309 {
1310 /* Check the parameters */
1311 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1312 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1313 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1314 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1315 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1316
1317 /* Disable the Channel 3: Reset the CC3E Bit */
1318 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1319
1320 /* Select the Input and set the filter and the prescaler value */
1321 MODIFY_REG(TIMx->CCMR2,
1322 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1323 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1324
1325 /* Select the Polarity and set the CC3E Bit */
1326 MODIFY_REG(TIMx->CCER,
1327 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1328 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1329
1330 return SUCCESS;
1331 }
1332
1333 /**
1334 * @brief Configure the TIMx input channel 4.
1335 * @param TIMx Timer Instance
1336 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1337 * @retval An ErrorStatus enumeration value:
1338 * - SUCCESS: TIMx registers are de-initialized
1339 * - ERROR: not applicable
1340 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1341 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1342 {
1343 /* Check the parameters */
1344 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1345 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1346 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1347 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1348 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1349
1350 /* Disable the Channel 4: Reset the CC4E Bit */
1351 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1352
1353 /* Select the Input and set the filter and the prescaler value */
1354 MODIFY_REG(TIMx->CCMR2,
1355 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1356 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1357
1358 /* Select the Polarity and set the CC4E Bit */
1359 MODIFY_REG(TIMx->CCER,
1360 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1361 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1362
1363 return SUCCESS;
1364 }
1365
1366
1367 /**
1368 * @}
1369 */
1370
1371 /**
1372 * @}
1373 */
1374
1375 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
1376
1377 /**
1378 * @}
1379 */
1380
1381 #endif /* USE_FULL_LL_DRIVER */
1382
1383
