1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2019 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (overridden) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (overridden) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
95 and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 or HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (overridden) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32g4xx_hal.h"
117
118 #if defined(FMC_BANK1)
119
120 /** @addtogroup STM32G4xx_HAL_Driver
121 * @{
122 */
123
124 #ifdef HAL_SRAM_MODULE_ENABLED
125
126 /** @defgroup SRAM SRAM
127 * @brief SRAM driver modules
128 * @{
129 */
130
131 /* Private typedef -----------------------------------------------------------*/
132 /* Private define ------------------------------------------------------------*/
133 /* Private macro -------------------------------------------------------------*/
134 /* Private variables ---------------------------------------------------------*/
135 /* Private function prototypes -----------------------------------------------*/
136 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
137 * @{
138 */
139 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
140 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
141 static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
142 /**
143 * @}
144 */
145
146 /* Exported functions --------------------------------------------------------*/
147
148 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
149 * @{
150 */
151
152 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
153 * @brief Initialization and Configuration functions.
154 *
155 @verbatim
156 ==============================================================================
157 ##### SRAM Initialization and de_initialization functions #####
158 ==============================================================================
159 [..] This section provides functions allowing to initialize/de-initialize
160 the SRAM memory
161
162 @endverbatim
163 * @{
164 */
165
166 /**
167 * @brief Performs the SRAM device initialization sequence
168 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
169 * the configuration information for SRAM module.
170 * @param Timing Pointer to SRAM control timing structure
171 * @param ExtTiming Pointer to SRAM extended mode timing structure
172 * @retval HAL status
173 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)174 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
175 FMC_NORSRAM_TimingTypeDef *ExtTiming)
176 {
177 /* Check the SRAM handle parameter */
178 if (hsram == NULL)
179 {
180 return HAL_ERROR;
181 }
182
183 if (hsram->State == HAL_SRAM_STATE_RESET)
184 {
185 /* Allocate lock resource and initialize it */
186 hsram->Lock = HAL_UNLOCKED;
187
188 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
189 if (hsram->MspInitCallback == NULL)
190 {
191 hsram->MspInitCallback = HAL_SRAM_MspInit;
192 }
193 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
194 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
195
196 /* Init the low level hardware */
197 hsram->MspInitCallback(hsram);
198 #else
199 /* Initialize the low level hardware (MSP) */
200 HAL_SRAM_MspInit(hsram);
201 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
202 }
203
204 /* Initialize SRAM control Interface */
205 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
206
207 /* Initialize SRAM timing Interface */
208 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
209
210 /* Initialize SRAM extended mode timing Interface */
211 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
212 hsram->Init.ExtendedMode);
213
214 /* Enable the NORSRAM device */
215 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
216
217 /* Initialize the SRAM controller state */
218 hsram->State = HAL_SRAM_STATE_READY;
219
220 return HAL_OK;
221 }
222
223 /**
224 * @brief Performs the SRAM device De-initialization sequence.
225 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
226 * the configuration information for SRAM module.
227 * @retval HAL status
228 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)229 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
230 {
231 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
232 if (hsram->MspDeInitCallback == NULL)
233 {
234 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
235 }
236
237 /* DeInit the low level hardware */
238 hsram->MspDeInitCallback(hsram);
239 #else
240 /* De-Initialize the low level hardware (MSP) */
241 HAL_SRAM_MspDeInit(hsram);
242 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
243
244 /* Configure the SRAM registers with their reset values */
245 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
246
247 /* Reset the SRAM controller state */
248 hsram->State = HAL_SRAM_STATE_RESET;
249
250 /* Release Lock */
251 __HAL_UNLOCK(hsram);
252
253 return HAL_OK;
254 }
255
256 /**
257 * @brief SRAM MSP Init.
258 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
259 * the configuration information for SRAM module.
260 * @retval None
261 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)262 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
263 {
264 /* Prevent unused argument(s) compilation warning */
265 UNUSED(hsram);
266
267 /* NOTE : This function Should not be modified, when the callback is needed,
268 the HAL_SRAM_MspInit could be implemented in the user file
269 */
270 }
271
272 /**
273 * @brief SRAM MSP DeInit.
274 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
275 * the configuration information for SRAM module.
276 * @retval None
277 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)278 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
279 {
280 /* Prevent unused argument(s) compilation warning */
281 UNUSED(hsram);
282
283 /* NOTE : This function Should not be modified, when the callback is needed,
284 the HAL_SRAM_MspDeInit could be implemented in the user file
285 */
286 }
287
288 /**
289 * @brief DMA transfer complete callback.
290 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
291 * the configuration information for SRAM module.
292 * @retval None
293 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)294 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
295 {
296 /* Prevent unused argument(s) compilation warning */
297 UNUSED(hdma);
298
299 /* NOTE : This function Should not be modified, when the callback is needed,
300 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
301 */
302 }
303
304 /**
305 * @brief DMA transfer complete error callback.
306 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
307 * the configuration information for SRAM module.
308 * @retval None
309 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)310 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
311 {
312 /* Prevent unused argument(s) compilation warning */
313 UNUSED(hdma);
314
315 /* NOTE : This function Should not be modified, when the callback is needed,
316 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
317 */
318 }
319
320 /**
321 * @}
322 */
323
324 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
325 * @brief Input Output and memory control functions
326 *
327 @verbatim
328 ==============================================================================
329 ##### SRAM Input and Output functions #####
330 ==============================================================================
331 [..]
332 This section provides functions allowing to use and control the SRAM memory
333
334 @endverbatim
335 * @{
336 */
337
338 /**
339 * @brief Reads 8-bit buffer from SRAM memory.
340 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
341 * the configuration information for SRAM module.
342 * @param pAddress Pointer to read start address
343 * @param pDstBuffer Pointer to destination buffer
344 * @param BufferSize Size of the buffer to read from memory
345 * @retval HAL status
346 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)347 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
348 uint32_t BufferSize)
349 {
350 uint32_t size;
351 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
352 uint8_t *pdestbuff = pDstBuffer;
353 HAL_SRAM_StateTypeDef state = hsram->State;
354
355 /* Check the SRAM controller state */
356 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
357 {
358 /* Process Locked */
359 __HAL_LOCK(hsram);
360
361 /* Update the SRAM controller state */
362 hsram->State = HAL_SRAM_STATE_BUSY;
363
364 /* Read data from memory */
365 for (size = BufferSize; size != 0U; size--)
366 {
367 *pdestbuff = *psramaddress;
368 pdestbuff++;
369 psramaddress++;
370 }
371
372 /* Update the SRAM controller state */
373 hsram->State = state;
374
375 /* Process unlocked */
376 __HAL_UNLOCK(hsram);
377 }
378 else
379 {
380 return HAL_ERROR;
381 }
382
383 return HAL_OK;
384 }
385
386 /**
387 * @brief Writes 8-bit buffer to SRAM memory.
388 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
389 * the configuration information for SRAM module.
390 * @param pAddress Pointer to write start address
391 * @param pSrcBuffer Pointer to source buffer to write
392 * @param BufferSize Size of the buffer to write to memory
393 * @retval HAL status
394 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)395 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
396 uint32_t BufferSize)
397 {
398 uint32_t size;
399 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
400 uint8_t *psrcbuff = pSrcBuffer;
401
402 /* Check the SRAM controller state */
403 if (hsram->State == HAL_SRAM_STATE_READY)
404 {
405 /* Process Locked */
406 __HAL_LOCK(hsram);
407
408 /* Update the SRAM controller state */
409 hsram->State = HAL_SRAM_STATE_BUSY;
410
411 /* Write data to memory */
412 for (size = BufferSize; size != 0U; size--)
413 {
414 *psramaddress = *psrcbuff;
415 psrcbuff++;
416 psramaddress++;
417 }
418
419 /* Update the SRAM controller state */
420 hsram->State = HAL_SRAM_STATE_READY;
421
422 /* Process unlocked */
423 __HAL_UNLOCK(hsram);
424 }
425 else
426 {
427 return HAL_ERROR;
428 }
429
430 return HAL_OK;
431 }
432
433 /**
434 * @brief Reads 16-bit buffer from SRAM memory.
435 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
436 * the configuration information for SRAM module.
437 * @param pAddress Pointer to read start address
438 * @param pDstBuffer Pointer to destination buffer
439 * @param BufferSize Size of the buffer to read from memory
440 * @retval HAL status
441 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)442 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
443 uint32_t BufferSize)
444 {
445 uint32_t size;
446 __IO uint32_t *psramaddress = pAddress;
447 uint16_t *pdestbuff = pDstBuffer;
448 uint8_t limit;
449 HAL_SRAM_StateTypeDef state = hsram->State;
450
451 /* Check the SRAM controller state */
452 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
453 {
454 /* Process Locked */
455 __HAL_LOCK(hsram);
456
457 /* Update the SRAM controller state */
458 hsram->State = HAL_SRAM_STATE_BUSY;
459
460 /* Check if the size is a 32-bits multiple */
461 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
462
463 /* Read data from memory */
464 for (size = BufferSize; size != limit; size -= 2U)
465 {
466 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
467 pdestbuff++;
468 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
469 pdestbuff++;
470 psramaddress++;
471 }
472
473 /* Read last 16-bits if size is not 32-bits multiple */
474 if (limit != 0U)
475 {
476 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
477 }
478
479 /* Update the SRAM controller state */
480 hsram->State = state;
481
482 /* Process unlocked */
483 __HAL_UNLOCK(hsram);
484 }
485 else
486 {
487 return HAL_ERROR;
488 }
489
490 return HAL_OK;
491 }
492
493 /**
494 * @brief Writes 16-bit buffer to SRAM memory.
495 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
496 * the configuration information for SRAM module.
497 * @param pAddress Pointer to write start address
498 * @param pSrcBuffer Pointer to source buffer to write
499 * @param BufferSize Size of the buffer to write to memory
500 * @retval HAL status
501 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)502 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
503 uint32_t BufferSize)
504 {
505 uint32_t size;
506 __IO uint32_t *psramaddress = pAddress;
507 uint16_t *psrcbuff = pSrcBuffer;
508 uint8_t limit;
509
510 /* Check the SRAM controller state */
511 if (hsram->State == HAL_SRAM_STATE_READY)
512 {
513 /* Process Locked */
514 __HAL_LOCK(hsram);
515
516 /* Update the SRAM controller state */
517 hsram->State = HAL_SRAM_STATE_BUSY;
518
519 /* Check if the size is a 32-bits multiple */
520 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
521
522 /* Write data to memory */
523 for (size = BufferSize; size != limit; size -= 2U)
524 {
525 *psramaddress = (uint32_t)(*psrcbuff);
526 psrcbuff++;
527 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
528 psrcbuff++;
529 psramaddress++;
530 }
531
532 /* Write last 16-bits if size is not 32-bits multiple */
533 if (limit != 0U)
534 {
535 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
536 }
537
538 /* Update the SRAM controller state */
539 hsram->State = HAL_SRAM_STATE_READY;
540
541 /* Process unlocked */
542 __HAL_UNLOCK(hsram);
543 }
544 else
545 {
546 return HAL_ERROR;
547 }
548
549 return HAL_OK;
550 }
551
552 /**
553 * @brief Reads 32-bit buffer from SRAM memory.
554 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
555 * the configuration information for SRAM module.
556 * @param pAddress Pointer to read start address
557 * @param pDstBuffer Pointer to destination buffer
558 * @param BufferSize Size of the buffer to read from memory
559 * @retval HAL status
560 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)561 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
562 uint32_t BufferSize)
563 {
564 uint32_t size;
565 __IO uint32_t *psramaddress = pAddress;
566 uint32_t *pdestbuff = pDstBuffer;
567 HAL_SRAM_StateTypeDef state = hsram->State;
568
569 /* Check the SRAM controller state */
570 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
571 {
572 /* Process Locked */
573 __HAL_LOCK(hsram);
574
575 /* Update the SRAM controller state */
576 hsram->State = HAL_SRAM_STATE_BUSY;
577
578 /* Read data from memory */
579 for (size = BufferSize; size != 0U; size--)
580 {
581 *pdestbuff = *psramaddress;
582 pdestbuff++;
583 psramaddress++;
584 }
585
586 /* Update the SRAM controller state */
587 hsram->State = state;
588
589 /* Process unlocked */
590 __HAL_UNLOCK(hsram);
591 }
592 else
593 {
594 return HAL_ERROR;
595 }
596
597 return HAL_OK;
598 }
599
600 /**
601 * @brief Writes 32-bit buffer to SRAM memory.
602 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
603 * the configuration information for SRAM module.
604 * @param pAddress Pointer to write start address
605 * @param pSrcBuffer Pointer to source buffer to write
606 * @param BufferSize Size of the buffer to write to memory
607 * @retval HAL status
608 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)609 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
610 uint32_t BufferSize)
611 {
612 uint32_t size;
613 __IO uint32_t *psramaddress = pAddress;
614 uint32_t *psrcbuff = pSrcBuffer;
615
616 /* Check the SRAM controller state */
617 if (hsram->State == HAL_SRAM_STATE_READY)
618 {
619 /* Process Locked */
620 __HAL_LOCK(hsram);
621
622 /* Update the SRAM controller state */
623 hsram->State = HAL_SRAM_STATE_BUSY;
624
625 /* Write data to memory */
626 for (size = BufferSize; size != 0U; size--)
627 {
628 *psramaddress = *psrcbuff;
629 psrcbuff++;
630 psramaddress++;
631 }
632
633 /* Update the SRAM controller state */
634 hsram->State = HAL_SRAM_STATE_READY;
635
636 /* Process unlocked */
637 __HAL_UNLOCK(hsram);
638 }
639 else
640 {
641 return HAL_ERROR;
642 }
643
644 return HAL_OK;
645 }
646
647 /**
648 * @brief Reads a Words data from the SRAM memory using DMA transfer.
649 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
650 * the configuration information for SRAM module.
651 * @param pAddress Pointer to read start address
652 * @param pDstBuffer Pointer to destination buffer
653 * @param BufferSize Size of the buffer to read from memory
654 * @retval HAL status
655 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)656 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
657 uint32_t BufferSize)
658 {
659 HAL_StatusTypeDef status;
660 HAL_SRAM_StateTypeDef state = hsram->State;
661
662 /* Check the SRAM controller state */
663 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
664 {
665 /* Process Locked */
666 __HAL_LOCK(hsram);
667
668 /* Update the SRAM controller state */
669 hsram->State = HAL_SRAM_STATE_BUSY;
670
671 /* Configure DMA user callbacks */
672 if (state == HAL_SRAM_STATE_READY)
673 {
674 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
675 }
676 else
677 {
678 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
679 }
680 hsram->hdma->XferErrorCallback = SRAM_DMAError;
681
682 /* Enable the DMA Stream */
683 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
684
685 /* Process unlocked */
686 __HAL_UNLOCK(hsram);
687 }
688 else
689 {
690 status = HAL_ERROR;
691 }
692
693 return status;
694 }
695
696 /**
697 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
698 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
699 * the configuration information for SRAM module.
700 * @param pAddress Pointer to write start address
701 * @param pSrcBuffer Pointer to source buffer to write
702 * @param BufferSize Size of the buffer to write to memory
703 * @retval HAL status
704 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)705 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
706 uint32_t BufferSize)
707 {
708 HAL_StatusTypeDef status;
709
710 /* Check the SRAM controller state */
711 if (hsram->State == HAL_SRAM_STATE_READY)
712 {
713 /* Process Locked */
714 __HAL_LOCK(hsram);
715
716 /* Update the SRAM controller state */
717 hsram->State = HAL_SRAM_STATE_BUSY;
718
719 /* Configure DMA user callbacks */
720 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
721 hsram->hdma->XferErrorCallback = SRAM_DMAError;
722
723 /* Enable the DMA Stream */
724 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
725
726 /* Process unlocked */
727 __HAL_UNLOCK(hsram);
728 }
729 else
730 {
731 status = HAL_ERROR;
732 }
733
734 return status;
735 }
736
737 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
738 /**
739 * @brief Register a User SRAM Callback
740 * To be used to override the weak predefined callback
741 * @param hsram : SRAM handle
742 * @param CallbackId : ID of the callback to be registered
743 * This parameter can be one of the following values:
744 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
745 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
746 * @param pCallback : pointer to the Callback function
747 * @retval status
748 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)749 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
750 pSRAM_CallbackTypeDef pCallback)
751 {
752 HAL_StatusTypeDef status = HAL_OK;
753 HAL_SRAM_StateTypeDef state;
754
755 if (pCallback == NULL)
756 {
757 return HAL_ERROR;
758 }
759
760 state = hsram->State;
761 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
762 {
763 switch (CallbackId)
764 {
765 case HAL_SRAM_MSP_INIT_CB_ID :
766 hsram->MspInitCallback = pCallback;
767 break;
768 case HAL_SRAM_MSP_DEINIT_CB_ID :
769 hsram->MspDeInitCallback = pCallback;
770 break;
771 default :
772 /* update return status */
773 status = HAL_ERROR;
774 break;
775 }
776 }
777 else
778 {
779 /* update return status */
780 status = HAL_ERROR;
781 }
782
783 return status;
784 }
785
786 /**
787 * @brief Unregister a User SRAM Callback
788 * SRAM Callback is redirected to the weak predefined callback
789 * @param hsram : SRAM handle
790 * @param CallbackId : ID of the callback to be unregistered
791 * This parameter can be one of the following values:
792 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
793 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
794 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
795 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
796 * @retval status
797 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)798 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
799 {
800 HAL_StatusTypeDef status = HAL_OK;
801 HAL_SRAM_StateTypeDef state;
802
803 state = hsram->State;
804 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
805 {
806 switch (CallbackId)
807 {
808 case HAL_SRAM_MSP_INIT_CB_ID :
809 hsram->MspInitCallback = HAL_SRAM_MspInit;
810 break;
811 case HAL_SRAM_MSP_DEINIT_CB_ID :
812 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
813 break;
814 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
815 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
816 break;
817 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
818 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
819 break;
820 default :
821 /* update return status */
822 status = HAL_ERROR;
823 break;
824 }
825 }
826 else if (state == HAL_SRAM_STATE_RESET)
827 {
828 switch (CallbackId)
829 {
830 case HAL_SRAM_MSP_INIT_CB_ID :
831 hsram->MspInitCallback = HAL_SRAM_MspInit;
832 break;
833 case HAL_SRAM_MSP_DEINIT_CB_ID :
834 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
835 break;
836 default :
837 /* update return status */
838 status = HAL_ERROR;
839 break;
840 }
841 }
842 else
843 {
844 /* update return status */
845 status = HAL_ERROR;
846 }
847
848 return status;
849 }
850
851 /**
852 * @brief Register a User SRAM Callback for DMA transfers
853 * To be used to override the weak predefined callback
854 * @param hsram : SRAM handle
855 * @param CallbackId : ID of the callback to be registered
856 * This parameter can be one of the following values:
857 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
858 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
859 * @param pCallback : pointer to the Callback function
860 * @retval status
861 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)862 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
863 pSRAM_DmaCallbackTypeDef pCallback)
864 {
865 HAL_StatusTypeDef status = HAL_OK;
866 HAL_SRAM_StateTypeDef state;
867
868 if (pCallback == NULL)
869 {
870 return HAL_ERROR;
871 }
872
873 /* Process locked */
874 __HAL_LOCK(hsram);
875
876 state = hsram->State;
877 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
878 {
879 switch (CallbackId)
880 {
881 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
882 hsram->DmaXferCpltCallback = pCallback;
883 break;
884 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
885 hsram->DmaXferErrorCallback = pCallback;
886 break;
887 default :
888 /* update return status */
889 status = HAL_ERROR;
890 break;
891 }
892 }
893 else
894 {
895 /* update return status */
896 status = HAL_ERROR;
897 }
898
899 /* Release Lock */
900 __HAL_UNLOCK(hsram);
901 return status;
902 }
903 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
904
905 /**
906 * @}
907 */
908
909 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
910 * @brief Control functions
911 *
912 @verbatim
913 ==============================================================================
914 ##### SRAM Control functions #####
915 ==============================================================================
916 [..]
917 This subsection provides a set of functions allowing to control dynamically
918 the SRAM interface.
919
920 @endverbatim
921 * @{
922 */
923
924 /**
925 * @brief Enables dynamically SRAM write operation.
926 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
927 * the configuration information for SRAM module.
928 * @retval HAL status
929 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)930 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
931 {
932 /* Check the SRAM controller state */
933 if (hsram->State == HAL_SRAM_STATE_PROTECTED)
934 {
935 /* Process Locked */
936 __HAL_LOCK(hsram);
937
938 /* Update the SRAM controller state */
939 hsram->State = HAL_SRAM_STATE_BUSY;
940
941 /* Enable write operation */
942 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
943
944 /* Update the SRAM controller state */
945 hsram->State = HAL_SRAM_STATE_READY;
946
947 /* Process unlocked */
948 __HAL_UNLOCK(hsram);
949 }
950 else
951 {
952 return HAL_ERROR;
953 }
954
955 return HAL_OK;
956 }
957
958 /**
959 * @brief Disables dynamically SRAM write operation.
960 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
961 * the configuration information for SRAM module.
962 * @retval HAL status
963 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)964 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
965 {
966 /* Check the SRAM controller state */
967 if (hsram->State == HAL_SRAM_STATE_READY)
968 {
969 /* Process Locked */
970 __HAL_LOCK(hsram);
971
972 /* Update the SRAM controller state */
973 hsram->State = HAL_SRAM_STATE_BUSY;
974
975 /* Disable write operation */
976 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
977
978 /* Update the SRAM controller state */
979 hsram->State = HAL_SRAM_STATE_PROTECTED;
980
981 /* Process unlocked */
982 __HAL_UNLOCK(hsram);
983 }
984 else
985 {
986 return HAL_ERROR;
987 }
988
989 return HAL_OK;
990 }
991
992 /**
993 * @}
994 */
995
996 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
997 * @brief Peripheral State functions
998 *
999 @verbatim
1000 ==============================================================================
1001 ##### SRAM State functions #####
1002 ==============================================================================
1003 [..]
1004 This subsection permits to get in run-time the status of the SRAM controller
1005 and the data flow.
1006
1007 @endverbatim
1008 * @{
1009 */
1010
1011 /**
1012 * @brief Returns the SRAM controller state
1013 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1014 * the configuration information for SRAM module.
1015 * @retval HAL state
1016 */
HAL_SRAM_GetState(const SRAM_HandleTypeDef * hsram)1017 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
1018 {
1019 return hsram->State;
1020 }
1021
1022 /**
1023 * @}
1024 */
1025
1026 /**
1027 * @}
1028 */
1029
1030 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
1031 * @{
1032 */
1033
1034 /**
1035 * @brief DMA SRAM process complete callback.
1036 * @param hdma : DMA handle
1037 * @retval None
1038 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1039 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1040 {
1041 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1042
1043 /* Disable the DMA channel */
1044 __HAL_DMA_DISABLE(hdma);
1045
1046 /* Update the SRAM controller state */
1047 hsram->State = HAL_SRAM_STATE_READY;
1048
1049 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1050 hsram->DmaXferCpltCallback(hdma);
1051 #else
1052 HAL_SRAM_DMA_XferCpltCallback(hdma);
1053 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1054 }
1055
1056 /**
1057 * @brief DMA SRAM process complete callback.
1058 * @param hdma : DMA handle
1059 * @retval None
1060 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1061 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1062 {
1063 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1064
1065 /* Disable the DMA channel */
1066 __HAL_DMA_DISABLE(hdma);
1067
1068 /* Update the SRAM controller state */
1069 hsram->State = HAL_SRAM_STATE_PROTECTED;
1070
1071 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1072 hsram->DmaXferCpltCallback(hdma);
1073 #else
1074 HAL_SRAM_DMA_XferCpltCallback(hdma);
1075 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1076 }
1077
1078 /**
1079 * @brief DMA SRAM error callback.
1080 * @param hdma : DMA handle
1081 * @retval None
1082 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1083 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1084 {
1085 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1086
1087 /* Disable the DMA channel */
1088 __HAL_DMA_DISABLE(hdma);
1089
1090 /* Update the SRAM controller state */
1091 hsram->State = HAL_SRAM_STATE_ERROR;
1092
1093 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1094 hsram->DmaXferErrorCallback(hdma);
1095 #else
1096 HAL_SRAM_DMA_XferErrorCallback(hdma);
1097 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1098 }
1099
1100 /**
1101 * @}
1102 */
1103
1104 /**
1105 * @}
1106 */
1107
1108 #endif /* HAL_SRAM_MODULE_ENABLED */
1109
1110 /**
1111 * @}
1112 */
1113
1114 #endif /* FMC_BANK1 */
1115
