1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * Copyright (c) 2017 STMicroelectronics.
17 * All rights reserved.
18 *
19 * This software is licensed under terms that can be found in the LICENSE file
20 * in the root directory of this software component.
21 * If no LICENSE file comes with this software, it is provided AS-IS.
22 *
23 ******************************************************************************
24 @verbatim
25 ==============================================================================
26 ##### FMC peripheral features #####
27 ==============================================================================
28 [..] The Flexible memory controller (FMC) includes following memory controllers:
29 (+) The NOR/PSRAM memory controller
30 (+) The NAND memory controller
31 (+) The Synchronous DRAM (SDRAM) controller
32
33 [..] The FMC functional block makes the interface with synchronous and asynchronous static
34 memories and SDRAM memories. Its main purposes are:
35 (+) to translate AHB transactions into the appropriate external device protocol
36 (+) to meet the access time requirements of the external memory devices
37
38 [..] All external memories share the addresses, data and control signals with the controller.
39 Each external device is accessed by means of a unique Chip Select. The FMC performs
40 only one access at a time to an external device.
41 The main features of the FMC controller are the following:
42 (+) Interface with static-memory mapped devices including:
43 (++) Static random access memory (SRAM)
44 (++) Read-only memory (ROM)
45 (++) NOR Flash memory/OneNAND Flash memory
46 (++) PSRAM (4 memory banks)
47 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
48 data
49 (+) Interface with synchronous DRAM (SDRAM) memories
50 (+) Independent Chip Select control for each memory bank
51 (+) Independent configuration for each memory bank
52
53 @endverbatim
54 ******************************************************************************
55 */
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32f7xx_hal.h"
59
60 /** @addtogroup STM32F7xx_HAL_Driver
61 * @{
62 */
63 #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
64 || defined(HAL_SRAM_MODULE_ENABLED)
65
66 /** @defgroup FMC_LL FMC Low Layer
67 * @brief FMC driver modules
68 * @{
69 */
70
71 /* Private typedef -----------------------------------------------------------*/
72 /* Private define ------------------------------------------------------------*/
73
74 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
75 * @{
76 */
77
78 /* ----------------------- FMC registers bit mask --------------------------- */
79
80 /* --- BCR Register ---*/
81 /* BCR register clear mask */
82
83 /* --- BTR Register ---*/
84 /* BTR register clear mask */
85 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\
86 FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
87 FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\
88 FMC_BTR1_ACCMOD))
89
90 /* --- BWTR Register ---*/
91 /* BWTR register clear mask */
92 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\
93 FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
94 FMC_BWTR1_ACCMOD))
95
96 /* --- PCR Register ---*/
97 /* PCR register clear mask */
98 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
99 FMC_PCR_PTYP | FMC_PCR_PWID | \
100 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
101 FMC_PCR_TAR | FMC_PCR_ECCPS))
102 /* --- PMEM Register ---*/
103 /* PMEM register clear mask */
104 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 |\
105 FMC_PMEM_MEMHOLD3 | FMC_PMEM_MEMHIZ3))
106
107 /* --- PATT Register ---*/
108 /* PATT register clear mask */
109 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 |\
110 FMC_PATT_ATTHOLD3 | FMC_PATT_ATTHIZ3))
111
112
113 /* --- SDCR Register ---*/
114 /* SDCR register clear mask */
115 #define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \
116 FMC_SDCR1_MWID | FMC_SDCR1_NB | \
117 FMC_SDCR1_CAS | FMC_SDCR1_WP | \
118 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
119 FMC_SDCR1_RPIPE))
120
121 /* --- SDTR Register ---*/
122 /* SDTR register clear mask */
123 #define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \
124 FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \
125 FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
126 FMC_SDTR1_TRCD))
127
128 /**
129 * @}
130 */
131
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 /* Exported functions --------------------------------------------------------*/
136
137 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
138 * @{
139 */
140
141
142 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
143 * @brief NORSRAM Controller functions
144 *
145 @verbatim
146 ==============================================================================
147 ##### How to use NORSRAM device driver #####
148 ==============================================================================
149
150 [..]
151 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
152 to run the NORSRAM external devices.
153
154 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
155 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
156 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
157 (+) FMC NORSRAM bank extended timing configuration using the function
158 FMC_NORSRAM_Extended_Timing_Init()
159 (+) FMC NORSRAM bank enable/disable write operation using the functions
160 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
161
162 @endverbatim
163 * @{
164 */
165
166 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
167 * @brief Initialization and Configuration functions
168 *
169 @verbatim
170 ==============================================================================
171 ##### Initialization and de_initialization functions #####
172 ==============================================================================
173 [..]
174 This section provides functions allowing to:
175 (+) Initialize and configure the FMC NORSRAM interface
176 (+) De-initialize the FMC NORSRAM interface
177 (+) Configure the FMC clock and associated GPIOs
178
179 @endverbatim
180 * @{
181 */
182
183 /**
184 * @brief Initialize the FMC_NORSRAM device according to the specified
185 * control parameters in the FMC_NORSRAM_InitTypeDef
186 * @param Device Pointer to NORSRAM device instance
187 * @param Init Pointer to NORSRAM Initialization structure
188 * @retval HAL status
189 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)190 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
191 FMC_NORSRAM_InitTypeDef *Init)
192 {
193 uint32_t flashaccess;
194 uint32_t btcr_reg;
195 uint32_t mask;
196
197 /* Check the parameters */
198 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
199 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
200 assert_param(IS_FMC_MUX(Init->DataAddressMux));
201 assert_param(IS_FMC_MEMORY(Init->MemoryType));
202 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
203 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
204 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
205 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
206 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
207 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
208 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
209 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
210 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
211 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
212 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
213 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
214
215 /* Disable NORSRAM Device */
216 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
217
218 /* Set NORSRAM device control parameters */
219 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
220 {
221 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
222 }
223 else
224 {
225 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
226 }
227
228 btcr_reg = (flashaccess | \
229 Init->DataAddressMux | \
230 Init->MemoryType | \
231 Init->MemoryDataWidth | \
232 Init->BurstAccessMode | \
233 Init->WaitSignalPolarity | \
234 Init->WaitSignalActive | \
235 Init->WriteOperation | \
236 Init->WaitSignal | \
237 Init->ExtendedMode | \
238 Init->AsynchronousWait | \
239 Init->WriteBurst);
240
241 btcr_reg |= Init->ContinuousClock;
242 btcr_reg |= Init->WriteFifo;
243 btcr_reg |= Init->PageSize;
244
245 mask = (FMC_BCR1_MBKEN |
246 FMC_BCR1_MUXEN |
247 FMC_BCR1_MTYP |
248 FMC_BCR1_MWID |
249 FMC_BCR1_FACCEN |
250 FMC_BCR1_BURSTEN |
251 FMC_BCR1_WAITPOL |
252 FMC_BCR1_WAITCFG |
253 FMC_BCR1_WREN |
254 FMC_BCR1_WAITEN |
255 FMC_BCR1_EXTMOD |
256 FMC_BCR1_ASYNCWAIT |
257 FMC_BCR1_CBURSTRW);
258
259 mask |= FMC_BCR1_CCLKEN;
260 mask |= FMC_BCR1_WFDIS;
261 mask |= FMC_BCR1_CPSIZE;
262
263 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
264
265 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
266 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
267 {
268 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
269 }
270
271 if (Init->NSBank != FMC_NORSRAM_BANK1)
272 {
273 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
274 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
275 }
276
277 return HAL_OK;
278 }
279
280 /**
281 * @brief DeInitialize the FMC_NORSRAM peripheral
282 * @param Device Pointer to NORSRAM device instance
283 * @param ExDevice Pointer to NORSRAM extended mode device instance
284 * @param Bank NORSRAM bank number
285 * @retval HAL status
286 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)287 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
288 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
289 {
290 /* Check the parameters */
291 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
292 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
293 assert_param(IS_FMC_NORSRAM_BANK(Bank));
294
295 /* Disable the FMC_NORSRAM device */
296 __FMC_NORSRAM_DISABLE(Device, Bank);
297
298 /* De-initialize the FMC_NORSRAM device */
299 /* FMC_NORSRAM_BANK1 */
300 if (Bank == FMC_NORSRAM_BANK1)
301 {
302 Device->BTCR[Bank] = 0x000030DBU;
303 }
304 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
305 else
306 {
307 Device->BTCR[Bank] = 0x000030D2U;
308 }
309
310 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
311 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
312
313 return HAL_OK;
314 }
315
316 /**
317 * @brief Initialize the FMC_NORSRAM Timing according to the specified
318 * parameters in the FMC_NORSRAM_TimingTypeDef
319 * @param Device Pointer to NORSRAM device instance
320 * @param Timing Pointer to NORSRAM Timing structure
321 * @param Bank NORSRAM bank number
322 * @retval HAL status
323 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)324 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
325 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
326 {
327 uint32_t tmpr;
328
329 /* Check the parameters */
330 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
331 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
332 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
333 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
334 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
335 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
336 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
337 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
338 assert_param(IS_FMC_NORSRAM_BANK(Bank));
339
340 /* Set FMC_NORSRAM device timing parameters */
341 MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
342 ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) |
343 ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) |
344 ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) |
345 (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) |
346 (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) |
347 (Timing->AccessMode)));
348
349 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
350 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
351 {
352 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
353 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
354 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
355 }
356
357 return HAL_OK;
358 }
359
360 /**
361 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
362 * parameters in the FMC_NORSRAM_TimingTypeDef
363 * @param Device Pointer to NORSRAM device instance
364 * @param Timing Pointer to NORSRAM Timing structure
365 * @param Bank NORSRAM bank number
366 * @param ExtendedMode FMC Extended Mode
367 * This parameter can be one of the following values:
368 * @arg FMC_EXTENDED_MODE_DISABLE
369 * @arg FMC_EXTENDED_MODE_ENABLE
370 * @retval HAL status
371 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)372 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
373 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
374 uint32_t ExtendedMode)
375 {
376 /* Check the parameters */
377 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
378
379 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
380 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
381 {
382 /* Check the parameters */
383 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
384 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
385 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
386 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
387 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
388 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
389 assert_param(IS_FMC_NORSRAM_BANK(Bank));
390
391 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
392 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
393 ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) |
394 ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) |
395 Timing->AccessMode |
396 ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
397 }
398 else
399 {
400 Device->BWTR[Bank] = 0x0FFFFFFFU;
401 }
402
403 return HAL_OK;
404 }
405 /**
406 * @}
407 */
408
409 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
410 * @brief management functions
411 *
412 @verbatim
413 ==============================================================================
414 ##### FMC_NORSRAM Control functions #####
415 ==============================================================================
416 [..]
417 This subsection provides a set of functions allowing to control dynamically
418 the FMC NORSRAM interface.
419
420 @endverbatim
421 * @{
422 */
423
424 /**
425 * @brief Enables dynamically FMC_NORSRAM write operation.
426 * @param Device Pointer to NORSRAM device instance
427 * @param Bank NORSRAM bank number
428 * @retval HAL status
429 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)430 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
431 {
432 /* Check the parameters */
433 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
434 assert_param(IS_FMC_NORSRAM_BANK(Bank));
435
436 /* Enable write operation */
437 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
438
439 return HAL_OK;
440 }
441
442 /**
443 * @brief Disables dynamically FMC_NORSRAM write operation.
444 * @param Device Pointer to NORSRAM device instance
445 * @param Bank NORSRAM bank number
446 * @retval HAL status
447 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)448 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
449 {
450 /* Check the parameters */
451 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
452 assert_param(IS_FMC_NORSRAM_BANK(Bank));
453
454 /* Disable write operation */
455 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
456
457 return HAL_OK;
458 }
459
460 /**
461 * @}
462 */
463
464 /**
465 * @}
466 */
467
468
469 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
470 * @brief NAND Controller functions
471 *
472 @verbatim
473 ==============================================================================
474 ##### How to use NAND device driver #####
475 ==============================================================================
476 [..]
477 This driver contains a set of APIs to interface with the FMC NAND banks in order
478 to run the NAND external devices.
479
480 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
481 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
482 (+) FMC NAND bank common space timing configuration using the function
483 FMC_NAND_CommonSpace_Timing_Init()
484 (+) FMC NAND bank attribute space timing configuration using the function
485 FMC_NAND_AttributeSpace_Timing_Init()
486 (+) FMC NAND bank enable/disable ECC correction feature using the functions
487 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
488 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
489
490 @endverbatim
491 * @{
492 */
493
494 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
495 * @brief Initialization and Configuration functions
496 *
497 @verbatim
498 ==============================================================================
499 ##### Initialization and de_initialization functions #####
500 ==============================================================================
501 [..]
502 This section provides functions allowing to:
503 (+) Initialize and configure the FMC NAND interface
504 (+) De-initialize the FMC NAND interface
505 (+) Configure the FMC clock and associated GPIOs
506
507 @endverbatim
508 * @{
509 */
510
511 /**
512 * @brief Initializes the FMC_NAND device according to the specified
513 * control parameters in the FMC_NAND_HandleTypeDef
514 * @param Device Pointer to NAND device instance
515 * @param Init Pointer to NAND Initialization structure
516 * @retval HAL status
517 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)518 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
519 {
520 /* Check the parameters */
521 assert_param(IS_FMC_NAND_DEVICE(Device));
522 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
523 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
524 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
525 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
526 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
527 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
528 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
529
530 /* NAND bank 3 registers configuration */
531 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
532 FMC_PCR_MEMORY_TYPE_NAND |
533 Init->MemoryDataWidth |
534 Init->EccComputation |
535 Init->ECCPageSize |
536 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
537 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
538
539 return HAL_OK;
540 }
541
542 /**
543 * @brief Initializes the FMC_NAND Common space Timing according to the specified
544 * parameters in the FMC_NAND_PCC_TimingTypeDef
545 * @param Device Pointer to NAND device instance
546 * @param Timing Pointer to NAND timing structure
547 * @param Bank NAND bank number
548 * @retval HAL status
549 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)550 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
551 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
552 {
553 /* Check the parameters */
554 assert_param(IS_FMC_NAND_DEVICE(Device));
555 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
556 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
557 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
558 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
559 assert_param(IS_FMC_NAND_BANK(Bank));
560
561 /* Prevent unused argument(s) compilation warning if no assert_param check */
562 UNUSED(Bank);
563
564 /* NAND bank 3 registers configuration */
565 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
566 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT3_Pos) |
567 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD3_Pos) |
568 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ3_Pos)));
569
570 return HAL_OK;
571 }
572
573 /**
574 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
575 * parameters in the FMC_NAND_PCC_TimingTypeDef
576 * @param Device Pointer to NAND device instance
577 * @param Timing Pointer to NAND timing structure
578 * @param Bank NAND bank number
579 * @retval HAL status
580 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)581 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
582 FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
583 {
584 /* Check the parameters */
585 assert_param(IS_FMC_NAND_DEVICE(Device));
586 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
587 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
588 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
589 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
590 assert_param(IS_FMC_NAND_BANK(Bank));
591
592 /* Prevent unused argument(s) compilation warning if no assert_param check */
593 UNUSED(Bank);
594
595 /* NAND bank 3 registers configuration */
596 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
597 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT3_Pos) |
598 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD3_Pos) |
599 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ3_Pos)));
600
601 return HAL_OK;
602 }
603
604 /**
605 * @brief DeInitializes the FMC_NAND device
606 * @param Device Pointer to NAND device instance
607 * @param Bank NAND bank number
608 * @retval HAL status
609 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)610 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
611 {
612 /* Check the parameters */
613 assert_param(IS_FMC_NAND_DEVICE(Device));
614 assert_param(IS_FMC_NAND_BANK(Bank));
615
616 /* Disable the NAND Bank */
617 __FMC_NAND_DISABLE(Device, Bank);
618
619 /* De-initialize the NAND Bank */
620 /* Prevent unused argument(s) compilation warning if no assert_param check */
621 UNUSED(Bank);
622
623 /* Set the FMC_NAND_BANK3 registers to their reset values */
624 WRITE_REG(Device->PCR, 0x00000018U);
625 WRITE_REG(Device->SR, 0x00000040U);
626 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
627 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
628
629 return HAL_OK;
630 }
631
632 /**
633 * @}
634 */
635
636 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
637 * @brief management functions
638 *
639 @verbatim
640 ==============================================================================
641 ##### FMC_NAND Control functions #####
642 ==============================================================================
643 [..]
644 This subsection provides a set of functions allowing to control dynamically
645 the FMC NAND interface.
646
647 @endverbatim
648 * @{
649 */
650
651
652 /**
653 * @brief Enables dynamically FMC_NAND ECC feature.
654 * @param Device Pointer to NAND device instance
655 * @param Bank NAND bank number
656 * @retval HAL status
657 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)658 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
659 {
660 /* Check the parameters */
661 assert_param(IS_FMC_NAND_DEVICE(Device));
662 assert_param(IS_FMC_NAND_BANK(Bank));
663
664 /* Enable ECC feature */
665 /* Prevent unused argument(s) compilation warning if no assert_param check */
666 UNUSED(Bank);
667
668 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
669
670 return HAL_OK;
671 }
672
673
674 /**
675 * @brief Disables dynamically FMC_NAND ECC feature.
676 * @param Device Pointer to NAND device instance
677 * @param Bank NAND bank number
678 * @retval HAL status
679 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)680 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
681 {
682 /* Check the parameters */
683 assert_param(IS_FMC_NAND_DEVICE(Device));
684 assert_param(IS_FMC_NAND_BANK(Bank));
685
686 /* Disable ECC feature */
687 /* Prevent unused argument(s) compilation warning if no assert_param check */
688 UNUSED(Bank);
689
690 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
691
692 return HAL_OK;
693 }
694
695 /**
696 * @brief Disables dynamically FMC_NAND ECC feature.
697 * @param Device Pointer to NAND device instance
698 * @param ECCval Pointer to ECC value
699 * @param Bank NAND bank number
700 * @param Timeout Timeout wait value
701 * @retval HAL status
702 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)703 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
704 uint32_t Timeout)
705 {
706 uint32_t tickstart;
707
708 /* Check the parameters */
709 assert_param(IS_FMC_NAND_DEVICE(Device));
710 assert_param(IS_FMC_NAND_BANK(Bank));
711
712 /* Get tick */
713 tickstart = HAL_GetTick();
714
715 /* Wait until FIFO is empty */
716 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
717 {
718 /* Check for the Timeout */
719 if (Timeout != HAL_MAX_DELAY)
720 {
721 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
722 {
723 return HAL_TIMEOUT;
724 }
725 }
726 }
727
728 /* Prevent unused argument(s) compilation warning if no assert_param check */
729 UNUSED(Bank);
730
731 /* Get the ECCR register value */
732 *ECCval = (uint32_t)Device->ECCR;
733
734 return HAL_OK;
735 }
736
737 /**
738 * @}
739 */
740
741
742
743 /** @defgroup FMC_LL_SDRAM
744 * @brief SDRAM Controller functions
745 *
746 @verbatim
747 ==============================================================================
748 ##### How to use SDRAM device driver #####
749 ==============================================================================
750 [..]
751 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
752 to run the SDRAM external devices.
753
754 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
755 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
756 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
757 (+) FMC SDRAM bank enable/disable write operation using the functions
758 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
759 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
760
761 @endverbatim
762 * @{
763 */
764
765 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
766 * @brief Initialization and Configuration functions
767 *
768 @verbatim
769 ==============================================================================
770 ##### Initialization and de_initialization functions #####
771 ==============================================================================
772 [..]
773 This section provides functions allowing to:
774 (+) Initialize and configure the FMC SDRAM interface
775 (+) De-initialize the FMC SDRAM interface
776 (+) Configure the FMC clock and associated GPIOs
777
778 @endverbatim
779 * @{
780 */
781
782 /**
783 * @brief Initializes the FMC_SDRAM device according to the specified
784 * control parameters in the FMC_SDRAM_InitTypeDef
785 * @param Device Pointer to SDRAM device instance
786 * @param Init Pointer to SDRAM Initialization structure
787 * @retval HAL status
788 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_InitTypeDef * Init)789 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
790 {
791 /* Check the parameters */
792 assert_param(IS_FMC_SDRAM_DEVICE(Device));
793 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
794 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
795 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
796 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
797 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
798 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
799 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
800 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
801 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
802 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
803
804 /* Set SDRAM bank configuration parameters */
805 if (Init->SDBank == FMC_SDRAM_BANK1)
806 {
807 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
808 SDCR_CLEAR_MASK,
809 (Init->ColumnBitsNumber |
810 Init->RowBitsNumber |
811 Init->MemoryDataWidth |
812 Init->InternalBankNumber |
813 Init->CASLatency |
814 Init->WriteProtection |
815 Init->SDClockPeriod |
816 Init->ReadBurst |
817 Init->ReadPipeDelay));
818 }
819 else /* FMC_Bank2_SDRAM */
820 {
821 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
822 FMC_SDCR1_SDCLK |
823 FMC_SDCR1_RBURST |
824 FMC_SDCR1_RPIPE,
825 (Init->SDClockPeriod |
826 Init->ReadBurst |
827 Init->ReadPipeDelay));
828
829 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
830 SDCR_CLEAR_MASK,
831 (Init->ColumnBitsNumber |
832 Init->RowBitsNumber |
833 Init->MemoryDataWidth |
834 Init->InternalBankNumber |
835 Init->CASLatency |
836 Init->WriteProtection));
837 }
838
839 return HAL_OK;
840 }
841
842
843 /**
844 * @brief Initializes the FMC_SDRAM device timing according to the specified
845 * parameters in the FMC_SDRAM_TimingTypeDef
846 * @param Device Pointer to SDRAM device instance
847 * @param Timing Pointer to SDRAM Timing structure
848 * @param Bank SDRAM bank number
849 * @retval HAL status
850 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)851 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
852 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
853 {
854 /* Check the parameters */
855 assert_param(IS_FMC_SDRAM_DEVICE(Device));
856 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
857 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
858 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
859 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
860 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
861 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
862 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
863 assert_param(IS_FMC_SDRAM_BANK(Bank));
864
865 /* Set SDRAM device timing parameters */
866 if (Bank == FMC_SDRAM_BANK1)
867 {
868 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
869 SDTR_CLEAR_MASK,
870 (((Timing->LoadToActiveDelay) - 1U) |
871 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
872 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
873 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
874 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
875 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
876 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
877 }
878 else /* FMC_Bank2_SDRAM */
879 {
880 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
881 FMC_SDTR1_TRC |
882 FMC_SDTR1_TRP,
883 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
884 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
885
886 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
887 SDTR_CLEAR_MASK,
888 (((Timing->LoadToActiveDelay) - 1U) |
889 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
890 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
891 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
892 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
893 }
894
895 return HAL_OK;
896 }
897
898 /**
899 * @brief DeInitializes the FMC_SDRAM peripheral
900 * @param Device Pointer to SDRAM device instance
901 * @retval HAL status
902 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)903 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
904 {
905 /* Check the parameters */
906 assert_param(IS_FMC_SDRAM_DEVICE(Device));
907 assert_param(IS_FMC_SDRAM_BANK(Bank));
908
909 /* De-initialize the SDRAM device */
910 Device->SDCR[Bank] = 0x000002D0U;
911 Device->SDTR[Bank] = 0x0FFFFFFFU;
912 Device->SDCMR = 0x00000000U;
913 Device->SDRTR = 0x00000000U;
914 Device->SDSR = 0x00000000U;
915
916 return HAL_OK;
917 }
918
919 /**
920 * @}
921 */
922
923 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
924 * @brief management functions
925 *
926 @verbatim
927 ==============================================================================
928 ##### FMC_SDRAM Control functions #####
929 ==============================================================================
930 [..]
931 This subsection provides a set of functions allowing to control dynamically
932 the FMC SDRAM interface.
933
934 @endverbatim
935 * @{
936 */
937
938 /**
939 * @brief Enables dynamically FMC_SDRAM write protection.
940 * @param Device Pointer to SDRAM device instance
941 * @param Bank SDRAM bank number
942 * @retval HAL status
943 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)944 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
945 {
946 /* Check the parameters */
947 assert_param(IS_FMC_SDRAM_DEVICE(Device));
948 assert_param(IS_FMC_SDRAM_BANK(Bank));
949
950 /* Enable write protection */
951 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
952
953 return HAL_OK;
954 }
955
956 /**
957 * @brief Disables dynamically FMC_SDRAM write protection.
958 * @param hsdram FMC_SDRAM handle
959 * @retval HAL status
960 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)961 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
962 {
963 /* Check the parameters */
964 assert_param(IS_FMC_SDRAM_DEVICE(Device));
965 assert_param(IS_FMC_SDRAM_BANK(Bank));
966
967 /* Disable write protection */
968 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
969
970 return HAL_OK;
971 }
972
973 /**
974 * @brief Send Command to the FMC SDRAM bank
975 * @param Device Pointer to SDRAM device instance
976 * @param Command Pointer to SDRAM command structure
977 * @param Timing Pointer to SDRAM Timing structure
978 * @param Timeout Timeout wait value
979 * @retval HAL state
980 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)981 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
982 FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
983 {
984 /* Check the parameters */
985 assert_param(IS_FMC_SDRAM_DEVICE(Device));
986 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
987 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
988 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
989 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
990
991 /* Set command register */
992 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
993 ((Command->CommandMode) | (Command->CommandTarget) |
994 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
995 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
996 /* Prevent unused argument(s) compilation warning */
997 UNUSED(Timeout);
998 return HAL_OK;
999 }
1000
1001 /**
1002 * @brief Program the SDRAM Memory Refresh rate.
1003 * @param Device Pointer to SDRAM device instance
1004 * @param RefreshRate The SDRAM refresh rate value.
1005 * @retval HAL state
1006 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1007 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1008 {
1009 /* Check the parameters */
1010 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1011 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1012
1013 /* Set the refresh rate in command register */
1014 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1015
1016 return HAL_OK;
1017 }
1018
1019 /**
1020 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1021 * @param Device Pointer to SDRAM device instance
1022 * @param AutoRefreshNumber Specifies the auto Refresh number.
1023 * @retval None
1024 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1025 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1026 uint32_t AutoRefreshNumber)
1027 {
1028 /* Check the parameters */
1029 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1030 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1031
1032 /* Set the Auto-refresh number in command register */
1033 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1034
1035 return HAL_OK;
1036 }
1037
1038 /**
1039 * @brief Returns the indicated FMC SDRAM bank mode status.
1040 * @param Device Pointer to SDRAM device instance
1041 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1042 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1043 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1044 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1045 * FMC_SDRAM_POWER_DOWN_MODE.
1046 */
FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef * Device,uint32_t Bank)1047 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1048 {
1049 uint32_t tmpreg;
1050
1051 /* Check the parameters */
1052 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1053 assert_param(IS_FMC_SDRAM_BANK(Bank));
1054
1055 /* Get the corresponding bank mode */
1056 if (Bank == FMC_SDRAM_BANK1)
1057 {
1058 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1059 }
1060 else
1061 {
1062 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1063 }
1064
1065 /* Return the mode status */
1066 return tmpreg;
1067 }
1068
1069 /**
1070 * @}
1071 */
1072
1073 /**
1074 * @}
1075 */
1076
1077
1078 /**
1079 * @}
1080 */
1081
1082 /**
1083 * @}
1084 */
1085
1086 #endif /* HAL_NOR_MODULE_ENABLED */
1087 /**
1088 * @}
1089 */
1090 /**
1091 * @}
1092 */
1093
