1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (overridden) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (overridden) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (overridden) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32f7xx_hal.h"
116
117
118 /** @addtogroup STM32F7xx_HAL_Driver
119 * @{
120 */
121
122 #ifdef HAL_SDRAM_MODULE_ENABLED
123
124 /** @defgroup SDRAM SDRAM
125 * @brief SDRAM driver modules
126 * @{
127 */
128
129 /* Private typedef -----------------------------------------------------------*/
130 /* Private define ------------------------------------------------------------*/
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
135 * @{
136 */
137 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma);
138 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
139 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma);
140 /**
141 * @}
142 */
143
144 /* Exported functions --------------------------------------------------------*/
145 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
146 * @{
147 */
148
149 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
150 * @brief Initialization and Configuration functions
151 *
152 @verbatim
153 ==============================================================================
154 ##### SDRAM Initialization and de_initialization functions #####
155 ==============================================================================
156 [..]
157 This section provides functions allowing to initialize/de-initialize
158 the SDRAM memory
159
160 @endverbatim
161 * @{
162 */
163
164 /**
165 * @brief Performs the SDRAM device initialization sequence.
166 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
167 * the configuration information for SDRAM module.
168 * @param Timing Pointer to SDRAM control timing structure
169 * @retval HAL status
170 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)171 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
172 {
173 /* Check the SDRAM handle parameter */
174 if (hsdram == NULL)
175 {
176 return HAL_ERROR;
177 }
178
179 if (hsdram->State == HAL_SDRAM_STATE_RESET)
180 {
181 /* Allocate lock resource and initialize it */
182 hsdram->Lock = HAL_UNLOCKED;
183 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
184 if (hsdram->MspInitCallback == NULL)
185 {
186 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
187 }
188 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
189 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
190 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
191
192 /* Init the low level hardware */
193 hsdram->MspInitCallback(hsdram);
194 #else
195 /* Initialize the low level hardware (MSP) */
196 HAL_SDRAM_MspInit(hsdram);
197 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
198 }
199
200 /* Initialize the SDRAM controller state */
201 hsdram->State = HAL_SDRAM_STATE_BUSY;
202
203 /* Initialize SDRAM control Interface */
204 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
205
206 /* Initialize SDRAM timing Interface */
207 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
208 /* Update the SDRAM controller state */
209 hsdram->State = HAL_SDRAM_STATE_READY;
210
211 return HAL_OK;
212 }
213
214 /**
215 * @brief Perform the SDRAM device initialization sequence.
216 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
217 * the configuration information for SDRAM module.
218 * @retval HAL status
219 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)220 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
221 {
222 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
223 if (hsdram->MspDeInitCallback == NULL)
224 {
225 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
226 }
227
228 /* DeInit the low level hardware */
229 hsdram->MspDeInitCallback(hsdram);
230 #else
231 /* Initialize the low level hardware (MSP) */
232 HAL_SDRAM_MspDeInit(hsdram);
233 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
234
235 /* Configure the SDRAM registers with their reset values */
236 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
237
238 /* Reset the SDRAM controller state */
239 hsdram->State = HAL_SDRAM_STATE_RESET;
240
241 /* Release Lock */
242 __HAL_UNLOCK(hsdram);
243
244 return HAL_OK;
245 }
246
247 /**
248 * @brief SDRAM MSP Init.
249 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
250 * the configuration information for SDRAM module.
251 * @retval None
252 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)253 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
254 {
255 /* Prevent unused argument(s) compilation warning */
256 UNUSED(hsdram);
257
258 /* NOTE: This function Should not be modified, when the callback is needed,
259 the HAL_SDRAM_MspInit could be implemented in the user file
260 */
261 }
262
263 /**
264 * @brief SDRAM MSP DeInit.
265 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
266 * the configuration information for SDRAM module.
267 * @retval None
268 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)269 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
270 {
271 /* Prevent unused argument(s) compilation warning */
272 UNUSED(hsdram);
273
274 /* NOTE: This function Should not be modified, when the callback is needed,
275 the HAL_SDRAM_MspDeInit could be implemented in the user file
276 */
277 }
278
279 /**
280 * @brief This function handles SDRAM refresh error interrupt request.
281 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
282 * the configuration information for SDRAM module.
283 * @retval HAL status
284 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)285 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
286 {
287 /* Check SDRAM interrupt Rising edge flag */
288 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
289 {
290 /* SDRAM refresh error interrupt callback */
291 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
292 hsdram->RefreshErrorCallback(hsdram);
293 #else
294 HAL_SDRAM_RefreshErrorCallback(hsdram);
295 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
296
297 /* Clear SDRAM refresh error interrupt pending bit */
298 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
299 }
300 }
301
302 /**
303 * @brief SDRAM Refresh error callback.
304 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
305 * the configuration information for SDRAM module.
306 * @retval None
307 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)308 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
309 {
310 /* Prevent unused argument(s) compilation warning */
311 UNUSED(hsdram);
312
313 /* NOTE: This function Should not be modified, when the callback is needed,
314 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
315 */
316 }
317
318 /**
319 * @brief DMA transfer complete callback.
320 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
321 * the configuration information for the specified DMA module.
322 * @retval None
323 */
HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)324 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
325 {
326 /* Prevent unused argument(s) compilation warning */
327 UNUSED(hdma);
328
329 /* NOTE: This function Should not be modified, when the callback is needed,
330 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
331 */
332 }
333
334 /**
335 * @brief DMA transfer complete error callback.
336 * @param hdma DMA handle
337 * @retval None
338 */
HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)339 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
340 {
341 /* Prevent unused argument(s) compilation warning */
342 UNUSED(hdma);
343
344 /* NOTE: This function Should not be modified, when the callback is needed,
345 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
346 */
347 }
348
349 /**
350 * @}
351 */
352
353 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
354 * @brief Input Output and memory control functions
355 *
356 @verbatim
357 ==============================================================================
358 ##### SDRAM Input and Output functions #####
359 ==============================================================================
360 [..]
361 This section provides functions allowing to use and control the SDRAM memory
362
363 @endverbatim
364 * @{
365 */
366
367 /**
368 * @brief Reads 8-bit data buffer from the SDRAM memory.
369 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
370 * the configuration information for SDRAM module.
371 * @param pAddress Pointer to read start address
372 * @param pDstBuffer Pointer to destination buffer
373 * @param BufferSize Size of the buffer to read from memory
374 * @retval HAL status
375 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)376 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
377 uint32_t BufferSize)
378 {
379 uint32_t size;
380 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
381 uint8_t *pdestbuff = pDstBuffer;
382 HAL_SDRAM_StateTypeDef state = hsdram->State;
383
384 /* Check the SDRAM controller state */
385 if (state == HAL_SDRAM_STATE_BUSY)
386 {
387 return HAL_BUSY;
388 }
389 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
390 {
391 /* Process Locked */
392 __HAL_LOCK(hsdram);
393
394 /* Update the SDRAM controller state */
395 hsdram->State = HAL_SDRAM_STATE_BUSY;
396
397 /* Read data from source */
398 for (size = BufferSize; size != 0U; size--)
399 {
400 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
401 pdestbuff++;
402 pSdramAddress++;
403 }
404
405 /* Update the SDRAM controller state */
406 hsdram->State = state;
407
408 /* Process Unlocked */
409 __HAL_UNLOCK(hsdram);
410 }
411 else
412 {
413 return HAL_ERROR;
414 }
415
416 return HAL_OK;
417 }
418
419 /**
420 * @brief Writes 8-bit data buffer to SDRAM memory.
421 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
422 * the configuration information for SDRAM module.
423 * @param pAddress Pointer to write start address
424 * @param pSrcBuffer Pointer to source buffer to write
425 * @param BufferSize Size of the buffer to write to memory
426 * @retval HAL status
427 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)428 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
429 uint32_t BufferSize)
430 {
431 uint32_t size;
432 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
433 uint8_t *psrcbuff = pSrcBuffer;
434
435 /* Check the SDRAM controller state */
436 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
437 {
438 return HAL_BUSY;
439 }
440 else if (hsdram->State == HAL_SDRAM_STATE_READY)
441 {
442 /* Process Locked */
443 __HAL_LOCK(hsdram);
444
445 /* Update the SDRAM controller state */
446 hsdram->State = HAL_SDRAM_STATE_BUSY;
447
448 /* Write data to memory */
449 for (size = BufferSize; size != 0U; size--)
450 {
451 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
452 psrcbuff++;
453 pSdramAddress++;
454 }
455
456 /* Update the SDRAM controller state */
457 hsdram->State = HAL_SDRAM_STATE_READY;
458
459 /* Process Unlocked */
460 __HAL_UNLOCK(hsdram);
461 }
462 else
463 {
464 return HAL_ERROR;
465 }
466
467 return HAL_OK;
468 }
469
470 /**
471 * @brief Reads 16-bit data buffer from the SDRAM memory.
472 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
473 * the configuration information for SDRAM module.
474 * @param pAddress Pointer to read start address
475 * @param pDstBuffer Pointer to destination buffer
476 * @param BufferSize Size of the buffer to read from memory
477 * @retval HAL status
478 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)479 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
480 uint32_t BufferSize)
481 {
482 uint32_t size;
483 __IO uint32_t *pSdramAddress = pAddress;
484 uint16_t *pdestbuff = pDstBuffer;
485 HAL_SDRAM_StateTypeDef state = hsdram->State;
486
487 /* Check the SDRAM controller state */
488 if (state == HAL_SDRAM_STATE_BUSY)
489 {
490 return HAL_BUSY;
491 }
492 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
493 {
494 /* Process Locked */
495 __HAL_LOCK(hsdram);
496
497 /* Update the SDRAM controller state */
498 hsdram->State = HAL_SDRAM_STATE_BUSY;
499
500 /* Read data from memory */
501 for (size = BufferSize; size >= 2U ; size -= 2U)
502 {
503 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
504 pdestbuff++;
505 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
506 pdestbuff++;
507 pSdramAddress++;
508 }
509
510 /* Read last 16-bits if size is not 32-bits multiple */
511 if ((BufferSize % 2U) != 0U)
512 {
513 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
514 }
515
516 /* Update the SDRAM controller state */
517 hsdram->State = state;
518
519 /* Process Unlocked */
520 __HAL_UNLOCK(hsdram);
521 }
522 else
523 {
524 return HAL_ERROR;
525 }
526
527 return HAL_OK;
528 }
529
530 /**
531 * @brief Writes 16-bit data buffer to SDRAM memory.
532 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
533 * the configuration information for SDRAM module.
534 * @param pAddress Pointer to write start address
535 * @param pSrcBuffer Pointer to source buffer to write
536 * @param BufferSize Size of the buffer to write to memory
537 * @retval HAL status
538 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)539 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
540 uint32_t BufferSize)
541 {
542 uint32_t size;
543 __IO uint32_t *psdramaddress = pAddress;
544 uint16_t *psrcbuff = pSrcBuffer;
545
546 /* Check the SDRAM controller state */
547 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
548 {
549 return HAL_BUSY;
550 }
551 else if (hsdram->State == HAL_SDRAM_STATE_READY)
552 {
553 /* Process Locked */
554 __HAL_LOCK(hsdram);
555
556 /* Update the SDRAM controller state */
557 hsdram->State = HAL_SDRAM_STATE_BUSY;
558
559 /* Write data to memory */
560 for (size = BufferSize; size >= 2U ; size -= 2U)
561 {
562 *psdramaddress = (uint32_t)(*psrcbuff);
563 psrcbuff++;
564 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
565 psrcbuff++;
566 psdramaddress++;
567 }
568
569 /* Write last 16-bits if size is not 32-bits multiple */
570 if ((BufferSize % 2U) != 0U)
571 {
572 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
573 }
574
575 /* Update the SDRAM controller state */
576 hsdram->State = HAL_SDRAM_STATE_READY;
577
578 /* Process Unlocked */
579 __HAL_UNLOCK(hsdram);
580 }
581 else
582 {
583 return HAL_ERROR;
584 }
585
586 return HAL_OK;
587 }
588
589 /**
590 * @brief Reads 32-bit data buffer from the SDRAM memory.
591 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
592 * the configuration information for SDRAM module.
593 * @param pAddress Pointer to read start address
594 * @param pDstBuffer Pointer to destination buffer
595 * @param BufferSize Size of the buffer to read from memory
596 * @retval HAL status
597 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)598 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
599 uint32_t BufferSize)
600 {
601 uint32_t size;
602 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
603 uint32_t *pdestbuff = pDstBuffer;
604 HAL_SDRAM_StateTypeDef state = hsdram->State;
605
606 /* Check the SDRAM controller state */
607 if (state == HAL_SDRAM_STATE_BUSY)
608 {
609 return HAL_BUSY;
610 }
611 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
612 {
613 /* Process Locked */
614 __HAL_LOCK(hsdram);
615
616 /* Update the SDRAM controller state */
617 hsdram->State = HAL_SDRAM_STATE_BUSY;
618
619 /* Read data from source */
620 for (size = BufferSize; size != 0U; size--)
621 {
622 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
623 pdestbuff++;
624 pSdramAddress++;
625 }
626
627 /* Update the SDRAM controller state */
628 hsdram->State = state;
629
630 /* Process Unlocked */
631 __HAL_UNLOCK(hsdram);
632 }
633 else
634 {
635 return HAL_ERROR;
636 }
637
638 return HAL_OK;
639 }
640
641 /**
642 * @brief Writes 32-bit data buffer to SDRAM memory.
643 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
644 * the configuration information for SDRAM module.
645 * @param pAddress Pointer to write start address
646 * @param pSrcBuffer Pointer to source buffer to write
647 * @param BufferSize Size of the buffer to write to memory
648 * @retval HAL status
649 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)650 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
651 uint32_t BufferSize)
652 {
653 uint32_t size;
654 __IO uint32_t *pSdramAddress = pAddress;
655 uint32_t *psrcbuff = pSrcBuffer;
656
657 /* Check the SDRAM controller state */
658 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
659 {
660 return HAL_BUSY;
661 }
662 else if (hsdram->State == HAL_SDRAM_STATE_READY)
663 {
664 /* Process Locked */
665 __HAL_LOCK(hsdram);
666
667 /* Update the SDRAM controller state */
668 hsdram->State = HAL_SDRAM_STATE_BUSY;
669
670 /* Write data to memory */
671 for (size = BufferSize; size != 0U; size--)
672 {
673 *pSdramAddress = *psrcbuff;
674 psrcbuff++;
675 pSdramAddress++;
676 }
677
678 /* Update the SDRAM controller state */
679 hsdram->State = HAL_SDRAM_STATE_READY;
680
681 /* Process Unlocked */
682 __HAL_UNLOCK(hsdram);
683 }
684 else
685 {
686 return HAL_ERROR;
687 }
688
689 return HAL_OK;
690 }
691
692 /**
693 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
694 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
695 * the configuration information for SDRAM module.
696 * @param pAddress Pointer to read start address
697 * @param pDstBuffer Pointer to destination buffer
698 * @param BufferSize Size of the buffer to read from memory
699 * @retval HAL status
700 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)701 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
702 uint32_t BufferSize)
703 {
704 HAL_StatusTypeDef status;
705 HAL_SDRAM_StateTypeDef state = hsdram->State;
706
707 /* Check the SDRAM controller state */
708 if (state == HAL_SDRAM_STATE_BUSY)
709 {
710 status = HAL_BUSY;
711 }
712 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
713 {
714 /* Process Locked */
715 __HAL_LOCK(hsdram);
716
717 /* Update the SDRAM controller state */
718 hsdram->State = HAL_SDRAM_STATE_BUSY;
719
720 /* Configure DMA user callbacks */
721 if (state == HAL_SDRAM_STATE_READY)
722 {
723 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
724 }
725 else
726 {
727 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt;
728 }
729 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
730
731 /* Enable the DMA Stream */
732 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
733
734 /* Process Unlocked */
735 __HAL_UNLOCK(hsdram);
736 }
737 else
738 {
739 status = HAL_ERROR;
740 }
741
742 return status;
743 }
744
745 /**
746 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
747 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
748 * the configuration information for SDRAM module.
749 * @param pAddress Pointer to write start address
750 * @param pSrcBuffer Pointer to source buffer to write
751 * @param BufferSize Size of the buffer to write to memory
752 * @retval HAL status
753 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)754 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
755 uint32_t BufferSize)
756 {
757 HAL_StatusTypeDef status;
758
759 /* Check the SDRAM controller state */
760 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
761 {
762 status = HAL_BUSY;
763 }
764 else if (hsdram->State == HAL_SDRAM_STATE_READY)
765 {
766 /* Process Locked */
767 __HAL_LOCK(hsdram);
768
769 /* Update the SDRAM controller state */
770 hsdram->State = HAL_SDRAM_STATE_BUSY;
771
772 /* Configure DMA user callbacks */
773 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt;
774 hsdram->hdma->XferErrorCallback = SDRAM_DMAError;
775
776 /* Enable the DMA Stream */
777 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
778
779 /* Process Unlocked */
780 __HAL_UNLOCK(hsdram);
781 }
782 else
783 {
784 status = HAL_ERROR;
785 }
786
787 return status;
788 }
789
790 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
791 /**
792 * @brief Register a User SDRAM Callback
793 * To be used to override the weak predefined callback
794 * @param hsdram : SDRAM handle
795 * @param CallbackId : ID of the callback to be registered
796 * This parameter can be one of the following values:
797 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
798 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
799 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
800 * @param pCallback : pointer to the Callback function
801 * @retval status
802 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)803 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
804 pSDRAM_CallbackTypeDef pCallback)
805 {
806 HAL_StatusTypeDef status = HAL_OK;
807 HAL_SDRAM_StateTypeDef state;
808
809 if (pCallback == NULL)
810 {
811 return HAL_ERROR;
812 }
813
814 state = hsdram->State;
815 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
816 {
817 switch (CallbackId)
818 {
819 case HAL_SDRAM_MSP_INIT_CB_ID :
820 hsdram->MspInitCallback = pCallback;
821 break;
822 case HAL_SDRAM_MSP_DEINIT_CB_ID :
823 hsdram->MspDeInitCallback = pCallback;
824 break;
825 case HAL_SDRAM_REFRESH_ERR_CB_ID :
826 hsdram->RefreshErrorCallback = pCallback;
827 break;
828 default :
829 /* update return status */
830 status = HAL_ERROR;
831 break;
832 }
833 }
834 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
835 {
836 switch (CallbackId)
837 {
838 case HAL_SDRAM_MSP_INIT_CB_ID :
839 hsdram->MspInitCallback = pCallback;
840 break;
841 case HAL_SDRAM_MSP_DEINIT_CB_ID :
842 hsdram->MspDeInitCallback = pCallback;
843 break;
844 default :
845 /* update return status */
846 status = HAL_ERROR;
847 break;
848 }
849 }
850 else
851 {
852 /* update return status */
853 status = HAL_ERROR;
854 }
855
856 return status;
857 }
858
859 /**
860 * @brief Unregister a User SDRAM Callback
861 * SDRAM Callback is redirected to the weak predefined callback
862 * @param hsdram : SDRAM handle
863 * @param CallbackId : ID of the callback to be unregistered
864 * This parameter can be one of the following values:
865 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
866 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
867 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
868 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
869 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
870 * @retval status
871 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)872 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875 HAL_SDRAM_StateTypeDef state;
876
877 state = hsdram->State;
878 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
879 {
880 switch (CallbackId)
881 {
882 case HAL_SDRAM_MSP_INIT_CB_ID :
883 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
884 break;
885 case HAL_SDRAM_MSP_DEINIT_CB_ID :
886 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
887 break;
888 case HAL_SDRAM_REFRESH_ERR_CB_ID :
889 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
890 break;
891 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
892 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
893 break;
894 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
895 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
896 break;
897 default :
898 /* update return status */
899 status = HAL_ERROR;
900 break;
901 }
902 }
903 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
904 {
905 switch (CallbackId)
906 {
907 case HAL_SDRAM_MSP_INIT_CB_ID :
908 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
909 break;
910 case HAL_SDRAM_MSP_DEINIT_CB_ID :
911 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
912 break;
913 default :
914 /* update return status */
915 status = HAL_ERROR;
916 break;
917 }
918 }
919 else
920 {
921 /* update return status */
922 status = HAL_ERROR;
923 }
924
925 return status;
926 }
927
928 /**
929 * @brief Register a User SDRAM Callback for DMA transfers
930 * To be used to override the weak predefined callback
931 * @param hsdram : SDRAM handle
932 * @param CallbackId : ID of the callback to be registered
933 * This parameter can be one of the following values:
934 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
935 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
936 * @param pCallback : pointer to the Callback function
937 * @retval status
938 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)939 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
940 pSDRAM_DmaCallbackTypeDef pCallback)
941 {
942 HAL_StatusTypeDef status = HAL_OK;
943 HAL_SDRAM_StateTypeDef state;
944
945 if (pCallback == NULL)
946 {
947 return HAL_ERROR;
948 }
949
950 /* Process locked */
951 __HAL_LOCK(hsdram);
952
953 state = hsdram->State;
954 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
955 {
956 switch (CallbackId)
957 {
958 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
959 hsdram->DmaXferCpltCallback = pCallback;
960 break;
961 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
962 hsdram->DmaXferErrorCallback = pCallback;
963 break;
964 default :
965 /* update return status */
966 status = HAL_ERROR;
967 break;
968 }
969 }
970 else
971 {
972 /* update return status */
973 status = HAL_ERROR;
974 }
975
976 /* Release Lock */
977 __HAL_UNLOCK(hsdram);
978 return status;
979 }
980 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
981
982 /**
983 * @}
984 */
985
986 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
987 * @brief management functions
988 *
989 @verbatim
990 ==============================================================================
991 ##### SDRAM Control functions #####
992 ==============================================================================
993 [..]
994 This subsection provides a set of functions allowing to control dynamically
995 the SDRAM interface.
996
997 @endverbatim
998 * @{
999 */
1000
1001 /**
1002 * @brief Enables dynamically SDRAM write protection.
1003 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1004 * the configuration information for SDRAM module.
1005 * @retval HAL status
1006 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1007 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1008 {
1009 /* Check the SDRAM controller state */
1010 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1011 {
1012 return HAL_BUSY;
1013 }
1014 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1015 {
1016 /* Update the SDRAM state */
1017 hsdram->State = HAL_SDRAM_STATE_BUSY;
1018
1019 /* Enable write protection */
1020 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1021
1022 /* Update the SDRAM state */
1023 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1024 }
1025 else
1026 {
1027 return HAL_ERROR;
1028 }
1029
1030 return HAL_OK;
1031 }
1032
1033 /**
1034 * @brief Disables dynamically SDRAM write protection.
1035 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1036 * the configuration information for SDRAM module.
1037 * @retval HAL status
1038 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1039 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1040 {
1041 HAL_SDRAM_StateTypeDef state = hsdram->State;
1042
1043 /* Check the SDRAM controller state */
1044 if (state == HAL_SDRAM_STATE_BUSY)
1045 {
1046 return HAL_BUSY;
1047 }
1048 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1049 {
1050 /* Update the SDRAM state */
1051 hsdram->State = HAL_SDRAM_STATE_BUSY;
1052
1053 /* Disable write protection */
1054 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1055
1056 /* Update the SDRAM state */
1057 hsdram->State = HAL_SDRAM_STATE_READY;
1058 }
1059 else
1060 {
1061 return HAL_ERROR;
1062 }
1063
1064 return HAL_OK;
1065 }
1066
1067 /**
1068 * @brief Sends Command to the SDRAM bank.
1069 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1070 * the configuration information for SDRAM module.
1071 * @param Command SDRAM command structure
1072 * @param Timeout Timeout duration
1073 * @retval HAL status
1074 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1075 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1076 uint32_t Timeout)
1077 {
1078 HAL_SDRAM_StateTypeDef state = hsdram->State;
1079
1080 /* Check the SDRAM controller state */
1081 if (state == HAL_SDRAM_STATE_BUSY)
1082 {
1083 return HAL_BUSY;
1084 }
1085 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1086 {
1087 /* Update the SDRAM state */
1088 hsdram->State = HAL_SDRAM_STATE_BUSY;
1089
1090 /* Send SDRAM command */
1091 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1092
1093 /* Update the SDRAM controller state state */
1094 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1095 {
1096 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1097 }
1098 else
1099 {
1100 hsdram->State = HAL_SDRAM_STATE_READY;
1101 }
1102 }
1103 else
1104 {
1105 return HAL_ERROR;
1106 }
1107
1108 return HAL_OK;
1109 }
1110
1111 /**
1112 * @brief Programs the SDRAM Memory Refresh rate.
1113 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1114 * the configuration information for SDRAM module.
1115 * @param RefreshRate The SDRAM refresh rate value
1116 * @retval HAL status
1117 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1118 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1119 {
1120 /* Check the SDRAM controller state */
1121 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1122 {
1123 return HAL_BUSY;
1124 }
1125 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1126 {
1127 /* Update the SDRAM state */
1128 hsdram->State = HAL_SDRAM_STATE_BUSY;
1129
1130 /* Program the refresh rate */
1131 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1132
1133 /* Update the SDRAM state */
1134 hsdram->State = HAL_SDRAM_STATE_READY;
1135 }
1136 else
1137 {
1138 return HAL_ERROR;
1139 }
1140
1141 return HAL_OK;
1142 }
1143
1144 /**
1145 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1146 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1147 * the configuration information for SDRAM module.
1148 * @param AutoRefreshNumber The SDRAM auto Refresh number
1149 * @retval HAL status
1150 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1151 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1152 {
1153 /* Check the SDRAM controller state */
1154 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1155 {
1156 return HAL_BUSY;
1157 }
1158 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1159 {
1160 /* Update the SDRAM state */
1161 hsdram->State = HAL_SDRAM_STATE_BUSY;
1162
1163 /* Set the Auto-Refresh number */
1164 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1165
1166 /* Update the SDRAM state */
1167 hsdram->State = HAL_SDRAM_STATE_READY;
1168 }
1169 else
1170 {
1171 return HAL_ERROR;
1172 }
1173
1174 return HAL_OK;
1175 }
1176
1177 /**
1178 * @brief Returns the SDRAM memory current mode.
1179 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1180 * the configuration information for SDRAM module.
1181 * @retval The SDRAM memory mode.
1182 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1183 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1184 {
1185 /* Return the SDRAM memory current mode */
1186 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1187 }
1188
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1194 * @brief Peripheral State functions
1195 *
1196 @verbatim
1197 ==============================================================================
1198 ##### SDRAM State functions #####
1199 ==============================================================================
1200 [..]
1201 This subsection permits to get in run-time the status of the SDRAM controller
1202 and the data flow.
1203
1204 @endverbatim
1205 * @{
1206 */
1207
1208 /**
1209 * @brief Returns the SDRAM state.
1210 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1211 * the configuration information for SDRAM module.
1212 * @retval HAL state
1213 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)1214 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1215 {
1216 return hsdram->State;
1217 }
1218
1219 /**
1220 * @}
1221 */
1222
1223 /**
1224 * @}
1225 */
1226
1227 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
1228 * @{
1229 */
1230 /**
1231 * @brief DMA SDRAM process complete callback.
1232 * @param hdma : DMA handle
1233 * @retval None
1234 */
SDRAM_DMACplt(DMA_HandleTypeDef * hdma)1235 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma)
1236 {
1237 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1238
1239 /* Disable the DMA channel */
1240 __HAL_DMA_DISABLE(hdma);
1241
1242 /* Update the SDRAM controller state */
1243 hsdram->State = HAL_SDRAM_STATE_READY;
1244
1245 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1246 hsdram->DmaXferCpltCallback(hdma);
1247 #else
1248 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1249 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1250 }
1251
1252 /**
1253 * @brief DMA SRAM process complete callback.
1254 * @param hdma : DMA handle
1255 * @retval None
1256 */
SDRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1257 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1258 {
1259 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1260
1261 /* Disable the DMA channel */
1262 __HAL_DMA_DISABLE(hdma);
1263
1264 /* Update the SDRAM controller state */
1265 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1266
1267 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1268 hsdram->DmaXferCpltCallback(hdma);
1269 #else
1270 HAL_SDRAM_DMA_XferCpltCallback(hdma);
1271 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1272 }
1273
1274 /**
1275 * @brief DMA SDRAM error callback.
1276 * @param hdma : DMA handle
1277 * @retval None
1278 */
SDRAM_DMAError(DMA_HandleTypeDef * hdma)1279 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma)
1280 {
1281 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent);
1282
1283 /* Disable the DMA channel */
1284 __HAL_DMA_DISABLE(hdma);
1285
1286 /* Update the SDRAM controller state */
1287 hsdram->State = HAL_SDRAM_STATE_ERROR;
1288
1289 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1290 hsdram->DmaXferErrorCallback(hdma);
1291 #else
1292 HAL_SDRAM_DMA_XferErrorCallback(hdma);
1293 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1294 }
1295
1296 /**
1297 * @}
1298 */
1299 /**
1300 * @}
1301 */
1302
1303 #endif /* HAL_SDRAM_MODULE_ENABLED */
1304
1305 /**
1306 * @}
1307 */
1308
1309
