1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_hal_cec.h 4 * @author MCD Application Team 5 * @brief Header file of CEC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F7xx_HAL_CEC_H 21 #define STM32F7xx_HAL_CEC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f7xx_hal_def.h" 29 30 #if defined (CEC) 31 32 /** @addtogroup STM32F7xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup CEC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup CEC_Exported_Types CEC Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief CEC Init Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. 51 It can be one of CEC_Signal_Free_Time 52 and belongs to the set {0,...,7} where 53 0x0 is the default configuration 54 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ 55 56 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, 57 it can be a value of CEC_Tolerance : 58 it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ 59 60 uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising 61 Error stops the reception. 62 CEC_NO_RX_STOP_ON_BRE: reception is not stopped. 63 CEC_RX_STOP_ON_BRE: reception is stopped. */ 64 65 uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an 66 Error-Bit is generated on the 67 CEC line upon Bit Rising Error detection. 68 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. 69 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ 70 71 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an 72 Error-Bit is generated on the 73 CEC line upon Long Bit Period Error detection. 74 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. 75 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ 76 77 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an 78 Error-Bit generation on the CEC line 79 upon an error detected on a broadcast message. 80 81 It supersedes BREGEN and LBPEGEN bits for a broadcast message error 82 handling. It can take two values: 83 84 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. 85 a) BRE detection: error-bit generation on the CEC line if 86 BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. 87 b) LBPE detection: error-bit generation on the CEC line 88 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 89 90 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. 91 no error-bit generation in case neither a) nor b) are satisfied. 92 Additionally, there is no error-bit generation in case of Short Bit 93 Period Error detection in a broadcast message while LSTN bit is set. */ 94 95 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. 96 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. 97 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end 98 of message transmission/reception. */ 99 100 uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. 101 It can take two values: 102 103 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed 104 to its own address (OAR). Messages addressed to different destination 105 are ignored. 106 Broadcast messages are always received. 107 108 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its 109 own address (OAR) with positive acknowledge. Messages addressed to 110 different destination are received, but without interfering with the 111 CEC bus: no acknowledge sent. */ 112 113 uint16_t OwnAddress; /*!< Own addresses configuration 114 This parameter can be a value of CEC_OWN_ADDRESS */ 115 116 uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ 117 118 119 } CEC_InitTypeDef; 120 121 /** 122 * @brief HAL CEC State definition 123 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState 124 (see CEC_State_Definition). 125 * - gState contains CEC state information related to global Handle management 126 * and also information related to Tx operations. 127 * gState value coding follow below described bitmap : 128 * b7 (not used) 129 * x : Should be set to 0 130 * b6 Error information 131 * 0 : No Error 132 * 1 : Error 133 * b5 CEC peripheral initialization status 134 * 0 : Reset (peripheral not initialized) 135 * 1 : Init done (peripheral initialized. HAL CEC Init function already called) 136 * b4-b3 (not used) 137 * xx : Should be set to 00 138 * b2 Intrinsic process state 139 * 0 : Ready 140 * 1 : Busy (peripheral busy with some configuration or internal operations) 141 * b1 (not used) 142 * x : Should be set to 0 143 * b0 Tx state 144 * 0 : Ready (no Tx operation ongoing) 145 * 1 : Busy (Tx operation ongoing) 146 * - RxState contains information related to Rx operations. 147 * RxState value coding follow below described bitmap : 148 * b7-b6 (not used) 149 * xx : Should be set to 00 150 * b5 CEC peripheral initialization status 151 * 0 : Reset (peripheral not initialized) 152 * 1 : Init done (peripheral initialized) 153 * b4-b2 (not used) 154 * xxx : Should be set to 000 155 * b1 Rx state 156 * 0 : Ready (no Rx operation ongoing) 157 * 1 : Busy (Rx operation ongoing) 158 * b0 (not used) 159 * x : Should be set to 0. 160 */ 161 typedef uint32_t HAL_CEC_StateTypeDef; 162 163 /** 164 * @brief CEC handle Structure definition 165 */ 166 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 167 typedef struct __CEC_HandleTypeDef 168 #else 169 typedef struct 170 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 171 { 172 CEC_TypeDef *Instance; /*!< CEC registers base address */ 173 174 CEC_InitTypeDef Init; /*!< CEC communication parameters */ 175 176 const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ 177 178 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ 179 180 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ 181 182 HAL_LockTypeDef Lock; /*!< Locking object */ 183 184 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management 185 and also related to Tx operations. 186 This parameter can be a value of HAL_CEC_StateTypeDef */ 187 188 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. 189 This parameter can be a value of HAL_CEC_StateTypeDef */ 190 191 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register 192 in case error is reported */ 193 194 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 195 void (* TxCpltCallback)(struct __CEC_HandleTypeDef 196 *hcec); /*!< CEC Tx Transfer completed callback */ 197 void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, 198 uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ 199 void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ 200 201 void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ 202 void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ 203 204 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ 205 } CEC_HandleTypeDef; 206 207 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 208 /** 209 * @brief HAL CEC Callback ID enumeration definition 210 */ 211 typedef enum 212 { 213 HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ 214 HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ 215 HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ 216 HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ 217 HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ 218 } HAL_CEC_CallbackIDTypeDef; 219 220 /** 221 * @brief HAL CEC Callback pointer definition 222 */ 223 typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ 224 typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, 225 uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed 226 callback function */ 227 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 228 /** 229 * @} 230 */ 231 232 /* Exported constants --------------------------------------------------------*/ 233 /** @defgroup CEC_Exported_Constants CEC Exported Constants 234 * @{ 235 */ 236 /** @defgroup CEC_State_Definition CEC State Code Definition 237 * @{ 238 */ 239 #define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized 240 Value is allowed for gState and RxState */ 241 #define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use 242 Value is allowed for gState and RxState */ 243 #define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing 244 Value is allowed for gState only */ 245 #define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing 246 Value is allowed for RxState only */ 247 #define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing 248 Value is allowed for gState only */ 249 #define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing 250 Value is allowed for gState only */ 251 #define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ 252 /** 253 * @} 254 */ 255 /** @defgroup CEC_Error_Code CEC Error Code 256 * @{ 257 */ 258 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ 259 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ 260 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ 261 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ 262 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ 263 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ 264 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ 265 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ 266 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ 267 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ 268 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 269 #define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */ 270 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 271 /** 272 * @} 273 */ 274 275 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter 276 * @{ 277 */ 278 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) 279 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) 280 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) 281 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) 282 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) 283 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) 284 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) 285 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) 286 /** 287 * @} 288 */ 289 290 /** @defgroup CEC_Tolerance CEC Receiver Tolerance 291 * @{ 292 */ 293 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) 294 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) 295 /** 296 * @} 297 */ 298 299 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error 300 * @{ 301 */ 302 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) 303 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) 304 /** 305 * @} 306 */ 307 308 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported 309 * @{ 310 */ 311 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 312 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) 313 /** 314 * @} 315 */ 316 317 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported 318 * @{ 319 */ 320 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 321 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) 322 /** 323 * @} 324 */ 325 326 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message 327 * @{ 328 */ 329 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) 330 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) 331 /** 332 * @} 333 */ 334 335 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option 336 * @{ 337 */ 338 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) 339 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) 340 /** 341 * @} 342 */ 343 344 /** @defgroup CEC_Listening_Mode CEC Listening mode option 345 * @{ 346 */ 347 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) 348 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) 349 /** 350 * @} 351 */ 352 353 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register 354 * @{ 355 */ 356 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) 357 /** 358 * @} 359 */ 360 361 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header 362 * @{ 363 */ 364 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) 365 /** 366 * @} 367 */ 368 369 /** @defgroup CEC_OWN_ADDRESS CEC Own Address 370 * @{ 371 */ 372 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ 373 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ 374 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ 375 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ 376 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ 377 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ 378 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ 379 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ 380 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ 381 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ 382 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ 383 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ 384 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ 385 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ 386 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ 387 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ 388 /** 389 * @} 390 */ 391 392 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition 393 * @{ 394 */ 395 #define CEC_IT_TXACKE CEC_IER_TXACKEIE 396 #define CEC_IT_TXERR CEC_IER_TXERRIE 397 #define CEC_IT_TXUDR CEC_IER_TXUDRIE 398 #define CEC_IT_TXEND CEC_IER_TXENDIE 399 #define CEC_IT_TXBR CEC_IER_TXBRIE 400 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE 401 #define CEC_IT_RXACKE CEC_IER_RXACKEIE 402 #define CEC_IT_LBPE CEC_IER_LBPEIE 403 #define CEC_IT_SBPE CEC_IER_SBPEIE 404 #define CEC_IT_BRE CEC_IER_BREIE 405 #define CEC_IT_RXOVR CEC_IER_RXOVRIE 406 #define CEC_IT_RXEND CEC_IER_RXENDIE 407 #define CEC_IT_RXBR CEC_IER_RXBRIE 408 /** 409 * @} 410 */ 411 412 /** @defgroup CEC_Flags_Definitions CEC Flags definition 413 * @{ 414 */ 415 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE 416 #define CEC_FLAG_TXERR CEC_ISR_TXERR 417 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR 418 #define CEC_FLAG_TXEND CEC_ISR_TXEND 419 #define CEC_FLAG_TXBR CEC_ISR_TXBR 420 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST 421 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE 422 #define CEC_FLAG_LBPE CEC_ISR_LBPE 423 #define CEC_FLAG_SBPE CEC_ISR_SBPE 424 #define CEC_FLAG_BRE CEC_ISR_BRE 425 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR 426 #define CEC_FLAG_RXEND CEC_ISR_RXEND 427 #define CEC_FLAG_RXBR CEC_ISR_RXBR 428 /** 429 * @} 430 */ 431 432 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags 433 * @{ 434 */ 435 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ 436 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) 437 /** 438 * @} 439 */ 440 441 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag 442 * @{ 443 */ 444 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) 445 /** 446 * @} 447 */ 448 449 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag 450 * @{ 451 */ 452 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) 453 /** 454 * @} 455 */ 456 457 /** 458 * @} 459 */ 460 461 /* Exported macros -----------------------------------------------------------*/ 462 /** @defgroup CEC_Exported_Macros CEC Exported Macros 463 * @{ 464 */ 465 466 /** @brief Reset CEC handle gstate & RxState 467 * @param __HANDLE__ CEC handle. 468 * @retval None 469 */ 470 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 471 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 472 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 473 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 474 (__HANDLE__)->MspInitCallback = NULL; \ 475 (__HANDLE__)->MspDeInitCallback = NULL; \ 476 } while(0) 477 #else 478 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 479 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 480 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 481 } while(0) 482 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 483 /** @brief Checks whether or not the specified CEC interrupt flag is set. 484 * @param __HANDLE__ specifies the CEC Handle. 485 * @param __FLAG__ specifies the flag to check. 486 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 487 * @arg CEC_FLAG_TXERR: Tx Error. 488 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 489 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 490 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 491 * @arg CEC_FLAG_ARBLST: Arbitration Lost 492 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 493 * @arg CEC_FLAG_LBPE: Rx Long period Error 494 * @arg CEC_FLAG_SBPE: Rx Short period Error 495 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 496 * @arg CEC_FLAG_RXOVR: Rx Overrun. 497 * @arg CEC_FLAG_RXEND: End Of Reception. 498 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 499 * @retval ITStatus 500 */ 501 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 502 503 /** @brief Clears the interrupt or status flag when raised (write at 1) 504 * @param __HANDLE__ specifies the CEC Handle. 505 * @param __FLAG__ specifies the interrupt/status flag to clear. 506 * This parameter can be one of the following values: 507 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 508 * @arg CEC_FLAG_TXERR: Tx Error. 509 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 510 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 511 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 512 * @arg CEC_FLAG_ARBLST: Arbitration Lost 513 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 514 * @arg CEC_FLAG_LBPE: Rx Long period Error 515 * @arg CEC_FLAG_SBPE: Rx Short period Error 516 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 517 * @arg CEC_FLAG_RXOVR: Rx Overrun. 518 * @arg CEC_FLAG_RXEND: End Of Reception. 519 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 520 * @retval none 521 */ 522 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 523 524 /** @brief Enables the specified CEC interrupt. 525 * @param __HANDLE__ specifies the CEC Handle. 526 * @param __INTERRUPT__ specifies the CEC interrupt to enable. 527 * This parameter can be one of the following values: 528 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 529 * @arg CEC_IT_TXERR: Tx Error IT Enable 530 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 531 * @arg CEC_IT_TXEND: End of transmission IT Enable 532 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 533 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 534 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 535 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 536 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 537 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 538 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 539 * @arg CEC_IT_RXEND: End Of Reception IT Enable 540 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 541 * @retval none 542 */ 543 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 544 545 /** @brief Disables the specified CEC interrupt. 546 * @param __HANDLE__ specifies the CEC Handle. 547 * @param __INTERRUPT__ specifies the CEC interrupt to disable. 548 * This parameter can be one of the following values: 549 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 550 * @arg CEC_IT_TXERR: Tx Error IT Enable 551 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 552 * @arg CEC_IT_TXEND: End of transmission IT Enable 553 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 554 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 555 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 556 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 557 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 558 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 559 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 560 * @arg CEC_IT_RXEND: End Of Reception IT Enable 561 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 562 * @retval none 563 */ 564 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 565 566 /** @brief Checks whether or not the specified CEC interrupt is enabled. 567 * @param __HANDLE__ specifies the CEC Handle. 568 * @param __INTERRUPT__ specifies the CEC interrupt to check. 569 * This parameter can be one of the following values: 570 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 571 * @arg CEC_IT_TXERR: Tx Error IT Enable 572 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 573 * @arg CEC_IT_TXEND: End of transmission IT Enable 574 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 575 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 576 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 577 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 578 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 579 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 580 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 581 * @arg CEC_IT_RXEND: End Of Reception IT Enable 582 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 583 * @retval FlagStatus 584 */ 585 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 586 587 /** @brief Enables the CEC device 588 * @param __HANDLE__ specifies the CEC Handle. 589 * @retval none 590 */ 591 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) 592 593 /** @brief Disables the CEC device 594 * @param __HANDLE__ specifies the CEC Handle. 595 * @retval none 596 */ 597 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) 598 599 /** @brief Set Transmission Start flag 600 * @param __HANDLE__ specifies the CEC Handle. 601 * @retval none 602 */ 603 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) 604 605 /** @brief Set Transmission End flag 606 * @param __HANDLE__ specifies the CEC Handle. 607 * @retval none 608 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. 609 */ 610 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) 611 612 /** @brief Get Transmission Start flag 613 * @param __HANDLE__ specifies the CEC Handle. 614 * @retval FlagStatus 615 */ 616 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) 617 618 /** @brief Get Transmission End flag 619 * @param __HANDLE__ specifies the CEC Handle. 620 * @retval FlagStatus 621 */ 622 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) 623 624 /** @brief Clear OAR register 625 * @param __HANDLE__ specifies the CEC Handle. 626 * @retval none 627 */ 628 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) 629 630 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) 631 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand 632 * @param __HANDLE__ specifies the CEC Handle. 633 * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) 634 * @retval none 635 */ 636 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ 637 (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) 638 639 /** 640 * @} 641 */ 642 643 /* Exported functions --------------------------------------------------------*/ 644 /** @addtogroup CEC_Exported_Functions 645 * @{ 646 */ 647 648 /** @addtogroup CEC_Exported_Functions_Group1 649 * @{ 650 */ 651 /* Initialization and de-initialization functions ****************************/ 652 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); 653 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); 654 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); 655 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); 656 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); 657 658 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 659 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, 660 pCEC_CallbackTypeDef pCallback); 661 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); 662 663 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); 664 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); 665 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 666 /** 667 * @} 668 */ 669 670 /** @addtogroup CEC_Exported_Functions_Group2 671 * @{ 672 */ 673 /* I/O operation functions ***************************************************/ 674 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, 675 const uint8_t *pData, uint32_t Size); 676 uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); 677 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); 678 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); 679 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); 680 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); 681 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); 682 /** 683 * @} 684 */ 685 686 /** @addtogroup CEC_Exported_Functions_Group3 687 * @{ 688 */ 689 /* Peripheral State functions ************************************************/ 690 HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); 691 uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); 692 /** 693 * @} 694 */ 695 696 /** 697 * @} 698 */ 699 700 /* Private types -------------------------------------------------------------*/ 701 /** @defgroup CEC_Private_Types CEC Private Types 702 * @{ 703 */ 704 705 /** 706 * @} 707 */ 708 709 /* Private variables ---------------------------------------------------------*/ 710 /** @defgroup CEC_Private_Variables CEC Private Variables 711 * @{ 712 */ 713 714 /** 715 * @} 716 */ 717 718 /* Private constants ---------------------------------------------------------*/ 719 /** @defgroup CEC_Private_Constants CEC Private Constants 720 * @{ 721 */ 722 723 /** 724 * @} 725 */ 726 727 /* Private macros ------------------------------------------------------------*/ 728 /** @defgroup CEC_Private_Macros CEC Private Macros 729 * @{ 730 */ 731 732 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) 733 734 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ 735 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) 736 737 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ 738 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) 739 740 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ 741 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) 742 743 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ 744 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) 745 746 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ 747 (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ 748 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) 749 750 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ 751 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) 752 753 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ 754 ((__MODE__) == CEC_FULL_LISTENING_MODE)) 755 756 /** @brief Check CEC message size. 757 * The message size is the payload size: without counting the header, 758 * it varies from 0 byte (ping operation, one header only, no payload) to 759 * 15 bytes (1 opcode and up to 14 operands following the header). 760 * @param __SIZE__ CEC message size. 761 * @retval Test result (TRUE or FALSE). 762 */ 763 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) 764 765 /** @brief Check CEC device Own Address Register (OAR) setting. 766 * OAR address is written in a 15-bit field within CEC_CFGR register. 767 * @param __ADDRESS__ CEC own address. 768 * @retval Test result (TRUE or FALSE). 769 */ 770 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) 771 772 /** @brief Check CEC initiator or destination logical address setting. 773 * Initiator and destination addresses are coded over 4 bits. 774 * @param __ADDRESS__ CEC initiator or logical address. 775 * @retval Test result (TRUE or FALSE). 776 */ 777 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU) 778 /** 779 * @} 780 */ 781 /* Private functions ---------------------------------------------------------*/ 782 /** @defgroup CEC_Private_Functions CEC Private Functions 783 * @{ 784 */ 785 786 /** 787 * @} 788 */ 789 790 /** 791 * @} 792 */ 793 794 /** 795 * @} 796 */ 797 798 #endif /* CEC */ 799 800 #ifdef __cplusplus 801 } 802 #endif 803 804 #endif /* STM32F7xxHAL_CEC_H */ 805
