1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 *Copyright (c) 2017 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32F4xx_LL_SYSTEM_H
35 #define __STM32F4xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32f4xx.h"
43
44 /** @addtogroup STM32F4xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61
62 /**
63 * @}
64 */
65
66 /* Private macros ------------------------------------------------------------*/
67
68 /* Exported types ------------------------------------------------------------*/
69 /* Exported constants --------------------------------------------------------*/
70 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
71 * @{
72 */
73
74 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
75 * @{
76 */
77 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */
78 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
79 #if defined(FSMC_Bank1)
80 #define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
81 #endif /* FSMC_Bank1 */
82 #if defined(FMC_Bank1)
83 #define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */
84 #define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */
85 #endif /* FMC_Bank1 */
86 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
87
88 /**
89 * @}
90 */
91
92 #if defined(SYSCFG_PMC_MII_RMII_SEL)
93 /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
94 * @{
95 */
96 #define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */
97 #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
98
99 /**
100 * @}
101 */
102 #endif /* SYSCFG_PMC_MII_RMII_SEL */
103
104
105
106 #if defined(SYSCFG_MEMRMP_UFB_MODE)
107 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
108 * @{
109 */
110 #define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
111 and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
112 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
113 and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
114 /**
115 * @}
116 */
117 #endif /* SYSCFG_MEMRMP_UFB_MODE */
118 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
119 * @{
120 */
121 #if defined(SYSCFG_CFGR_FMPI2C1_SCL)
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
123 #define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
124 #endif /* SYSCFG_CFGR_FMPI2C1_SCL */
125 /**
126 * @}
127 */
128
129 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
130 * @{
131 */
132 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
133 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
134 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
135 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
136 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
137 #if defined(GPIOF)
138 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
139 #endif /* GPIOF */
140 #if defined(GPIOG)
141 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
142 #endif /* GPIOG */
143 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */
144 #if defined(GPIOI)
145 #define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */
146 #endif /* GPIOI */
147 #if defined(GPIOJ)
148 #define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */
149 #endif /* GPIOJ */
150 #if defined(GPIOK)
151 #define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */
152 #endif /* GPIOK */
153 /**
154 * @}
155 */
156
157 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
158 * @{
159 */
160 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
161 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
162 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
163 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
164 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
165 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
166 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
167 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
168 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
169 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
170 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
171 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
172 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
173 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
174 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
175 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
176 /**
177 * @}
178 */
179
180 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
181 * @{
182 */
183 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
184 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
185 with Break Input of TIM1/8 */
186 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
187 and also the PVDE and PLS bits of the Power Control Interface */
188 #endif /* SYSCFG_CFGR2_CLL */
189 /**
190 * @}
191 */
192
193 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
194 /** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
195 * @{
196 */
197 #define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
198 #define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
199 /**
200 * @}
201 */
202 /** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
203 * @{
204 */
205 #define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
206 #define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
207 /**
208 * @}
209 */
210 /** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL
211 * @{
212 */
213 #define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
214 #define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
215
216 #define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
217 #define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
218 #define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
219 #define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
220 /**
221 * @}
222 */
223 /** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
224 * @{
225 */
226 #define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
227 #define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
228
229 #define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
230 #define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
231 #define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
232 #define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
233 /**
234 * @}
235 */
236 /** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
237 * @{
238 */
239 #define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
240 #define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
241 /**
242 * @}
243 */
244 /** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
245 * @{
246 */
247 #define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
248 #define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
249 /**
250 * @}
251 */
252 /** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
253 * @{
254 */
255 #define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
256 #define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
257 /**
258 * @}
259 */
260 /** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
261 * @{
262 */
263 #define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
264 #define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
265 /**
266 * @}
267 */
268
269 /** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
270 * @{
271 */
272 #define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
273 #define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
274 /**
275 * @}
276 */
277 /** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
278 * @{
279 */
280 #define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
281 #define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
282 /**
283 * @}
284 */
285 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
286 * @{
287 */
288 #define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
289 #define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
290 /**
291 * @}
292 */
293 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
294 * @{
295 */
296 #define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
297 #define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
298 /**
299 * @}
300 */
301 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
302 * @{
303 */
304 #define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
305 #define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
306 /**
307 * @}
308 */
309 /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
310 * @{
311 */
312 #define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
313 #define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
314 /**
315 * @}
316 */
317 /** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
318 * @{
319 */
320 #define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
321 #define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
322 /**
323 * @}
324 */
325 /** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
326 * @{
327 */
328 #define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
329 #define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
330 /**
331 * @}
332 */
333 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
334
335 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
336 * @{
337 */
338 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
339 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
340 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
341 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
342 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
343 /**
344 * @}
345 */
346
347 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
348 * @{
349 */
350 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
351 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
352 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
353 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
354 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
355 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
356 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
357 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
358 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
359 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
360 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
361 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
362 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
363 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
364 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
365 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
366 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
367 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
368 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
369 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
370 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
371 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
372 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
373 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
374 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
375 #if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
376 #define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /*!< LPTIM counter stopped when core is halted */
377 #endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
378 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
379 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
380 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
381 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
382 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
383 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
384 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
385 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
386 #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
387 #define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
388 #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
389 #if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
390 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
391 #endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
392 #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
393 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
394 #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
395 #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
396 #define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */
397 #endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
398 /**
399 * @}
400 */
401
402 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
403 * @{
404 */
405 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
406 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
407 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
408 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
409 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
410 #if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
411 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
412 #endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
413 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
414 /**
415 * @}
416 */
417
418 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
419 * @{
420 */
421 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
422 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
423 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
424 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
425 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
426 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
427 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
428 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
429 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
430 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
431 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
432 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
433 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
434 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
435 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
436 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
437 /**
438 * @}
439 */
440
441 /**
442 * @}
443 */
444
445 /* Exported macro ------------------------------------------------------------*/
446
447 /* Exported functions --------------------------------------------------------*/
448 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
449 * @{
450 */
451
452 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
453 * @{
454 */
455 /**
456 * @brief Set memory mapping at address 0x00000000
457 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
458 * @param Memory This parameter can be one of the following values:
459 * @arg @ref LL_SYSCFG_REMAP_FLASH
460 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
461 * @arg @ref LL_SYSCFG_REMAP_SRAM
462 * @arg @ref LL_SYSCFG_REMAP_FSMC (*)
463 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
464 * @retval None
465 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)466 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
467 {
468 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
469 }
470
471 /**
472 * @brief Get memory mapping at address 0x00000000
473 * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
474 * @retval Returned value can be one of the following values:
475 * @arg @ref LL_SYSCFG_REMAP_FLASH
476 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
477 * @arg @ref LL_SYSCFG_REMAP_SRAM
478 * @arg @ref LL_SYSCFG_REMAP_FSMC (*)
479 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
480 */
LL_SYSCFG_GetRemapMemory(void)481 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
482 {
483 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
484 }
485
486 #if defined(SYSCFG_MEMRMP_SWP_FMC)
487 /**
488 * @brief Enables the FMC Memory Mapping Swapping
489 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
490 * @note SDRAM is accessible at 0x60000000 and NOR/RAM
491 * is accessible at 0xC0000000
492 * @retval None
493 */
LL_SYSCFG_EnableFMCMemorySwapping(void)494 __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
495 {
496 SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
497 }
498
499 /**
500 * @brief Disables the FMC Memory Mapping Swapping
501 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
502 * @note SDRAM is accessible at 0xC0000000 (default mapping)
503 * and NOR/RAM is accessible at 0x60000000 (default mapping)
504 * @retval None
505 */
LL_SYSCFG_DisableFMCMemorySwapping(void)506 __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
507 {
508 CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
509 }
510
511 #endif /* SYSCFG_MEMRMP_SWP_FMC */
512 /**
513 * @brief Enables the Compensation cell Power Down
514 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
515 * @note The I/O compensation cell can be used only when the device supply
516 * voltage ranges from 2.4 to 3.6 V
517 * @retval None
518 */
LL_SYSCFG_EnableCompensationCell(void)519 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
520 {
521 SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
522 }
523
524 /**
525 * @brief Disables the Compensation cell Power Down
526 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
527 * @note The I/O compensation cell can be used only when the device supply
528 * voltage ranges from 2.4 to 3.6 V
529 * @retval None
530 */
LL_SYSCFG_DisableCompensationCell(void)531 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
532 {
533 CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
534 }
535
536 /**
537 * @brief Get Compensation Cell ready Flag
538 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
539 * @retval State of bit (1 or 0).
540 */
LL_SYSCFG_IsActiveFlag_CMPCR(void)541 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
542 {
543 return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
544 }
545
546 #if defined(SYSCFG_PMC_MII_RMII_SEL)
547 /**
548 * @brief Select Ethernet PHY interface
549 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
550 * @param Interface This parameter can be one of the following values:
551 * @arg @ref LL_SYSCFG_PMC_ETHMII
552 * @arg @ref LL_SYSCFG_PMC_ETHRMII
553 * @retval None
554 */
LL_SYSCFG_SetPHYInterface(uint32_t Interface)555 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
556 {
557 MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
558 }
559
560 /**
561 * @brief Get Ethernet PHY interface
562 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
563 * @retval Returned value can be one of the following values:
564 * @arg @ref LL_SYSCFG_PMC_ETHMII
565 * @arg @ref LL_SYSCFG_PMC_ETHRMII
566 * @retval None
567 */
LL_SYSCFG_GetPHYInterface(void)568 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
569 {
570 return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
571 }
572 #endif /* SYSCFG_PMC_MII_RMII_SEL */
573
574
575
576 #if defined(SYSCFG_MEMRMP_UFB_MODE)
577 /**
578 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
579 * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode
580 * @param Bank This parameter can be one of the following values:
581 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
582 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
583 * @retval None
584 */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)585 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
586 {
587 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
588 }
589
590 /**
591 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
592 * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode
593 * @retval Returned value can be one of the following values:
594 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
595 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
596 */
LL_SYSCFG_GetFlashBankMode(void)597 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
598 {
599 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
600 }
601 #endif /* SYSCFG_MEMRMP_UFB_MODE */
602
603 #if defined(SYSCFG_CFGR_FMPI2C1_SCL)
604 /**
605 * @brief Enable the I2C fast mode plus driving capability.
606 * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n
607 * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus
608 * @param ConfigFastModePlus This parameter can be a combination of the following values:
609 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
610 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
611 * (*) value not defined in all devices
612 * @retval None
613 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)614 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
615 {
616 SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
617 }
618
619 /**
620 * @brief Disable the I2C fast mode plus driving capability.
621 * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n
622 * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n
623 * @param ConfigFastModePlus This parameter can be a combination of the following values:
624 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
625 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
626 * (*) value not defined in all devices
627 * @retval None
628 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)629 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
630 {
631 CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
632 }
633 #endif /* SYSCFG_CFGR_FMPI2C1_SCL */
634
635 /**
636 * @brief Configure source input for the EXTI external interrupt.
637 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
638 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
639 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
640 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
641 * @param Port This parameter can be one of the following values:
642 * @arg @ref LL_SYSCFG_EXTI_PORTA
643 * @arg @ref LL_SYSCFG_EXTI_PORTB
644 * @arg @ref LL_SYSCFG_EXTI_PORTC
645 * @arg @ref LL_SYSCFG_EXTI_PORTD
646 * @arg @ref LL_SYSCFG_EXTI_PORTE
647 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
648 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
649 * @arg @ref LL_SYSCFG_EXTI_PORTH
650 *
651 * (*) value not defined in all devices
652 * @param Line This parameter can be one of the following values:
653 * @arg @ref LL_SYSCFG_EXTI_LINE0
654 * @arg @ref LL_SYSCFG_EXTI_LINE1
655 * @arg @ref LL_SYSCFG_EXTI_LINE2
656 * @arg @ref LL_SYSCFG_EXTI_LINE3
657 * @arg @ref LL_SYSCFG_EXTI_LINE4
658 * @arg @ref LL_SYSCFG_EXTI_LINE5
659 * @arg @ref LL_SYSCFG_EXTI_LINE6
660 * @arg @ref LL_SYSCFG_EXTI_LINE7
661 * @arg @ref LL_SYSCFG_EXTI_LINE8
662 * @arg @ref LL_SYSCFG_EXTI_LINE9
663 * @arg @ref LL_SYSCFG_EXTI_LINE10
664 * @arg @ref LL_SYSCFG_EXTI_LINE11
665 * @arg @ref LL_SYSCFG_EXTI_LINE12
666 * @arg @ref LL_SYSCFG_EXTI_LINE13
667 * @arg @ref LL_SYSCFG_EXTI_LINE14
668 * @arg @ref LL_SYSCFG_EXTI_LINE15
669 * @retval None
670 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)671 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
672 {
673 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
674 }
675
676 /**
677 * @brief Get the configured defined for specific EXTI Line
678 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
679 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
680 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
681 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
682 * @param Line This parameter can be one of the following values:
683 * @arg @ref LL_SYSCFG_EXTI_LINE0
684 * @arg @ref LL_SYSCFG_EXTI_LINE1
685 * @arg @ref LL_SYSCFG_EXTI_LINE2
686 * @arg @ref LL_SYSCFG_EXTI_LINE3
687 * @arg @ref LL_SYSCFG_EXTI_LINE4
688 * @arg @ref LL_SYSCFG_EXTI_LINE5
689 * @arg @ref LL_SYSCFG_EXTI_LINE6
690 * @arg @ref LL_SYSCFG_EXTI_LINE7
691 * @arg @ref LL_SYSCFG_EXTI_LINE8
692 * @arg @ref LL_SYSCFG_EXTI_LINE9
693 * @arg @ref LL_SYSCFG_EXTI_LINE10
694 * @arg @ref LL_SYSCFG_EXTI_LINE11
695 * @arg @ref LL_SYSCFG_EXTI_LINE12
696 * @arg @ref LL_SYSCFG_EXTI_LINE13
697 * @arg @ref LL_SYSCFG_EXTI_LINE14
698 * @arg @ref LL_SYSCFG_EXTI_LINE15
699 * @retval Returned value can be one of the following values:
700 * @arg @ref LL_SYSCFG_EXTI_PORTA
701 * @arg @ref LL_SYSCFG_EXTI_PORTB
702 * @arg @ref LL_SYSCFG_EXTI_PORTC
703 * @arg @ref LL_SYSCFG_EXTI_PORTD
704 * @arg @ref LL_SYSCFG_EXTI_PORTE
705 * @arg @ref LL_SYSCFG_EXTI_PORTF (*)
706 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
707 * @arg @ref LL_SYSCFG_EXTI_PORTH
708 * (*) value not defined in all devices
709 */
LL_SYSCFG_GetEXTISource(uint32_t Line)710 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
711 {
712 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
713 }
714
715 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
716 /**
717 * @brief Set connections to TIM1/8 break inputs
718 * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
719 * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
720 * @param Break This parameter can be a combination of the following values:
721 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
722 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
723 * @retval None
724 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)725 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
726 {
727 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
728 }
729
730 /**
731 * @brief Get connections to TIM1/8 Break inputs
732 * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n
733 * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs
734 * @retval Returned value can be can be a combination of the following values:
735 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
736 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
737 */
LL_SYSCFG_GetTIMBreakInputs(void)738 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
739 {
740 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
741 }
742 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
743 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
744 /**
745 * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
746 * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
747 * @param ClockSource This parameter can be one of the following values:
748 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
749 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
750 * @retval None
751 */
LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)752 __STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
753 {
754 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
755 }
756 /**
757 * @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
758 * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
759 * @retval Returned value can be one of the following values:
760 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
761 * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
762 * @retval None
763 */
LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)764 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
765 {
766 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
767 }
768 /**
769 * @brief Enables the DFSDM1 or DFSDM2 Delay clock
770 * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock
771 * @param MCHDLY This parameter can be one of the following values
772 * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
773 * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
774 * @retval None
775 */
LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)776 __STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
777 {
778 SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
779 }
780
781 /**
782 * @brief Disables the DFSDM1 or the DFSDM2 Delay clock
783 * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock
784 * @param MCHDLY This parameter can be one of the following values
785 * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
786 * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
787 * @retval None
788 */
LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)789 __STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
790 {
791 CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
792 }
793
794 /**
795 * @brief Select the source for DFSDM1 or DFSDM2 DatIn0
796 * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
797 * @param Source This parameter can be one of the following values:
798 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
799 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
800 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
801 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
802 * @retval None
803 */
LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)804 __STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
805 {
806 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
807 }
808 /**
809 * @brief Get the source for DFSDM1 or DFSDM2 DatIn0.
810 * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source
811 * @param Source This parameter can be one of the following values:
812 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0
813 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0
814 * @retval Returned value can be one of the following values:
815 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
816 * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
817 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
818 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
819 * @retval None
820 */
LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)821 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
822 {
823 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
824 }
825 /**
826 * @brief Select the source for DFSDM1 or DFSDM2 DatIn2
827 * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
828 * @param Source This parameter can be one of the following values:
829 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
830 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
831 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
832 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
833 * @retval None
834 */
LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)835 __STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
836 {
837 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
838 }
839 /**
840 * @brief Get the source for DFSDM1 or DFSDM2 DatIn2.
841 * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source
842 * @param Source This parameter can be one of the following values:
843 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2
844 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2
845 * @retval Returned value can be one of the following values:
846 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
847 * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
848 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
849 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
850 * @retval None
851 */
LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)852 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
853 {
854 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
855 }
856
857 /**
858 * @brief Select the distribution of the bitsream lock gated by TIM4 OC2
859 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
860 * @param Source This parameter can be one of the following values:
861 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
862 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
863 * @retval None
864 */
LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)865 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
866 {
867 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
868 }
869 /**
870 * @brief Get the distribution of the bitsream lock gated by TIM4 OC2
871 * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
872 * @retval Returned value can be one of the following values:
873 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
874 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
875 * @retval None
876 */
LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)877 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
878 {
879 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
880 }
881
882 /**
883 * @brief Select the distribution of the bitsream lock gated by TIM4 OC1
884 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
885 * @param Source This parameter can be one of the following values:
886 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
887 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
888 * @retval None
889 */
LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)890 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
891 {
892 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
893 }
894 /**
895 * @brief Get the distribution of the bitsream lock gated by TIM4 OC1
896 * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
897 * @retval Returned value can be one of the following values:
898 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
899 * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
900 * @retval None
901 */
LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)902 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
903 {
904 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
905 }
906
907 /**
908 * @brief Select the DFSDM1 Clock In
909 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
910 * @param ClockSource This parameter can be one of the following values:
911 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
912 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
913 * @retval None
914 */
LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)915 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
916 {
917 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
918 }
919 /**
920 * @brief GET the DFSDM1 Clock In
921 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection
922 * @retval Returned value can be one of the following values:
923 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
924 * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
925 * @retval None
926 */
LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)927 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
928 {
929 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
930 }
931
932 /**
933 * @brief Select the DFSDM1 Clock Out
934 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
935 * @param ClockSource This parameter can be one of the following values:
936 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT
937 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
938 * @retval None
939 */
LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)940 __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
941 {
942 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
943 }
944 /**
945 * @brief GET the DFSDM1 Clock Out
946 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
947 * @retval Returned value can be one of the following values:
948 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT
949 * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
950 * @retval None
951 */
LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)952 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
953 {
954 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
955 }
956
957 /**
958 * @brief Enables the DFSDM2 Delay clock
959 * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock
960 * @retval None
961 */
LL_SYSCFG_DFSDM2_EnableDelayClock(void)962 __STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
963 {
964 SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
965 }
966
967 /**
968 * @brief Disables the DFSDM2 Delay clock
969 * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock
970 * @retval None
971 */
LL_SYSCFG_DFSDM2_DisableDelayClock(void)972 __STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
973 {
974 CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
975 }
976 /**
977 * @brief Select the source for DFSDM2 DatIn0
978 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
979 * @param Source This parameter can be one of the following values:
980 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
981 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
982 * @retval None
983 */
LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)984 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
985 {
986 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
987 }
988 /**
989 * @brief Get the source for DFSDM2 DatIn0.
990 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source
991 * @retval Returned value can be one of the following values:
992 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
993 * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
994 * @retval None
995 */
LL_SYSCFG_DFSDM2_GetDataIn0Source(void)996 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
997 {
998 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
999 }
1000
1001 /**
1002 * @brief Select the source for DFSDM2 DatIn2
1003 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
1004 * @param Source This parameter can be one of the following values:
1005 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
1006 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
1007 * @retval None
1008 */
LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)1009 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
1010 {
1011 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
1012 }
1013 /**
1014 * @brief Get the source for DFSDM2 DatIn2.
1015 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source
1016 * @retval Returned value can be one of the following values:
1017 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
1018 * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
1019 * @retval None
1020 */
LL_SYSCFG_DFSDM2_GetDataIn2Source(void)1021 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
1022 {
1023 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
1024 }
1025
1026 /**
1027 * @brief Select the source for DFSDM2 DatIn4
1028 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
1029 * @param Source This parameter can be one of the following values:
1030 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
1031 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
1032 * @retval None
1033 */
LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)1034 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
1035 {
1036 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
1037 }
1038 /**
1039 * @brief Get the source for DFSDM2 DatIn4.
1040 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source
1041 * @retval Returned value can be one of the following values:
1042 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
1043 * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
1044 * @retval None
1045 */
LL_SYSCFG_DFSDM2_GetDataIn4Source(void)1046 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
1047 {
1048 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
1049 }
1050
1051 /**
1052 * @brief Select the source for DFSDM2 DatIn6
1053 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
1054 * @param Source This parameter can be one of the following values:
1055 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
1056 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
1057 * @retval None
1058 */
LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)1059 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
1060 {
1061 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
1062 }
1063 /**
1064 * @brief Get the source for DFSDM2 DatIn6.
1065 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source
1066 * @retval Returned value can be one of the following values:
1067 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
1068 * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
1069 * @retval None
1070 */
LL_SYSCFG_DFSDM2_GetDataIn6Source(void)1071 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
1072 {
1073 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
1074 }
1075
1076 /**
1077 * @brief Select the distribution of the bitsream lock gated by TIM3 OC4
1078 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
1079 * @param Source This parameter can be one of the following values:
1080 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
1081 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
1082 * @retval None
1083 */
LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)1084 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
1085 {
1086 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
1087 }
1088 /**
1089 * @brief Get the distribution of the bitsream lock gated by TIM3 OC4
1090 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
1091 * @retval Returned value can be one of the following values:
1092 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
1093 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
1094 * @retval None
1095 */
LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)1096 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
1097 {
1098 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
1099 }
1100
1101 /**
1102 * @brief Select the distribution of the bitsream lock gated by TIM3 OC3
1103 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
1104 * @param Source This parameter can be one of the following values:
1105 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
1106 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
1107 * @retval None
1108 */
LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)1109 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
1110 {
1111 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
1112 }
1113 /**
1114 * @brief Get the distribution of the bitsream lock gated by TIM3 OC4
1115 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
1116 * @retval Returned value can be one of the following values:
1117 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
1118 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
1119 * @retval None
1120 */
LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)1121 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
1122 {
1123 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
1124 }
1125
1126 /**
1127 * @brief Select the distribution of the bitsream lock gated by TIM3 OC2
1128 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
1129 * @param Source This parameter can be one of the following values:
1130 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
1131 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
1132 * @retval None
1133 */
LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)1134 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
1135 {
1136 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
1137 }
1138 /**
1139 * @brief Get the distribution of the bitsream lock gated by TIM3 OC2
1140 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
1141 * @retval Returned value can be one of the following values:
1142 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
1143 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
1144 * @retval None
1145 */
LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)1146 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
1147 {
1148 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
1149 }
1150
1151 /**
1152 * @brief Select the distribution of the bitsream lock gated by TIM3 OC1
1153 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
1154 * @param Source This parameter can be one of the following values:
1155 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
1156 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
1157 * @retval None
1158 */
LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)1159 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
1160 {
1161 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
1162 }
1163 /**
1164 * @brief Get the distribution of the bitsream lock gated by TIM3 OC1
1165 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
1166 * @retval Returned value can be one of the following values:
1167 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
1168 * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
1169 * @retval None
1170 */
LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)1171 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
1172 {
1173 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
1174 }
1175
1176 /**
1177 * @brief Select the DFSDM2 Clock In
1178 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
1179 * @param ClockSource This parameter can be one of the following values:
1180 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
1181 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
1182 * @retval None
1183 */
LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)1184 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
1185 {
1186 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
1187 }
1188 /**
1189 * @brief GET the DFSDM2 Clock In
1190 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection
1191 * @retval Returned value can be one of the following values:
1192 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
1193 * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
1194 * @retval None
1195 */
LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)1196 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
1197 {
1198 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
1199 }
1200
1201 /**
1202 * @brief Select the DFSDM2 Clock Out
1203 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
1204 * @param ClockSource This parameter can be one of the following values:
1205 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT
1206 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
1207 * @retval None
1208 */
LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)1209 __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
1210 {
1211 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
1212 }
1213 /**
1214 * @brief GET the DFSDM2 Clock Out
1215 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
1216 * @retval Returned value can be one of the following values:
1217 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT
1218 * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
1219 * @retval None
1220 */
LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)1221 __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
1222 {
1223 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
1224 }
1225
1226 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
1227 /**
1228 * @}
1229 */
1230
1231
1232 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1233 * @{
1234 */
1235
1236 /**
1237 * @brief Return the device identifier
1238 * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
1239 * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
1240 * @note For STM32F401xx devices, the device ID is 0x423
1241 * @note For STM32F401xx devices, the device ID is 0x433
1242 * @note For STM32F411xx devices, the device ID is 0x431
1243 * @note For STM32F410xx devices, the device ID is 0x458
1244 * @note For STM32F412xx devices, the device ID is 0x441
1245 * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
1246 * @note For STM32F446xx devices, the device ID is 0x421
1247 * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
1248 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1249 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1250 */
LL_DBGMCU_GetDeviceID(void)1251 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1252 {
1253 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1254 }
1255
1256 /**
1257 * @brief Return the device revision identifier
1258 * @note This field indicates the revision of the device.
1259 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
1260 For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
1261 For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
1262 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
1263 For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
1264 For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
1265 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1266 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1267 */
LL_DBGMCU_GetRevisionID(void)1268 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1269 {
1270 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1271 }
1272
1273 /**
1274 * @brief Enable the Debug Module during SLEEP mode
1275 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1276 * @retval None
1277 */
LL_DBGMCU_EnableDBGSleepMode(void)1278 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1279 {
1280 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1281 }
1282
1283 /**
1284 * @brief Disable the Debug Module during SLEEP mode
1285 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1286 * @retval None
1287 */
LL_DBGMCU_DisableDBGSleepMode(void)1288 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1289 {
1290 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1291 }
1292
1293 /**
1294 * @brief Enable the Debug Module during STOP mode
1295 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1296 * @retval None
1297 */
LL_DBGMCU_EnableDBGStopMode(void)1298 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1299 {
1300 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1301 }
1302
1303 /**
1304 * @brief Disable the Debug Module during STOP mode
1305 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1306 * @retval None
1307 */
LL_DBGMCU_DisableDBGStopMode(void)1308 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1309 {
1310 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1311 }
1312
1313 /**
1314 * @brief Enable the Debug Module during STANDBY mode
1315 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1316 * @retval None
1317 */
LL_DBGMCU_EnableDBGStandbyMode(void)1318 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1319 {
1320 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1321 }
1322
1323 /**
1324 * @brief Disable the Debug Module during STANDBY mode
1325 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1326 * @retval None
1327 */
LL_DBGMCU_DisableDBGStandbyMode(void)1328 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1329 {
1330 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1331 }
1332
1333 /**
1334 * @brief Set Trace pin assignment control
1335 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1336 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1337 * @param PinAssignment This parameter can be one of the following values:
1338 * @arg @ref LL_DBGMCU_TRACE_NONE
1339 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1340 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1341 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1342 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1343 * @retval None
1344 */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1345 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1346 {
1347 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1348 }
1349
1350 /**
1351 * @brief Get Trace pin assignment control
1352 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1353 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1354 * @retval Returned value can be one of the following values:
1355 * @arg @ref LL_DBGMCU_TRACE_NONE
1356 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1357 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1358 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1359 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1360 */
LL_DBGMCU_GetTracePinAssignment(void)1361 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1362 {
1363 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1364 }
1365
1366 /**
1367 * @brief Freeze APB1 peripherals (group1 peripherals)
1368 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1369 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1370 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1371 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1372 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1373 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1374 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1375 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1376 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1377 * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1378 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1379 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1380 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1381 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1382 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1383 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1384 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1385 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1386 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1387 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1388 * @param Periphs This parameter can be a combination of the following values:
1389 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1390 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1391 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1392 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1393 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1394 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1395 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1396 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1397 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1398 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
1399 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1400 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1401 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1402 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1403 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1404 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1405 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
1406 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
1407 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1408 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
1409 *
1410 * (*) value not defined in all devices.
1411 * @retval None
1412 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1413 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1414 {
1415 SET_BIT(DBGMCU->APB1FZ, Periphs);
1416 }
1417
1418 /**
1419 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1420 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1421 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1422 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1423 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1424 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1425 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1426 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1427 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1428 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1429 * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1430 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1431 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1432 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1433 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1434 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1435 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1436 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1437 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1438 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1439 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1440 * @param Periphs This parameter can be a combination of the following values:
1441 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
1442 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1443 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1444 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1445 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
1446 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1447 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1448 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1449 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1450 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
1451 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1452 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1453 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1454 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1455 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1456 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1457 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
1458 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
1459 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1460 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
1461 *
1462 * (*) value not defined in all devices.
1463 * @retval None
1464 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1465 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1466 {
1467 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1468 }
1469
1470 /**
1471 * @brief Freeze APB2 peripherals
1472 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1473 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1474 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1475 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1476 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1477 * @param Periphs This parameter can be a combination of the following values:
1478 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1479 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1480 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
1481 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
1482 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
1483 *
1484 * (*) value not defined in all devices.
1485 * @retval None
1486 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1487 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1488 {
1489 SET_BIT(DBGMCU->APB2FZ, Periphs);
1490 }
1491
1492 /**
1493 * @brief Unfreeze APB2 peripherals
1494 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1495 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1496 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1497 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1498 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1499 * @param Periphs This parameter can be a combination of the following values:
1500 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1501 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1502 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
1503 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
1504 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
1505 *
1506 * (*) value not defined in all devices.
1507 * @retval None
1508 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1509 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1510 {
1511 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1512 }
1513 /**
1514 * @}
1515 */
1516
1517 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1518 * @{
1519 */
1520
1521 /**
1522 * @brief Set FLASH Latency
1523 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1524 * @param Latency This parameter can be one of the following values:
1525 * @arg @ref LL_FLASH_LATENCY_0
1526 * @arg @ref LL_FLASH_LATENCY_1
1527 * @arg @ref LL_FLASH_LATENCY_2
1528 * @arg @ref LL_FLASH_LATENCY_3
1529 * @arg @ref LL_FLASH_LATENCY_4
1530 * @arg @ref LL_FLASH_LATENCY_5
1531 * @arg @ref LL_FLASH_LATENCY_6
1532 * @arg @ref LL_FLASH_LATENCY_7
1533 * @arg @ref LL_FLASH_LATENCY_8
1534 * @arg @ref LL_FLASH_LATENCY_9
1535 * @arg @ref LL_FLASH_LATENCY_10
1536 * @arg @ref LL_FLASH_LATENCY_11
1537 * @arg @ref LL_FLASH_LATENCY_12
1538 * @arg @ref LL_FLASH_LATENCY_13
1539 * @arg @ref LL_FLASH_LATENCY_14
1540 * @arg @ref LL_FLASH_LATENCY_15
1541 * @retval None
1542 */
LL_FLASH_SetLatency(uint32_t Latency)1543 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1544 {
1545 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1546 }
1547
1548 /**
1549 * @brief Get FLASH Latency
1550 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1551 * @retval Returned value can be one of the following values:
1552 * @arg @ref LL_FLASH_LATENCY_0
1553 * @arg @ref LL_FLASH_LATENCY_1
1554 * @arg @ref LL_FLASH_LATENCY_2
1555 * @arg @ref LL_FLASH_LATENCY_3
1556 * @arg @ref LL_FLASH_LATENCY_4
1557 * @arg @ref LL_FLASH_LATENCY_5
1558 * @arg @ref LL_FLASH_LATENCY_6
1559 * @arg @ref LL_FLASH_LATENCY_7
1560 * @arg @ref LL_FLASH_LATENCY_8
1561 * @arg @ref LL_FLASH_LATENCY_9
1562 * @arg @ref LL_FLASH_LATENCY_10
1563 * @arg @ref LL_FLASH_LATENCY_11
1564 * @arg @ref LL_FLASH_LATENCY_12
1565 * @arg @ref LL_FLASH_LATENCY_13
1566 * @arg @ref LL_FLASH_LATENCY_14
1567 * @arg @ref LL_FLASH_LATENCY_15
1568 */
LL_FLASH_GetLatency(void)1569 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1570 {
1571 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1572 }
1573
1574 /**
1575 * @brief Enable Prefetch
1576 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
1577 * @retval None
1578 */
LL_FLASH_EnablePrefetch(void)1579 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1580 {
1581 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1582 }
1583
1584 /**
1585 * @brief Disable Prefetch
1586 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
1587 * @retval None
1588 */
LL_FLASH_DisablePrefetch(void)1589 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1590 {
1591 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1592 }
1593
1594 /**
1595 * @brief Check if Prefetch buffer is enabled
1596 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
1597 * @retval State of bit (1 or 0).
1598 */
LL_FLASH_IsPrefetchEnabled(void)1599 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1600 {
1601 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1602 }
1603
1604 /**
1605 * @brief Enable Instruction cache
1606 * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
1607 * @retval None
1608 */
LL_FLASH_EnableInstCache(void)1609 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1610 {
1611 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1612 }
1613
1614 /**
1615 * @brief Disable Instruction cache
1616 * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
1617 * @retval None
1618 */
LL_FLASH_DisableInstCache(void)1619 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1620 {
1621 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1622 }
1623
1624 /**
1625 * @brief Enable Data cache
1626 * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
1627 * @retval None
1628 */
LL_FLASH_EnableDataCache(void)1629 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1630 {
1631 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1632 }
1633
1634 /**
1635 * @brief Disable Data cache
1636 * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
1637 * @retval None
1638 */
LL_FLASH_DisableDataCache(void)1639 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1640 {
1641 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1642 }
1643
1644 /**
1645 * @brief Enable Instruction cache reset
1646 * @note bit can be written only when the instruction cache is disabled
1647 * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
1648 * @retval None
1649 */
LL_FLASH_EnableInstCacheReset(void)1650 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1651 {
1652 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1653 }
1654
1655 /**
1656 * @brief Disable Instruction cache reset
1657 * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
1658 * @retval None
1659 */
LL_FLASH_DisableInstCacheReset(void)1660 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1661 {
1662 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1663 }
1664
1665 /**
1666 * @brief Enable Data cache reset
1667 * @note bit can be written only when the data cache is disabled
1668 * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
1669 * @retval None
1670 */
LL_FLASH_EnableDataCacheReset(void)1671 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1672 {
1673 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1674 }
1675
1676 /**
1677 * @brief Disable Data cache reset
1678 * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
1679 * @retval None
1680 */
LL_FLASH_DisableDataCacheReset(void)1681 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1682 {
1683 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1684 }
1685
1686
1687 /**
1688 * @}
1689 */
1690
1691 /**
1692 * @}
1693 */
1694
1695 /**
1696 * @}
1697 */
1698
1699 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1700
1701 /**
1702 * @}
1703 */
1704
1705 #ifdef __cplusplus
1706 }
1707 #endif
1708
1709 #endif /* __STM32F4xx_LL_SYSTEM_H */
1710
1711
