1 /**
2   ******************************************************************************
3   * @file    stm32f103xg.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32F1xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2017-2021 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 
28 /** @addtogroup CMSIS
29   * @{
30   */
31 
32 /** @addtogroup stm32f103xg
33   * @{
34   */
35 
36 #ifndef __STM32F103xG_H
37 #define __STM32F103xG_H
38 
39 #ifdef __cplusplus
40  extern "C" {
41 #endif
42 
43 /** @addtogroup Configuration_section_for_CMSIS
44   * @{
45   */
46 /**
47   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
48  */
49 #define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */
50  #define __MPU_PRESENT             1U       /*!< STM32 XL-density devices provide an MPU      */
51 #define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */
52 #define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32F10x Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 
67  /*!< Interrupt Number Definition */
68 typedef enum
69 {
70 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
71   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
72   HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
73   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
74   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
75   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
76   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
77   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
78   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
79   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
80 
81 /******  STM32 specific Interrupt Numbers *********************************************************/
82   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
83   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
84   TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
85   RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
86   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
87   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
88   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
89   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
90   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
91   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
92   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
93   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
94   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
95   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
96   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
97   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
98   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
99   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
100   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
101   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
102   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
103   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
104   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
105   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
106   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break Interrupt and TIM9 global Interrupt       */
107   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global Interrupt     */
108   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
109   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
110   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
111   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
112   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
113   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
114   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
115   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
116   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
117   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
118   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
119   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
120   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
121   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
122   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
123   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
124   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
125   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global Interrupt      */
126   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global Interrupt     */
127   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
128   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                       */
129   ADC3_IRQn                   = 47,     /*!< ADC3 global Interrupt                                */
130   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                */
131   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                */
132   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                */
133   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                */
134   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                               */
135   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                               */
136   TIM6_IRQn                   = 54,     /*!< TIM6 global Interrupt                                */
137   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
138   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                      */
139   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                      */
140   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                      */
141   DMA2_Channel4_5_IRQn        = 59,     /*!< DMA2 Channel 4 and Channel 5 global Interrupt        */
142 } IRQn_Type;
143 
144 /**
145   * @}
146   */
147 
148 #include "core_cm3.h"
149 #include "system_stm32f1xx.h"
150 #include <stdint.h>
151 
152 /** @addtogroup Peripheral_registers_structures
153   * @{
154   */
155 
156 /**
157   * @brief Analog to Digital Converter
158   */
159 
160 typedef struct
161 {
162   __IO uint32_t SR;
163   __IO uint32_t CR1;
164   __IO uint32_t CR2;
165   __IO uint32_t SMPR1;
166   __IO uint32_t SMPR2;
167   __IO uint32_t JOFR1;
168   __IO uint32_t JOFR2;
169   __IO uint32_t JOFR3;
170   __IO uint32_t JOFR4;
171   __IO uint32_t HTR;
172   __IO uint32_t LTR;
173   __IO uint32_t SQR1;
174   __IO uint32_t SQR2;
175   __IO uint32_t SQR3;
176   __IO uint32_t JSQR;
177   __IO uint32_t JDR1;
178   __IO uint32_t JDR2;
179   __IO uint32_t JDR3;
180   __IO uint32_t JDR4;
181   __IO uint32_t DR;
182 } ADC_TypeDef;
183 
184 typedef struct
185 {
186   __IO uint32_t SR;               /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */
187   __IO uint32_t CR1;              /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */
188   __IO uint32_t CR2;              /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */
189   uint32_t  RESERVED[16];
190   __IO uint32_t DR;               /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */
191 } ADC_Common_TypeDef;
192 
193 /**
194   * @brief Backup Registers
195   */
196 
197 typedef struct
198 {
199   uint32_t  RESERVED0;
200   __IO uint32_t DR1;
201   __IO uint32_t DR2;
202   __IO uint32_t DR3;
203   __IO uint32_t DR4;
204   __IO uint32_t DR5;
205   __IO uint32_t DR6;
206   __IO uint32_t DR7;
207   __IO uint32_t DR8;
208   __IO uint32_t DR9;
209   __IO uint32_t DR10;
210   __IO uint32_t RTCCR;
211   __IO uint32_t CR;
212   __IO uint32_t CSR;
213   uint32_t  RESERVED13[2];
214   __IO uint32_t DR11;
215   __IO uint32_t DR12;
216   __IO uint32_t DR13;
217   __IO uint32_t DR14;
218   __IO uint32_t DR15;
219   __IO uint32_t DR16;
220   __IO uint32_t DR17;
221   __IO uint32_t DR18;
222   __IO uint32_t DR19;
223   __IO uint32_t DR20;
224   __IO uint32_t DR21;
225   __IO uint32_t DR22;
226   __IO uint32_t DR23;
227   __IO uint32_t DR24;
228   __IO uint32_t DR25;
229   __IO uint32_t DR26;
230   __IO uint32_t DR27;
231   __IO uint32_t DR28;
232   __IO uint32_t DR29;
233   __IO uint32_t DR30;
234   __IO uint32_t DR31;
235   __IO uint32_t DR32;
236   __IO uint32_t DR33;
237   __IO uint32_t DR34;
238   __IO uint32_t DR35;
239   __IO uint32_t DR36;
240   __IO uint32_t DR37;
241   __IO uint32_t DR38;
242   __IO uint32_t DR39;
243   __IO uint32_t DR40;
244   __IO uint32_t DR41;
245   __IO uint32_t DR42;
246 } BKP_TypeDef;
247 
248 /**
249   * @brief Controller Area Network TxMailBox
250   */
251 
252 typedef struct
253 {
254   __IO uint32_t TIR;
255   __IO uint32_t TDTR;
256   __IO uint32_t TDLR;
257   __IO uint32_t TDHR;
258 } CAN_TxMailBox_TypeDef;
259 
260 /**
261   * @brief Controller Area Network FIFOMailBox
262   */
263 
264 typedef struct
265 {
266   __IO uint32_t RIR;
267   __IO uint32_t RDTR;
268   __IO uint32_t RDLR;
269   __IO uint32_t RDHR;
270 } CAN_FIFOMailBox_TypeDef;
271 
272 /**
273   * @brief Controller Area Network FilterRegister
274   */
275 
276 typedef struct
277 {
278   __IO uint32_t FR1;
279   __IO uint32_t FR2;
280 } CAN_FilterRegister_TypeDef;
281 
282 /**
283   * @brief Controller Area Network
284   */
285 
286 typedef struct
287 {
288   __IO uint32_t MCR;
289   __IO uint32_t MSR;
290   __IO uint32_t TSR;
291   __IO uint32_t RF0R;
292   __IO uint32_t RF1R;
293   __IO uint32_t IER;
294   __IO uint32_t ESR;
295   __IO uint32_t BTR;
296   uint32_t  RESERVED0[88];
297   CAN_TxMailBox_TypeDef sTxMailBox[3];
298   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
299   uint32_t  RESERVED1[12];
300   __IO uint32_t FMR;
301   __IO uint32_t FM1R;
302   uint32_t  RESERVED2;
303   __IO uint32_t FS1R;
304   uint32_t  RESERVED3;
305   __IO uint32_t FFA1R;
306   uint32_t  RESERVED4;
307   __IO uint32_t FA1R;
308   uint32_t  RESERVED5[8];
309   CAN_FilterRegister_TypeDef sFilterRegister[14];
310 } CAN_TypeDef;
311 
312 /**
313   * @brief CRC calculation unit
314   */
315 
316 typedef struct
317 {
318   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
319   __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
320   uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
321   uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */
322   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
323 } CRC_TypeDef;
324 
325 /**
326   * @brief Digital to Analog Converter
327   */
328 
329 typedef struct
330 {
331   __IO uint32_t CR;
332   __IO uint32_t SWTRIGR;
333   __IO uint32_t DHR12R1;
334   __IO uint32_t DHR12L1;
335   __IO uint32_t DHR8R1;
336   __IO uint32_t DHR12R2;
337   __IO uint32_t DHR12L2;
338   __IO uint32_t DHR8R2;
339   __IO uint32_t DHR12RD;
340   __IO uint32_t DHR12LD;
341   __IO uint32_t DHR8RD;
342   __IO uint32_t DOR1;
343   __IO uint32_t DOR2;
344 } DAC_TypeDef;
345 
346 /**
347   * @brief Debug MCU
348   */
349 
350 typedef struct
351 {
352   __IO uint32_t IDCODE;
353   __IO uint32_t CR;
354 }DBGMCU_TypeDef;
355 
356 /**
357   * @brief DMA Controller
358   */
359 
360 typedef struct
361 {
362   __IO uint32_t CCR;
363   __IO uint32_t CNDTR;
364   __IO uint32_t CPAR;
365   __IO uint32_t CMAR;
366 } DMA_Channel_TypeDef;
367 
368 typedef struct
369 {
370   __IO uint32_t ISR;
371   __IO uint32_t IFCR;
372 } DMA_TypeDef;
373 
374 
375 
376 /**
377   * @brief External Interrupt/Event Controller
378   */
379 
380 typedef struct
381 {
382   __IO uint32_t IMR;
383   __IO uint32_t EMR;
384   __IO uint32_t RTSR;
385   __IO uint32_t FTSR;
386   __IO uint32_t SWIER;
387   __IO uint32_t PR;
388 } EXTI_TypeDef;
389 
390 /**
391   * @brief FLASH Registers
392   */
393 
394 typedef struct
395 {
396   __IO uint32_t ACR;
397   __IO uint32_t KEYR;
398   __IO uint32_t OPTKEYR;
399   __IO uint32_t SR;
400   __IO uint32_t CR;
401   __IO uint32_t AR;
402   __IO uint32_t RESERVED;
403   __IO uint32_t OBR;
404   __IO uint32_t WRPR;
405   uint32_t RESERVED1[8];
406   __IO uint32_t KEYR2;
407   uint32_t RESERVED2;
408   __IO uint32_t SR2;
409   __IO uint32_t CR2;
410   __IO uint32_t AR2;
411 } FLASH_TypeDef;
412 
413 /**
414   * @brief Option Bytes Registers
415   */
416 
417 typedef struct
418 {
419   __IO uint16_t RDP;
420   __IO uint16_t USER;
421   __IO uint16_t Data0;
422   __IO uint16_t Data1;
423   __IO uint16_t WRP0;
424   __IO uint16_t WRP1;
425   __IO uint16_t WRP2;
426   __IO uint16_t WRP3;
427 } OB_TypeDef;
428 
429 /**
430   * @brief Flexible Static Memory Controller
431   */
432 
433 typedef struct
434 {
435   __IO uint32_t BTCR[8];
436 } FSMC_Bank1_TypeDef;
437 
438 /**
439   * @brief Flexible Static Memory Controller Bank1E
440   */
441 
442 typedef struct
443 {
444   __IO uint32_t BWTR[7];
445 } FSMC_Bank1E_TypeDef;
446 
447 /**
448   * @brief Flexible Static Memory Controller Bank2
449   */
450 
451 typedef struct
452 {
453   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
454   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
455   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
456   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
457   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
458   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
459   uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
460   uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
461   __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
462   __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
463   __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
464   __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
465   uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
466   __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
467 } FSMC_Bank2_3_TypeDef;
468 
469 /**
470   * @brief Flexible Static Memory Controller Bank4
471   */
472 
473 typedef struct
474 {
475   __IO uint32_t PCR4;
476   __IO uint32_t SR4;
477   __IO uint32_t PMEM4;
478   __IO uint32_t PATT4;
479   __IO uint32_t PIO4;
480 } FSMC_Bank4_TypeDef;
481 
482 /**
483   * @brief General Purpose I/O
484   */
485 
486 typedef struct
487 {
488   __IO uint32_t CRL;
489   __IO uint32_t CRH;
490   __IO uint32_t IDR;
491   __IO uint32_t ODR;
492   __IO uint32_t BSRR;
493   __IO uint32_t BRR;
494   __IO uint32_t LCKR;
495 } GPIO_TypeDef;
496 
497 /**
498   * @brief Alternate Function I/O
499   */
500 
501 typedef struct
502 {
503   __IO uint32_t EVCR;
504   __IO uint32_t MAPR;
505   __IO uint32_t EXTICR[4];
506   uint32_t RESERVED0;
507   __IO uint32_t MAPR2;
508 } AFIO_TypeDef;
509 /**
510   * @brief Inter Integrated Circuit Interface
511   */
512 
513 typedef struct
514 {
515   __IO uint32_t CR1;
516   __IO uint32_t CR2;
517   __IO uint32_t OAR1;
518   __IO uint32_t OAR2;
519   __IO uint32_t DR;
520   __IO uint32_t SR1;
521   __IO uint32_t SR2;
522   __IO uint32_t CCR;
523   __IO uint32_t TRISE;
524 } I2C_TypeDef;
525 
526 /**
527   * @brief Independent WATCHDOG
528   */
529 
530 typedef struct
531 {
532   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
533   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
534   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
535   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
536 } IWDG_TypeDef;
537 
538 /**
539   * @brief Power Control
540   */
541 
542 typedef struct
543 {
544   __IO uint32_t CR;
545   __IO uint32_t CSR;
546 } PWR_TypeDef;
547 
548 /**
549   * @brief Reset and Clock Control
550   */
551 
552 typedef struct
553 {
554   __IO uint32_t CR;
555   __IO uint32_t CFGR;
556   __IO uint32_t CIR;
557   __IO uint32_t APB2RSTR;
558   __IO uint32_t APB1RSTR;
559   __IO uint32_t AHBENR;
560   __IO uint32_t APB2ENR;
561   __IO uint32_t APB1ENR;
562   __IO uint32_t BDCR;
563   __IO uint32_t CSR;
564 
565 
566 } RCC_TypeDef;
567 
568 /**
569   * @brief Real-Time Clock
570   */
571 
572 typedef struct
573 {
574   __IO uint32_t CRH;
575   __IO uint32_t CRL;
576   __IO uint32_t PRLH;
577   __IO uint32_t PRLL;
578   __IO uint32_t DIVH;
579   __IO uint32_t DIVL;
580   __IO uint32_t CNTH;
581   __IO uint32_t CNTL;
582   __IO uint32_t ALRH;
583   __IO uint32_t ALRL;
584 } RTC_TypeDef;
585 
586 /**
587   * @brief SD host Interface
588   */
589 
590 typedef struct
591 {
592   __IO uint32_t POWER;
593   __IO uint32_t CLKCR;
594   __IO uint32_t ARG;
595   __IO uint32_t CMD;
596   __I uint32_t RESPCMD;
597   __I uint32_t RESP1;
598   __I uint32_t RESP2;
599   __I uint32_t RESP3;
600   __I uint32_t RESP4;
601   __IO uint32_t DTIMER;
602   __IO uint32_t DLEN;
603   __IO uint32_t DCTRL;
604   __I uint32_t DCOUNT;
605   __I uint32_t STA;
606   __IO uint32_t ICR;
607   __IO uint32_t MASK;
608   uint32_t  RESERVED0[2];
609   __I uint32_t FIFOCNT;
610   uint32_t  RESERVED1[13];
611   __IO uint32_t FIFO;
612 } SDIO_TypeDef;
613 
614 /**
615   * @brief Serial Peripheral Interface
616   */
617 
618 typedef struct
619 {
620   __IO uint32_t CR1;
621   __IO uint32_t CR2;
622   __IO uint32_t SR;
623   __IO uint32_t DR;
624   __IO uint32_t CRCPR;
625   __IO uint32_t RXCRCR;
626   __IO uint32_t TXCRCR;
627   __IO uint32_t I2SCFGR;
628   __IO uint32_t I2SPR;
629 } SPI_TypeDef;
630 
631 /**
632   * @brief TIM Timers
633   */
634 typedef struct
635 {
636   __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
637   __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
638   __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
639   __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
640   __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
641   __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
642   __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
643   __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
644   __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
645   __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
646   __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
647   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
648   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
649   __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
650   __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
651   __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
652   __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
653   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
654   __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
655   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
656   __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
657 }TIM_TypeDef;
658 
659 
660 /**
661   * @brief Universal Synchronous Asynchronous Receiver Transmitter
662   */
663 
664 typedef struct
665 {
666   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
667   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
668   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
669   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
670   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
671   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
672   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
673 } USART_TypeDef;
674 
675 /**
676   * @brief Universal Serial Bus Full Speed Device
677   */
678 
679 typedef struct
680 {
681   __IO uint16_t EP0R;                 /*!< USB Endpoint 0 register,                   Address offset: 0x00 */
682   __IO uint16_t RESERVED0;            /*!< Reserved */
683   __IO uint16_t EP1R;                 /*!< USB Endpoint 1 register,                   Address offset: 0x04 */
684   __IO uint16_t RESERVED1;            /*!< Reserved */
685   __IO uint16_t EP2R;                 /*!< USB Endpoint 2 register,                   Address offset: 0x08 */
686   __IO uint16_t RESERVED2;            /*!< Reserved */
687   __IO uint16_t EP3R;                 /*!< USB Endpoint 3 register,                   Address offset: 0x0C */
688   __IO uint16_t RESERVED3;            /*!< Reserved */
689   __IO uint16_t EP4R;                 /*!< USB Endpoint 4 register,                   Address offset: 0x10 */
690   __IO uint16_t RESERVED4;            /*!< Reserved */
691   __IO uint16_t EP5R;                 /*!< USB Endpoint 5 register,                   Address offset: 0x14 */
692   __IO uint16_t RESERVED5;            /*!< Reserved */
693   __IO uint16_t EP6R;                 /*!< USB Endpoint 6 register,                   Address offset: 0x18 */
694   __IO uint16_t RESERVED6;            /*!< Reserved */
695   __IO uint16_t EP7R;                 /*!< USB Endpoint 7 register,                   Address offset: 0x1C */
696   __IO uint16_t RESERVED7[17];        /*!< Reserved */
697   __IO uint16_t CNTR;                 /*!< Control register,                          Address offset: 0x40 */
698   __IO uint16_t RESERVED8;            /*!< Reserved */
699   __IO uint16_t ISTR;                 /*!< Interrupt status register,                 Address offset: 0x44 */
700   __IO uint16_t RESERVED9;            /*!< Reserved */
701   __IO uint16_t FNR;                  /*!< Frame number register,                     Address offset: 0x48 */
702   __IO uint16_t RESERVEDA;            /*!< Reserved */
703   __IO uint16_t DADDR;                /*!< Device address register,                   Address offset: 0x4C */
704   __IO uint16_t RESERVEDB;            /*!< Reserved */
705   __IO uint16_t BTABLE;               /*!< Buffer Table address register,             Address offset: 0x50 */
706   __IO uint16_t RESERVEDC;            /*!< Reserved */
707 } USB_TypeDef;
708 
709 
710 /**
711   * @brief Window WATCHDOG
712   */
713 
714 typedef struct
715 {
716   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
717   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
718   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
719 } WWDG_TypeDef;
720 
721 /**
722   * @}
723   */
724 
725 /** @addtogroup Peripheral_memory_map
726   * @{
727   */
728 
729 
730 #define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */
731 #define FLASH_BANK1_END       0x0807FFFFUL /*!< FLASH END address of bank1 */
732 #define FLASH_BANK2_END       0x080FFFFFUL /*!< FLASH END address of bank2 */
733 #define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */
734 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */
735 
736 #define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */
737 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */
738 
739 #define FSMC_BASE             0x60000000UL /*!< FSMC base address */
740 #define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address */
741 
742 /*!< Peripheral memory map */
743 #define APB1PERIPH_BASE       PERIPH_BASE
744 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
745 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
746 
747 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
748 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
749 #define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)
750 #define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00UL)
751 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000UL)
752 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400UL)
753 #define TIM12_BASE            (APB1PERIPH_BASE + 0x00001800UL)
754 #define TIM13_BASE            (APB1PERIPH_BASE + 0x00001C00UL)
755 #define TIM14_BASE            (APB1PERIPH_BASE + 0x00002000UL)
756 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
757 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
758 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
759 #define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)
760 #define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00UL)
761 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
762 #define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)
763 #define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00UL)
764 #define UART5_BASE            (APB1PERIPH_BASE + 0x00005000UL)
765 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
766 #define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)
767 #define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400UL)
768 #define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00UL)
769 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
770 #define DAC_BASE              (APB1PERIPH_BASE + 0x00007400UL)
771 #define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000UL)
772 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
773 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800UL)
774 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
775 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000UL)
776 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400UL)
777 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800UL)
778 #define GPIOF_BASE            (APB2PERIPH_BASE + 0x00001C00UL)
779 #define GPIOG_BASE            (APB2PERIPH_BASE + 0x00002000UL)
780 #define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
781 #define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800UL)
782 #define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
783 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
784 #define TIM8_BASE             (APB2PERIPH_BASE + 0x00003400UL)
785 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
786 #define ADC3_BASE             (APB2PERIPH_BASE + 0x00003C00UL)
787 #define TIM9_BASE             (APB2PERIPH_BASE + 0x00004C00UL)
788 #define TIM10_BASE            (APB2PERIPH_BASE + 0x00005000UL)
789 #define TIM11_BASE            (APB2PERIPH_BASE + 0x00005400UL)
790 
791 #define SDIO_BASE             (PERIPH_BASE + 0x00018000UL)
792 
793 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
794 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008UL)
795 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CUL)
796 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030UL)
797 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044UL)
798 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058UL)
799 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CUL)
800 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080UL)
801 #define DMA2_BASE             (AHBPERIPH_BASE + 0x00000400UL)
802 #define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x00000408UL)
803 #define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x0000041CUL)
804 #define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x00000430UL)
805 #define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x00000444UL)
806 #define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x00000458UL)
807 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
808 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
809 
810 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
811 #define FLASHSIZE_BASE        0x1FFFF7E0UL    /*!< FLASH Size register base address */
812 #define UID_BASE              0x1FFFF7E8UL    /*!< Unique device ID register base address */
813 #define OB_BASE               0x1FFFF800UL    /*!< Flash Option Bytes base address */
814 
815 
816 #define FSMC_BANK1            (FSMC_BASE)               /*!< FSMC Bank1 base address */
817 #define FSMC_BANK1_1          (FSMC_BANK1)              /*!< FSMC Bank1_1 base address */
818 #define FSMC_BANK1_2          (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */
819 #define FSMC_BANK1_3          (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */
820 #define FSMC_BANK1_4          (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */
821 
822 #define FSMC_BANK2            (FSMC_BASE + 0x10000000UL)  /*!< FSMC Bank2 base address */
823 #define FSMC_BANK3            (FSMC_BASE + 0x20000000UL)  /*!< FSMC Bank3 base address */
824 #define FSMC_BANK4            (FSMC_BASE + 0x30000000UL)  /*!< FSMC Bank4 base address */
825 
826 #define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x00000000UL)    /*!< FSMC Bank1 registers base address */
827 #define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x00000104UL)    /*!< FSMC Bank1E registers base address */
828 #define FSMC_BANK2_3_R_BASE   (FSMC_R_BASE + 0x00000060UL)    /*!< FSMC Bank2/Bank3 registers base address */
829 #define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x000000A0UL)    /*!< FSMC Bank4 registers base address */
830 
831 #define DBGMCU_BASE          0xE0042000UL /*!< Debug MCU registers base address */
832 
833 /* USB device FS */
834 #define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
835 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
836 
837 
838 /**
839   * @}
840   */
841 
842 /** @addtogroup Peripheral_declaration
843   * @{
844   */
845 
846 #define TIM2                ((TIM_TypeDef *)TIM2_BASE)
847 #define TIM3                ((TIM_TypeDef *)TIM3_BASE)
848 #define TIM4                ((TIM_TypeDef *)TIM4_BASE)
849 #define TIM5                ((TIM_TypeDef *)TIM5_BASE)
850 #define TIM6                ((TIM_TypeDef *)TIM6_BASE)
851 #define TIM7                ((TIM_TypeDef *)TIM7_BASE)
852 #define TIM12               ((TIM_TypeDef *)TIM12_BASE)
853 #define TIM13               ((TIM_TypeDef *)TIM13_BASE)
854 #define TIM14               ((TIM_TypeDef *)TIM14_BASE)
855 #define RTC                 ((RTC_TypeDef *)RTC_BASE)
856 #define WWDG                ((WWDG_TypeDef *)WWDG_BASE)
857 #define IWDG                ((IWDG_TypeDef *)IWDG_BASE)
858 #define SPI2                ((SPI_TypeDef *)SPI2_BASE)
859 #define SPI3                ((SPI_TypeDef *)SPI3_BASE)
860 #define USART2              ((USART_TypeDef *)USART2_BASE)
861 #define USART3              ((USART_TypeDef *)USART3_BASE)
862 #define UART4               ((USART_TypeDef *)UART4_BASE)
863 #define UART5               ((USART_TypeDef *)UART5_BASE)
864 #define I2C1                ((I2C_TypeDef *)I2C1_BASE)
865 #define I2C2                ((I2C_TypeDef *)I2C2_BASE)
866 #define USB                 ((USB_TypeDef *)USB_BASE)
867 #define CAN1                ((CAN_TypeDef *)CAN1_BASE)
868 #define BKP                 ((BKP_TypeDef *)BKP_BASE)
869 #define PWR                 ((PWR_TypeDef *)PWR_BASE)
870 #define DAC1                ((DAC_TypeDef *)DAC_BASE)
871 #define DAC                 ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
872 #define AFIO                ((AFIO_TypeDef *)AFIO_BASE)
873 #define EXTI                ((EXTI_TypeDef *)EXTI_BASE)
874 #define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)
875 #define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)
876 #define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)
877 #define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)
878 #define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)
879 #define GPIOF               ((GPIO_TypeDef *)GPIOF_BASE)
880 #define GPIOG               ((GPIO_TypeDef *)GPIOG_BASE)
881 #define ADC1                ((ADC_TypeDef *)ADC1_BASE)
882 #define ADC2                ((ADC_TypeDef *)ADC2_BASE)
883 #define ADC3                ((ADC_TypeDef *)ADC3_BASE)
884 #define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)
885 #define TIM1                ((TIM_TypeDef *)TIM1_BASE)
886 #define SPI1                ((SPI_TypeDef *)SPI1_BASE)
887 #define TIM8                ((TIM_TypeDef *)TIM8_BASE)
888 #define USART1              ((USART_TypeDef *)USART1_BASE)
889 #define TIM9                ((TIM_TypeDef *)TIM9_BASE)
890 #define TIM10               ((TIM_TypeDef *)TIM10_BASE)
891 #define TIM11               ((TIM_TypeDef *)TIM11_BASE)
892 #define SDIO                ((SDIO_TypeDef *)SDIO_BASE)
893 #define DMA1                ((DMA_TypeDef *)DMA1_BASE)
894 #define DMA2                ((DMA_TypeDef *)DMA2_BASE)
895 #define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
896 #define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
897 #define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
898 #define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
899 #define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
900 #define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
901 #define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
902 #define DMA2_Channel1       ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
903 #define DMA2_Channel2       ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
904 #define DMA2_Channel3       ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
905 #define DMA2_Channel4       ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
906 #define DMA2_Channel5       ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
907 #define RCC                 ((RCC_TypeDef *)RCC_BASE)
908 #define CRC                 ((CRC_TypeDef *)CRC_BASE)
909 #define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)
910 #define OB                  ((OB_TypeDef *)OB_BASE)
911 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
912 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
913 #define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
914 #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
915 #define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)
916 
917 
918 /**
919   * @}
920   */
921 
922 /** @addtogroup Exported_constants
923   * @{
924   */
925 
926   /** @addtogroup Hardware_Constant_Definition
927     * @{
928     */
929 #define LSI_STARTUP_TIME                85U /*!< LSI Maximum startup time in us */
930   /**
931     * @}
932     */
933 
934   /** @addtogroup Peripheral_Registers_Bits_Definition
935   * @{
936   */
937 
938 /******************************************************************************/
939 /*                         Peripheral Registers_Bits_Definition               */
940 /******************************************************************************/
941 
942 /******************************************************************************/
943 /*                                                                            */
944 /*                       CRC calculation unit (CRC)                           */
945 /*                                                                            */
946 /******************************************************************************/
947 
948 /*******************  Bit definition for CRC_DR register  *********************/
949 #define CRC_DR_DR_Pos                       (0U)
950 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
951 #define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
952 
953 /*******************  Bit definition for CRC_IDR register  ********************/
954 #define CRC_IDR_IDR_Pos                     (0U)
955 #define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
956 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
957 
958 /********************  Bit definition for CRC_CR register  ********************/
959 #define CRC_CR_RESET_Pos                    (0U)
960 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
961 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
962 
963 /******************************************************************************/
964 /*                                                                            */
965 /*                             Power Control                                  */
966 /*                                                                            */
967 /******************************************************************************/
968 
969 /********************  Bit definition for PWR_CR register  ********************/
970 #define PWR_CR_LPDS_Pos                     (0U)
971 #define PWR_CR_LPDS_Msk                     (0x1UL << PWR_CR_LPDS_Pos)          /*!< 0x00000001 */
972 #define PWR_CR_LPDS                         PWR_CR_LPDS_Msk                    /*!< Low-Power Deepsleep */
973 #define PWR_CR_PDDS_Pos                     (1U)
974 #define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
975 #define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
976 #define PWR_CR_CWUF_Pos                     (2U)
977 #define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
978 #define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
979 #define PWR_CR_CSBF_Pos                     (3U)
980 #define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
981 #define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
982 #define PWR_CR_PVDE_Pos                     (4U)
983 #define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
984 #define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
985 
986 #define PWR_CR_PLS_Pos                      (5U)
987 #define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
988 #define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
989 #define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
990 #define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
991 #define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
992 
993 /*!< PVD level configuration */
994 #define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */
995 #define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */
996 #define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */
997 #define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */
998 #define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */
999 #define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */
1000 #define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */
1001 #define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */
1002 
1003 /* Legacy defines */
1004 #define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0
1005 #define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1
1006 #define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2
1007 #define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3
1008 #define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4
1009 #define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5
1010 #define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6
1011 #define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7
1012 
1013 #define PWR_CR_DBP_Pos                      (8U)
1014 #define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
1015 #define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
1016 
1017 
1018 /*******************  Bit definition for PWR_CSR register  ********************/
1019 #define PWR_CSR_WUF_Pos                     (0U)
1020 #define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
1021 #define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
1022 #define PWR_CSR_SBF_Pos                     (1U)
1023 #define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
1024 #define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
1025 #define PWR_CSR_PVDO_Pos                    (2U)
1026 #define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
1027 #define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
1028 #define PWR_CSR_EWUP_Pos                    (8U)
1029 #define PWR_CSR_EWUP_Msk                    (0x1UL << PWR_CSR_EWUP_Pos)         /*!< 0x00000100 */
1030 #define PWR_CSR_EWUP                        PWR_CSR_EWUP_Msk                   /*!< Enable WKUP pin */
1031 
1032 /******************************************************************************/
1033 /*                                                                            */
1034 /*                            Backup registers                                */
1035 /*                                                                            */
1036 /******************************************************************************/
1037 
1038 /*******************  Bit definition for BKP_DR1 register  ********************/
1039 #define BKP_DR1_D_Pos                       (0U)
1040 #define BKP_DR1_D_Msk                       (0xFFFFUL << BKP_DR1_D_Pos)         /*!< 0x0000FFFF */
1041 #define BKP_DR1_D                           BKP_DR1_D_Msk                      /*!< Backup data */
1042 
1043 /*******************  Bit definition for BKP_DR2 register  ********************/
1044 #define BKP_DR2_D_Pos                       (0U)
1045 #define BKP_DR2_D_Msk                       (0xFFFFUL << BKP_DR2_D_Pos)         /*!< 0x0000FFFF */
1046 #define BKP_DR2_D                           BKP_DR2_D_Msk                      /*!< Backup data */
1047 
1048 /*******************  Bit definition for BKP_DR3 register  ********************/
1049 #define BKP_DR3_D_Pos                       (0U)
1050 #define BKP_DR3_D_Msk                       (0xFFFFUL << BKP_DR3_D_Pos)         /*!< 0x0000FFFF */
1051 #define BKP_DR3_D                           BKP_DR3_D_Msk                      /*!< Backup data */
1052 
1053 /*******************  Bit definition for BKP_DR4 register  ********************/
1054 #define BKP_DR4_D_Pos                       (0U)
1055 #define BKP_DR4_D_Msk                       (0xFFFFUL << BKP_DR4_D_Pos)         /*!< 0x0000FFFF */
1056 #define BKP_DR4_D                           BKP_DR4_D_Msk                      /*!< Backup data */
1057 
1058 /*******************  Bit definition for BKP_DR5 register  ********************/
1059 #define BKP_DR5_D_Pos                       (0U)
1060 #define BKP_DR5_D_Msk                       (0xFFFFUL << BKP_DR5_D_Pos)         /*!< 0x0000FFFF */
1061 #define BKP_DR5_D                           BKP_DR5_D_Msk                      /*!< Backup data */
1062 
1063 /*******************  Bit definition for BKP_DR6 register  ********************/
1064 #define BKP_DR6_D_Pos                       (0U)
1065 #define BKP_DR6_D_Msk                       (0xFFFFUL << BKP_DR6_D_Pos)         /*!< 0x0000FFFF */
1066 #define BKP_DR6_D                           BKP_DR6_D_Msk                      /*!< Backup data */
1067 
1068 /*******************  Bit definition for BKP_DR7 register  ********************/
1069 #define BKP_DR7_D_Pos                       (0U)
1070 #define BKP_DR7_D_Msk                       (0xFFFFUL << BKP_DR7_D_Pos)         /*!< 0x0000FFFF */
1071 #define BKP_DR7_D                           BKP_DR7_D_Msk                      /*!< Backup data */
1072 
1073 /*******************  Bit definition for BKP_DR8 register  ********************/
1074 #define BKP_DR8_D_Pos                       (0U)
1075 #define BKP_DR8_D_Msk                       (0xFFFFUL << BKP_DR8_D_Pos)         /*!< 0x0000FFFF */
1076 #define BKP_DR8_D                           BKP_DR8_D_Msk                      /*!< Backup data */
1077 
1078 /*******************  Bit definition for BKP_DR9 register  ********************/
1079 #define BKP_DR9_D_Pos                       (0U)
1080 #define BKP_DR9_D_Msk                       (0xFFFFUL << BKP_DR9_D_Pos)         /*!< 0x0000FFFF */
1081 #define BKP_DR9_D                           BKP_DR9_D_Msk                      /*!< Backup data */
1082 
1083 /*******************  Bit definition for BKP_DR10 register  *******************/
1084 #define BKP_DR10_D_Pos                      (0U)
1085 #define BKP_DR10_D_Msk                      (0xFFFFUL << BKP_DR10_D_Pos)        /*!< 0x0000FFFF */
1086 #define BKP_DR10_D                          BKP_DR10_D_Msk                     /*!< Backup data */
1087 
1088 /*******************  Bit definition for BKP_DR11 register  *******************/
1089 #define BKP_DR11_D_Pos                      (0U)
1090 #define BKP_DR11_D_Msk                      (0xFFFFUL << BKP_DR11_D_Pos)        /*!< 0x0000FFFF */
1091 #define BKP_DR11_D                          BKP_DR11_D_Msk                     /*!< Backup data */
1092 
1093 /*******************  Bit definition for BKP_DR12 register  *******************/
1094 #define BKP_DR12_D_Pos                      (0U)
1095 #define BKP_DR12_D_Msk                      (0xFFFFUL << BKP_DR12_D_Pos)        /*!< 0x0000FFFF */
1096 #define BKP_DR12_D                          BKP_DR12_D_Msk                     /*!< Backup data */
1097 
1098 /*******************  Bit definition for BKP_DR13 register  *******************/
1099 #define BKP_DR13_D_Pos                      (0U)
1100 #define BKP_DR13_D_Msk                      (0xFFFFUL << BKP_DR13_D_Pos)        /*!< 0x0000FFFF */
1101 #define BKP_DR13_D                          BKP_DR13_D_Msk                     /*!< Backup data */
1102 
1103 /*******************  Bit definition for BKP_DR14 register  *******************/
1104 #define BKP_DR14_D_Pos                      (0U)
1105 #define BKP_DR14_D_Msk                      (0xFFFFUL << BKP_DR14_D_Pos)        /*!< 0x0000FFFF */
1106 #define BKP_DR14_D                          BKP_DR14_D_Msk                     /*!< Backup data */
1107 
1108 /*******************  Bit definition for BKP_DR15 register  *******************/
1109 #define BKP_DR15_D_Pos                      (0U)
1110 #define BKP_DR15_D_Msk                      (0xFFFFUL << BKP_DR15_D_Pos)        /*!< 0x0000FFFF */
1111 #define BKP_DR15_D                          BKP_DR15_D_Msk                     /*!< Backup data */
1112 
1113 /*******************  Bit definition for BKP_DR16 register  *******************/
1114 #define BKP_DR16_D_Pos                      (0U)
1115 #define BKP_DR16_D_Msk                      (0xFFFFUL << BKP_DR16_D_Pos)        /*!< 0x0000FFFF */
1116 #define BKP_DR16_D                          BKP_DR16_D_Msk                     /*!< Backup data */
1117 
1118 /*******************  Bit definition for BKP_DR17 register  *******************/
1119 #define BKP_DR17_D_Pos                      (0U)
1120 #define BKP_DR17_D_Msk                      (0xFFFFUL << BKP_DR17_D_Pos)        /*!< 0x0000FFFF */
1121 #define BKP_DR17_D                          BKP_DR17_D_Msk                     /*!< Backup data */
1122 
1123 /******************  Bit definition for BKP_DR18 register  ********************/
1124 #define BKP_DR18_D_Pos                      (0U)
1125 #define BKP_DR18_D_Msk                      (0xFFFFUL << BKP_DR18_D_Pos)        /*!< 0x0000FFFF */
1126 #define BKP_DR18_D                          BKP_DR18_D_Msk                     /*!< Backup data */
1127 
1128 /*******************  Bit definition for BKP_DR19 register  *******************/
1129 #define BKP_DR19_D_Pos                      (0U)
1130 #define BKP_DR19_D_Msk                      (0xFFFFUL << BKP_DR19_D_Pos)        /*!< 0x0000FFFF */
1131 #define BKP_DR19_D                          BKP_DR19_D_Msk                     /*!< Backup data */
1132 
1133 /*******************  Bit definition for BKP_DR20 register  *******************/
1134 #define BKP_DR20_D_Pos                      (0U)
1135 #define BKP_DR20_D_Msk                      (0xFFFFUL << BKP_DR20_D_Pos)        /*!< 0x0000FFFF */
1136 #define BKP_DR20_D                          BKP_DR20_D_Msk                     /*!< Backup data */
1137 
1138 /*******************  Bit definition for BKP_DR21 register  *******************/
1139 #define BKP_DR21_D_Pos                      (0U)
1140 #define BKP_DR21_D_Msk                      (0xFFFFUL << BKP_DR21_D_Pos)        /*!< 0x0000FFFF */
1141 #define BKP_DR21_D                          BKP_DR21_D_Msk                     /*!< Backup data */
1142 
1143 /*******************  Bit definition for BKP_DR22 register  *******************/
1144 #define BKP_DR22_D_Pos                      (0U)
1145 #define BKP_DR22_D_Msk                      (0xFFFFUL << BKP_DR22_D_Pos)        /*!< 0x0000FFFF */
1146 #define BKP_DR22_D                          BKP_DR22_D_Msk                     /*!< Backup data */
1147 
1148 /*******************  Bit definition for BKP_DR23 register  *******************/
1149 #define BKP_DR23_D_Pos                      (0U)
1150 #define BKP_DR23_D_Msk                      (0xFFFFUL << BKP_DR23_D_Pos)        /*!< 0x0000FFFF */
1151 #define BKP_DR23_D                          BKP_DR23_D_Msk                     /*!< Backup data */
1152 
1153 /*******************  Bit definition for BKP_DR24 register  *******************/
1154 #define BKP_DR24_D_Pos                      (0U)
1155 #define BKP_DR24_D_Msk                      (0xFFFFUL << BKP_DR24_D_Pos)        /*!< 0x0000FFFF */
1156 #define BKP_DR24_D                          BKP_DR24_D_Msk                     /*!< Backup data */
1157 
1158 /*******************  Bit definition for BKP_DR25 register  *******************/
1159 #define BKP_DR25_D_Pos                      (0U)
1160 #define BKP_DR25_D_Msk                      (0xFFFFUL << BKP_DR25_D_Pos)        /*!< 0x0000FFFF */
1161 #define BKP_DR25_D                          BKP_DR25_D_Msk                     /*!< Backup data */
1162 
1163 /*******************  Bit definition for BKP_DR26 register  *******************/
1164 #define BKP_DR26_D_Pos                      (0U)
1165 #define BKP_DR26_D_Msk                      (0xFFFFUL << BKP_DR26_D_Pos)        /*!< 0x0000FFFF */
1166 #define BKP_DR26_D                          BKP_DR26_D_Msk                     /*!< Backup data */
1167 
1168 /*******************  Bit definition for BKP_DR27 register  *******************/
1169 #define BKP_DR27_D_Pos                      (0U)
1170 #define BKP_DR27_D_Msk                      (0xFFFFUL << BKP_DR27_D_Pos)        /*!< 0x0000FFFF */
1171 #define BKP_DR27_D                          BKP_DR27_D_Msk                     /*!< Backup data */
1172 
1173 /*******************  Bit definition for BKP_DR28 register  *******************/
1174 #define BKP_DR28_D_Pos                      (0U)
1175 #define BKP_DR28_D_Msk                      (0xFFFFUL << BKP_DR28_D_Pos)        /*!< 0x0000FFFF */
1176 #define BKP_DR28_D                          BKP_DR28_D_Msk                     /*!< Backup data */
1177 
1178 /*******************  Bit definition for BKP_DR29 register  *******************/
1179 #define BKP_DR29_D_Pos                      (0U)
1180 #define BKP_DR29_D_Msk                      (0xFFFFUL << BKP_DR29_D_Pos)        /*!< 0x0000FFFF */
1181 #define BKP_DR29_D                          BKP_DR29_D_Msk                     /*!< Backup data */
1182 
1183 /*******************  Bit definition for BKP_DR30 register  *******************/
1184 #define BKP_DR30_D_Pos                      (0U)
1185 #define BKP_DR30_D_Msk                      (0xFFFFUL << BKP_DR30_D_Pos)        /*!< 0x0000FFFF */
1186 #define BKP_DR30_D                          BKP_DR30_D_Msk                     /*!< Backup data */
1187 
1188 /*******************  Bit definition for BKP_DR31 register  *******************/
1189 #define BKP_DR31_D_Pos                      (0U)
1190 #define BKP_DR31_D_Msk                      (0xFFFFUL << BKP_DR31_D_Pos)        /*!< 0x0000FFFF */
1191 #define BKP_DR31_D                          BKP_DR31_D_Msk                     /*!< Backup data */
1192 
1193 /*******************  Bit definition for BKP_DR32 register  *******************/
1194 #define BKP_DR32_D_Pos                      (0U)
1195 #define BKP_DR32_D_Msk                      (0xFFFFUL << BKP_DR32_D_Pos)        /*!< 0x0000FFFF */
1196 #define BKP_DR32_D                          BKP_DR32_D_Msk                     /*!< Backup data */
1197 
1198 /*******************  Bit definition for BKP_DR33 register  *******************/
1199 #define BKP_DR33_D_Pos                      (0U)
1200 #define BKP_DR33_D_Msk                      (0xFFFFUL << BKP_DR33_D_Pos)        /*!< 0x0000FFFF */
1201 #define BKP_DR33_D                          BKP_DR33_D_Msk                     /*!< Backup data */
1202 
1203 /*******************  Bit definition for BKP_DR34 register  *******************/
1204 #define BKP_DR34_D_Pos                      (0U)
1205 #define BKP_DR34_D_Msk                      (0xFFFFUL << BKP_DR34_D_Pos)        /*!< 0x0000FFFF */
1206 #define BKP_DR34_D                          BKP_DR34_D_Msk                     /*!< Backup data */
1207 
1208 /*******************  Bit definition for BKP_DR35 register  *******************/
1209 #define BKP_DR35_D_Pos                      (0U)
1210 #define BKP_DR35_D_Msk                      (0xFFFFUL << BKP_DR35_D_Pos)        /*!< 0x0000FFFF */
1211 #define BKP_DR35_D                          BKP_DR35_D_Msk                     /*!< Backup data */
1212 
1213 /*******************  Bit definition for BKP_DR36 register  *******************/
1214 #define BKP_DR36_D_Pos                      (0U)
1215 #define BKP_DR36_D_Msk                      (0xFFFFUL << BKP_DR36_D_Pos)        /*!< 0x0000FFFF */
1216 #define BKP_DR36_D                          BKP_DR36_D_Msk                     /*!< Backup data */
1217 
1218 /*******************  Bit definition for BKP_DR37 register  *******************/
1219 #define BKP_DR37_D_Pos                      (0U)
1220 #define BKP_DR37_D_Msk                      (0xFFFFUL << BKP_DR37_D_Pos)        /*!< 0x0000FFFF */
1221 #define BKP_DR37_D                          BKP_DR37_D_Msk                     /*!< Backup data */
1222 
1223 /*******************  Bit definition for BKP_DR38 register  *******************/
1224 #define BKP_DR38_D_Pos                      (0U)
1225 #define BKP_DR38_D_Msk                      (0xFFFFUL << BKP_DR38_D_Pos)        /*!< 0x0000FFFF */
1226 #define BKP_DR38_D                          BKP_DR38_D_Msk                     /*!< Backup data */
1227 
1228 /*******************  Bit definition for BKP_DR39 register  *******************/
1229 #define BKP_DR39_D_Pos                      (0U)
1230 #define BKP_DR39_D_Msk                      (0xFFFFUL << BKP_DR39_D_Pos)        /*!< 0x0000FFFF */
1231 #define BKP_DR39_D                          BKP_DR39_D_Msk                     /*!< Backup data */
1232 
1233 /*******************  Bit definition for BKP_DR40 register  *******************/
1234 #define BKP_DR40_D_Pos                      (0U)
1235 #define BKP_DR40_D_Msk                      (0xFFFFUL << BKP_DR40_D_Pos)        /*!< 0x0000FFFF */
1236 #define BKP_DR40_D                          BKP_DR40_D_Msk                     /*!< Backup data */
1237 
1238 /*******************  Bit definition for BKP_DR41 register  *******************/
1239 #define BKP_DR41_D_Pos                      (0U)
1240 #define BKP_DR41_D_Msk                      (0xFFFFUL << BKP_DR41_D_Pos)        /*!< 0x0000FFFF */
1241 #define BKP_DR41_D                          BKP_DR41_D_Msk                     /*!< Backup data */
1242 
1243 /*******************  Bit definition for BKP_DR42 register  *******************/
1244 #define BKP_DR42_D_Pos                      (0U)
1245 #define BKP_DR42_D_Msk                      (0xFFFFUL << BKP_DR42_D_Pos)        /*!< 0x0000FFFF */
1246 #define BKP_DR42_D                          BKP_DR42_D_Msk                     /*!< Backup data */
1247 
1248 #define RTC_BKP_NUMBER 42
1249 
1250 /******************  Bit definition for BKP_RTCCR register  *******************/
1251 #define BKP_RTCCR_CAL_Pos                   (0U)
1252 #define BKP_RTCCR_CAL_Msk                   (0x7FUL << BKP_RTCCR_CAL_Pos)       /*!< 0x0000007F */
1253 #define BKP_RTCCR_CAL                       BKP_RTCCR_CAL_Msk                  /*!< Calibration value */
1254 #define BKP_RTCCR_CCO_Pos                   (7U)
1255 #define BKP_RTCCR_CCO_Msk                   (0x1UL << BKP_RTCCR_CCO_Pos)        /*!< 0x00000080 */
1256 #define BKP_RTCCR_CCO                       BKP_RTCCR_CCO_Msk                  /*!< Calibration Clock Output */
1257 #define BKP_RTCCR_ASOE_Pos                  (8U)
1258 #define BKP_RTCCR_ASOE_Msk                  (0x1UL << BKP_RTCCR_ASOE_Pos)       /*!< 0x00000100 */
1259 #define BKP_RTCCR_ASOE                      BKP_RTCCR_ASOE_Msk                 /*!< Alarm or Second Output Enable */
1260 #define BKP_RTCCR_ASOS_Pos                  (9U)
1261 #define BKP_RTCCR_ASOS_Msk                  (0x1UL << BKP_RTCCR_ASOS_Pos)       /*!< 0x00000200 */
1262 #define BKP_RTCCR_ASOS                      BKP_RTCCR_ASOS_Msk                 /*!< Alarm or Second Output Selection */
1263 
1264 /********************  Bit definition for BKP_CR register  ********************/
1265 #define BKP_CR_TPE_Pos                      (0U)
1266 #define BKP_CR_TPE_Msk                      (0x1UL << BKP_CR_TPE_Pos)           /*!< 0x00000001 */
1267 #define BKP_CR_TPE                          BKP_CR_TPE_Msk                     /*!< TAMPER pin enable */
1268 #define BKP_CR_TPAL_Pos                     (1U)
1269 #define BKP_CR_TPAL_Msk                     (0x1UL << BKP_CR_TPAL_Pos)          /*!< 0x00000002 */
1270 #define BKP_CR_TPAL                         BKP_CR_TPAL_Msk                    /*!< TAMPER pin active level */
1271 
1272 /*******************  Bit definition for BKP_CSR register  ********************/
1273 #define BKP_CSR_CTE_Pos                     (0U)
1274 #define BKP_CSR_CTE_Msk                     (0x1UL << BKP_CSR_CTE_Pos)          /*!< 0x00000001 */
1275 #define BKP_CSR_CTE                         BKP_CSR_CTE_Msk                    /*!< Clear Tamper event */
1276 #define BKP_CSR_CTI_Pos                     (1U)
1277 #define BKP_CSR_CTI_Msk                     (0x1UL << BKP_CSR_CTI_Pos)          /*!< 0x00000002 */
1278 #define BKP_CSR_CTI                         BKP_CSR_CTI_Msk                    /*!< Clear Tamper Interrupt */
1279 #define BKP_CSR_TPIE_Pos                    (2U)
1280 #define BKP_CSR_TPIE_Msk                    (0x1UL << BKP_CSR_TPIE_Pos)         /*!< 0x00000004 */
1281 #define BKP_CSR_TPIE                        BKP_CSR_TPIE_Msk                   /*!< TAMPER Pin interrupt enable */
1282 #define BKP_CSR_TEF_Pos                     (8U)
1283 #define BKP_CSR_TEF_Msk                     (0x1UL << BKP_CSR_TEF_Pos)          /*!< 0x00000100 */
1284 #define BKP_CSR_TEF                         BKP_CSR_TEF_Msk                    /*!< Tamper Event Flag */
1285 #define BKP_CSR_TIF_Pos                     (9U)
1286 #define BKP_CSR_TIF_Msk                     (0x1UL << BKP_CSR_TIF_Pos)          /*!< 0x00000200 */
1287 #define BKP_CSR_TIF                         BKP_CSR_TIF_Msk                    /*!< Tamper Interrupt Flag */
1288 
1289 /******************************************************************************/
1290 /*                                                                            */
1291 /*                         Reset and Clock Control                            */
1292 /*                                                                            */
1293 /******************************************************************************/
1294 
1295 /********************  Bit definition for RCC_CR register  ********************/
1296 #define RCC_CR_HSION_Pos                     (0U)
1297 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)        /*!< 0x00000001 */
1298 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed clock enable */
1299 #define RCC_CR_HSIRDY_Pos                    (1U)
1300 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)       /*!< 0x00000002 */
1301 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed clock ready flag */
1302 #define RCC_CR_HSITRIM_Pos                   (3U)
1303 #define RCC_CR_HSITRIM_Msk                   (0x1FUL << RCC_CR_HSITRIM_Pos)     /*!< 0x000000F8 */
1304 #define RCC_CR_HSITRIM                       RCC_CR_HSITRIM_Msk                /*!< Internal High Speed clock trimming */
1305 #define RCC_CR_HSICAL_Pos                    (8U)
1306 #define RCC_CR_HSICAL_Msk                    (0xFFUL << RCC_CR_HSICAL_Pos)      /*!< 0x0000FF00 */
1307 #define RCC_CR_HSICAL                        RCC_CR_HSICAL_Msk                 /*!< Internal High Speed clock Calibration */
1308 #define RCC_CR_HSEON_Pos                     (16U)
1309 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
1310 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed clock enable */
1311 #define RCC_CR_HSERDY_Pos                    (17U)
1312 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
1313 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed clock ready flag */
1314 #define RCC_CR_HSEBYP_Pos                    (18U)
1315 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
1316 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed clock Bypass */
1317 #define RCC_CR_CSSON_Pos                     (19U)
1318 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
1319 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< Clock Security System enable */
1320 #define RCC_CR_PLLON_Pos                     (24U)
1321 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
1322 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< PLL enable */
1323 #define RCC_CR_PLLRDY_Pos                    (25U)
1324 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
1325 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */
1326 
1327 
1328 /*******************  Bit definition for RCC_CFGR register  *******************/
1329 /*!< SW configuration */
1330 #define RCC_CFGR_SW_Pos                      (0U)
1331 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
1332 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
1333 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
1334 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
1335 
1336 #define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */
1337 #define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */
1338 #define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */
1339 
1340 /*!< SWS configuration */
1341 #define RCC_CFGR_SWS_Pos                     (2U)
1342 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
1343 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
1344 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
1345 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
1346 
1347 #define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */
1348 #define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */
1349 #define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */
1350 
1351 /*!< HPRE configuration */
1352 #define RCC_CFGR_HPRE_Pos                    (4U)
1353 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
1354 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
1355 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
1356 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
1357 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
1358 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
1359 
1360 #define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */
1361 #define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */
1362 #define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */
1363 #define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */
1364 #define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */
1365 #define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */
1366 #define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */
1367 #define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */
1368 #define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */
1369 
1370 /*!< PPRE1 configuration */
1371 #define RCC_CFGR_PPRE1_Pos                   (8U)
1372 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
1373 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
1374 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
1375 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
1376 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
1377 
1378 #define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */
1379 #define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */
1380 #define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */
1381 #define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */
1382 #define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */
1383 
1384 /*!< PPRE2 configuration */
1385 #define RCC_CFGR_PPRE2_Pos                   (11U)
1386 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
1387 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
1388 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
1389 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
1390 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
1391 
1392 #define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */
1393 #define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */
1394 #define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */
1395 #define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */
1396 #define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */
1397 
1398 /*!< ADCPPRE configuration */
1399 #define RCC_CFGR_ADCPRE_Pos                  (14U)
1400 #define RCC_CFGR_ADCPRE_Msk                  (0x3UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x0000C000 */
1401 #define RCC_CFGR_ADCPRE                      RCC_CFGR_ADCPRE_Msk               /*!< ADCPRE[1:0] bits (ADC prescaler) */
1402 #define RCC_CFGR_ADCPRE_0                    (0x1UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */
1403 #define RCC_CFGR_ADCPRE_1                    (0x2UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */
1404 
1405 #define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */
1406 #define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */
1407 #define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */
1408 #define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */
1409 
1410 #define RCC_CFGR_PLLSRC_Pos                  (16U)
1411 #define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
1412 #define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
1413 
1414 #define RCC_CFGR_PLLXTPRE_Pos                (17U)
1415 #define RCC_CFGR_PLLXTPRE_Msk                (0x1UL << RCC_CFGR_PLLXTPRE_Pos)   /*!< 0x00020000 */
1416 #define RCC_CFGR_PLLXTPRE                    RCC_CFGR_PLLXTPRE_Msk             /*!< HSE divider for PLL entry */
1417 
1418 /*!< PLLMUL configuration */
1419 #define RCC_CFGR_PLLMULL_Pos                 (18U)
1420 #define RCC_CFGR_PLLMULL_Msk                 (0xFUL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x003C0000 */
1421 #define RCC_CFGR_PLLMULL                     RCC_CFGR_PLLMULL_Msk              /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1422 #define RCC_CFGR_PLLMULL_0                   (0x1UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00040000 */
1423 #define RCC_CFGR_PLLMULL_1                   (0x2UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00080000 */
1424 #define RCC_CFGR_PLLMULL_2                   (0x4UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */
1425 #define RCC_CFGR_PLLMULL_3                   (0x8UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */
1426 
1427 #define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */
1428 #define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */
1429 
1430 #define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */
1431 #define RCC_CFGR_PLLMULL3_Pos                (18U)
1432 #define RCC_CFGR_PLLMULL3_Msk                (0x1UL << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */
1433 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */
1434 #define RCC_CFGR_PLLMULL4_Pos                (19U)
1435 #define RCC_CFGR_PLLMULL4_Msk                (0x1UL << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */
1436 #define RCC_CFGR_PLLMULL4                    RCC_CFGR_PLLMULL4_Msk             /*!< PLL input clock*4 */
1437 #define RCC_CFGR_PLLMULL5_Pos                (18U)
1438 #define RCC_CFGR_PLLMULL5_Msk                (0x3UL << RCC_CFGR_PLLMULL5_Pos)   /*!< 0x000C0000 */
1439 #define RCC_CFGR_PLLMULL5                    RCC_CFGR_PLLMULL5_Msk             /*!< PLL input clock*5 */
1440 #define RCC_CFGR_PLLMULL6_Pos                (20U)
1441 #define RCC_CFGR_PLLMULL6_Msk                (0x1UL << RCC_CFGR_PLLMULL6_Pos)   /*!< 0x00100000 */
1442 #define RCC_CFGR_PLLMULL6                    RCC_CFGR_PLLMULL6_Msk             /*!< PLL input clock*6 */
1443 #define RCC_CFGR_PLLMULL7_Pos                (18U)
1444 #define RCC_CFGR_PLLMULL7_Msk                (0x5UL << RCC_CFGR_PLLMULL7_Pos)   /*!< 0x00140000 */
1445 #define RCC_CFGR_PLLMULL7                    RCC_CFGR_PLLMULL7_Msk             /*!< PLL input clock*7 */
1446 #define RCC_CFGR_PLLMULL8_Pos                (19U)
1447 #define RCC_CFGR_PLLMULL8_Msk                (0x3UL << RCC_CFGR_PLLMULL8_Pos)   /*!< 0x00180000 */
1448 #define RCC_CFGR_PLLMULL8                    RCC_CFGR_PLLMULL8_Msk             /*!< PLL input clock*8 */
1449 #define RCC_CFGR_PLLMULL9_Pos                (18U)
1450 #define RCC_CFGR_PLLMULL9_Msk                (0x7UL << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */
1451 #define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock*9 */
1452 #define RCC_CFGR_PLLMULL10_Pos               (21U)
1453 #define RCC_CFGR_PLLMULL10_Msk               (0x1UL << RCC_CFGR_PLLMULL10_Pos)  /*!< 0x00200000 */
1454 #define RCC_CFGR_PLLMULL10                   RCC_CFGR_PLLMULL10_Msk            /*!< PLL input clock10 */
1455 #define RCC_CFGR_PLLMULL11_Pos               (18U)
1456 #define RCC_CFGR_PLLMULL11_Msk               (0x9UL << RCC_CFGR_PLLMULL11_Pos)  /*!< 0x00240000 */
1457 #define RCC_CFGR_PLLMULL11                   RCC_CFGR_PLLMULL11_Msk            /*!< PLL input clock*11 */
1458 #define RCC_CFGR_PLLMULL12_Pos               (19U)
1459 #define RCC_CFGR_PLLMULL12_Msk               (0x5UL << RCC_CFGR_PLLMULL12_Pos)  /*!< 0x00280000 */
1460 #define RCC_CFGR_PLLMULL12                   RCC_CFGR_PLLMULL12_Msk            /*!< PLL input clock*12 */
1461 #define RCC_CFGR_PLLMULL13_Pos               (18U)
1462 #define RCC_CFGR_PLLMULL13_Msk               (0xBUL << RCC_CFGR_PLLMULL13_Pos)  /*!< 0x002C0000 */
1463 #define RCC_CFGR_PLLMULL13                   RCC_CFGR_PLLMULL13_Msk            /*!< PLL input clock*13 */
1464 #define RCC_CFGR_PLLMULL14_Pos               (20U)
1465 #define RCC_CFGR_PLLMULL14_Msk               (0x3UL << RCC_CFGR_PLLMULL14_Pos)  /*!< 0x00300000 */
1466 #define RCC_CFGR_PLLMULL14                   RCC_CFGR_PLLMULL14_Msk            /*!< PLL input clock*14 */
1467 #define RCC_CFGR_PLLMULL15_Pos               (18U)
1468 #define RCC_CFGR_PLLMULL15_Msk               (0xDUL << RCC_CFGR_PLLMULL15_Pos)  /*!< 0x00340000 */
1469 #define RCC_CFGR_PLLMULL15                   RCC_CFGR_PLLMULL15_Msk            /*!< PLL input clock*15 */
1470 #define RCC_CFGR_PLLMULL16_Pos               (19U)
1471 #define RCC_CFGR_PLLMULL16_Msk               (0x7UL << RCC_CFGR_PLLMULL16_Pos)  /*!< 0x00380000 */
1472 #define RCC_CFGR_PLLMULL16                   RCC_CFGR_PLLMULL16_Msk            /*!< PLL input clock*16 */
1473 #define RCC_CFGR_USBPRE_Pos                  (22U)
1474 #define RCC_CFGR_USBPRE_Msk                  (0x1UL << RCC_CFGR_USBPRE_Pos)     /*!< 0x00400000 */
1475 #define RCC_CFGR_USBPRE                      RCC_CFGR_USBPRE_Msk               /*!< USB Device prescaler */
1476 
1477 /*!< MCO configuration */
1478 #define RCC_CFGR_MCO_Pos                     (24U)
1479 #define RCC_CFGR_MCO_Msk                     (0x7UL << RCC_CFGR_MCO_Pos)        /*!< 0x07000000 */
1480 #define RCC_CFGR_MCO                         RCC_CFGR_MCO_Msk                  /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1481 #define RCC_CFGR_MCO_0                       (0x1UL << RCC_CFGR_MCO_Pos)        /*!< 0x01000000 */
1482 #define RCC_CFGR_MCO_1                       (0x2UL << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */
1483 #define RCC_CFGR_MCO_2                       (0x4UL << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */
1484 
1485 #define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */
1486 #define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */
1487 #define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */
1488 #define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */
1489 #define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */
1490 
1491  /* Reference defines */
1492  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
1493  #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
1494  #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
1495  #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
1496  #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
1497  #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
1498  #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
1499  #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
1500  #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2
1501 
1502 /*!<******************  Bit definition for RCC_CIR register  ********************/
1503 #define RCC_CIR_LSIRDYF_Pos                  (0U)
1504 #define RCC_CIR_LSIRDYF_Msk                  (0x1UL << RCC_CIR_LSIRDYF_Pos)     /*!< 0x00000001 */
1505 #define RCC_CIR_LSIRDYF                      RCC_CIR_LSIRDYF_Msk               /*!< LSI Ready Interrupt flag */
1506 #define RCC_CIR_LSERDYF_Pos                  (1U)
1507 #define RCC_CIR_LSERDYF_Msk                  (0x1UL << RCC_CIR_LSERDYF_Pos)     /*!< 0x00000002 */
1508 #define RCC_CIR_LSERDYF                      RCC_CIR_LSERDYF_Msk               /*!< LSE Ready Interrupt flag */
1509 #define RCC_CIR_HSIRDYF_Pos                  (2U)
1510 #define RCC_CIR_HSIRDYF_Msk                  (0x1UL << RCC_CIR_HSIRDYF_Pos)     /*!< 0x00000004 */
1511 #define RCC_CIR_HSIRDYF                      RCC_CIR_HSIRDYF_Msk               /*!< HSI Ready Interrupt flag */
1512 #define RCC_CIR_HSERDYF_Pos                  (3U)
1513 #define RCC_CIR_HSERDYF_Msk                  (0x1UL << RCC_CIR_HSERDYF_Pos)     /*!< 0x00000008 */
1514 #define RCC_CIR_HSERDYF                      RCC_CIR_HSERDYF_Msk               /*!< HSE Ready Interrupt flag */
1515 #define RCC_CIR_PLLRDYF_Pos                  (4U)
1516 #define RCC_CIR_PLLRDYF_Msk                  (0x1UL << RCC_CIR_PLLRDYF_Pos)     /*!< 0x00000010 */
1517 #define RCC_CIR_PLLRDYF                      RCC_CIR_PLLRDYF_Msk               /*!< PLL Ready Interrupt flag */
1518 #define RCC_CIR_CSSF_Pos                     (7U)
1519 #define RCC_CIR_CSSF_Msk                     (0x1UL << RCC_CIR_CSSF_Pos)        /*!< 0x00000080 */
1520 #define RCC_CIR_CSSF                         RCC_CIR_CSSF_Msk                  /*!< Clock Security System Interrupt flag */
1521 #define RCC_CIR_LSIRDYIE_Pos                 (8U)
1522 #define RCC_CIR_LSIRDYIE_Msk                 (0x1UL << RCC_CIR_LSIRDYIE_Pos)    /*!< 0x00000100 */
1523 #define RCC_CIR_LSIRDYIE                     RCC_CIR_LSIRDYIE_Msk              /*!< LSI Ready Interrupt Enable */
1524 #define RCC_CIR_LSERDYIE_Pos                 (9U)
1525 #define RCC_CIR_LSERDYIE_Msk                 (0x1UL << RCC_CIR_LSERDYIE_Pos)    /*!< 0x00000200 */
1526 #define RCC_CIR_LSERDYIE                     RCC_CIR_LSERDYIE_Msk              /*!< LSE Ready Interrupt Enable */
1527 #define RCC_CIR_HSIRDYIE_Pos                 (10U)
1528 #define RCC_CIR_HSIRDYIE_Msk                 (0x1UL << RCC_CIR_HSIRDYIE_Pos)    /*!< 0x00000400 */
1529 #define RCC_CIR_HSIRDYIE                     RCC_CIR_HSIRDYIE_Msk              /*!< HSI Ready Interrupt Enable */
1530 #define RCC_CIR_HSERDYIE_Pos                 (11U)
1531 #define RCC_CIR_HSERDYIE_Msk                 (0x1UL << RCC_CIR_HSERDYIE_Pos)    /*!< 0x00000800 */
1532 #define RCC_CIR_HSERDYIE                     RCC_CIR_HSERDYIE_Msk              /*!< HSE Ready Interrupt Enable */
1533 #define RCC_CIR_PLLRDYIE_Pos                 (12U)
1534 #define RCC_CIR_PLLRDYIE_Msk                 (0x1UL << RCC_CIR_PLLRDYIE_Pos)    /*!< 0x00001000 */
1535 #define RCC_CIR_PLLRDYIE                     RCC_CIR_PLLRDYIE_Msk              /*!< PLL Ready Interrupt Enable */
1536 #define RCC_CIR_LSIRDYC_Pos                  (16U)
1537 #define RCC_CIR_LSIRDYC_Msk                  (0x1UL << RCC_CIR_LSIRDYC_Pos)     /*!< 0x00010000 */
1538 #define RCC_CIR_LSIRDYC                      RCC_CIR_LSIRDYC_Msk               /*!< LSI Ready Interrupt Clear */
1539 #define RCC_CIR_LSERDYC_Pos                  (17U)
1540 #define RCC_CIR_LSERDYC_Msk                  (0x1UL << RCC_CIR_LSERDYC_Pos)     /*!< 0x00020000 */
1541 #define RCC_CIR_LSERDYC                      RCC_CIR_LSERDYC_Msk               /*!< LSE Ready Interrupt Clear */
1542 #define RCC_CIR_HSIRDYC_Pos                  (18U)
1543 #define RCC_CIR_HSIRDYC_Msk                  (0x1UL << RCC_CIR_HSIRDYC_Pos)     /*!< 0x00040000 */
1544 #define RCC_CIR_HSIRDYC                      RCC_CIR_HSIRDYC_Msk               /*!< HSI Ready Interrupt Clear */
1545 #define RCC_CIR_HSERDYC_Pos                  (19U)
1546 #define RCC_CIR_HSERDYC_Msk                  (0x1UL << RCC_CIR_HSERDYC_Pos)     /*!< 0x00080000 */
1547 #define RCC_CIR_HSERDYC                      RCC_CIR_HSERDYC_Msk               /*!< HSE Ready Interrupt Clear */
1548 #define RCC_CIR_PLLRDYC_Pos                  (20U)
1549 #define RCC_CIR_PLLRDYC_Msk                  (0x1UL << RCC_CIR_PLLRDYC_Pos)     /*!< 0x00100000 */
1550 #define RCC_CIR_PLLRDYC                      RCC_CIR_PLLRDYC_Msk               /*!< PLL Ready Interrupt Clear */
1551 #define RCC_CIR_CSSC_Pos                     (23U)
1552 #define RCC_CIR_CSSC_Msk                     (0x1UL << RCC_CIR_CSSC_Pos)        /*!< 0x00800000 */
1553 #define RCC_CIR_CSSC                         RCC_CIR_CSSC_Msk                  /*!< Clock Security System Interrupt Clear */
1554 
1555 
1556 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
1557 #define RCC_APB2RSTR_AFIORST_Pos             (0U)
1558 #define RCC_APB2RSTR_AFIORST_Msk             (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
1559 #define RCC_APB2RSTR_AFIORST                 RCC_APB2RSTR_AFIORST_Msk          /*!< Alternate Function I/O reset */
1560 #define RCC_APB2RSTR_IOPARST_Pos             (2U)
1561 #define RCC_APB2RSTR_IOPARST_Msk             (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
1562 #define RCC_APB2RSTR_IOPARST                 RCC_APB2RSTR_IOPARST_Msk          /*!< I/O port A reset */
1563 #define RCC_APB2RSTR_IOPBRST_Pos             (3U)
1564 #define RCC_APB2RSTR_IOPBRST_Msk             (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
1565 #define RCC_APB2RSTR_IOPBRST                 RCC_APB2RSTR_IOPBRST_Msk          /*!< I/O port B reset */
1566 #define RCC_APB2RSTR_IOPCRST_Pos             (4U)
1567 #define RCC_APB2RSTR_IOPCRST_Msk             (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
1568 #define RCC_APB2RSTR_IOPCRST                 RCC_APB2RSTR_IOPCRST_Msk          /*!< I/O port C reset */
1569 #define RCC_APB2RSTR_IOPDRST_Pos             (5U)
1570 #define RCC_APB2RSTR_IOPDRST_Msk             (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
1571 #define RCC_APB2RSTR_IOPDRST                 RCC_APB2RSTR_IOPDRST_Msk          /*!< I/O port D reset */
1572 #define RCC_APB2RSTR_ADC1RST_Pos             (9U)
1573 #define RCC_APB2RSTR_ADC1RST_Msk             (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
1574 #define RCC_APB2RSTR_ADC1RST                 RCC_APB2RSTR_ADC1RST_Msk          /*!< ADC 1 interface reset */
1575 
1576 #define RCC_APB2RSTR_ADC2RST_Pos             (10U)
1577 #define RCC_APB2RSTR_ADC2RST_Msk             (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
1578 #define RCC_APB2RSTR_ADC2RST                 RCC_APB2RSTR_ADC2RST_Msk          /*!< ADC 2 interface reset */
1579 
1580 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
1581 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
1582 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          /*!< TIM1 Timer reset */
1583 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
1584 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
1585 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          /*!< SPI 1 reset */
1586 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
1587 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
1588 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        /*!< USART1 reset */
1589 
1590 
1591 #define RCC_APB2RSTR_IOPERST_Pos             (6U)
1592 #define RCC_APB2RSTR_IOPERST_Msk             (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
1593 #define RCC_APB2RSTR_IOPERST                 RCC_APB2RSTR_IOPERST_Msk          /*!< I/O port E reset */
1594 
1595 #define RCC_APB2RSTR_IOPFRST_Pos             (7U)
1596 #define RCC_APB2RSTR_IOPFRST_Msk             (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */
1597 #define RCC_APB2RSTR_IOPFRST                 RCC_APB2RSTR_IOPFRST_Msk          /*!< I/O port F reset */
1598 #define RCC_APB2RSTR_IOPGRST_Pos             (8U)
1599 #define RCC_APB2RSTR_IOPGRST_Msk             (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */
1600 #define RCC_APB2RSTR_IOPGRST                 RCC_APB2RSTR_IOPGRST_Msk          /*!< I/O port G reset */
1601 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
1602 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
1603 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk          /*!< TIM8 Timer reset */
1604 #define RCC_APB2RSTR_ADC3RST_Pos             (15U)
1605 #define RCC_APB2RSTR_ADC3RST_Msk             (0x1UL << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */
1606 #define RCC_APB2RSTR_ADC3RST                 RCC_APB2RSTR_ADC3RST_Msk          /*!< ADC3 interface reset */
1607 
1608 
1609 #define RCC_APB2RSTR_TIM9RST_Pos             (19U)
1610 #define RCC_APB2RSTR_TIM9RST_Msk             (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */
1611 #define RCC_APB2RSTR_TIM9RST                 RCC_APB2RSTR_TIM9RST_Msk          /*!< TIM9 Timer reset */
1612 #define RCC_APB2RSTR_TIM10RST_Pos            (20U)
1613 #define RCC_APB2RSTR_TIM10RST_Msk            (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00100000 */
1614 #define RCC_APB2RSTR_TIM10RST                RCC_APB2RSTR_TIM10RST_Msk         /*!< TIM10 Timer reset */
1615 #define RCC_APB2RSTR_TIM11RST_Pos            (21U)
1616 #define RCC_APB2RSTR_TIM11RST_Msk            (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00200000 */
1617 #define RCC_APB2RSTR_TIM11RST                RCC_APB2RSTR_TIM11RST_Msk         /*!< TIM11 Timer reset */
1618 
1619 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
1620 #define RCC_APB1RSTR_TIM2RST_Pos             (0U)
1621 #define RCC_APB1RSTR_TIM2RST_Msk             (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
1622 #define RCC_APB1RSTR_TIM2RST                 RCC_APB1RSTR_TIM2RST_Msk          /*!< Timer 2 reset */
1623 #define RCC_APB1RSTR_TIM3RST_Pos             (1U)
1624 #define RCC_APB1RSTR_TIM3RST_Msk             (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
1625 #define RCC_APB1RSTR_TIM3RST                 RCC_APB1RSTR_TIM3RST_Msk          /*!< Timer 3 reset */
1626 #define RCC_APB1RSTR_WWDGRST_Pos             (11U)
1627 #define RCC_APB1RSTR_WWDGRST_Msk             (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
1628 #define RCC_APB1RSTR_WWDGRST                 RCC_APB1RSTR_WWDGRST_Msk          /*!< Window Watchdog reset */
1629 #define RCC_APB1RSTR_USART2RST_Pos           (17U)
1630 #define RCC_APB1RSTR_USART2RST_Msk           (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
1631 #define RCC_APB1RSTR_USART2RST               RCC_APB1RSTR_USART2RST_Msk        /*!< USART 2 reset */
1632 #define RCC_APB1RSTR_I2C1RST_Pos             (21U)
1633 #define RCC_APB1RSTR_I2C1RST_Msk             (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
1634 #define RCC_APB1RSTR_I2C1RST                 RCC_APB1RSTR_I2C1RST_Msk          /*!< I2C 1 reset */
1635 
1636 #define RCC_APB1RSTR_CAN1RST_Pos             (25U)
1637 #define RCC_APB1RSTR_CAN1RST_Msk             (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
1638 #define RCC_APB1RSTR_CAN1RST                 RCC_APB1RSTR_CAN1RST_Msk          /*!< CAN1 reset */
1639 
1640 #define RCC_APB1RSTR_BKPRST_Pos              (27U)
1641 #define RCC_APB1RSTR_BKPRST_Msk              (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
1642 #define RCC_APB1RSTR_BKPRST                  RCC_APB1RSTR_BKPRST_Msk           /*!< Backup interface reset */
1643 #define RCC_APB1RSTR_PWRRST_Pos              (28U)
1644 #define RCC_APB1RSTR_PWRRST_Msk              (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
1645 #define RCC_APB1RSTR_PWRRST                  RCC_APB1RSTR_PWRRST_Msk           /*!< Power interface reset */
1646 
1647 #define RCC_APB1RSTR_TIM4RST_Pos             (2U)
1648 #define RCC_APB1RSTR_TIM4RST_Msk             (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
1649 #define RCC_APB1RSTR_TIM4RST                 RCC_APB1RSTR_TIM4RST_Msk          /*!< Timer 4 reset */
1650 #define RCC_APB1RSTR_SPI2RST_Pos             (14U)
1651 #define RCC_APB1RSTR_SPI2RST_Msk             (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
1652 #define RCC_APB1RSTR_SPI2RST                 RCC_APB1RSTR_SPI2RST_Msk          /*!< SPI 2 reset */
1653 #define RCC_APB1RSTR_USART3RST_Pos           (18U)
1654 #define RCC_APB1RSTR_USART3RST_Msk           (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
1655 #define RCC_APB1RSTR_USART3RST               RCC_APB1RSTR_USART3RST_Msk        /*!< USART 3 reset */
1656 #define RCC_APB1RSTR_I2C2RST_Pos             (22U)
1657 #define RCC_APB1RSTR_I2C2RST_Msk             (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
1658 #define RCC_APB1RSTR_I2C2RST                 RCC_APB1RSTR_I2C2RST_Msk          /*!< I2C 2 reset */
1659 
1660 #define RCC_APB1RSTR_USBRST_Pos              (23U)
1661 #define RCC_APB1RSTR_USBRST_Msk              (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
1662 #define RCC_APB1RSTR_USBRST                  RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */
1663 
1664 #define RCC_APB1RSTR_TIM5RST_Pos             (3U)
1665 #define RCC_APB1RSTR_TIM5RST_Msk             (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
1666 #define RCC_APB1RSTR_TIM5RST                 RCC_APB1RSTR_TIM5RST_Msk          /*!< Timer 5 reset */
1667 #define RCC_APB1RSTR_TIM6RST_Pos             (4U)
1668 #define RCC_APB1RSTR_TIM6RST_Msk             (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
1669 #define RCC_APB1RSTR_TIM6RST                 RCC_APB1RSTR_TIM6RST_Msk          /*!< Timer 6 reset */
1670 #define RCC_APB1RSTR_TIM7RST_Pos             (5U)
1671 #define RCC_APB1RSTR_TIM7RST_Msk             (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
1672 #define RCC_APB1RSTR_TIM7RST                 RCC_APB1RSTR_TIM7RST_Msk          /*!< Timer 7 reset */
1673 #define RCC_APB1RSTR_SPI3RST_Pos             (15U)
1674 #define RCC_APB1RSTR_SPI3RST_Msk             (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
1675 #define RCC_APB1RSTR_SPI3RST                 RCC_APB1RSTR_SPI3RST_Msk          /*!< SPI 3 reset */
1676 #define RCC_APB1RSTR_UART4RST_Pos            (19U)
1677 #define RCC_APB1RSTR_UART4RST_Msk            (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
1678 #define RCC_APB1RSTR_UART4RST                RCC_APB1RSTR_UART4RST_Msk         /*!< UART 4 reset */
1679 #define RCC_APB1RSTR_UART5RST_Pos            (20U)
1680 #define RCC_APB1RSTR_UART5RST_Msk            (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
1681 #define RCC_APB1RSTR_UART5RST                RCC_APB1RSTR_UART5RST_Msk         /*!< UART 5 reset */
1682 
1683 
1684 
1685 
1686 #define RCC_APB1RSTR_TIM12RST_Pos            (6U)
1687 #define RCC_APB1RSTR_TIM12RST_Msk            (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
1688 #define RCC_APB1RSTR_TIM12RST                RCC_APB1RSTR_TIM12RST_Msk         /*!< TIM12 Timer reset */
1689 #define RCC_APB1RSTR_TIM13RST_Pos            (7U)
1690 #define RCC_APB1RSTR_TIM13RST_Msk            (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
1691 #define RCC_APB1RSTR_TIM13RST                RCC_APB1RSTR_TIM13RST_Msk         /*!< TIM13 Timer reset */
1692 #define RCC_APB1RSTR_TIM14RST_Pos            (8U)
1693 #define RCC_APB1RSTR_TIM14RST_Msk            (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
1694 #define RCC_APB1RSTR_TIM14RST                RCC_APB1RSTR_TIM14RST_Msk         /*!< TIM14 Timer reset */
1695 #define RCC_APB1RSTR_DACRST_Pos              (29U)
1696 #define RCC_APB1RSTR_DACRST_Msk              (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
1697 #define RCC_APB1RSTR_DACRST                  RCC_APB1RSTR_DACRST_Msk           /*!< DAC interface reset */
1698 
1699 /******************  Bit definition for RCC_AHBENR register  ******************/
1700 #define RCC_AHBENR_DMA1EN_Pos                (0U)
1701 #define RCC_AHBENR_DMA1EN_Msk                (0x1UL << RCC_AHBENR_DMA1EN_Pos)   /*!< 0x00000001 */
1702 #define RCC_AHBENR_DMA1EN                    RCC_AHBENR_DMA1EN_Msk             /*!< DMA1 clock enable */
1703 #define RCC_AHBENR_SRAMEN_Pos                (2U)
1704 #define RCC_AHBENR_SRAMEN_Msk                (0x1UL << RCC_AHBENR_SRAMEN_Pos)   /*!< 0x00000004 */
1705 #define RCC_AHBENR_SRAMEN                    RCC_AHBENR_SRAMEN_Msk             /*!< SRAM interface clock enable */
1706 #define RCC_AHBENR_FLITFEN_Pos               (4U)
1707 #define RCC_AHBENR_FLITFEN_Msk               (0x1UL << RCC_AHBENR_FLITFEN_Pos)  /*!< 0x00000010 */
1708 #define RCC_AHBENR_FLITFEN                   RCC_AHBENR_FLITFEN_Msk            /*!< FLITF clock enable */
1709 #define RCC_AHBENR_CRCEN_Pos                 (6U)
1710 #define RCC_AHBENR_CRCEN_Msk                 (0x1UL << RCC_AHBENR_CRCEN_Pos)    /*!< 0x00000040 */
1711 #define RCC_AHBENR_CRCEN                     RCC_AHBENR_CRCEN_Msk              /*!< CRC clock enable */
1712 
1713 #define RCC_AHBENR_DMA2EN_Pos                (1U)
1714 #define RCC_AHBENR_DMA2EN_Msk                (0x1UL << RCC_AHBENR_DMA2EN_Pos)   /*!< 0x00000002 */
1715 #define RCC_AHBENR_DMA2EN                    RCC_AHBENR_DMA2EN_Msk             /*!< DMA2 clock enable */
1716 
1717 #define RCC_AHBENR_FSMCEN_Pos                (8U)
1718 #define RCC_AHBENR_FSMCEN_Msk                (0x1UL << RCC_AHBENR_FSMCEN_Pos)   /*!< 0x00000100 */
1719 #define RCC_AHBENR_FSMCEN                    RCC_AHBENR_FSMCEN_Msk             /*!< FSMC clock enable */
1720 #define RCC_AHBENR_SDIOEN_Pos                (10U)
1721 #define RCC_AHBENR_SDIOEN_Msk                (0x1UL << RCC_AHBENR_SDIOEN_Pos)   /*!< 0x00000400 */
1722 #define RCC_AHBENR_SDIOEN                    RCC_AHBENR_SDIOEN_Msk             /*!< SDIO clock enable */
1723 
1724 
1725 /******************  Bit definition for RCC_APB2ENR register  *****************/
1726 #define RCC_APB2ENR_AFIOEN_Pos               (0U)
1727 #define RCC_APB2ENR_AFIOEN_Msk               (0x1UL << RCC_APB2ENR_AFIOEN_Pos)  /*!< 0x00000001 */
1728 #define RCC_APB2ENR_AFIOEN                   RCC_APB2ENR_AFIOEN_Msk            /*!< Alternate Function I/O clock enable */
1729 #define RCC_APB2ENR_IOPAEN_Pos               (2U)
1730 #define RCC_APB2ENR_IOPAEN_Msk               (0x1UL << RCC_APB2ENR_IOPAEN_Pos)  /*!< 0x00000004 */
1731 #define RCC_APB2ENR_IOPAEN                   RCC_APB2ENR_IOPAEN_Msk            /*!< I/O port A clock enable */
1732 #define RCC_APB2ENR_IOPBEN_Pos               (3U)
1733 #define RCC_APB2ENR_IOPBEN_Msk               (0x1UL << RCC_APB2ENR_IOPBEN_Pos)  /*!< 0x00000008 */
1734 #define RCC_APB2ENR_IOPBEN                   RCC_APB2ENR_IOPBEN_Msk            /*!< I/O port B clock enable */
1735 #define RCC_APB2ENR_IOPCEN_Pos               (4U)
1736 #define RCC_APB2ENR_IOPCEN_Msk               (0x1UL << RCC_APB2ENR_IOPCEN_Pos)  /*!< 0x00000010 */
1737 #define RCC_APB2ENR_IOPCEN                   RCC_APB2ENR_IOPCEN_Msk            /*!< I/O port C clock enable */
1738 #define RCC_APB2ENR_IOPDEN_Pos               (5U)
1739 #define RCC_APB2ENR_IOPDEN_Msk               (0x1UL << RCC_APB2ENR_IOPDEN_Pos)  /*!< 0x00000020 */
1740 #define RCC_APB2ENR_IOPDEN                   RCC_APB2ENR_IOPDEN_Msk            /*!< I/O port D clock enable */
1741 #define RCC_APB2ENR_ADC1EN_Pos               (9U)
1742 #define RCC_APB2ENR_ADC1EN_Msk               (0x1UL << RCC_APB2ENR_ADC1EN_Pos)  /*!< 0x00000200 */
1743 #define RCC_APB2ENR_ADC1EN                   RCC_APB2ENR_ADC1EN_Msk            /*!< ADC 1 interface clock enable */
1744 
1745 #define RCC_APB2ENR_ADC2EN_Pos               (10U)
1746 #define RCC_APB2ENR_ADC2EN_Msk               (0x1UL << RCC_APB2ENR_ADC2EN_Pos)  /*!< 0x00000400 */
1747 #define RCC_APB2ENR_ADC2EN                   RCC_APB2ENR_ADC2EN_Msk            /*!< ADC 2 interface clock enable */
1748 
1749 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
1750 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
1751 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            /*!< TIM1 Timer clock enable */
1752 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
1753 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
1754 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            /*!< SPI 1 clock enable */
1755 #define RCC_APB2ENR_USART1EN_Pos             (14U)
1756 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
1757 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          /*!< USART1 clock enable */
1758 
1759 
1760 #define RCC_APB2ENR_IOPEEN_Pos               (6U)
1761 #define RCC_APB2ENR_IOPEEN_Msk               (0x1UL << RCC_APB2ENR_IOPEEN_Pos)  /*!< 0x00000040 */
1762 #define RCC_APB2ENR_IOPEEN                   RCC_APB2ENR_IOPEEN_Msk            /*!< I/O port E clock enable */
1763 
1764 #define RCC_APB2ENR_IOPFEN_Pos               (7U)
1765 #define RCC_APB2ENR_IOPFEN_Msk               (0x1UL << RCC_APB2ENR_IOPFEN_Pos)  /*!< 0x00000080 */
1766 #define RCC_APB2ENR_IOPFEN                   RCC_APB2ENR_IOPFEN_Msk            /*!< I/O port F clock enable */
1767 #define RCC_APB2ENR_IOPGEN_Pos               (8U)
1768 #define RCC_APB2ENR_IOPGEN_Msk               (0x1UL << RCC_APB2ENR_IOPGEN_Pos)  /*!< 0x00000100 */
1769 #define RCC_APB2ENR_IOPGEN                   RCC_APB2ENR_IOPGEN_Msk            /*!< I/O port G clock enable */
1770 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
1771 #define RCC_APB2ENR_TIM8EN_Msk               (0x1UL << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
1772 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk            /*!< TIM8 Timer clock enable */
1773 #define RCC_APB2ENR_ADC3EN_Pos               (15U)
1774 #define RCC_APB2ENR_ADC3EN_Msk               (0x1UL << RCC_APB2ENR_ADC3EN_Pos)  /*!< 0x00008000 */
1775 #define RCC_APB2ENR_ADC3EN                   RCC_APB2ENR_ADC3EN_Msk            /*!< DMA1 clock enable */
1776 
1777 
1778 #define RCC_APB2ENR_TIM9EN_Pos               (19U)
1779 #define RCC_APB2ENR_TIM9EN_Msk               (0x1UL << RCC_APB2ENR_TIM9EN_Pos)  /*!< 0x00080000 */
1780 #define RCC_APB2ENR_TIM9EN                   RCC_APB2ENR_TIM9EN_Msk            /*!< TIM9 Timer clock enable  */
1781 #define RCC_APB2ENR_TIM10EN_Pos              (20U)
1782 #define RCC_APB2ENR_TIM10EN_Msk              (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00100000 */
1783 #define RCC_APB2ENR_TIM10EN                  RCC_APB2ENR_TIM10EN_Msk           /*!< TIM10 Timer clock enable  */
1784 #define RCC_APB2ENR_TIM11EN_Pos              (21U)
1785 #define RCC_APB2ENR_TIM11EN_Msk              (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00200000 */
1786 #define RCC_APB2ENR_TIM11EN                  RCC_APB2ENR_TIM11EN_Msk           /*!< TIM11 Timer clock enable */
1787 
1788 /*****************  Bit definition for RCC_APB1ENR register  ******************/
1789 #define RCC_APB1ENR_TIM2EN_Pos               (0U)
1790 #define RCC_APB1ENR_TIM2EN_Msk               (0x1UL << RCC_APB1ENR_TIM2EN_Pos)  /*!< 0x00000001 */
1791 #define RCC_APB1ENR_TIM2EN                   RCC_APB1ENR_TIM2EN_Msk            /*!< Timer 2 clock enabled*/
1792 #define RCC_APB1ENR_TIM3EN_Pos               (1U)
1793 #define RCC_APB1ENR_TIM3EN_Msk               (0x1UL << RCC_APB1ENR_TIM3EN_Pos)  /*!< 0x00000002 */
1794 #define RCC_APB1ENR_TIM3EN                   RCC_APB1ENR_TIM3EN_Msk            /*!< Timer 3 clock enable */
1795 #define RCC_APB1ENR_WWDGEN_Pos               (11U)
1796 #define RCC_APB1ENR_WWDGEN_Msk               (0x1UL << RCC_APB1ENR_WWDGEN_Pos)  /*!< 0x00000800 */
1797 #define RCC_APB1ENR_WWDGEN                   RCC_APB1ENR_WWDGEN_Msk            /*!< Window Watchdog clock enable */
1798 #define RCC_APB1ENR_USART2EN_Pos             (17U)
1799 #define RCC_APB1ENR_USART2EN_Msk             (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
1800 #define RCC_APB1ENR_USART2EN                 RCC_APB1ENR_USART2EN_Msk          /*!< USART 2 clock enable */
1801 #define RCC_APB1ENR_I2C1EN_Pos               (21U)
1802 #define RCC_APB1ENR_I2C1EN_Msk               (0x1UL << RCC_APB1ENR_I2C1EN_Pos)  /*!< 0x00200000 */
1803 #define RCC_APB1ENR_I2C1EN                   RCC_APB1ENR_I2C1EN_Msk            /*!< I2C 1 clock enable */
1804 
1805 #define RCC_APB1ENR_CAN1EN_Pos               (25U)
1806 #define RCC_APB1ENR_CAN1EN_Msk               (0x1UL << RCC_APB1ENR_CAN1EN_Pos)  /*!< 0x02000000 */
1807 #define RCC_APB1ENR_CAN1EN                   RCC_APB1ENR_CAN1EN_Msk            /*!< CAN1 clock enable */
1808 
1809 #define RCC_APB1ENR_BKPEN_Pos                (27U)
1810 #define RCC_APB1ENR_BKPEN_Msk                (0x1UL << RCC_APB1ENR_BKPEN_Pos)   /*!< 0x08000000 */
1811 #define RCC_APB1ENR_BKPEN                    RCC_APB1ENR_BKPEN_Msk             /*!< Backup interface clock enable */
1812 #define RCC_APB1ENR_PWREN_Pos                (28U)
1813 #define RCC_APB1ENR_PWREN_Msk                (0x1UL << RCC_APB1ENR_PWREN_Pos)   /*!< 0x10000000 */
1814 #define RCC_APB1ENR_PWREN                    RCC_APB1ENR_PWREN_Msk             /*!< Power interface clock enable */
1815 
1816 #define RCC_APB1ENR_TIM4EN_Pos               (2U)
1817 #define RCC_APB1ENR_TIM4EN_Msk               (0x1UL << RCC_APB1ENR_TIM4EN_Pos)  /*!< 0x00000004 */
1818 #define RCC_APB1ENR_TIM4EN                   RCC_APB1ENR_TIM4EN_Msk            /*!< Timer 4 clock enable */
1819 #define RCC_APB1ENR_SPI2EN_Pos               (14U)
1820 #define RCC_APB1ENR_SPI2EN_Msk               (0x1UL << RCC_APB1ENR_SPI2EN_Pos)  /*!< 0x00004000 */
1821 #define RCC_APB1ENR_SPI2EN                   RCC_APB1ENR_SPI2EN_Msk            /*!< SPI 2 clock enable */
1822 #define RCC_APB1ENR_USART3EN_Pos             (18U)
1823 #define RCC_APB1ENR_USART3EN_Msk             (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
1824 #define RCC_APB1ENR_USART3EN                 RCC_APB1ENR_USART3EN_Msk          /*!< USART 3 clock enable */
1825 #define RCC_APB1ENR_I2C2EN_Pos               (22U)
1826 #define RCC_APB1ENR_I2C2EN_Msk               (0x1UL << RCC_APB1ENR_I2C2EN_Pos)  /*!< 0x00400000 */
1827 #define RCC_APB1ENR_I2C2EN                   RCC_APB1ENR_I2C2EN_Msk            /*!< I2C 2 clock enable */
1828 
1829 #define RCC_APB1ENR_USBEN_Pos                (23U)
1830 #define RCC_APB1ENR_USBEN_Msk                (0x1UL << RCC_APB1ENR_USBEN_Pos)   /*!< 0x00800000 */
1831 #define RCC_APB1ENR_USBEN                    RCC_APB1ENR_USBEN_Msk             /*!< USB Device clock enable */
1832 
1833 #define RCC_APB1ENR_TIM5EN_Pos               (3U)
1834 #define RCC_APB1ENR_TIM5EN_Msk               (0x1UL << RCC_APB1ENR_TIM5EN_Pos)  /*!< 0x00000008 */
1835 #define RCC_APB1ENR_TIM5EN                   RCC_APB1ENR_TIM5EN_Msk            /*!< Timer 5 clock enable */
1836 #define RCC_APB1ENR_TIM6EN_Pos               (4U)
1837 #define RCC_APB1ENR_TIM6EN_Msk               (0x1UL << RCC_APB1ENR_TIM6EN_Pos)  /*!< 0x00000010 */
1838 #define RCC_APB1ENR_TIM6EN                   RCC_APB1ENR_TIM6EN_Msk            /*!< Timer 6 clock enable */
1839 #define RCC_APB1ENR_TIM7EN_Pos               (5U)
1840 #define RCC_APB1ENR_TIM7EN_Msk               (0x1UL << RCC_APB1ENR_TIM7EN_Pos)  /*!< 0x00000020 */
1841 #define RCC_APB1ENR_TIM7EN                   RCC_APB1ENR_TIM7EN_Msk            /*!< Timer 7 clock enable */
1842 #define RCC_APB1ENR_SPI3EN_Pos               (15U)
1843 #define RCC_APB1ENR_SPI3EN_Msk               (0x1UL << RCC_APB1ENR_SPI3EN_Pos)  /*!< 0x00008000 */
1844 #define RCC_APB1ENR_SPI3EN                   RCC_APB1ENR_SPI3EN_Msk            /*!< SPI 3 clock enable */
1845 #define RCC_APB1ENR_UART4EN_Pos              (19U)
1846 #define RCC_APB1ENR_UART4EN_Msk              (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
1847 #define RCC_APB1ENR_UART4EN                  RCC_APB1ENR_UART4EN_Msk           /*!< UART 4 clock enable */
1848 #define RCC_APB1ENR_UART5EN_Pos              (20U)
1849 #define RCC_APB1ENR_UART5EN_Msk              (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
1850 #define RCC_APB1ENR_UART5EN                  RCC_APB1ENR_UART5EN_Msk           /*!< UART 5 clock enable */
1851 
1852 
1853 
1854 
1855 #define RCC_APB1ENR_TIM12EN_Pos              (6U)
1856 #define RCC_APB1ENR_TIM12EN_Msk              (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
1857 #define RCC_APB1ENR_TIM12EN                  RCC_APB1ENR_TIM12EN_Msk           /*!< TIM12 Timer clock enable  */
1858 #define RCC_APB1ENR_TIM13EN_Pos              (7U)
1859 #define RCC_APB1ENR_TIM13EN_Msk              (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
1860 #define RCC_APB1ENR_TIM13EN                  RCC_APB1ENR_TIM13EN_Msk           /*!< TIM13 Timer clock enable  */
1861 #define RCC_APB1ENR_TIM14EN_Pos              (8U)
1862 #define RCC_APB1ENR_TIM14EN_Msk              (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
1863 #define RCC_APB1ENR_TIM14EN                  RCC_APB1ENR_TIM14EN_Msk           /*!< TIM14 Timer clock enable */
1864 #define RCC_APB1ENR_DACEN_Pos                (29U)
1865 #define RCC_APB1ENR_DACEN_Msk                (0x1UL << RCC_APB1ENR_DACEN_Pos)   /*!< 0x20000000 */
1866 #define RCC_APB1ENR_DACEN                    RCC_APB1ENR_DACEN_Msk             /*!< DAC interface clock enable */
1867 
1868 /*******************  Bit definition for RCC_BDCR register  *******************/
1869 #define RCC_BDCR_LSEON_Pos                   (0U)
1870 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
1871 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                /*!< External Low Speed oscillator enable */
1872 #define RCC_BDCR_LSERDY_Pos                  (1U)
1873 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
1874 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               /*!< External Low Speed oscillator Ready */
1875 #define RCC_BDCR_LSEBYP_Pos                  (2U)
1876 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
1877 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               /*!< External Low Speed oscillator Bypass */
1878 
1879 #define RCC_BDCR_RTCSEL_Pos                  (8U)
1880 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
1881 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1882 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
1883 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
1884 
1885 /*!< RTC configuration */
1886 #define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */
1887 #define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */
1888 #define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */
1889 #define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */
1890 
1891 #define RCC_BDCR_RTCEN_Pos                   (15U)
1892 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
1893 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                /*!< RTC clock enable */
1894 #define RCC_BDCR_BDRST_Pos                   (16U)
1895 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
1896 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                /*!< Backup domain software reset  */
1897 
1898 /*******************  Bit definition for RCC_CSR register  ********************/
1899 #define RCC_CSR_LSION_Pos                    (0U)
1900 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
1901 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 /*!< Internal Low Speed oscillator enable */
1902 #define RCC_CSR_LSIRDY_Pos                   (1U)
1903 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
1904 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                /*!< Internal Low Speed oscillator Ready */
1905 #define RCC_CSR_RMVF_Pos                     (24U)
1906 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x01000000 */
1907 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  /*!< Remove reset flag */
1908 #define RCC_CSR_PINRSTF_Pos                  (26U)
1909 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
1910 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               /*!< PIN reset flag */
1911 #define RCC_CSR_PORRSTF_Pos                  (27U)
1912 #define RCC_CSR_PORRSTF_Msk                  (0x1UL << RCC_CSR_PORRSTF_Pos)     /*!< 0x08000000 */
1913 #define RCC_CSR_PORRSTF                      RCC_CSR_PORRSTF_Msk               /*!< POR/PDR reset flag */
1914 #define RCC_CSR_SFTRSTF_Pos                  (28U)
1915 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
1916 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               /*!< Software Reset flag */
1917 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
1918 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
1919 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              /*!< Independent Watchdog reset flag */
1920 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
1921 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
1922 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              /*!< Window watchdog reset flag */
1923 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
1924 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
1925 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              /*!< Low-Power reset flag */
1926 
1927 
1928 
1929 /******************************************************************************/
1930 /*                                                                            */
1931 /*                General Purpose and Alternate Function I/O                  */
1932 /*                                                                            */
1933 /******************************************************************************/
1934 
1935 /*******************  Bit definition for GPIO_CRL register  *******************/
1936 #define GPIO_CRL_MODE_Pos                    (0U)
1937 #define GPIO_CRL_MODE_Msk                    (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
1938 #define GPIO_CRL_MODE                        GPIO_CRL_MODE_Msk                 /*!< Port x mode bits */
1939 
1940 #define GPIO_CRL_MODE0_Pos                   (0U)
1941 #define GPIO_CRL_MODE0_Msk                   (0x3UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000003 */
1942 #define GPIO_CRL_MODE0                       GPIO_CRL_MODE0_Msk                /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1943 #define GPIO_CRL_MODE0_0                     (0x1UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000001 */
1944 #define GPIO_CRL_MODE0_1                     (0x2UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000002 */
1945 
1946 #define GPIO_CRL_MODE1_Pos                   (4U)
1947 #define GPIO_CRL_MODE1_Msk                   (0x3UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000030 */
1948 #define GPIO_CRL_MODE1                       GPIO_CRL_MODE1_Msk                /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1949 #define GPIO_CRL_MODE1_0                     (0x1UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000010 */
1950 #define GPIO_CRL_MODE1_1                     (0x2UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000020 */
1951 
1952 #define GPIO_CRL_MODE2_Pos                   (8U)
1953 #define GPIO_CRL_MODE2_Msk                   (0x3UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000300 */
1954 #define GPIO_CRL_MODE2                       GPIO_CRL_MODE2_Msk                /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1955 #define GPIO_CRL_MODE2_0                     (0x1UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000100 */
1956 #define GPIO_CRL_MODE2_1                     (0x2UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000200 */
1957 
1958 #define GPIO_CRL_MODE3_Pos                   (12U)
1959 #define GPIO_CRL_MODE3_Msk                   (0x3UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00003000 */
1960 #define GPIO_CRL_MODE3                       GPIO_CRL_MODE3_Msk                /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1961 #define GPIO_CRL_MODE3_0                     (0x1UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00001000 */
1962 #define GPIO_CRL_MODE3_1                     (0x2UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00002000 */
1963 
1964 #define GPIO_CRL_MODE4_Pos                   (16U)
1965 #define GPIO_CRL_MODE4_Msk                   (0x3UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00030000 */
1966 #define GPIO_CRL_MODE4                       GPIO_CRL_MODE4_Msk                /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1967 #define GPIO_CRL_MODE4_0                     (0x1UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00010000 */
1968 #define GPIO_CRL_MODE4_1                     (0x2UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00020000 */
1969 
1970 #define GPIO_CRL_MODE5_Pos                   (20U)
1971 #define GPIO_CRL_MODE5_Msk                   (0x3UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00300000 */
1972 #define GPIO_CRL_MODE5                       GPIO_CRL_MODE5_Msk                /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1973 #define GPIO_CRL_MODE5_0                     (0x1UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00100000 */
1974 #define GPIO_CRL_MODE5_1                     (0x2UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00200000 */
1975 
1976 #define GPIO_CRL_MODE6_Pos                   (24U)
1977 #define GPIO_CRL_MODE6_Msk                   (0x3UL << GPIO_CRL_MODE6_Pos)      /*!< 0x03000000 */
1978 #define GPIO_CRL_MODE6                       GPIO_CRL_MODE6_Msk                /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1979 #define GPIO_CRL_MODE6_0                     (0x1UL << GPIO_CRL_MODE6_Pos)      /*!< 0x01000000 */
1980 #define GPIO_CRL_MODE6_1                     (0x2UL << GPIO_CRL_MODE6_Pos)      /*!< 0x02000000 */
1981 
1982 #define GPIO_CRL_MODE7_Pos                   (28U)
1983 #define GPIO_CRL_MODE7_Msk                   (0x3UL << GPIO_CRL_MODE7_Pos)      /*!< 0x30000000 */
1984 #define GPIO_CRL_MODE7                       GPIO_CRL_MODE7_Msk                /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1985 #define GPIO_CRL_MODE7_0                     (0x1UL << GPIO_CRL_MODE7_Pos)      /*!< 0x10000000 */
1986 #define GPIO_CRL_MODE7_1                     (0x2UL << GPIO_CRL_MODE7_Pos)      /*!< 0x20000000 */
1987 
1988 #define GPIO_CRL_CNF_Pos                     (2U)
1989 #define GPIO_CRL_CNF_Msk                     (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
1990 #define GPIO_CRL_CNF                         GPIO_CRL_CNF_Msk                  /*!< Port x configuration bits */
1991 
1992 #define GPIO_CRL_CNF0_Pos                    (2U)
1993 #define GPIO_CRL_CNF0_Msk                    (0x3UL << GPIO_CRL_CNF0_Pos)       /*!< 0x0000000C */
1994 #define GPIO_CRL_CNF0                        GPIO_CRL_CNF0_Msk                 /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1995 #define GPIO_CRL_CNF0_0                      (0x1UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000004 */
1996 #define GPIO_CRL_CNF0_1                      (0x2UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000008 */
1997 
1998 #define GPIO_CRL_CNF1_Pos                    (6U)
1999 #define GPIO_CRL_CNF1_Msk                    (0x3UL << GPIO_CRL_CNF1_Pos)       /*!< 0x000000C0 */
2000 #define GPIO_CRL_CNF1                        GPIO_CRL_CNF1_Msk                 /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
2001 #define GPIO_CRL_CNF1_0                      (0x1UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000040 */
2002 #define GPIO_CRL_CNF1_1                      (0x2UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000080 */
2003 
2004 #define GPIO_CRL_CNF2_Pos                    (10U)
2005 #define GPIO_CRL_CNF2_Msk                    (0x3UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000C00 */
2006 #define GPIO_CRL_CNF2                        GPIO_CRL_CNF2_Msk                 /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
2007 #define GPIO_CRL_CNF2_0                      (0x1UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000400 */
2008 #define GPIO_CRL_CNF2_1                      (0x2UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000800 */
2009 
2010 #define GPIO_CRL_CNF3_Pos                    (14U)
2011 #define GPIO_CRL_CNF3_Msk                    (0x3UL << GPIO_CRL_CNF3_Pos)       /*!< 0x0000C000 */
2012 #define GPIO_CRL_CNF3                        GPIO_CRL_CNF3_Msk                 /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
2013 #define GPIO_CRL_CNF3_0                      (0x1UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00004000 */
2014 #define GPIO_CRL_CNF3_1                      (0x2UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00008000 */
2015 
2016 #define GPIO_CRL_CNF4_Pos                    (18U)
2017 #define GPIO_CRL_CNF4_Msk                    (0x3UL << GPIO_CRL_CNF4_Pos)       /*!< 0x000C0000 */
2018 #define GPIO_CRL_CNF4                        GPIO_CRL_CNF4_Msk                 /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
2019 #define GPIO_CRL_CNF4_0                      (0x1UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00040000 */
2020 #define GPIO_CRL_CNF4_1                      (0x2UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00080000 */
2021 
2022 #define GPIO_CRL_CNF5_Pos                    (22U)
2023 #define GPIO_CRL_CNF5_Msk                    (0x3UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00C00000 */
2024 #define GPIO_CRL_CNF5                        GPIO_CRL_CNF5_Msk                 /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
2025 #define GPIO_CRL_CNF5_0                      (0x1UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00400000 */
2026 #define GPIO_CRL_CNF5_1                      (0x2UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00800000 */
2027 
2028 #define GPIO_CRL_CNF6_Pos                    (26U)
2029 #define GPIO_CRL_CNF6_Msk                    (0x3UL << GPIO_CRL_CNF6_Pos)       /*!< 0x0C000000 */
2030 #define GPIO_CRL_CNF6                        GPIO_CRL_CNF6_Msk                 /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
2031 #define GPIO_CRL_CNF6_0                      (0x1UL << GPIO_CRL_CNF6_Pos)       /*!< 0x04000000 */
2032 #define GPIO_CRL_CNF6_1                      (0x2UL << GPIO_CRL_CNF6_Pos)       /*!< 0x08000000 */
2033 
2034 #define GPIO_CRL_CNF7_Pos                    (30U)
2035 #define GPIO_CRL_CNF7_Msk                    (0x3UL << GPIO_CRL_CNF7_Pos)       /*!< 0xC0000000 */
2036 #define GPIO_CRL_CNF7                        GPIO_CRL_CNF7_Msk                 /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
2037 #define GPIO_CRL_CNF7_0                      (0x1UL << GPIO_CRL_CNF7_Pos)       /*!< 0x40000000 */
2038 #define GPIO_CRL_CNF7_1                      (0x2UL << GPIO_CRL_CNF7_Pos)       /*!< 0x80000000 */
2039 
2040 /*******************  Bit definition for GPIO_CRH register  *******************/
2041 #define GPIO_CRH_MODE_Pos                    (0U)
2042 #define GPIO_CRH_MODE_Msk                    (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
2043 #define GPIO_CRH_MODE                        GPIO_CRH_MODE_Msk                 /*!< Port x mode bits */
2044 
2045 #define GPIO_CRH_MODE8_Pos                   (0U)
2046 #define GPIO_CRH_MODE8_Msk                   (0x3UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000003 */
2047 #define GPIO_CRH_MODE8                       GPIO_CRH_MODE8_Msk                /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
2048 #define GPIO_CRH_MODE8_0                     (0x1UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000001 */
2049 #define GPIO_CRH_MODE8_1                     (0x2UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000002 */
2050 
2051 #define GPIO_CRH_MODE9_Pos                   (4U)
2052 #define GPIO_CRH_MODE9_Msk                   (0x3UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000030 */
2053 #define GPIO_CRH_MODE9                       GPIO_CRH_MODE9_Msk                /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
2054 #define GPIO_CRH_MODE9_0                     (0x1UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000010 */
2055 #define GPIO_CRH_MODE9_1                     (0x2UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000020 */
2056 
2057 #define GPIO_CRH_MODE10_Pos                  (8U)
2058 #define GPIO_CRH_MODE10_Msk                  (0x3UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000300 */
2059 #define GPIO_CRH_MODE10                      GPIO_CRH_MODE10_Msk               /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
2060 #define GPIO_CRH_MODE10_0                    (0x1UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000100 */
2061 #define GPIO_CRH_MODE10_1                    (0x2UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000200 */
2062 
2063 #define GPIO_CRH_MODE11_Pos                  (12U)
2064 #define GPIO_CRH_MODE11_Msk                  (0x3UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00003000 */
2065 #define GPIO_CRH_MODE11                      GPIO_CRH_MODE11_Msk               /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
2066 #define GPIO_CRH_MODE11_0                    (0x1UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00001000 */
2067 #define GPIO_CRH_MODE11_1                    (0x2UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00002000 */
2068 
2069 #define GPIO_CRH_MODE12_Pos                  (16U)
2070 #define GPIO_CRH_MODE12_Msk                  (0x3UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00030000 */
2071 #define GPIO_CRH_MODE12                      GPIO_CRH_MODE12_Msk               /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
2072 #define GPIO_CRH_MODE12_0                    (0x1UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00010000 */
2073 #define GPIO_CRH_MODE12_1                    (0x2UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00020000 */
2074 
2075 #define GPIO_CRH_MODE13_Pos                  (20U)
2076 #define GPIO_CRH_MODE13_Msk                  (0x3UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00300000 */
2077 #define GPIO_CRH_MODE13                      GPIO_CRH_MODE13_Msk               /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
2078 #define GPIO_CRH_MODE13_0                    (0x1UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00100000 */
2079 #define GPIO_CRH_MODE13_1                    (0x2UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00200000 */
2080 
2081 #define GPIO_CRH_MODE14_Pos                  (24U)
2082 #define GPIO_CRH_MODE14_Msk                  (0x3UL << GPIO_CRH_MODE14_Pos)     /*!< 0x03000000 */
2083 #define GPIO_CRH_MODE14                      GPIO_CRH_MODE14_Msk               /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
2084 #define GPIO_CRH_MODE14_0                    (0x1UL << GPIO_CRH_MODE14_Pos)     /*!< 0x01000000 */
2085 #define GPIO_CRH_MODE14_1                    (0x2UL << GPIO_CRH_MODE14_Pos)     /*!< 0x02000000 */
2086 
2087 #define GPIO_CRH_MODE15_Pos                  (28U)
2088 #define GPIO_CRH_MODE15_Msk                  (0x3UL << GPIO_CRH_MODE15_Pos)     /*!< 0x30000000 */
2089 #define GPIO_CRH_MODE15                      GPIO_CRH_MODE15_Msk               /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
2090 #define GPIO_CRH_MODE15_0                    (0x1UL << GPIO_CRH_MODE15_Pos)     /*!< 0x10000000 */
2091 #define GPIO_CRH_MODE15_1                    (0x2UL << GPIO_CRH_MODE15_Pos)     /*!< 0x20000000 */
2092 
2093 #define GPIO_CRH_CNF_Pos                     (2U)
2094 #define GPIO_CRH_CNF_Msk                     (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
2095 #define GPIO_CRH_CNF                         GPIO_CRH_CNF_Msk                  /*!< Port x configuration bits */
2096 
2097 #define GPIO_CRH_CNF8_Pos                    (2U)
2098 #define GPIO_CRH_CNF8_Msk                    (0x3UL << GPIO_CRH_CNF8_Pos)       /*!< 0x0000000C */
2099 #define GPIO_CRH_CNF8                        GPIO_CRH_CNF8_Msk                 /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
2100 #define GPIO_CRH_CNF8_0                      (0x1UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000004 */
2101 #define GPIO_CRH_CNF8_1                      (0x2UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000008 */
2102 
2103 #define GPIO_CRH_CNF9_Pos                    (6U)
2104 #define GPIO_CRH_CNF9_Msk                    (0x3UL << GPIO_CRH_CNF9_Pos)       /*!< 0x000000C0 */
2105 #define GPIO_CRH_CNF9                        GPIO_CRH_CNF9_Msk                 /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
2106 #define GPIO_CRH_CNF9_0                      (0x1UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000040 */
2107 #define GPIO_CRH_CNF9_1                      (0x2UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000080 */
2108 
2109 #define GPIO_CRH_CNF10_Pos                   (10U)
2110 #define GPIO_CRH_CNF10_Msk                   (0x3UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000C00 */
2111 #define GPIO_CRH_CNF10                       GPIO_CRH_CNF10_Msk                /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
2112 #define GPIO_CRH_CNF10_0                     (0x1UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000400 */
2113 #define GPIO_CRH_CNF10_1                     (0x2UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000800 */
2114 
2115 #define GPIO_CRH_CNF11_Pos                   (14U)
2116 #define GPIO_CRH_CNF11_Msk                   (0x3UL << GPIO_CRH_CNF11_Pos)      /*!< 0x0000C000 */
2117 #define GPIO_CRH_CNF11                       GPIO_CRH_CNF11_Msk                /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
2118 #define GPIO_CRH_CNF11_0                     (0x1UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00004000 */
2119 #define GPIO_CRH_CNF11_1                     (0x2UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00008000 */
2120 
2121 #define GPIO_CRH_CNF12_Pos                   (18U)
2122 #define GPIO_CRH_CNF12_Msk                   (0x3UL << GPIO_CRH_CNF12_Pos)      /*!< 0x000C0000 */
2123 #define GPIO_CRH_CNF12                       GPIO_CRH_CNF12_Msk                /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
2124 #define GPIO_CRH_CNF12_0                     (0x1UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00040000 */
2125 #define GPIO_CRH_CNF12_1                     (0x2UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00080000 */
2126 
2127 #define GPIO_CRH_CNF13_Pos                   (22U)
2128 #define GPIO_CRH_CNF13_Msk                   (0x3UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00C00000 */
2129 #define GPIO_CRH_CNF13                       GPIO_CRH_CNF13_Msk                /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
2130 #define GPIO_CRH_CNF13_0                     (0x1UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00400000 */
2131 #define GPIO_CRH_CNF13_1                     (0x2UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00800000 */
2132 
2133 #define GPIO_CRH_CNF14_Pos                   (26U)
2134 #define GPIO_CRH_CNF14_Msk                   (0x3UL << GPIO_CRH_CNF14_Pos)      /*!< 0x0C000000 */
2135 #define GPIO_CRH_CNF14                       GPIO_CRH_CNF14_Msk                /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
2136 #define GPIO_CRH_CNF14_0                     (0x1UL << GPIO_CRH_CNF14_Pos)      /*!< 0x04000000 */
2137 #define GPIO_CRH_CNF14_1                     (0x2UL << GPIO_CRH_CNF14_Pos)      /*!< 0x08000000 */
2138 
2139 #define GPIO_CRH_CNF15_Pos                   (30U)
2140 #define GPIO_CRH_CNF15_Msk                   (0x3UL << GPIO_CRH_CNF15_Pos)      /*!< 0xC0000000 */
2141 #define GPIO_CRH_CNF15                       GPIO_CRH_CNF15_Msk                /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
2142 #define GPIO_CRH_CNF15_0                     (0x1UL << GPIO_CRH_CNF15_Pos)      /*!< 0x40000000 */
2143 #define GPIO_CRH_CNF15_1                     (0x2UL << GPIO_CRH_CNF15_Pos)      /*!< 0x80000000 */
2144 
2145 /*!<******************  Bit definition for GPIO_IDR register  *******************/
2146 #define GPIO_IDR_IDR0_Pos                    (0U)
2147 #define GPIO_IDR_IDR0_Msk                    (0x1UL << GPIO_IDR_IDR0_Pos)       /*!< 0x00000001 */
2148 #define GPIO_IDR_IDR0                        GPIO_IDR_IDR0_Msk                 /*!< Port input data, bit 0 */
2149 #define GPIO_IDR_IDR1_Pos                    (1U)
2150 #define GPIO_IDR_IDR1_Msk                    (0x1UL << GPIO_IDR_IDR1_Pos)       /*!< 0x00000002 */
2151 #define GPIO_IDR_IDR1                        GPIO_IDR_IDR1_Msk                 /*!< Port input data, bit 1 */
2152 #define GPIO_IDR_IDR2_Pos                    (2U)
2153 #define GPIO_IDR_IDR2_Msk                    (0x1UL << GPIO_IDR_IDR2_Pos)       /*!< 0x00000004 */
2154 #define GPIO_IDR_IDR2                        GPIO_IDR_IDR2_Msk                 /*!< Port input data, bit 2 */
2155 #define GPIO_IDR_IDR3_Pos                    (3U)
2156 #define GPIO_IDR_IDR3_Msk                    (0x1UL << GPIO_IDR_IDR3_Pos)       /*!< 0x00000008 */
2157 #define GPIO_IDR_IDR3                        GPIO_IDR_IDR3_Msk                 /*!< Port input data, bit 3 */
2158 #define GPIO_IDR_IDR4_Pos                    (4U)
2159 #define GPIO_IDR_IDR4_Msk                    (0x1UL << GPIO_IDR_IDR4_Pos)       /*!< 0x00000010 */
2160 #define GPIO_IDR_IDR4                        GPIO_IDR_IDR4_Msk                 /*!< Port input data, bit 4 */
2161 #define GPIO_IDR_IDR5_Pos                    (5U)
2162 #define GPIO_IDR_IDR5_Msk                    (0x1UL << GPIO_IDR_IDR5_Pos)       /*!< 0x00000020 */
2163 #define GPIO_IDR_IDR5                        GPIO_IDR_IDR5_Msk                 /*!< Port input data, bit 5 */
2164 #define GPIO_IDR_IDR6_Pos                    (6U)
2165 #define GPIO_IDR_IDR6_Msk                    (0x1UL << GPIO_IDR_IDR6_Pos)       /*!< 0x00000040 */
2166 #define GPIO_IDR_IDR6                        GPIO_IDR_IDR6_Msk                 /*!< Port input data, bit 6 */
2167 #define GPIO_IDR_IDR7_Pos                    (7U)
2168 #define GPIO_IDR_IDR7_Msk                    (0x1UL << GPIO_IDR_IDR7_Pos)       /*!< 0x00000080 */
2169 #define GPIO_IDR_IDR7                        GPIO_IDR_IDR7_Msk                 /*!< Port input data, bit 7 */
2170 #define GPIO_IDR_IDR8_Pos                    (8U)
2171 #define GPIO_IDR_IDR8_Msk                    (0x1UL << GPIO_IDR_IDR8_Pos)       /*!< 0x00000100 */
2172 #define GPIO_IDR_IDR8                        GPIO_IDR_IDR8_Msk                 /*!< Port input data, bit 8 */
2173 #define GPIO_IDR_IDR9_Pos                    (9U)
2174 #define GPIO_IDR_IDR9_Msk                    (0x1UL << GPIO_IDR_IDR9_Pos)       /*!< 0x00000200 */
2175 #define GPIO_IDR_IDR9                        GPIO_IDR_IDR9_Msk                 /*!< Port input data, bit 9 */
2176 #define GPIO_IDR_IDR10_Pos                   (10U)
2177 #define GPIO_IDR_IDR10_Msk                   (0x1UL << GPIO_IDR_IDR10_Pos)      /*!< 0x00000400 */
2178 #define GPIO_IDR_IDR10                       GPIO_IDR_IDR10_Msk                /*!< Port input data, bit 10 */
2179 #define GPIO_IDR_IDR11_Pos                   (11U)
2180 #define GPIO_IDR_IDR11_Msk                   (0x1UL << GPIO_IDR_IDR11_Pos)      /*!< 0x00000800 */
2181 #define GPIO_IDR_IDR11                       GPIO_IDR_IDR11_Msk                /*!< Port input data, bit 11 */
2182 #define GPIO_IDR_IDR12_Pos                   (12U)
2183 #define GPIO_IDR_IDR12_Msk                   (0x1UL << GPIO_IDR_IDR12_Pos)      /*!< 0x00001000 */
2184 #define GPIO_IDR_IDR12                       GPIO_IDR_IDR12_Msk                /*!< Port input data, bit 12 */
2185 #define GPIO_IDR_IDR13_Pos                   (13U)
2186 #define GPIO_IDR_IDR13_Msk                   (0x1UL << GPIO_IDR_IDR13_Pos)      /*!< 0x00002000 */
2187 #define GPIO_IDR_IDR13                       GPIO_IDR_IDR13_Msk                /*!< Port input data, bit 13 */
2188 #define GPIO_IDR_IDR14_Pos                   (14U)
2189 #define GPIO_IDR_IDR14_Msk                   (0x1UL << GPIO_IDR_IDR14_Pos)      /*!< 0x00004000 */
2190 #define GPIO_IDR_IDR14                       GPIO_IDR_IDR14_Msk                /*!< Port input data, bit 14 */
2191 #define GPIO_IDR_IDR15_Pos                   (15U)
2192 #define GPIO_IDR_IDR15_Msk                   (0x1UL << GPIO_IDR_IDR15_Pos)      /*!< 0x00008000 */
2193 #define GPIO_IDR_IDR15                       GPIO_IDR_IDR15_Msk                /*!< Port input data, bit 15 */
2194 
2195 /*******************  Bit definition for GPIO_ODR register  *******************/
2196 #define GPIO_ODR_ODR0_Pos                    (0U)
2197 #define GPIO_ODR_ODR0_Msk                    (0x1UL << GPIO_ODR_ODR0_Pos)       /*!< 0x00000001 */
2198 #define GPIO_ODR_ODR0                        GPIO_ODR_ODR0_Msk                 /*!< Port output data, bit 0 */
2199 #define GPIO_ODR_ODR1_Pos                    (1U)
2200 #define GPIO_ODR_ODR1_Msk                    (0x1UL << GPIO_ODR_ODR1_Pos)       /*!< 0x00000002 */
2201 #define GPIO_ODR_ODR1                        GPIO_ODR_ODR1_Msk                 /*!< Port output data, bit 1 */
2202 #define GPIO_ODR_ODR2_Pos                    (2U)
2203 #define GPIO_ODR_ODR2_Msk                    (0x1UL << GPIO_ODR_ODR2_Pos)       /*!< 0x00000004 */
2204 #define GPIO_ODR_ODR2                        GPIO_ODR_ODR2_Msk                 /*!< Port output data, bit 2 */
2205 #define GPIO_ODR_ODR3_Pos                    (3U)
2206 #define GPIO_ODR_ODR3_Msk                    (0x1UL << GPIO_ODR_ODR3_Pos)       /*!< 0x00000008 */
2207 #define GPIO_ODR_ODR3                        GPIO_ODR_ODR3_Msk                 /*!< Port output data, bit 3 */
2208 #define GPIO_ODR_ODR4_Pos                    (4U)
2209 #define GPIO_ODR_ODR4_Msk                    (0x1UL << GPIO_ODR_ODR4_Pos)       /*!< 0x00000010 */
2210 #define GPIO_ODR_ODR4                        GPIO_ODR_ODR4_Msk                 /*!< Port output data, bit 4 */
2211 #define GPIO_ODR_ODR5_Pos                    (5U)
2212 #define GPIO_ODR_ODR5_Msk                    (0x1UL << GPIO_ODR_ODR5_Pos)       /*!< 0x00000020 */
2213 #define GPIO_ODR_ODR5                        GPIO_ODR_ODR5_Msk                 /*!< Port output data, bit 5 */
2214 #define GPIO_ODR_ODR6_Pos                    (6U)
2215 #define GPIO_ODR_ODR6_Msk                    (0x1UL << GPIO_ODR_ODR6_Pos)       /*!< 0x00000040 */
2216 #define GPIO_ODR_ODR6                        GPIO_ODR_ODR6_Msk                 /*!< Port output data, bit 6 */
2217 #define GPIO_ODR_ODR7_Pos                    (7U)
2218 #define GPIO_ODR_ODR7_Msk                    (0x1UL << GPIO_ODR_ODR7_Pos)       /*!< 0x00000080 */
2219 #define GPIO_ODR_ODR7                        GPIO_ODR_ODR7_Msk                 /*!< Port output data, bit 7 */
2220 #define GPIO_ODR_ODR8_Pos                    (8U)
2221 #define GPIO_ODR_ODR8_Msk                    (0x1UL << GPIO_ODR_ODR8_Pos)       /*!< 0x00000100 */
2222 #define GPIO_ODR_ODR8                        GPIO_ODR_ODR8_Msk                 /*!< Port output data, bit 8 */
2223 #define GPIO_ODR_ODR9_Pos                    (9U)
2224 #define GPIO_ODR_ODR9_Msk                    (0x1UL << GPIO_ODR_ODR9_Pos)       /*!< 0x00000200 */
2225 #define GPIO_ODR_ODR9                        GPIO_ODR_ODR9_Msk                 /*!< Port output data, bit 9 */
2226 #define GPIO_ODR_ODR10_Pos                   (10U)
2227 #define GPIO_ODR_ODR10_Msk                   (0x1UL << GPIO_ODR_ODR10_Pos)      /*!< 0x00000400 */
2228 #define GPIO_ODR_ODR10                       GPIO_ODR_ODR10_Msk                /*!< Port output data, bit 10 */
2229 #define GPIO_ODR_ODR11_Pos                   (11U)
2230 #define GPIO_ODR_ODR11_Msk                   (0x1UL << GPIO_ODR_ODR11_Pos)      /*!< 0x00000800 */
2231 #define GPIO_ODR_ODR11                       GPIO_ODR_ODR11_Msk                /*!< Port output data, bit 11 */
2232 #define GPIO_ODR_ODR12_Pos                   (12U)
2233 #define GPIO_ODR_ODR12_Msk                   (0x1UL << GPIO_ODR_ODR12_Pos)      /*!< 0x00001000 */
2234 #define GPIO_ODR_ODR12                       GPIO_ODR_ODR12_Msk                /*!< Port output data, bit 12 */
2235 #define GPIO_ODR_ODR13_Pos                   (13U)
2236 #define GPIO_ODR_ODR13_Msk                   (0x1UL << GPIO_ODR_ODR13_Pos)      /*!< 0x00002000 */
2237 #define GPIO_ODR_ODR13                       GPIO_ODR_ODR13_Msk                /*!< Port output data, bit 13 */
2238 #define GPIO_ODR_ODR14_Pos                   (14U)
2239 #define GPIO_ODR_ODR14_Msk                   (0x1UL << GPIO_ODR_ODR14_Pos)      /*!< 0x00004000 */
2240 #define GPIO_ODR_ODR14                       GPIO_ODR_ODR14_Msk                /*!< Port output data, bit 14 */
2241 #define GPIO_ODR_ODR15_Pos                   (15U)
2242 #define GPIO_ODR_ODR15_Msk                   (0x1UL << GPIO_ODR_ODR15_Pos)      /*!< 0x00008000 */
2243 #define GPIO_ODR_ODR15                       GPIO_ODR_ODR15_Msk                /*!< Port output data, bit 15 */
2244 
2245 /******************  Bit definition for GPIO_BSRR register  *******************/
2246 #define GPIO_BSRR_BS0_Pos                    (0U)
2247 #define GPIO_BSRR_BS0_Msk                    (0x1UL << GPIO_BSRR_BS0_Pos)       /*!< 0x00000001 */
2248 #define GPIO_BSRR_BS0                        GPIO_BSRR_BS0_Msk                 /*!< Port x Set bit 0 */
2249 #define GPIO_BSRR_BS1_Pos                    (1U)
2250 #define GPIO_BSRR_BS1_Msk                    (0x1UL << GPIO_BSRR_BS1_Pos)       /*!< 0x00000002 */
2251 #define GPIO_BSRR_BS1                        GPIO_BSRR_BS1_Msk                 /*!< Port x Set bit 1 */
2252 #define GPIO_BSRR_BS2_Pos                    (2U)
2253 #define GPIO_BSRR_BS2_Msk                    (0x1UL << GPIO_BSRR_BS2_Pos)       /*!< 0x00000004 */
2254 #define GPIO_BSRR_BS2                        GPIO_BSRR_BS2_Msk                 /*!< Port x Set bit 2 */
2255 #define GPIO_BSRR_BS3_Pos                    (3U)
2256 #define GPIO_BSRR_BS3_Msk                    (0x1UL << GPIO_BSRR_BS3_Pos)       /*!< 0x00000008 */
2257 #define GPIO_BSRR_BS3                        GPIO_BSRR_BS3_Msk                 /*!< Port x Set bit 3 */
2258 #define GPIO_BSRR_BS4_Pos                    (4U)
2259 #define GPIO_BSRR_BS4_Msk                    (0x1UL << GPIO_BSRR_BS4_Pos)       /*!< 0x00000010 */
2260 #define GPIO_BSRR_BS4                        GPIO_BSRR_BS4_Msk                 /*!< Port x Set bit 4 */
2261 #define GPIO_BSRR_BS5_Pos                    (5U)
2262 #define GPIO_BSRR_BS5_Msk                    (0x1UL << GPIO_BSRR_BS5_Pos)       /*!< 0x00000020 */
2263 #define GPIO_BSRR_BS5                        GPIO_BSRR_BS5_Msk                 /*!< Port x Set bit 5 */
2264 #define GPIO_BSRR_BS6_Pos                    (6U)
2265 #define GPIO_BSRR_BS6_Msk                    (0x1UL << GPIO_BSRR_BS6_Pos)       /*!< 0x00000040 */
2266 #define GPIO_BSRR_BS6                        GPIO_BSRR_BS6_Msk                 /*!< Port x Set bit 6 */
2267 #define GPIO_BSRR_BS7_Pos                    (7U)
2268 #define GPIO_BSRR_BS7_Msk                    (0x1UL << GPIO_BSRR_BS7_Pos)       /*!< 0x00000080 */
2269 #define GPIO_BSRR_BS7                        GPIO_BSRR_BS7_Msk                 /*!< Port x Set bit 7 */
2270 #define GPIO_BSRR_BS8_Pos                    (8U)
2271 #define GPIO_BSRR_BS8_Msk                    (0x1UL << GPIO_BSRR_BS8_Pos)       /*!< 0x00000100 */
2272 #define GPIO_BSRR_BS8                        GPIO_BSRR_BS8_Msk                 /*!< Port x Set bit 8 */
2273 #define GPIO_BSRR_BS9_Pos                    (9U)
2274 #define GPIO_BSRR_BS9_Msk                    (0x1UL << GPIO_BSRR_BS9_Pos)       /*!< 0x00000200 */
2275 #define GPIO_BSRR_BS9                        GPIO_BSRR_BS9_Msk                 /*!< Port x Set bit 9 */
2276 #define GPIO_BSRR_BS10_Pos                   (10U)
2277 #define GPIO_BSRR_BS10_Msk                   (0x1UL << GPIO_BSRR_BS10_Pos)      /*!< 0x00000400 */
2278 #define GPIO_BSRR_BS10                       GPIO_BSRR_BS10_Msk                /*!< Port x Set bit 10 */
2279 #define GPIO_BSRR_BS11_Pos                   (11U)
2280 #define GPIO_BSRR_BS11_Msk                   (0x1UL << GPIO_BSRR_BS11_Pos)      /*!< 0x00000800 */
2281 #define GPIO_BSRR_BS11                       GPIO_BSRR_BS11_Msk                /*!< Port x Set bit 11 */
2282 #define GPIO_BSRR_BS12_Pos                   (12U)
2283 #define GPIO_BSRR_BS12_Msk                   (0x1UL << GPIO_BSRR_BS12_Pos)      /*!< 0x00001000 */
2284 #define GPIO_BSRR_BS12                       GPIO_BSRR_BS12_Msk                /*!< Port x Set bit 12 */
2285 #define GPIO_BSRR_BS13_Pos                   (13U)
2286 #define GPIO_BSRR_BS13_Msk                   (0x1UL << GPIO_BSRR_BS13_Pos)      /*!< 0x00002000 */
2287 #define GPIO_BSRR_BS13                       GPIO_BSRR_BS13_Msk                /*!< Port x Set bit 13 */
2288 #define GPIO_BSRR_BS14_Pos                   (14U)
2289 #define GPIO_BSRR_BS14_Msk                   (0x1UL << GPIO_BSRR_BS14_Pos)      /*!< 0x00004000 */
2290 #define GPIO_BSRR_BS14                       GPIO_BSRR_BS14_Msk                /*!< Port x Set bit 14 */
2291 #define GPIO_BSRR_BS15_Pos                   (15U)
2292 #define GPIO_BSRR_BS15_Msk                   (0x1UL << GPIO_BSRR_BS15_Pos)      /*!< 0x00008000 */
2293 #define GPIO_BSRR_BS15                       GPIO_BSRR_BS15_Msk                /*!< Port x Set bit 15 */
2294 
2295 #define GPIO_BSRR_BR0_Pos                    (16U)
2296 #define GPIO_BSRR_BR0_Msk                    (0x1UL << GPIO_BSRR_BR0_Pos)       /*!< 0x00010000 */
2297 #define GPIO_BSRR_BR0                        GPIO_BSRR_BR0_Msk                 /*!< Port x Reset bit 0 */
2298 #define GPIO_BSRR_BR1_Pos                    (17U)
2299 #define GPIO_BSRR_BR1_Msk                    (0x1UL << GPIO_BSRR_BR1_Pos)       /*!< 0x00020000 */
2300 #define GPIO_BSRR_BR1                        GPIO_BSRR_BR1_Msk                 /*!< Port x Reset bit 1 */
2301 #define GPIO_BSRR_BR2_Pos                    (18U)
2302 #define GPIO_BSRR_BR2_Msk                    (0x1UL << GPIO_BSRR_BR2_Pos)       /*!< 0x00040000 */
2303 #define GPIO_BSRR_BR2                        GPIO_BSRR_BR2_Msk                 /*!< Port x Reset bit 2 */
2304 #define GPIO_BSRR_BR3_Pos                    (19U)
2305 #define GPIO_BSRR_BR3_Msk                    (0x1UL << GPIO_BSRR_BR3_Pos)       /*!< 0x00080000 */
2306 #define GPIO_BSRR_BR3                        GPIO_BSRR_BR3_Msk                 /*!< Port x Reset bit 3 */
2307 #define GPIO_BSRR_BR4_Pos                    (20U)
2308 #define GPIO_BSRR_BR4_Msk                    (0x1UL << GPIO_BSRR_BR4_Pos)       /*!< 0x00100000 */
2309 #define GPIO_BSRR_BR4                        GPIO_BSRR_BR4_Msk                 /*!< Port x Reset bit 4 */
2310 #define GPIO_BSRR_BR5_Pos                    (21U)
2311 #define GPIO_BSRR_BR5_Msk                    (0x1UL << GPIO_BSRR_BR5_Pos)       /*!< 0x00200000 */
2312 #define GPIO_BSRR_BR5                        GPIO_BSRR_BR5_Msk                 /*!< Port x Reset bit 5 */
2313 #define GPIO_BSRR_BR6_Pos                    (22U)
2314 #define GPIO_BSRR_BR6_Msk                    (0x1UL << GPIO_BSRR_BR6_Pos)       /*!< 0x00400000 */
2315 #define GPIO_BSRR_BR6                        GPIO_BSRR_BR6_Msk                 /*!< Port x Reset bit 6 */
2316 #define GPIO_BSRR_BR7_Pos                    (23U)
2317 #define GPIO_BSRR_BR7_Msk                    (0x1UL << GPIO_BSRR_BR7_Pos)       /*!< 0x00800000 */
2318 #define GPIO_BSRR_BR7                        GPIO_BSRR_BR7_Msk                 /*!< Port x Reset bit 7 */
2319 #define GPIO_BSRR_BR8_Pos                    (24U)
2320 #define GPIO_BSRR_BR8_Msk                    (0x1UL << GPIO_BSRR_BR8_Pos)       /*!< 0x01000000 */
2321 #define GPIO_BSRR_BR8                        GPIO_BSRR_BR8_Msk                 /*!< Port x Reset bit 8 */
2322 #define GPIO_BSRR_BR9_Pos                    (25U)
2323 #define GPIO_BSRR_BR9_Msk                    (0x1UL << GPIO_BSRR_BR9_Pos)       /*!< 0x02000000 */
2324 #define GPIO_BSRR_BR9                        GPIO_BSRR_BR9_Msk                 /*!< Port x Reset bit 9 */
2325 #define GPIO_BSRR_BR10_Pos                   (26U)
2326 #define GPIO_BSRR_BR10_Msk                   (0x1UL << GPIO_BSRR_BR10_Pos)      /*!< 0x04000000 */
2327 #define GPIO_BSRR_BR10                       GPIO_BSRR_BR10_Msk                /*!< Port x Reset bit 10 */
2328 #define GPIO_BSRR_BR11_Pos                   (27U)
2329 #define GPIO_BSRR_BR11_Msk                   (0x1UL << GPIO_BSRR_BR11_Pos)      /*!< 0x08000000 */
2330 #define GPIO_BSRR_BR11                       GPIO_BSRR_BR11_Msk                /*!< Port x Reset bit 11 */
2331 #define GPIO_BSRR_BR12_Pos                   (28U)
2332 #define GPIO_BSRR_BR12_Msk                   (0x1UL << GPIO_BSRR_BR12_Pos)      /*!< 0x10000000 */
2333 #define GPIO_BSRR_BR12                       GPIO_BSRR_BR12_Msk                /*!< Port x Reset bit 12 */
2334 #define GPIO_BSRR_BR13_Pos                   (29U)
2335 #define GPIO_BSRR_BR13_Msk                   (0x1UL << GPIO_BSRR_BR13_Pos)      /*!< 0x20000000 */
2336 #define GPIO_BSRR_BR13                       GPIO_BSRR_BR13_Msk                /*!< Port x Reset bit 13 */
2337 #define GPIO_BSRR_BR14_Pos                   (30U)
2338 #define GPIO_BSRR_BR14_Msk                   (0x1UL << GPIO_BSRR_BR14_Pos)      /*!< 0x40000000 */
2339 #define GPIO_BSRR_BR14                       GPIO_BSRR_BR14_Msk                /*!< Port x Reset bit 14 */
2340 #define GPIO_BSRR_BR15_Pos                   (31U)
2341 #define GPIO_BSRR_BR15_Msk                   (0x1UL << GPIO_BSRR_BR15_Pos)      /*!< 0x80000000 */
2342 #define GPIO_BSRR_BR15                       GPIO_BSRR_BR15_Msk                /*!< Port x Reset bit 15 */
2343 
2344 /*******************  Bit definition for GPIO_BRR register  *******************/
2345 #define GPIO_BRR_BR0_Pos                     (0U)
2346 #define GPIO_BRR_BR0_Msk                     (0x1UL << GPIO_BRR_BR0_Pos)        /*!< 0x00000001 */
2347 #define GPIO_BRR_BR0                         GPIO_BRR_BR0_Msk                  /*!< Port x Reset bit 0 */
2348 #define GPIO_BRR_BR1_Pos                     (1U)
2349 #define GPIO_BRR_BR1_Msk                     (0x1UL << GPIO_BRR_BR1_Pos)        /*!< 0x00000002 */
2350 #define GPIO_BRR_BR1                         GPIO_BRR_BR1_Msk                  /*!< Port x Reset bit 1 */
2351 #define GPIO_BRR_BR2_Pos                     (2U)
2352 #define GPIO_BRR_BR2_Msk                     (0x1UL << GPIO_BRR_BR2_Pos)        /*!< 0x00000004 */
2353 #define GPIO_BRR_BR2                         GPIO_BRR_BR2_Msk                  /*!< Port x Reset bit 2 */
2354 #define GPIO_BRR_BR3_Pos                     (3U)
2355 #define GPIO_BRR_BR3_Msk                     (0x1UL << GPIO_BRR_BR3_Pos)        /*!< 0x00000008 */
2356 #define GPIO_BRR_BR3                         GPIO_BRR_BR3_Msk                  /*!< Port x Reset bit 3 */
2357 #define GPIO_BRR_BR4_Pos                     (4U)
2358 #define GPIO_BRR_BR4_Msk                     (0x1UL << GPIO_BRR_BR4_Pos)        /*!< 0x00000010 */
2359 #define GPIO_BRR_BR4                         GPIO_BRR_BR4_Msk                  /*!< Port x Reset bit 4 */
2360 #define GPIO_BRR_BR5_Pos                     (5U)
2361 #define GPIO_BRR_BR5_Msk                     (0x1UL << GPIO_BRR_BR5_Pos)        /*!< 0x00000020 */
2362 #define GPIO_BRR_BR5                         GPIO_BRR_BR5_Msk                  /*!< Port x Reset bit 5 */
2363 #define GPIO_BRR_BR6_Pos                     (6U)
2364 #define GPIO_BRR_BR6_Msk                     (0x1UL << GPIO_BRR_BR6_Pos)        /*!< 0x00000040 */
2365 #define GPIO_BRR_BR6                         GPIO_BRR_BR6_Msk                  /*!< Port x Reset bit 6 */
2366 #define GPIO_BRR_BR7_Pos                     (7U)
2367 #define GPIO_BRR_BR7_Msk                     (0x1UL << GPIO_BRR_BR7_Pos)        /*!< 0x00000080 */
2368 #define GPIO_BRR_BR7                         GPIO_BRR_BR7_Msk                  /*!< Port x Reset bit 7 */
2369 #define GPIO_BRR_BR8_Pos                     (8U)
2370 #define GPIO_BRR_BR8_Msk                     (0x1UL << GPIO_BRR_BR8_Pos)        /*!< 0x00000100 */
2371 #define GPIO_BRR_BR8                         GPIO_BRR_BR8_Msk                  /*!< Port x Reset bit 8 */
2372 #define GPIO_BRR_BR9_Pos                     (9U)
2373 #define GPIO_BRR_BR9_Msk                     (0x1UL << GPIO_BRR_BR9_Pos)        /*!< 0x00000200 */
2374 #define GPIO_BRR_BR9                         GPIO_BRR_BR9_Msk                  /*!< Port x Reset bit 9 */
2375 #define GPIO_BRR_BR10_Pos                    (10U)
2376 #define GPIO_BRR_BR10_Msk                    (0x1UL << GPIO_BRR_BR10_Pos)       /*!< 0x00000400 */
2377 #define GPIO_BRR_BR10                        GPIO_BRR_BR10_Msk                 /*!< Port x Reset bit 10 */
2378 #define GPIO_BRR_BR11_Pos                    (11U)
2379 #define GPIO_BRR_BR11_Msk                    (0x1UL << GPIO_BRR_BR11_Pos)       /*!< 0x00000800 */
2380 #define GPIO_BRR_BR11                        GPIO_BRR_BR11_Msk                 /*!< Port x Reset bit 11 */
2381 #define GPIO_BRR_BR12_Pos                    (12U)
2382 #define GPIO_BRR_BR12_Msk                    (0x1UL << GPIO_BRR_BR12_Pos)       /*!< 0x00001000 */
2383 #define GPIO_BRR_BR12                        GPIO_BRR_BR12_Msk                 /*!< Port x Reset bit 12 */
2384 #define GPIO_BRR_BR13_Pos                    (13U)
2385 #define GPIO_BRR_BR13_Msk                    (0x1UL << GPIO_BRR_BR13_Pos)       /*!< 0x00002000 */
2386 #define GPIO_BRR_BR13                        GPIO_BRR_BR13_Msk                 /*!< Port x Reset bit 13 */
2387 #define GPIO_BRR_BR14_Pos                    (14U)
2388 #define GPIO_BRR_BR14_Msk                    (0x1UL << GPIO_BRR_BR14_Pos)       /*!< 0x00004000 */
2389 #define GPIO_BRR_BR14                        GPIO_BRR_BR14_Msk                 /*!< Port x Reset bit 14 */
2390 #define GPIO_BRR_BR15_Pos                    (15U)
2391 #define GPIO_BRR_BR15_Msk                    (0x1UL << GPIO_BRR_BR15_Pos)       /*!< 0x00008000 */
2392 #define GPIO_BRR_BR15                        GPIO_BRR_BR15_Msk                 /*!< Port x Reset bit 15 */
2393 
2394 /******************  Bit definition for GPIO_LCKR register  *******************/
2395 #define GPIO_LCKR_LCK0_Pos                   (0U)
2396 #define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
2397 #define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                /*!< Port x Lock bit 0 */
2398 #define GPIO_LCKR_LCK1_Pos                   (1U)
2399 #define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
2400 #define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                /*!< Port x Lock bit 1 */
2401 #define GPIO_LCKR_LCK2_Pos                   (2U)
2402 #define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
2403 #define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                /*!< Port x Lock bit 2 */
2404 #define GPIO_LCKR_LCK3_Pos                   (3U)
2405 #define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
2406 #define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                /*!< Port x Lock bit 3 */
2407 #define GPIO_LCKR_LCK4_Pos                   (4U)
2408 #define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
2409 #define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                /*!< Port x Lock bit 4 */
2410 #define GPIO_LCKR_LCK5_Pos                   (5U)
2411 #define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
2412 #define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                /*!< Port x Lock bit 5 */
2413 #define GPIO_LCKR_LCK6_Pos                   (6U)
2414 #define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
2415 #define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                /*!< Port x Lock bit 6 */
2416 #define GPIO_LCKR_LCK7_Pos                   (7U)
2417 #define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
2418 #define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                /*!< Port x Lock bit 7 */
2419 #define GPIO_LCKR_LCK8_Pos                   (8U)
2420 #define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
2421 #define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                /*!< Port x Lock bit 8 */
2422 #define GPIO_LCKR_LCK9_Pos                   (9U)
2423 #define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
2424 #define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                /*!< Port x Lock bit 9 */
2425 #define GPIO_LCKR_LCK10_Pos                  (10U)
2426 #define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
2427 #define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               /*!< Port x Lock bit 10 */
2428 #define GPIO_LCKR_LCK11_Pos                  (11U)
2429 #define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
2430 #define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               /*!< Port x Lock bit 11 */
2431 #define GPIO_LCKR_LCK12_Pos                  (12U)
2432 #define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
2433 #define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               /*!< Port x Lock bit 12 */
2434 #define GPIO_LCKR_LCK13_Pos                  (13U)
2435 #define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
2436 #define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               /*!< Port x Lock bit 13 */
2437 #define GPIO_LCKR_LCK14_Pos                  (14U)
2438 #define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
2439 #define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               /*!< Port x Lock bit 14 */
2440 #define GPIO_LCKR_LCK15_Pos                  (15U)
2441 #define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
2442 #define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               /*!< Port x Lock bit 15 */
2443 #define GPIO_LCKR_LCKK_Pos                   (16U)
2444 #define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
2445 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                /*!< Lock key */
2446 
2447 /*----------------------------------------------------------------------------*/
2448 
2449 /******************  Bit definition for AFIO_EVCR register  *******************/
2450 #define AFIO_EVCR_PIN_Pos                    (0U)
2451 #define AFIO_EVCR_PIN_Msk                    (0xFUL << AFIO_EVCR_PIN_Pos)       /*!< 0x0000000F */
2452 #define AFIO_EVCR_PIN                        AFIO_EVCR_PIN_Msk                 /*!< PIN[3:0] bits (Pin selection) */
2453 #define AFIO_EVCR_PIN_0                      (0x1UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000001 */
2454 #define AFIO_EVCR_PIN_1                      (0x2UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000002 */
2455 #define AFIO_EVCR_PIN_2                      (0x4UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000004 */
2456 #define AFIO_EVCR_PIN_3                      (0x8UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */
2457 
2458 /*!< PIN configuration */
2459 #define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */
2460 #define AFIO_EVCR_PIN_PX1_Pos                (0U)
2461 #define AFIO_EVCR_PIN_PX1_Msk                (0x1UL << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */
2462 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */
2463 #define AFIO_EVCR_PIN_PX2_Pos                (1U)
2464 #define AFIO_EVCR_PIN_PX2_Msk                (0x1UL << AFIO_EVCR_PIN_PX2_Pos)   /*!< 0x00000002 */
2465 #define AFIO_EVCR_PIN_PX2                    AFIO_EVCR_PIN_PX2_Msk             /*!< Pin 2 selected */
2466 #define AFIO_EVCR_PIN_PX3_Pos                (0U)
2467 #define AFIO_EVCR_PIN_PX3_Msk                (0x3UL << AFIO_EVCR_PIN_PX3_Pos)   /*!< 0x00000003 */
2468 #define AFIO_EVCR_PIN_PX3                    AFIO_EVCR_PIN_PX3_Msk             /*!< Pin 3 selected */
2469 #define AFIO_EVCR_PIN_PX4_Pos                (2U)
2470 #define AFIO_EVCR_PIN_PX4_Msk                (0x1UL << AFIO_EVCR_PIN_PX4_Pos)   /*!< 0x00000004 */
2471 #define AFIO_EVCR_PIN_PX4                    AFIO_EVCR_PIN_PX4_Msk             /*!< Pin 4 selected */
2472 #define AFIO_EVCR_PIN_PX5_Pos                (0U)
2473 #define AFIO_EVCR_PIN_PX5_Msk                (0x5UL << AFIO_EVCR_PIN_PX5_Pos)   /*!< 0x00000005 */
2474 #define AFIO_EVCR_PIN_PX5                    AFIO_EVCR_PIN_PX5_Msk             /*!< Pin 5 selected */
2475 #define AFIO_EVCR_PIN_PX6_Pos                (1U)
2476 #define AFIO_EVCR_PIN_PX6_Msk                (0x3UL << AFIO_EVCR_PIN_PX6_Pos)   /*!< 0x00000006 */
2477 #define AFIO_EVCR_PIN_PX6                    AFIO_EVCR_PIN_PX6_Msk             /*!< Pin 6 selected */
2478 #define AFIO_EVCR_PIN_PX7_Pos                (0U)
2479 #define AFIO_EVCR_PIN_PX7_Msk                (0x7UL << AFIO_EVCR_PIN_PX7_Pos)   /*!< 0x00000007 */
2480 #define AFIO_EVCR_PIN_PX7                    AFIO_EVCR_PIN_PX7_Msk             /*!< Pin 7 selected */
2481 #define AFIO_EVCR_PIN_PX8_Pos                (3U)
2482 #define AFIO_EVCR_PIN_PX8_Msk                (0x1UL << AFIO_EVCR_PIN_PX8_Pos)   /*!< 0x00000008 */
2483 #define AFIO_EVCR_PIN_PX8                    AFIO_EVCR_PIN_PX8_Msk             /*!< Pin 8 selected */
2484 #define AFIO_EVCR_PIN_PX9_Pos                (0U)
2485 #define AFIO_EVCR_PIN_PX9_Msk                (0x9UL << AFIO_EVCR_PIN_PX9_Pos)   /*!< 0x00000009 */
2486 #define AFIO_EVCR_PIN_PX9                    AFIO_EVCR_PIN_PX9_Msk             /*!< Pin 9 selected */
2487 #define AFIO_EVCR_PIN_PX10_Pos               (1U)
2488 #define AFIO_EVCR_PIN_PX10_Msk               (0x5UL << AFIO_EVCR_PIN_PX10_Pos)  /*!< 0x0000000A */
2489 #define AFIO_EVCR_PIN_PX10                   AFIO_EVCR_PIN_PX10_Msk            /*!< Pin 10 selected */
2490 #define AFIO_EVCR_PIN_PX11_Pos               (0U)
2491 #define AFIO_EVCR_PIN_PX11_Msk               (0xBUL << AFIO_EVCR_PIN_PX11_Pos)  /*!< 0x0000000B */
2492 #define AFIO_EVCR_PIN_PX11                   AFIO_EVCR_PIN_PX11_Msk            /*!< Pin 11 selected */
2493 #define AFIO_EVCR_PIN_PX12_Pos               (2U)
2494 #define AFIO_EVCR_PIN_PX12_Msk               (0x3UL << AFIO_EVCR_PIN_PX12_Pos)  /*!< 0x0000000C */
2495 #define AFIO_EVCR_PIN_PX12                   AFIO_EVCR_PIN_PX12_Msk            /*!< Pin 12 selected */
2496 #define AFIO_EVCR_PIN_PX13_Pos               (0U)
2497 #define AFIO_EVCR_PIN_PX13_Msk               (0xDUL << AFIO_EVCR_PIN_PX13_Pos)  /*!< 0x0000000D */
2498 #define AFIO_EVCR_PIN_PX13                   AFIO_EVCR_PIN_PX13_Msk            /*!< Pin 13 selected */
2499 #define AFIO_EVCR_PIN_PX14_Pos               (1U)
2500 #define AFIO_EVCR_PIN_PX14_Msk               (0x7UL << AFIO_EVCR_PIN_PX14_Pos)  /*!< 0x0000000E */
2501 #define AFIO_EVCR_PIN_PX14                   AFIO_EVCR_PIN_PX14_Msk            /*!< Pin 14 selected */
2502 #define AFIO_EVCR_PIN_PX15_Pos               (0U)
2503 #define AFIO_EVCR_PIN_PX15_Msk               (0xFUL << AFIO_EVCR_PIN_PX15_Pos)  /*!< 0x0000000F */
2504 #define AFIO_EVCR_PIN_PX15                   AFIO_EVCR_PIN_PX15_Msk            /*!< Pin 15 selected */
2505 
2506 #define AFIO_EVCR_PORT_Pos                   (4U)
2507 #define AFIO_EVCR_PORT_Msk                   (0x7UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000070 */
2508 #define AFIO_EVCR_PORT                       AFIO_EVCR_PORT_Msk                /*!< PORT[2:0] bits (Port selection) */
2509 #define AFIO_EVCR_PORT_0                     (0x1UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000010 */
2510 #define AFIO_EVCR_PORT_1                     (0x2UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000020 */
2511 #define AFIO_EVCR_PORT_2                     (0x4UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */
2512 
2513 /*!< PORT configuration */
2514 #define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */
2515 #define AFIO_EVCR_PORT_PB_Pos                (4U)
2516 #define AFIO_EVCR_PORT_PB_Msk                (0x1UL << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */
2517 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */
2518 #define AFIO_EVCR_PORT_PC_Pos                (5U)
2519 #define AFIO_EVCR_PORT_PC_Msk                (0x1UL << AFIO_EVCR_PORT_PC_Pos)   /*!< 0x00000020 */
2520 #define AFIO_EVCR_PORT_PC                    AFIO_EVCR_PORT_PC_Msk             /*!< Port C selected */
2521 #define AFIO_EVCR_PORT_PD_Pos                (4U)
2522 #define AFIO_EVCR_PORT_PD_Msk                (0x3UL << AFIO_EVCR_PORT_PD_Pos)   /*!< 0x00000030 */
2523 #define AFIO_EVCR_PORT_PD                    AFIO_EVCR_PORT_PD_Msk             /*!< Port D selected */
2524 #define AFIO_EVCR_PORT_PE_Pos                (6U)
2525 #define AFIO_EVCR_PORT_PE_Msk                (0x1UL << AFIO_EVCR_PORT_PE_Pos)   /*!< 0x00000040 */
2526 #define AFIO_EVCR_PORT_PE                    AFIO_EVCR_PORT_PE_Msk             /*!< Port E selected */
2527 
2528 #define AFIO_EVCR_EVOE_Pos                   (7U)
2529 #define AFIO_EVCR_EVOE_Msk                   (0x1UL << AFIO_EVCR_EVOE_Pos)      /*!< 0x00000080 */
2530 #define AFIO_EVCR_EVOE                       AFIO_EVCR_EVOE_Msk                /*!< Event Output Enable */
2531 
2532 /******************  Bit definition for AFIO_MAPR register  *******************/
2533 #define AFIO_MAPR_SPI1_REMAP_Pos             (0U)
2534 #define AFIO_MAPR_SPI1_REMAP_Msk             (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
2535 #define AFIO_MAPR_SPI1_REMAP                 AFIO_MAPR_SPI1_REMAP_Msk          /*!< SPI1 remapping */
2536 #define AFIO_MAPR_I2C1_REMAP_Pos             (1U)
2537 #define AFIO_MAPR_I2C1_REMAP_Msk             (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
2538 #define AFIO_MAPR_I2C1_REMAP                 AFIO_MAPR_I2C1_REMAP_Msk          /*!< I2C1 remapping */
2539 #define AFIO_MAPR_USART1_REMAP_Pos           (2U)
2540 #define AFIO_MAPR_USART1_REMAP_Msk           (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
2541 #define AFIO_MAPR_USART1_REMAP               AFIO_MAPR_USART1_REMAP_Msk        /*!< USART1 remapping */
2542 #define AFIO_MAPR_USART2_REMAP_Pos           (3U)
2543 #define AFIO_MAPR_USART2_REMAP_Msk           (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
2544 #define AFIO_MAPR_USART2_REMAP               AFIO_MAPR_USART2_REMAP_Msk        /*!< USART2 remapping */
2545 
2546 #define AFIO_MAPR_USART3_REMAP_Pos           (4U)
2547 #define AFIO_MAPR_USART3_REMAP_Msk           (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
2548 #define AFIO_MAPR_USART3_REMAP               AFIO_MAPR_USART3_REMAP_Msk        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
2549 #define AFIO_MAPR_USART3_REMAP_0             (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
2550 #define AFIO_MAPR_USART3_REMAP_1             (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
2551 
2552 /* USART3_REMAP configuration */
2553 #define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2554 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
2555 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
2556 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2557 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
2558 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
2559 #define AFIO_MAPR_USART3_REMAP_FULLREMAP     AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2560 
2561 #define AFIO_MAPR_TIM1_REMAP_Pos             (6U)
2562 #define AFIO_MAPR_TIM1_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
2563 #define AFIO_MAPR_TIM1_REMAP                 AFIO_MAPR_TIM1_REMAP_Msk          /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2564 #define AFIO_MAPR_TIM1_REMAP_0               (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
2565 #define AFIO_MAPR_TIM1_REMAP_1               (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
2566 
2567 /*!< TIM1_REMAP configuration */
2568 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2569 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2570 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
2571 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2572 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos   (6U)
2573 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
2574 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2575 
2576 #define AFIO_MAPR_TIM2_REMAP_Pos             (8U)
2577 #define AFIO_MAPR_TIM2_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
2578 #define AFIO_MAPR_TIM2_REMAP                 AFIO_MAPR_TIM2_REMAP_Msk          /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2579 #define AFIO_MAPR_TIM2_REMAP_0               (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
2580 #define AFIO_MAPR_TIM2_REMAP_1               (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
2581 
2582 /*!< TIM2_REMAP configuration */
2583 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2584 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2585 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
2586 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2587 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2588 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
2589 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2590 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos   (8U)
2591 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
2592 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2593 
2594 #define AFIO_MAPR_TIM3_REMAP_Pos             (10U)
2595 #define AFIO_MAPR_TIM3_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
2596 #define AFIO_MAPR_TIM3_REMAP                 AFIO_MAPR_TIM3_REMAP_Msk          /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2597 #define AFIO_MAPR_TIM3_REMAP_0               (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
2598 #define AFIO_MAPR_TIM3_REMAP_1               (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
2599 
2600 /*!< TIM3_REMAP configuration */
2601 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2602 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2603 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
2604 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2605 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos   (10U)
2606 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
2607 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2608 
2609 #define AFIO_MAPR_TIM4_REMAP_Pos             (12U)
2610 #define AFIO_MAPR_TIM4_REMAP_Msk             (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
2611 #define AFIO_MAPR_TIM4_REMAP                 AFIO_MAPR_TIM4_REMAP_Msk          /*!< TIM4_REMAP bit (TIM4 remapping) */
2612 
2613 #define AFIO_MAPR_CAN_REMAP_Pos              (13U)
2614 #define AFIO_MAPR_CAN_REMAP_Msk              (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
2615 #define AFIO_MAPR_CAN_REMAP                  AFIO_MAPR_CAN_REMAP_Msk           /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2616 #define AFIO_MAPR_CAN_REMAP_0                (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
2617 #define AFIO_MAPR_CAN_REMAP_1                (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
2618 
2619 /*!< CAN_REMAP configuration */
2620 #define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2621 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)
2622 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
2623 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2624 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos       (13U)
2625 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk       (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
2626 #define AFIO_MAPR_CAN_REMAP_REMAP3           AFIO_MAPR_CAN_REMAP_REMAP3_Msk    /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2627 
2628 #define AFIO_MAPR_PD01_REMAP_Pos             (15U)
2629 #define AFIO_MAPR_PD01_REMAP_Msk             (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
2630 #define AFIO_MAPR_PD01_REMAP                 AFIO_MAPR_PD01_REMAP_Msk          /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2631 #define AFIO_MAPR_TIM5CH4_IREMAP_Pos         (16U)
2632 #define AFIO_MAPR_TIM5CH4_IREMAP_Msk         (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */
2633 #define AFIO_MAPR_TIM5CH4_IREMAP             AFIO_MAPR_TIM5CH4_IREMAP_Msk      /*!< TIM5 Channel4 Internal Remap */
2634 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos     (17U)
2635 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */
2636 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP         AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk  /*!< ADC 1 External Trigger Injected Conversion remapping */
2637 #define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos     (18U)
2638 #define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */
2639 #define AFIO_MAPR_ADC1_ETRGREG_REMAP         AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk  /*!< ADC 1 External Trigger Regular Conversion remapping */
2640 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos     (19U)
2641 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */
2642 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP         AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk  /*!< ADC 2 External Trigger Injected Conversion remapping */
2643 #define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos     (20U)
2644 #define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk     (0x1UL << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */
2645 #define AFIO_MAPR_ADC2_ETRGREG_REMAP         AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk  /*!< ADC 2 External Trigger Regular Conversion remapping */
2646 
2647 /*!< SWJ_CFG configuration */
2648 #define AFIO_MAPR_SWJ_CFG_Pos                (24U)
2649 #define AFIO_MAPR_SWJ_CFG_Msk                (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x07000000 */
2650 #define AFIO_MAPR_SWJ_CFG                    AFIO_MAPR_SWJ_CFG_Msk             /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2651 #define AFIO_MAPR_SWJ_CFG_0                  (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x01000000 */
2652 #define AFIO_MAPR_SWJ_CFG_1                  (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */
2653 #define AFIO_MAPR_SWJ_CFG_2                  (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */
2654 
2655 #define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2656 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)
2657 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
2658 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2659 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos    (25U)
2660 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk    (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
2661 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
2662 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos        (26U)
2663 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk        (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
2664 #define AFIO_MAPR_SWJ_CFG_DISABLE            AFIO_MAPR_SWJ_CFG_DISABLE_Msk     /*!< JTAG-DP Disabled and SW-DP Disabled */
2665 
2666 
2667 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
2668 #define AFIO_EXTICR1_EXTI0_Pos               (0U)
2669 #define AFIO_EXTICR1_EXTI0_Msk               (0xFUL << AFIO_EXTICR1_EXTI0_Pos)  /*!< 0x0000000F */
2670 #define AFIO_EXTICR1_EXTI0                   AFIO_EXTICR1_EXTI0_Msk            /*!< EXTI 0 configuration */
2671 #define AFIO_EXTICR1_EXTI1_Pos               (4U)
2672 #define AFIO_EXTICR1_EXTI1_Msk               (0xFUL << AFIO_EXTICR1_EXTI1_Pos)  /*!< 0x000000F0 */
2673 #define AFIO_EXTICR1_EXTI1                   AFIO_EXTICR1_EXTI1_Msk            /*!< EXTI 1 configuration */
2674 #define AFIO_EXTICR1_EXTI2_Pos               (8U)
2675 #define AFIO_EXTICR1_EXTI2_Msk               (0xFUL << AFIO_EXTICR1_EXTI2_Pos)  /*!< 0x00000F00 */
2676 #define AFIO_EXTICR1_EXTI2                   AFIO_EXTICR1_EXTI2_Msk            /*!< EXTI 2 configuration */
2677 #define AFIO_EXTICR1_EXTI3_Pos               (12U)
2678 #define AFIO_EXTICR1_EXTI3_Msk               (0xFUL << AFIO_EXTICR1_EXTI3_Pos)  /*!< 0x0000F000 */
2679 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */
2680 
2681 /*!< EXTI0 configuration */
2682 #define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */
2683 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)
2684 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
2685 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */
2686 #define AFIO_EXTICR1_EXTI0_PC_Pos            (1U)
2687 #define AFIO_EXTICR1_EXTI0_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
2688 #define AFIO_EXTICR1_EXTI0_PC                AFIO_EXTICR1_EXTI0_PC_Msk         /*!< PC[0] pin */
2689 #define AFIO_EXTICR1_EXTI0_PD_Pos            (0U)
2690 #define AFIO_EXTICR1_EXTI0_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
2691 #define AFIO_EXTICR1_EXTI0_PD                AFIO_EXTICR1_EXTI0_PD_Msk         /*!< PD[0] pin */
2692 #define AFIO_EXTICR1_EXTI0_PE_Pos            (2U)
2693 #define AFIO_EXTICR1_EXTI0_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
2694 #define AFIO_EXTICR1_EXTI0_PE                AFIO_EXTICR1_EXTI0_PE_Msk         /*!< PE[0] pin */
2695 #define AFIO_EXTICR1_EXTI0_PF_Pos            (0U)
2696 #define AFIO_EXTICR1_EXTI0_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
2697 #define AFIO_EXTICR1_EXTI0_PF                AFIO_EXTICR1_EXTI0_PF_Msk         /*!< PF[0] pin */
2698 #define AFIO_EXTICR1_EXTI0_PG_Pos            (1U)
2699 #define AFIO_EXTICR1_EXTI0_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
2700 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */
2701 
2702 /*!< EXTI1 configuration */
2703 #define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */
2704 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)
2705 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
2706 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */
2707 #define AFIO_EXTICR1_EXTI1_PC_Pos            (5U)
2708 #define AFIO_EXTICR1_EXTI1_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
2709 #define AFIO_EXTICR1_EXTI1_PC                AFIO_EXTICR1_EXTI1_PC_Msk         /*!< PC[1] pin */
2710 #define AFIO_EXTICR1_EXTI1_PD_Pos            (4U)
2711 #define AFIO_EXTICR1_EXTI1_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
2712 #define AFIO_EXTICR1_EXTI1_PD                AFIO_EXTICR1_EXTI1_PD_Msk         /*!< PD[1] pin */
2713 #define AFIO_EXTICR1_EXTI1_PE_Pos            (6U)
2714 #define AFIO_EXTICR1_EXTI1_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
2715 #define AFIO_EXTICR1_EXTI1_PE                AFIO_EXTICR1_EXTI1_PE_Msk         /*!< PE[1] pin */
2716 #define AFIO_EXTICR1_EXTI1_PF_Pos            (4U)
2717 #define AFIO_EXTICR1_EXTI1_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
2718 #define AFIO_EXTICR1_EXTI1_PF                AFIO_EXTICR1_EXTI1_PF_Msk         /*!< PF[1] pin */
2719 #define AFIO_EXTICR1_EXTI1_PG_Pos            (5U)
2720 #define AFIO_EXTICR1_EXTI1_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
2721 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */
2722 
2723 /*!< EXTI2 configuration */
2724 #define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */
2725 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)
2726 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
2727 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */
2728 #define AFIO_EXTICR1_EXTI2_PC_Pos            (9U)
2729 #define AFIO_EXTICR1_EXTI2_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
2730 #define AFIO_EXTICR1_EXTI2_PC                AFIO_EXTICR1_EXTI2_PC_Msk         /*!< PC[2] pin */
2731 #define AFIO_EXTICR1_EXTI2_PD_Pos            (8U)
2732 #define AFIO_EXTICR1_EXTI2_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
2733 #define AFIO_EXTICR1_EXTI2_PD                AFIO_EXTICR1_EXTI2_PD_Msk         /*!< PD[2] pin */
2734 #define AFIO_EXTICR1_EXTI2_PE_Pos            (10U)
2735 #define AFIO_EXTICR1_EXTI2_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
2736 #define AFIO_EXTICR1_EXTI2_PE                AFIO_EXTICR1_EXTI2_PE_Msk         /*!< PE[2] pin */
2737 #define AFIO_EXTICR1_EXTI2_PF_Pos            (8U)
2738 #define AFIO_EXTICR1_EXTI2_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
2739 #define AFIO_EXTICR1_EXTI2_PF                AFIO_EXTICR1_EXTI2_PF_Msk         /*!< PF[2] pin */
2740 #define AFIO_EXTICR1_EXTI2_PG_Pos            (9U)
2741 #define AFIO_EXTICR1_EXTI2_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
2742 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */
2743 
2744 /*!< EXTI3 configuration */
2745 #define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */
2746 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)
2747 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
2748 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */
2749 #define AFIO_EXTICR1_EXTI3_PC_Pos            (13U)
2750 #define AFIO_EXTICR1_EXTI3_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
2751 #define AFIO_EXTICR1_EXTI3_PC                AFIO_EXTICR1_EXTI3_PC_Msk         /*!< PC[3] pin */
2752 #define AFIO_EXTICR1_EXTI3_PD_Pos            (12U)
2753 #define AFIO_EXTICR1_EXTI3_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
2754 #define AFIO_EXTICR1_EXTI3_PD                AFIO_EXTICR1_EXTI3_PD_Msk         /*!< PD[3] pin */
2755 #define AFIO_EXTICR1_EXTI3_PE_Pos            (14U)
2756 #define AFIO_EXTICR1_EXTI3_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
2757 #define AFIO_EXTICR1_EXTI3_PE                AFIO_EXTICR1_EXTI3_PE_Msk         /*!< PE[3] pin */
2758 #define AFIO_EXTICR1_EXTI3_PF_Pos            (12U)
2759 #define AFIO_EXTICR1_EXTI3_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
2760 #define AFIO_EXTICR1_EXTI3_PF                AFIO_EXTICR1_EXTI3_PF_Msk         /*!< PF[3] pin */
2761 #define AFIO_EXTICR1_EXTI3_PG_Pos            (13U)
2762 #define AFIO_EXTICR1_EXTI3_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
2763 #define AFIO_EXTICR1_EXTI3_PG                AFIO_EXTICR1_EXTI3_PG_Msk         /*!< PG[3] pin */
2764 
2765 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
2766 #define AFIO_EXTICR2_EXTI4_Pos               (0U)
2767 #define AFIO_EXTICR2_EXTI4_Msk               (0xFUL << AFIO_EXTICR2_EXTI4_Pos)  /*!< 0x0000000F */
2768 #define AFIO_EXTICR2_EXTI4                   AFIO_EXTICR2_EXTI4_Msk            /*!< EXTI 4 configuration */
2769 #define AFIO_EXTICR2_EXTI5_Pos               (4U)
2770 #define AFIO_EXTICR2_EXTI5_Msk               (0xFUL << AFIO_EXTICR2_EXTI5_Pos)  /*!< 0x000000F0 */
2771 #define AFIO_EXTICR2_EXTI5                   AFIO_EXTICR2_EXTI5_Msk            /*!< EXTI 5 configuration */
2772 #define AFIO_EXTICR2_EXTI6_Pos               (8U)
2773 #define AFIO_EXTICR2_EXTI6_Msk               (0xFUL << AFIO_EXTICR2_EXTI6_Pos)  /*!< 0x00000F00 */
2774 #define AFIO_EXTICR2_EXTI6                   AFIO_EXTICR2_EXTI6_Msk            /*!< EXTI 6 configuration */
2775 #define AFIO_EXTICR2_EXTI7_Pos               (12U)
2776 #define AFIO_EXTICR2_EXTI7_Msk               (0xFUL << AFIO_EXTICR2_EXTI7_Pos)  /*!< 0x0000F000 */
2777 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */
2778 
2779 /*!< EXTI4 configuration */
2780 #define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */
2781 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)
2782 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
2783 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */
2784 #define AFIO_EXTICR2_EXTI4_PC_Pos            (1U)
2785 #define AFIO_EXTICR2_EXTI4_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
2786 #define AFIO_EXTICR2_EXTI4_PC                AFIO_EXTICR2_EXTI4_PC_Msk         /*!< PC[4] pin */
2787 #define AFIO_EXTICR2_EXTI4_PD_Pos            (0U)
2788 #define AFIO_EXTICR2_EXTI4_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
2789 #define AFIO_EXTICR2_EXTI4_PD                AFIO_EXTICR2_EXTI4_PD_Msk         /*!< PD[4] pin */
2790 #define AFIO_EXTICR2_EXTI4_PE_Pos            (2U)
2791 #define AFIO_EXTICR2_EXTI4_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
2792 #define AFIO_EXTICR2_EXTI4_PE                AFIO_EXTICR2_EXTI4_PE_Msk         /*!< PE[4] pin */
2793 #define AFIO_EXTICR2_EXTI4_PF_Pos            (0U)
2794 #define AFIO_EXTICR2_EXTI4_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
2795 #define AFIO_EXTICR2_EXTI4_PF                AFIO_EXTICR2_EXTI4_PF_Msk         /*!< PF[4] pin */
2796 #define AFIO_EXTICR2_EXTI4_PG_Pos            (1U)
2797 #define AFIO_EXTICR2_EXTI4_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
2798 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */
2799 
2800 /* EXTI5 configuration */
2801 #define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */
2802 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)
2803 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
2804 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */
2805 #define AFIO_EXTICR2_EXTI5_PC_Pos            (5U)
2806 #define AFIO_EXTICR2_EXTI5_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
2807 #define AFIO_EXTICR2_EXTI5_PC                AFIO_EXTICR2_EXTI5_PC_Msk         /*!< PC[5] pin */
2808 #define AFIO_EXTICR2_EXTI5_PD_Pos            (4U)
2809 #define AFIO_EXTICR2_EXTI5_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
2810 #define AFIO_EXTICR2_EXTI5_PD                AFIO_EXTICR2_EXTI5_PD_Msk         /*!< PD[5] pin */
2811 #define AFIO_EXTICR2_EXTI5_PE_Pos            (6U)
2812 #define AFIO_EXTICR2_EXTI5_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
2813 #define AFIO_EXTICR2_EXTI5_PE                AFIO_EXTICR2_EXTI5_PE_Msk         /*!< PE[5] pin */
2814 #define AFIO_EXTICR2_EXTI5_PF_Pos            (4U)
2815 #define AFIO_EXTICR2_EXTI5_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
2816 #define AFIO_EXTICR2_EXTI5_PF                AFIO_EXTICR2_EXTI5_PF_Msk         /*!< PF[5] pin */
2817 #define AFIO_EXTICR2_EXTI5_PG_Pos            (5U)
2818 #define AFIO_EXTICR2_EXTI5_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
2819 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */
2820 
2821 /*!< EXTI6 configuration */
2822 #define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */
2823 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)
2824 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
2825 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */
2826 #define AFIO_EXTICR2_EXTI6_PC_Pos            (9U)
2827 #define AFIO_EXTICR2_EXTI6_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
2828 #define AFIO_EXTICR2_EXTI6_PC                AFIO_EXTICR2_EXTI6_PC_Msk         /*!< PC[6] pin */
2829 #define AFIO_EXTICR2_EXTI6_PD_Pos            (8U)
2830 #define AFIO_EXTICR2_EXTI6_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
2831 #define AFIO_EXTICR2_EXTI6_PD                AFIO_EXTICR2_EXTI6_PD_Msk         /*!< PD[6] pin */
2832 #define AFIO_EXTICR2_EXTI6_PE_Pos            (10U)
2833 #define AFIO_EXTICR2_EXTI6_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
2834 #define AFIO_EXTICR2_EXTI6_PE                AFIO_EXTICR2_EXTI6_PE_Msk         /*!< PE[6] pin */
2835 #define AFIO_EXTICR2_EXTI6_PF_Pos            (8U)
2836 #define AFIO_EXTICR2_EXTI6_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
2837 #define AFIO_EXTICR2_EXTI6_PF                AFIO_EXTICR2_EXTI6_PF_Msk         /*!< PF[6] pin */
2838 #define AFIO_EXTICR2_EXTI6_PG_Pos            (9U)
2839 #define AFIO_EXTICR2_EXTI6_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
2840 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */
2841 
2842 /*!< EXTI7 configuration */
2843 #define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */
2844 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)
2845 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
2846 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */
2847 #define AFIO_EXTICR2_EXTI7_PC_Pos            (13U)
2848 #define AFIO_EXTICR2_EXTI7_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
2849 #define AFIO_EXTICR2_EXTI7_PC                AFIO_EXTICR2_EXTI7_PC_Msk         /*!< PC[7] pin */
2850 #define AFIO_EXTICR2_EXTI7_PD_Pos            (12U)
2851 #define AFIO_EXTICR2_EXTI7_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
2852 #define AFIO_EXTICR2_EXTI7_PD                AFIO_EXTICR2_EXTI7_PD_Msk         /*!< PD[7] pin */
2853 #define AFIO_EXTICR2_EXTI7_PE_Pos            (14U)
2854 #define AFIO_EXTICR2_EXTI7_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
2855 #define AFIO_EXTICR2_EXTI7_PE                AFIO_EXTICR2_EXTI7_PE_Msk         /*!< PE[7] pin */
2856 #define AFIO_EXTICR2_EXTI7_PF_Pos            (12U)
2857 #define AFIO_EXTICR2_EXTI7_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
2858 #define AFIO_EXTICR2_EXTI7_PF                AFIO_EXTICR2_EXTI7_PF_Msk         /*!< PF[7] pin */
2859 #define AFIO_EXTICR2_EXTI7_PG_Pos            (13U)
2860 #define AFIO_EXTICR2_EXTI7_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
2861 #define AFIO_EXTICR2_EXTI7_PG                AFIO_EXTICR2_EXTI7_PG_Msk         /*!< PG[7] pin */
2862 
2863 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
2864 #define AFIO_EXTICR3_EXTI8_Pos               (0U)
2865 #define AFIO_EXTICR3_EXTI8_Msk               (0xFUL << AFIO_EXTICR3_EXTI8_Pos)  /*!< 0x0000000F */
2866 #define AFIO_EXTICR3_EXTI8                   AFIO_EXTICR3_EXTI8_Msk            /*!< EXTI 8 configuration */
2867 #define AFIO_EXTICR3_EXTI9_Pos               (4U)
2868 #define AFIO_EXTICR3_EXTI9_Msk               (0xFUL << AFIO_EXTICR3_EXTI9_Pos)  /*!< 0x000000F0 */
2869 #define AFIO_EXTICR3_EXTI9                   AFIO_EXTICR3_EXTI9_Msk            /*!< EXTI 9 configuration */
2870 #define AFIO_EXTICR3_EXTI10_Pos              (8U)
2871 #define AFIO_EXTICR3_EXTI10_Msk              (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
2872 #define AFIO_EXTICR3_EXTI10                  AFIO_EXTICR3_EXTI10_Msk           /*!< EXTI 10 configuration */
2873 #define AFIO_EXTICR3_EXTI11_Pos              (12U)
2874 #define AFIO_EXTICR3_EXTI11_Msk              (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
2875 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */
2876 
2877 /*!< EXTI8 configuration */
2878 #define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */
2879 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)
2880 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
2881 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */
2882 #define AFIO_EXTICR3_EXTI8_PC_Pos            (1U)
2883 #define AFIO_EXTICR3_EXTI8_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
2884 #define AFIO_EXTICR3_EXTI8_PC                AFIO_EXTICR3_EXTI8_PC_Msk         /*!< PC[8] pin */
2885 #define AFIO_EXTICR3_EXTI8_PD_Pos            (0U)
2886 #define AFIO_EXTICR3_EXTI8_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
2887 #define AFIO_EXTICR3_EXTI8_PD                AFIO_EXTICR3_EXTI8_PD_Msk         /*!< PD[8] pin */
2888 #define AFIO_EXTICR3_EXTI8_PE_Pos            (2U)
2889 #define AFIO_EXTICR3_EXTI8_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
2890 #define AFIO_EXTICR3_EXTI8_PE                AFIO_EXTICR3_EXTI8_PE_Msk         /*!< PE[8] pin */
2891 #define AFIO_EXTICR3_EXTI8_PF_Pos            (0U)
2892 #define AFIO_EXTICR3_EXTI8_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
2893 #define AFIO_EXTICR3_EXTI8_PF                AFIO_EXTICR3_EXTI8_PF_Msk         /*!< PF[8] pin */
2894 #define AFIO_EXTICR3_EXTI8_PG_Pos            (1U)
2895 #define AFIO_EXTICR3_EXTI8_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
2896 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */
2897 
2898 /*!< EXTI9 configuration */
2899 #define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */
2900 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)
2901 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
2902 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */
2903 #define AFIO_EXTICR3_EXTI9_PC_Pos            (5U)
2904 #define AFIO_EXTICR3_EXTI9_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
2905 #define AFIO_EXTICR3_EXTI9_PC                AFIO_EXTICR3_EXTI9_PC_Msk         /*!< PC[9] pin */
2906 #define AFIO_EXTICR3_EXTI9_PD_Pos            (4U)
2907 #define AFIO_EXTICR3_EXTI9_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
2908 #define AFIO_EXTICR3_EXTI9_PD                AFIO_EXTICR3_EXTI9_PD_Msk         /*!< PD[9] pin */
2909 #define AFIO_EXTICR3_EXTI9_PE_Pos            (6U)
2910 #define AFIO_EXTICR3_EXTI9_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
2911 #define AFIO_EXTICR3_EXTI9_PE                AFIO_EXTICR3_EXTI9_PE_Msk         /*!< PE[9] pin */
2912 #define AFIO_EXTICR3_EXTI9_PF_Pos            (4U)
2913 #define AFIO_EXTICR3_EXTI9_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
2914 #define AFIO_EXTICR3_EXTI9_PF                AFIO_EXTICR3_EXTI9_PF_Msk         /*!< PF[9] pin */
2915 #define AFIO_EXTICR3_EXTI9_PG_Pos            (5U)
2916 #define AFIO_EXTICR3_EXTI9_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
2917 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */
2918 
2919 /*!< EXTI10 configuration */
2920 #define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */
2921 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)
2922 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
2923 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */
2924 #define AFIO_EXTICR3_EXTI10_PC_Pos           (9U)
2925 #define AFIO_EXTICR3_EXTI10_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
2926 #define AFIO_EXTICR3_EXTI10_PC               AFIO_EXTICR3_EXTI10_PC_Msk        /*!< PC[10] pin */
2927 #define AFIO_EXTICR3_EXTI10_PD_Pos           (8U)
2928 #define AFIO_EXTICR3_EXTI10_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
2929 #define AFIO_EXTICR3_EXTI10_PD               AFIO_EXTICR3_EXTI10_PD_Msk        /*!< PD[10] pin */
2930 #define AFIO_EXTICR3_EXTI10_PE_Pos           (10U)
2931 #define AFIO_EXTICR3_EXTI10_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
2932 #define AFIO_EXTICR3_EXTI10_PE               AFIO_EXTICR3_EXTI10_PE_Msk        /*!< PE[10] pin */
2933 #define AFIO_EXTICR3_EXTI10_PF_Pos           (8U)
2934 #define AFIO_EXTICR3_EXTI10_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
2935 #define AFIO_EXTICR3_EXTI10_PF               AFIO_EXTICR3_EXTI10_PF_Msk        /*!< PF[10] pin */
2936 #define AFIO_EXTICR3_EXTI10_PG_Pos           (9U)
2937 #define AFIO_EXTICR3_EXTI10_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
2938 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */
2939 
2940 /*!< EXTI11 configuration */
2941 #define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */
2942 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)
2943 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
2944 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */
2945 #define AFIO_EXTICR3_EXTI11_PC_Pos           (13U)
2946 #define AFIO_EXTICR3_EXTI11_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
2947 #define AFIO_EXTICR3_EXTI11_PC               AFIO_EXTICR3_EXTI11_PC_Msk        /*!< PC[11] pin */
2948 #define AFIO_EXTICR3_EXTI11_PD_Pos           (12U)
2949 #define AFIO_EXTICR3_EXTI11_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
2950 #define AFIO_EXTICR3_EXTI11_PD               AFIO_EXTICR3_EXTI11_PD_Msk        /*!< PD[11] pin */
2951 #define AFIO_EXTICR3_EXTI11_PE_Pos           (14U)
2952 #define AFIO_EXTICR3_EXTI11_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
2953 #define AFIO_EXTICR3_EXTI11_PE               AFIO_EXTICR3_EXTI11_PE_Msk        /*!< PE[11] pin */
2954 #define AFIO_EXTICR3_EXTI11_PF_Pos           (12U)
2955 #define AFIO_EXTICR3_EXTI11_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
2956 #define AFIO_EXTICR3_EXTI11_PF               AFIO_EXTICR3_EXTI11_PF_Msk        /*!< PF[11] pin */
2957 #define AFIO_EXTICR3_EXTI11_PG_Pos           (13U)
2958 #define AFIO_EXTICR3_EXTI11_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
2959 #define AFIO_EXTICR3_EXTI11_PG               AFIO_EXTICR3_EXTI11_PG_Msk        /*!< PG[11] pin */
2960 
2961 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
2962 #define AFIO_EXTICR4_EXTI12_Pos              (0U)
2963 #define AFIO_EXTICR4_EXTI12_Msk              (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
2964 #define AFIO_EXTICR4_EXTI12                  AFIO_EXTICR4_EXTI12_Msk           /*!< EXTI 12 configuration */
2965 #define AFIO_EXTICR4_EXTI13_Pos              (4U)
2966 #define AFIO_EXTICR4_EXTI13_Msk              (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
2967 #define AFIO_EXTICR4_EXTI13                  AFIO_EXTICR4_EXTI13_Msk           /*!< EXTI 13 configuration */
2968 #define AFIO_EXTICR4_EXTI14_Pos              (8U)
2969 #define AFIO_EXTICR4_EXTI14_Msk              (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
2970 #define AFIO_EXTICR4_EXTI14                  AFIO_EXTICR4_EXTI14_Msk           /*!< EXTI 14 configuration */
2971 #define AFIO_EXTICR4_EXTI15_Pos              (12U)
2972 #define AFIO_EXTICR4_EXTI15_Msk              (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
2973 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */
2974 
2975 /* EXTI12 configuration */
2976 #define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */
2977 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)
2978 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
2979 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */
2980 #define AFIO_EXTICR4_EXTI12_PC_Pos           (1U)
2981 #define AFIO_EXTICR4_EXTI12_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
2982 #define AFIO_EXTICR4_EXTI12_PC               AFIO_EXTICR4_EXTI12_PC_Msk        /*!< PC[12] pin */
2983 #define AFIO_EXTICR4_EXTI12_PD_Pos           (0U)
2984 #define AFIO_EXTICR4_EXTI12_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
2985 #define AFIO_EXTICR4_EXTI12_PD               AFIO_EXTICR4_EXTI12_PD_Msk        /*!< PD[12] pin */
2986 #define AFIO_EXTICR4_EXTI12_PE_Pos           (2U)
2987 #define AFIO_EXTICR4_EXTI12_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
2988 #define AFIO_EXTICR4_EXTI12_PE               AFIO_EXTICR4_EXTI12_PE_Msk        /*!< PE[12] pin */
2989 #define AFIO_EXTICR4_EXTI12_PF_Pos           (0U)
2990 #define AFIO_EXTICR4_EXTI12_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
2991 #define AFIO_EXTICR4_EXTI12_PF               AFIO_EXTICR4_EXTI12_PF_Msk        /*!< PF[12] pin */
2992 #define AFIO_EXTICR4_EXTI12_PG_Pos           (1U)
2993 #define AFIO_EXTICR4_EXTI12_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
2994 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */
2995 
2996 /* EXTI13 configuration */
2997 #define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */
2998 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)
2999 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
3000 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */
3001 #define AFIO_EXTICR4_EXTI13_PC_Pos           (5U)
3002 #define AFIO_EXTICR4_EXTI13_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
3003 #define AFIO_EXTICR4_EXTI13_PC               AFIO_EXTICR4_EXTI13_PC_Msk        /*!< PC[13] pin */
3004 #define AFIO_EXTICR4_EXTI13_PD_Pos           (4U)
3005 #define AFIO_EXTICR4_EXTI13_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
3006 #define AFIO_EXTICR4_EXTI13_PD               AFIO_EXTICR4_EXTI13_PD_Msk        /*!< PD[13] pin */
3007 #define AFIO_EXTICR4_EXTI13_PE_Pos           (6U)
3008 #define AFIO_EXTICR4_EXTI13_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
3009 #define AFIO_EXTICR4_EXTI13_PE               AFIO_EXTICR4_EXTI13_PE_Msk        /*!< PE[13] pin */
3010 #define AFIO_EXTICR4_EXTI13_PF_Pos           (4U)
3011 #define AFIO_EXTICR4_EXTI13_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
3012 #define AFIO_EXTICR4_EXTI13_PF               AFIO_EXTICR4_EXTI13_PF_Msk        /*!< PF[13] pin */
3013 #define AFIO_EXTICR4_EXTI13_PG_Pos           (5U)
3014 #define AFIO_EXTICR4_EXTI13_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
3015 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */
3016 
3017 /*!< EXTI14 configuration */
3018 #define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */
3019 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)
3020 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
3021 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */
3022 #define AFIO_EXTICR4_EXTI14_PC_Pos           (9U)
3023 #define AFIO_EXTICR4_EXTI14_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
3024 #define AFIO_EXTICR4_EXTI14_PC               AFIO_EXTICR4_EXTI14_PC_Msk        /*!< PC[14] pin */
3025 #define AFIO_EXTICR4_EXTI14_PD_Pos           (8U)
3026 #define AFIO_EXTICR4_EXTI14_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
3027 #define AFIO_EXTICR4_EXTI14_PD               AFIO_EXTICR4_EXTI14_PD_Msk        /*!< PD[14] pin */
3028 #define AFIO_EXTICR4_EXTI14_PE_Pos           (10U)
3029 #define AFIO_EXTICR4_EXTI14_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
3030 #define AFIO_EXTICR4_EXTI14_PE               AFIO_EXTICR4_EXTI14_PE_Msk        /*!< PE[14] pin */
3031 #define AFIO_EXTICR4_EXTI14_PF_Pos           (8U)
3032 #define AFIO_EXTICR4_EXTI14_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
3033 #define AFIO_EXTICR4_EXTI14_PF               AFIO_EXTICR4_EXTI14_PF_Msk        /*!< PF[14] pin */
3034 #define AFIO_EXTICR4_EXTI14_PG_Pos           (9U)
3035 #define AFIO_EXTICR4_EXTI14_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
3036 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */
3037 
3038 /*!< EXTI15 configuration */
3039 #define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */
3040 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)
3041 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
3042 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */
3043 #define AFIO_EXTICR4_EXTI15_PC_Pos           (13U)
3044 #define AFIO_EXTICR4_EXTI15_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
3045 #define AFIO_EXTICR4_EXTI15_PC               AFIO_EXTICR4_EXTI15_PC_Msk        /*!< PC[15] pin */
3046 #define AFIO_EXTICR4_EXTI15_PD_Pos           (12U)
3047 #define AFIO_EXTICR4_EXTI15_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
3048 #define AFIO_EXTICR4_EXTI15_PD               AFIO_EXTICR4_EXTI15_PD_Msk        /*!< PD[15] pin */
3049 #define AFIO_EXTICR4_EXTI15_PE_Pos           (14U)
3050 #define AFIO_EXTICR4_EXTI15_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
3051 #define AFIO_EXTICR4_EXTI15_PE               AFIO_EXTICR4_EXTI15_PE_Msk        /*!< PE[15] pin */
3052 #define AFIO_EXTICR4_EXTI15_PF_Pos           (12U)
3053 #define AFIO_EXTICR4_EXTI15_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
3054 #define AFIO_EXTICR4_EXTI15_PF               AFIO_EXTICR4_EXTI15_PF_Msk        /*!< PF[15] pin */
3055 #define AFIO_EXTICR4_EXTI15_PG_Pos           (13U)
3056 #define AFIO_EXTICR4_EXTI15_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
3057 #define AFIO_EXTICR4_EXTI15_PG               AFIO_EXTICR4_EXTI15_PG_Msk        /*!< PG[15] pin */
3058 
3059 /******************  Bit definition for AFIO_MAPR2 register  ******************/
3060 
3061 
3062 #define AFIO_MAPR2_TIM9_REMAP_Pos            (5U)
3063 #define AFIO_MAPR2_TIM9_REMAP_Msk            (0x1UL << AFIO_MAPR2_TIM9_REMAP_Pos) /*!< 0x00000020 */
3064 #define AFIO_MAPR2_TIM9_REMAP                AFIO_MAPR2_TIM9_REMAP_Msk         /*!< TIM9 remapping */
3065 #define AFIO_MAPR2_TIM10_REMAP_Pos           (6U)
3066 #define AFIO_MAPR2_TIM10_REMAP_Msk           (0x1UL << AFIO_MAPR2_TIM10_REMAP_Pos) /*!< 0x00000040 */
3067 #define AFIO_MAPR2_TIM10_REMAP               AFIO_MAPR2_TIM10_REMAP_Msk        /*!< TIM10 remapping */
3068 #define AFIO_MAPR2_TIM11_REMAP_Pos           (7U)
3069 #define AFIO_MAPR2_TIM11_REMAP_Msk           (0x1UL << AFIO_MAPR2_TIM11_REMAP_Pos) /*!< 0x00000080 */
3070 #define AFIO_MAPR2_TIM11_REMAP               AFIO_MAPR2_TIM11_REMAP_Msk        /*!< TIM11 remapping */
3071 #define AFIO_MAPR2_TIM13_REMAP_Pos           (8U)
3072 #define AFIO_MAPR2_TIM13_REMAP_Msk           (0x1UL << AFIO_MAPR2_TIM13_REMAP_Pos) /*!< 0x00000100 */
3073 #define AFIO_MAPR2_TIM13_REMAP               AFIO_MAPR2_TIM13_REMAP_Msk        /*!< TIM13 remapping */
3074 #define AFIO_MAPR2_TIM14_REMAP_Pos           (9U)
3075 #define AFIO_MAPR2_TIM14_REMAP_Msk           (0x1UL << AFIO_MAPR2_TIM14_REMAP_Pos) /*!< 0x00000200 */
3076 #define AFIO_MAPR2_TIM14_REMAP               AFIO_MAPR2_TIM14_REMAP_Msk        /*!< TIM14 remapping */
3077 #define AFIO_MAPR2_FSMC_NADV_REMAP_Pos       (10U)
3078 #define AFIO_MAPR2_FSMC_NADV_REMAP_Msk       (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */
3079 #define AFIO_MAPR2_FSMC_NADV_REMAP           AFIO_MAPR2_FSMC_NADV_REMAP_Msk    /*!< FSMC NADV remapping */
3080 
3081 /******************************************************************************/
3082 /*                                                                            */
3083 /*                    External Interrupt/Event Controller                     */
3084 /*                                                                            */
3085 /******************************************************************************/
3086 
3087 /*******************  Bit definition for EXTI_IMR register  *******************/
3088 #define EXTI_IMR_MR0_Pos                    (0U)
3089 #define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
3090 #define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
3091 #define EXTI_IMR_MR1_Pos                    (1U)
3092 #define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
3093 #define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
3094 #define EXTI_IMR_MR2_Pos                    (2U)
3095 #define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
3096 #define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
3097 #define EXTI_IMR_MR3_Pos                    (3U)
3098 #define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
3099 #define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
3100 #define EXTI_IMR_MR4_Pos                    (4U)
3101 #define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
3102 #define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
3103 #define EXTI_IMR_MR5_Pos                    (5U)
3104 #define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
3105 #define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
3106 #define EXTI_IMR_MR6_Pos                    (6U)
3107 #define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
3108 #define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
3109 #define EXTI_IMR_MR7_Pos                    (7U)
3110 #define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
3111 #define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
3112 #define EXTI_IMR_MR8_Pos                    (8U)
3113 #define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
3114 #define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
3115 #define EXTI_IMR_MR9_Pos                    (9U)
3116 #define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
3117 #define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
3118 #define EXTI_IMR_MR10_Pos                   (10U)
3119 #define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
3120 #define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
3121 #define EXTI_IMR_MR11_Pos                   (11U)
3122 #define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
3123 #define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
3124 #define EXTI_IMR_MR12_Pos                   (12U)
3125 #define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
3126 #define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
3127 #define EXTI_IMR_MR13_Pos                   (13U)
3128 #define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
3129 #define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
3130 #define EXTI_IMR_MR14_Pos                   (14U)
3131 #define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
3132 #define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
3133 #define EXTI_IMR_MR15_Pos                   (15U)
3134 #define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
3135 #define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
3136 #define EXTI_IMR_MR16_Pos                   (16U)
3137 #define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
3138 #define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
3139 #define EXTI_IMR_MR17_Pos                   (17U)
3140 #define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
3141 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
3142 #define EXTI_IMR_MR18_Pos                   (18U)
3143 #define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
3144 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
3145 
3146 /* References Defines */
3147 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
3148 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
3149 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
3150 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
3151 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
3152 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
3153 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
3154 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
3155 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
3156 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
3157 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
3158 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
3159 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
3160 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
3161 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
3162 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
3163 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
3164 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
3165 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
3166 #define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */
3167 
3168 /*******************  Bit definition for EXTI_EMR register  *******************/
3169 #define EXTI_EMR_MR0_Pos                    (0U)
3170 #define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
3171 #define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
3172 #define EXTI_EMR_MR1_Pos                    (1U)
3173 #define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
3174 #define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
3175 #define EXTI_EMR_MR2_Pos                    (2U)
3176 #define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
3177 #define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
3178 #define EXTI_EMR_MR3_Pos                    (3U)
3179 #define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
3180 #define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
3181 #define EXTI_EMR_MR4_Pos                    (4U)
3182 #define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
3183 #define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
3184 #define EXTI_EMR_MR5_Pos                    (5U)
3185 #define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
3186 #define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
3187 #define EXTI_EMR_MR6_Pos                    (6U)
3188 #define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
3189 #define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
3190 #define EXTI_EMR_MR7_Pos                    (7U)
3191 #define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
3192 #define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
3193 #define EXTI_EMR_MR8_Pos                    (8U)
3194 #define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
3195 #define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
3196 #define EXTI_EMR_MR9_Pos                    (9U)
3197 #define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
3198 #define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
3199 #define EXTI_EMR_MR10_Pos                   (10U)
3200 #define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
3201 #define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
3202 #define EXTI_EMR_MR11_Pos                   (11U)
3203 #define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
3204 #define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
3205 #define EXTI_EMR_MR12_Pos                   (12U)
3206 #define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
3207 #define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
3208 #define EXTI_EMR_MR13_Pos                   (13U)
3209 #define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
3210 #define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
3211 #define EXTI_EMR_MR14_Pos                   (14U)
3212 #define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
3213 #define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
3214 #define EXTI_EMR_MR15_Pos                   (15U)
3215 #define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
3216 #define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
3217 #define EXTI_EMR_MR16_Pos                   (16U)
3218 #define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
3219 #define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
3220 #define EXTI_EMR_MR17_Pos                   (17U)
3221 #define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
3222 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
3223 #define EXTI_EMR_MR18_Pos                   (18U)
3224 #define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
3225 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
3226 
3227 /* References Defines */
3228 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
3229 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
3230 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
3231 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
3232 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
3233 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
3234 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
3235 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
3236 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
3237 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
3238 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
3239 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
3240 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
3241 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
3242 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
3243 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
3244 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
3245 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
3246 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
3247 
3248 /******************  Bit definition for EXTI_RTSR register  *******************/
3249 #define EXTI_RTSR_TR0_Pos                   (0U)
3250 #define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
3251 #define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
3252 #define EXTI_RTSR_TR1_Pos                   (1U)
3253 #define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
3254 #define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
3255 #define EXTI_RTSR_TR2_Pos                   (2U)
3256 #define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
3257 #define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
3258 #define EXTI_RTSR_TR3_Pos                   (3U)
3259 #define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
3260 #define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
3261 #define EXTI_RTSR_TR4_Pos                   (4U)
3262 #define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
3263 #define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
3264 #define EXTI_RTSR_TR5_Pos                   (5U)
3265 #define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
3266 #define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
3267 #define EXTI_RTSR_TR6_Pos                   (6U)
3268 #define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
3269 #define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
3270 #define EXTI_RTSR_TR7_Pos                   (7U)
3271 #define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
3272 #define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
3273 #define EXTI_RTSR_TR8_Pos                   (8U)
3274 #define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
3275 #define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
3276 #define EXTI_RTSR_TR9_Pos                   (9U)
3277 #define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
3278 #define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
3279 #define EXTI_RTSR_TR10_Pos                  (10U)
3280 #define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
3281 #define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
3282 #define EXTI_RTSR_TR11_Pos                  (11U)
3283 #define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
3284 #define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
3285 #define EXTI_RTSR_TR12_Pos                  (12U)
3286 #define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
3287 #define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
3288 #define EXTI_RTSR_TR13_Pos                  (13U)
3289 #define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
3290 #define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
3291 #define EXTI_RTSR_TR14_Pos                  (14U)
3292 #define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
3293 #define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
3294 #define EXTI_RTSR_TR15_Pos                  (15U)
3295 #define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
3296 #define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
3297 #define EXTI_RTSR_TR16_Pos                  (16U)
3298 #define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
3299 #define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
3300 #define EXTI_RTSR_TR17_Pos                  (17U)
3301 #define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
3302 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
3303 #define EXTI_RTSR_TR18_Pos                  (18U)
3304 #define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
3305 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
3306 
3307 /* References Defines */
3308 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
3309 #define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
3310 #define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
3311 #define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
3312 #define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
3313 #define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
3314 #define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
3315 #define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
3316 #define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
3317 #define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
3318 #define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
3319 #define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
3320 #define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
3321 #define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
3322 #define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
3323 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
3324 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
3325 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
3326 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
3327 
3328 /******************  Bit definition for EXTI_FTSR register  *******************/
3329 #define EXTI_FTSR_TR0_Pos                   (0U)
3330 #define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
3331 #define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
3332 #define EXTI_FTSR_TR1_Pos                   (1U)
3333 #define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
3334 #define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
3335 #define EXTI_FTSR_TR2_Pos                   (2U)
3336 #define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
3337 #define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
3338 #define EXTI_FTSR_TR3_Pos                   (3U)
3339 #define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
3340 #define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
3341 #define EXTI_FTSR_TR4_Pos                   (4U)
3342 #define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
3343 #define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
3344 #define EXTI_FTSR_TR5_Pos                   (5U)
3345 #define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
3346 #define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
3347 #define EXTI_FTSR_TR6_Pos                   (6U)
3348 #define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
3349 #define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
3350 #define EXTI_FTSR_TR7_Pos                   (7U)
3351 #define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
3352 #define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
3353 #define EXTI_FTSR_TR8_Pos                   (8U)
3354 #define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
3355 #define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
3356 #define EXTI_FTSR_TR9_Pos                   (9U)
3357 #define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
3358 #define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
3359 #define EXTI_FTSR_TR10_Pos                  (10U)
3360 #define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
3361 #define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
3362 #define EXTI_FTSR_TR11_Pos                  (11U)
3363 #define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
3364 #define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
3365 #define EXTI_FTSR_TR12_Pos                  (12U)
3366 #define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
3367 #define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
3368 #define EXTI_FTSR_TR13_Pos                  (13U)
3369 #define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
3370 #define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
3371 #define EXTI_FTSR_TR14_Pos                  (14U)
3372 #define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
3373 #define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
3374 #define EXTI_FTSR_TR15_Pos                  (15U)
3375 #define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
3376 #define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
3377 #define EXTI_FTSR_TR16_Pos                  (16U)
3378 #define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
3379 #define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
3380 #define EXTI_FTSR_TR17_Pos                  (17U)
3381 #define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
3382 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
3383 #define EXTI_FTSR_TR18_Pos                  (18U)
3384 #define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
3385 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
3386 
3387 /* References Defines */
3388 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
3389 #define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
3390 #define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
3391 #define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
3392 #define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
3393 #define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
3394 #define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
3395 #define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
3396 #define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
3397 #define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
3398 #define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
3399 #define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
3400 #define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
3401 #define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
3402 #define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
3403 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
3404 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
3405 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
3406 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
3407 
3408 /******************  Bit definition for EXTI_SWIER register  ******************/
3409 #define EXTI_SWIER_SWIER0_Pos               (0U)
3410 #define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
3411 #define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
3412 #define EXTI_SWIER_SWIER1_Pos               (1U)
3413 #define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
3414 #define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
3415 #define EXTI_SWIER_SWIER2_Pos               (2U)
3416 #define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
3417 #define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
3418 #define EXTI_SWIER_SWIER3_Pos               (3U)
3419 #define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
3420 #define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
3421 #define EXTI_SWIER_SWIER4_Pos               (4U)
3422 #define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
3423 #define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
3424 #define EXTI_SWIER_SWIER5_Pos               (5U)
3425 #define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
3426 #define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
3427 #define EXTI_SWIER_SWIER6_Pos               (6U)
3428 #define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
3429 #define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
3430 #define EXTI_SWIER_SWIER7_Pos               (7U)
3431 #define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
3432 #define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
3433 #define EXTI_SWIER_SWIER8_Pos               (8U)
3434 #define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
3435 #define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
3436 #define EXTI_SWIER_SWIER9_Pos               (9U)
3437 #define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
3438 #define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
3439 #define EXTI_SWIER_SWIER10_Pos              (10U)
3440 #define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
3441 #define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
3442 #define EXTI_SWIER_SWIER11_Pos              (11U)
3443 #define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
3444 #define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
3445 #define EXTI_SWIER_SWIER12_Pos              (12U)
3446 #define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
3447 #define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
3448 #define EXTI_SWIER_SWIER13_Pos              (13U)
3449 #define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
3450 #define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
3451 #define EXTI_SWIER_SWIER14_Pos              (14U)
3452 #define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
3453 #define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
3454 #define EXTI_SWIER_SWIER15_Pos              (15U)
3455 #define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
3456 #define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
3457 #define EXTI_SWIER_SWIER16_Pos              (16U)
3458 #define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
3459 #define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
3460 #define EXTI_SWIER_SWIER17_Pos              (17U)
3461 #define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
3462 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
3463 #define EXTI_SWIER_SWIER18_Pos              (18U)
3464 #define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
3465 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
3466 
3467 /* References Defines */
3468 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
3469 #define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
3470 #define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
3471 #define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
3472 #define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
3473 #define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
3474 #define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
3475 #define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
3476 #define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
3477 #define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
3478 #define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
3479 #define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
3480 #define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
3481 #define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
3482 #define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
3483 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
3484 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
3485 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
3486 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
3487 
3488 /*******************  Bit definition for EXTI_PR register  ********************/
3489 #define EXTI_PR_PR0_Pos                     (0U)
3490 #define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
3491 #define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
3492 #define EXTI_PR_PR1_Pos                     (1U)
3493 #define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
3494 #define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
3495 #define EXTI_PR_PR2_Pos                     (2U)
3496 #define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
3497 #define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
3498 #define EXTI_PR_PR3_Pos                     (3U)
3499 #define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
3500 #define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
3501 #define EXTI_PR_PR4_Pos                     (4U)
3502 #define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
3503 #define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
3504 #define EXTI_PR_PR5_Pos                     (5U)
3505 #define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
3506 #define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
3507 #define EXTI_PR_PR6_Pos                     (6U)
3508 #define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
3509 #define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
3510 #define EXTI_PR_PR7_Pos                     (7U)
3511 #define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
3512 #define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
3513 #define EXTI_PR_PR8_Pos                     (8U)
3514 #define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
3515 #define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
3516 #define EXTI_PR_PR9_Pos                     (9U)
3517 #define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
3518 #define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
3519 #define EXTI_PR_PR10_Pos                    (10U)
3520 #define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
3521 #define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
3522 #define EXTI_PR_PR11_Pos                    (11U)
3523 #define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
3524 #define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
3525 #define EXTI_PR_PR12_Pos                    (12U)
3526 #define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
3527 #define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
3528 #define EXTI_PR_PR13_Pos                    (13U)
3529 #define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
3530 #define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
3531 #define EXTI_PR_PR14_Pos                    (14U)
3532 #define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
3533 #define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
3534 #define EXTI_PR_PR15_Pos                    (15U)
3535 #define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
3536 #define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
3537 #define EXTI_PR_PR16_Pos                    (16U)
3538 #define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
3539 #define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
3540 #define EXTI_PR_PR17_Pos                    (17U)
3541 #define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
3542 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
3543 #define EXTI_PR_PR18_Pos                    (18U)
3544 #define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
3545 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
3546 
3547 /* References Defines */
3548 #define  EXTI_PR_PIF0 EXTI_PR_PR0
3549 #define  EXTI_PR_PIF1 EXTI_PR_PR1
3550 #define  EXTI_PR_PIF2 EXTI_PR_PR2
3551 #define  EXTI_PR_PIF3 EXTI_PR_PR3
3552 #define  EXTI_PR_PIF4 EXTI_PR_PR4
3553 #define  EXTI_PR_PIF5 EXTI_PR_PR5
3554 #define  EXTI_PR_PIF6 EXTI_PR_PR6
3555 #define  EXTI_PR_PIF7 EXTI_PR_PR7
3556 #define  EXTI_PR_PIF8 EXTI_PR_PR8
3557 #define  EXTI_PR_PIF9 EXTI_PR_PR9
3558 #define  EXTI_PR_PIF10 EXTI_PR_PR10
3559 #define  EXTI_PR_PIF11 EXTI_PR_PR11
3560 #define  EXTI_PR_PIF12 EXTI_PR_PR12
3561 #define  EXTI_PR_PIF13 EXTI_PR_PR13
3562 #define  EXTI_PR_PIF14 EXTI_PR_PR14
3563 #define  EXTI_PR_PIF15 EXTI_PR_PR15
3564 #define  EXTI_PR_PIF16 EXTI_PR_PR16
3565 #define  EXTI_PR_PIF17 EXTI_PR_PR17
3566 #define  EXTI_PR_PIF18 EXTI_PR_PR18
3567 
3568 /******************************************************************************/
3569 /*                                                                            */
3570 /*                             DMA Controller                                 */
3571 /*                                                                            */
3572 /******************************************************************************/
3573 
3574 /*******************  Bit definition for DMA_ISR register  ********************/
3575 #define DMA_ISR_GIF1_Pos                    (0U)
3576 #define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
3577 #define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
3578 #define DMA_ISR_TCIF1_Pos                   (1U)
3579 #define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
3580 #define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
3581 #define DMA_ISR_HTIF1_Pos                   (2U)
3582 #define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
3583 #define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
3584 #define DMA_ISR_TEIF1_Pos                   (3U)
3585 #define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
3586 #define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
3587 #define DMA_ISR_GIF2_Pos                    (4U)
3588 #define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
3589 #define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
3590 #define DMA_ISR_TCIF2_Pos                   (5U)
3591 #define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
3592 #define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
3593 #define DMA_ISR_HTIF2_Pos                   (6U)
3594 #define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
3595 #define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
3596 #define DMA_ISR_TEIF2_Pos                   (7U)
3597 #define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
3598 #define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
3599 #define DMA_ISR_GIF3_Pos                    (8U)
3600 #define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
3601 #define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
3602 #define DMA_ISR_TCIF3_Pos                   (9U)
3603 #define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
3604 #define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
3605 #define DMA_ISR_HTIF3_Pos                   (10U)
3606 #define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
3607 #define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
3608 #define DMA_ISR_TEIF3_Pos                   (11U)
3609 #define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
3610 #define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
3611 #define DMA_ISR_GIF4_Pos                    (12U)
3612 #define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
3613 #define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
3614 #define DMA_ISR_TCIF4_Pos                   (13U)
3615 #define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
3616 #define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
3617 #define DMA_ISR_HTIF4_Pos                   (14U)
3618 #define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
3619 #define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
3620 #define DMA_ISR_TEIF4_Pos                   (15U)
3621 #define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
3622 #define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
3623 #define DMA_ISR_GIF5_Pos                    (16U)
3624 #define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
3625 #define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
3626 #define DMA_ISR_TCIF5_Pos                   (17U)
3627 #define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
3628 #define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
3629 #define DMA_ISR_HTIF5_Pos                   (18U)
3630 #define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
3631 #define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
3632 #define DMA_ISR_TEIF5_Pos                   (19U)
3633 #define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
3634 #define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
3635 #define DMA_ISR_GIF6_Pos                    (20U)
3636 #define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
3637 #define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
3638 #define DMA_ISR_TCIF6_Pos                   (21U)
3639 #define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
3640 #define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
3641 #define DMA_ISR_HTIF6_Pos                   (22U)
3642 #define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
3643 #define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
3644 #define DMA_ISR_TEIF6_Pos                   (23U)
3645 #define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
3646 #define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
3647 #define DMA_ISR_GIF7_Pos                    (24U)
3648 #define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
3649 #define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
3650 #define DMA_ISR_TCIF7_Pos                   (25U)
3651 #define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
3652 #define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
3653 #define DMA_ISR_HTIF7_Pos                   (26U)
3654 #define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
3655 #define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
3656 #define DMA_ISR_TEIF7_Pos                   (27U)
3657 #define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
3658 #define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
3659 
3660 /*******************  Bit definition for DMA_IFCR register  *******************/
3661 #define DMA_IFCR_CGIF1_Pos                  (0U)
3662 #define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
3663 #define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
3664 #define DMA_IFCR_CTCIF1_Pos                 (1U)
3665 #define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
3666 #define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
3667 #define DMA_IFCR_CHTIF1_Pos                 (2U)
3668 #define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
3669 #define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
3670 #define DMA_IFCR_CTEIF1_Pos                 (3U)
3671 #define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
3672 #define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
3673 #define DMA_IFCR_CGIF2_Pos                  (4U)
3674 #define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
3675 #define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
3676 #define DMA_IFCR_CTCIF2_Pos                 (5U)
3677 #define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
3678 #define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
3679 #define DMA_IFCR_CHTIF2_Pos                 (6U)
3680 #define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
3681 #define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
3682 #define DMA_IFCR_CTEIF2_Pos                 (7U)
3683 #define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
3684 #define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
3685 #define DMA_IFCR_CGIF3_Pos                  (8U)
3686 #define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
3687 #define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
3688 #define DMA_IFCR_CTCIF3_Pos                 (9U)
3689 #define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
3690 #define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
3691 #define DMA_IFCR_CHTIF3_Pos                 (10U)
3692 #define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
3693 #define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
3694 #define DMA_IFCR_CTEIF3_Pos                 (11U)
3695 #define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
3696 #define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
3697 #define DMA_IFCR_CGIF4_Pos                  (12U)
3698 #define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
3699 #define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
3700 #define DMA_IFCR_CTCIF4_Pos                 (13U)
3701 #define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
3702 #define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
3703 #define DMA_IFCR_CHTIF4_Pos                 (14U)
3704 #define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
3705 #define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
3706 #define DMA_IFCR_CTEIF4_Pos                 (15U)
3707 #define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
3708 #define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
3709 #define DMA_IFCR_CGIF5_Pos                  (16U)
3710 #define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
3711 #define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
3712 #define DMA_IFCR_CTCIF5_Pos                 (17U)
3713 #define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
3714 #define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
3715 #define DMA_IFCR_CHTIF5_Pos                 (18U)
3716 #define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
3717 #define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
3718 #define DMA_IFCR_CTEIF5_Pos                 (19U)
3719 #define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
3720 #define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
3721 #define DMA_IFCR_CGIF6_Pos                  (20U)
3722 #define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
3723 #define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
3724 #define DMA_IFCR_CTCIF6_Pos                 (21U)
3725 #define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
3726 #define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
3727 #define DMA_IFCR_CHTIF6_Pos                 (22U)
3728 #define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
3729 #define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
3730 #define DMA_IFCR_CTEIF6_Pos                 (23U)
3731 #define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
3732 #define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
3733 #define DMA_IFCR_CGIF7_Pos                  (24U)
3734 #define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
3735 #define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
3736 #define DMA_IFCR_CTCIF7_Pos                 (25U)
3737 #define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
3738 #define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
3739 #define DMA_IFCR_CHTIF7_Pos                 (26U)
3740 #define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
3741 #define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
3742 #define DMA_IFCR_CTEIF7_Pos                 (27U)
3743 #define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
3744 #define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
3745 
3746 /*******************  Bit definition for DMA_CCR register   *******************/
3747 #define DMA_CCR_EN_Pos                      (0U)
3748 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
3749 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable */
3750 #define DMA_CCR_TCIE_Pos                    (1U)
3751 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
3752 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
3753 #define DMA_CCR_HTIE_Pos                    (2U)
3754 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
3755 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
3756 #define DMA_CCR_TEIE_Pos                    (3U)
3757 #define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
3758 #define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
3759 #define DMA_CCR_DIR_Pos                     (4U)
3760 #define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
3761 #define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
3762 #define DMA_CCR_CIRC_Pos                    (5U)
3763 #define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
3764 #define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
3765 #define DMA_CCR_PINC_Pos                    (6U)
3766 #define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
3767 #define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
3768 #define DMA_CCR_MINC_Pos                    (7U)
3769 #define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
3770 #define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
3771 
3772 #define DMA_CCR_PSIZE_Pos                   (8U)
3773 #define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
3774 #define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
3775 #define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
3776 #define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
3777 
3778 #define DMA_CCR_MSIZE_Pos                   (10U)
3779 #define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
3780 #define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
3781 #define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
3782 #define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
3783 
3784 #define DMA_CCR_PL_Pos                      (12U)
3785 #define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
3786 #define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
3787 #define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
3788 #define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
3789 
3790 #define DMA_CCR_MEM2MEM_Pos                 (14U)
3791 #define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
3792 #define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
3793 
3794 /******************  Bit definition for DMA_CNDTR  register  ******************/
3795 #define DMA_CNDTR_NDT_Pos                   (0U)
3796 #define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
3797 #define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
3798 
3799 /******************  Bit definition for DMA_CPAR  register  *******************/
3800 #define DMA_CPAR_PA_Pos                     (0U)
3801 #define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
3802 #define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
3803 
3804 /******************  Bit definition for DMA_CMAR  register  *******************/
3805 #define DMA_CMAR_MA_Pos                     (0U)
3806 #define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
3807 #define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
3808 
3809 /******************************************************************************/
3810 /*                                                                            */
3811 /*                      Analog to Digital Converter (ADC)                     */
3812 /*                                                                            */
3813 /******************************************************************************/
3814 
3815 /*
3816  * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3817  */
3818 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3819 
3820 /********************  Bit definition for ADC_SR register  ********************/
3821 #define ADC_SR_AWD_Pos                      (0U)
3822 #define ADC_SR_AWD_Msk                      (0x1UL << ADC_SR_AWD_Pos)           /*!< 0x00000001 */
3823 #define ADC_SR_AWD                          ADC_SR_AWD_Msk                     /*!< ADC analog watchdog 1 flag */
3824 #define ADC_SR_EOS_Pos                      (1U)
3825 #define ADC_SR_EOS_Msk                      (0x1UL << ADC_SR_EOS_Pos)           /*!< 0x00000002 */
3826 #define ADC_SR_EOS                          ADC_SR_EOS_Msk                     /*!< ADC group regular end of sequence conversions flag */
3827 #define ADC_SR_JEOS_Pos                     (2U)
3828 #define ADC_SR_JEOS_Msk                     (0x1UL << ADC_SR_JEOS_Pos)          /*!< 0x00000004 */
3829 #define ADC_SR_JEOS                         ADC_SR_JEOS_Msk                    /*!< ADC group injected end of sequence conversions flag */
3830 #define ADC_SR_JSTRT_Pos                    (3U)
3831 #define ADC_SR_JSTRT_Msk                    (0x1UL << ADC_SR_JSTRT_Pos)         /*!< 0x00000008 */
3832 #define ADC_SR_JSTRT                        ADC_SR_JSTRT_Msk                   /*!< ADC group injected conversion start flag */
3833 #define ADC_SR_STRT_Pos                     (4U)
3834 #define ADC_SR_STRT_Msk                     (0x1UL << ADC_SR_STRT_Pos)          /*!< 0x00000010 */
3835 #define ADC_SR_STRT                         ADC_SR_STRT_Msk                    /*!< ADC group regular conversion start flag */
3836 
3837 /* Legacy defines */
3838 #define  ADC_SR_EOC                          (ADC_SR_EOS)
3839 #define  ADC_SR_JEOC                         (ADC_SR_JEOS)
3840 
3841 /*******************  Bit definition for ADC_CR1 register  ********************/
3842 #define ADC_CR1_AWDCH_Pos                   (0U)
3843 #define ADC_CR1_AWDCH_Msk                   (0x1FUL << ADC_CR1_AWDCH_Pos)       /*!< 0x0000001F */
3844 #define ADC_CR1_AWDCH                       ADC_CR1_AWDCH_Msk                  /*!< ADC analog watchdog 1 monitored channel selection */
3845 #define ADC_CR1_AWDCH_0                     (0x01UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000001 */
3846 #define ADC_CR1_AWDCH_1                     (0x02UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000002 */
3847 #define ADC_CR1_AWDCH_2                     (0x04UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000004 */
3848 #define ADC_CR1_AWDCH_3                     (0x08UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000008 */
3849 #define ADC_CR1_AWDCH_4                     (0x10UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000010 */
3850 
3851 #define ADC_CR1_EOSIE_Pos                   (5U)
3852 #define ADC_CR1_EOSIE_Msk                   (0x1UL << ADC_CR1_EOSIE_Pos)        /*!< 0x00000020 */
3853 #define ADC_CR1_EOSIE                       ADC_CR1_EOSIE_Msk                  /*!< ADC group regular end of sequence conversions interrupt */
3854 #define ADC_CR1_AWDIE_Pos                   (6U)
3855 #define ADC_CR1_AWDIE_Msk                   (0x1UL << ADC_CR1_AWDIE_Pos)        /*!< 0x00000040 */
3856 #define ADC_CR1_AWDIE                       ADC_CR1_AWDIE_Msk                  /*!< ADC analog watchdog 1 interrupt */
3857 #define ADC_CR1_JEOSIE_Pos                  (7U)
3858 #define ADC_CR1_JEOSIE_Msk                  (0x1UL << ADC_CR1_JEOSIE_Pos)       /*!< 0x00000080 */
3859 #define ADC_CR1_JEOSIE                      ADC_CR1_JEOSIE_Msk                 /*!< ADC group injected end of sequence conversions interrupt */
3860 #define ADC_CR1_SCAN_Pos                    (8U)
3861 #define ADC_CR1_SCAN_Msk                    (0x1UL << ADC_CR1_SCAN_Pos)         /*!< 0x00000100 */
3862 #define ADC_CR1_SCAN                        ADC_CR1_SCAN_Msk                   /*!< ADC scan mode */
3863 #define ADC_CR1_AWDSGL_Pos                  (9U)
3864 #define ADC_CR1_AWDSGL_Msk                  (0x1UL << ADC_CR1_AWDSGL_Pos)       /*!< 0x00000200 */
3865 #define ADC_CR1_AWDSGL                      ADC_CR1_AWDSGL_Msk                 /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3866 #define ADC_CR1_JAUTO_Pos                   (10U)
3867 #define ADC_CR1_JAUTO_Msk                   (0x1UL << ADC_CR1_JAUTO_Pos)        /*!< 0x00000400 */
3868 #define ADC_CR1_JAUTO                       ADC_CR1_JAUTO_Msk                  /*!< ADC group injected automatic trigger mode */
3869 #define ADC_CR1_DISCEN_Pos                  (11U)
3870 #define ADC_CR1_DISCEN_Msk                  (0x1UL << ADC_CR1_DISCEN_Pos)       /*!< 0x00000800 */
3871 #define ADC_CR1_DISCEN                      ADC_CR1_DISCEN_Msk                 /*!< ADC group regular sequencer discontinuous mode */
3872 #define ADC_CR1_JDISCEN_Pos                 (12U)
3873 #define ADC_CR1_JDISCEN_Msk                 (0x1UL << ADC_CR1_JDISCEN_Pos)      /*!< 0x00001000 */
3874 #define ADC_CR1_JDISCEN                     ADC_CR1_JDISCEN_Msk                /*!< ADC group injected sequencer discontinuous mode */
3875 
3876 #define ADC_CR1_DISCNUM_Pos                 (13U)
3877 #define ADC_CR1_DISCNUM_Msk                 (0x7UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x0000E000 */
3878 #define ADC_CR1_DISCNUM                     ADC_CR1_DISCNUM_Msk                /*!< ADC group regular sequencer discontinuous number of ranks */
3879 #define ADC_CR1_DISCNUM_0                   (0x1UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00002000 */
3880 #define ADC_CR1_DISCNUM_1                   (0x2UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00004000 */
3881 #define ADC_CR1_DISCNUM_2                   (0x4UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00008000 */
3882 
3883 #define ADC_CR1_DUALMOD_Pos                 (16U)
3884 #define ADC_CR1_DUALMOD_Msk                 (0xFUL << ADC_CR1_DUALMOD_Pos)      /*!< 0x000F0000 */
3885 #define ADC_CR1_DUALMOD                     ADC_CR1_DUALMOD_Msk                /*!< ADC multimode mode selection */
3886 #define ADC_CR1_DUALMOD_0                   (0x1UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00010000 */
3887 #define ADC_CR1_DUALMOD_1                   (0x2UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00020000 */
3888 #define ADC_CR1_DUALMOD_2                   (0x4UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00040000 */
3889 #define ADC_CR1_DUALMOD_3                   (0x8UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00080000 */
3890 
3891 #define ADC_CR1_JAWDEN_Pos                  (22U)
3892 #define ADC_CR1_JAWDEN_Msk                  (0x1UL << ADC_CR1_JAWDEN_Pos)       /*!< 0x00400000 */
3893 #define ADC_CR1_JAWDEN                      ADC_CR1_JAWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3894 #define ADC_CR1_AWDEN_Pos                   (23U)
3895 #define ADC_CR1_AWDEN_Msk                   (0x1UL << ADC_CR1_AWDEN_Pos)        /*!< 0x00800000 */
3896 #define ADC_CR1_AWDEN                       ADC_CR1_AWDEN_Msk                  /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3897 
3898 /* Legacy defines */
3899 #define  ADC_CR1_EOCIE                       (ADC_CR1_EOSIE)
3900 #define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
3901 
3902 /*******************  Bit definition for ADC_CR2 register  ********************/
3903 #define ADC_CR2_ADON_Pos                    (0U)
3904 #define ADC_CR2_ADON_Msk                    (0x1UL << ADC_CR2_ADON_Pos)         /*!< 0x00000001 */
3905 #define ADC_CR2_ADON                        ADC_CR2_ADON_Msk                   /*!< ADC enable */
3906 #define ADC_CR2_CONT_Pos                    (1U)
3907 #define ADC_CR2_CONT_Msk                    (0x1UL << ADC_CR2_CONT_Pos)         /*!< 0x00000002 */
3908 #define ADC_CR2_CONT                        ADC_CR2_CONT_Msk                   /*!< ADC group regular continuous conversion mode */
3909 #define ADC_CR2_CAL_Pos                     (2U)
3910 #define ADC_CR2_CAL_Msk                     (0x1UL << ADC_CR2_CAL_Pos)          /*!< 0x00000004 */
3911 #define ADC_CR2_CAL                         ADC_CR2_CAL_Msk                    /*!< ADC calibration start */
3912 #define ADC_CR2_RSTCAL_Pos                  (3U)
3913 #define ADC_CR2_RSTCAL_Msk                  (0x1UL << ADC_CR2_RSTCAL_Pos)       /*!< 0x00000008 */
3914 #define ADC_CR2_RSTCAL                      ADC_CR2_RSTCAL_Msk                 /*!< ADC calibration reset */
3915 #define ADC_CR2_DMA_Pos                     (8U)
3916 #define ADC_CR2_DMA_Msk                     (0x1UL << ADC_CR2_DMA_Pos)          /*!< 0x00000100 */
3917 #define ADC_CR2_DMA                         ADC_CR2_DMA_Msk                    /*!< ADC DMA transfer enable */
3918 #define ADC_CR2_ALIGN_Pos                   (11U)
3919 #define ADC_CR2_ALIGN_Msk                   (0x1UL << ADC_CR2_ALIGN_Pos)        /*!< 0x00000800 */
3920 #define ADC_CR2_ALIGN                       ADC_CR2_ALIGN_Msk                  /*!< ADC data alignment */
3921 
3922 #define ADC_CR2_JEXTSEL_Pos                 (12U)
3923 #define ADC_CR2_JEXTSEL_Msk                 (0x7UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00007000 */
3924 #define ADC_CR2_JEXTSEL                     ADC_CR2_JEXTSEL_Msk                /*!< ADC group injected external trigger source */
3925 #define ADC_CR2_JEXTSEL_0                   (0x1UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00001000 */
3926 #define ADC_CR2_JEXTSEL_1                   (0x2UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00002000 */
3927 #define ADC_CR2_JEXTSEL_2                   (0x4UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00004000 */
3928 
3929 #define ADC_CR2_JEXTTRIG_Pos                (15U)
3930 #define ADC_CR2_JEXTTRIG_Msk                (0x1UL << ADC_CR2_JEXTTRIG_Pos)     /*!< 0x00008000 */
3931 #define ADC_CR2_JEXTTRIG                    ADC_CR2_JEXTTRIG_Msk               /*!< ADC group injected external trigger enable */
3932 
3933 #define ADC_CR2_EXTSEL_Pos                  (17U)
3934 #define ADC_CR2_EXTSEL_Msk                  (0x7UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x000E0000 */
3935 #define ADC_CR2_EXTSEL                      ADC_CR2_EXTSEL_Msk                 /*!< ADC group regular external trigger source */
3936 #define ADC_CR2_EXTSEL_0                    (0x1UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00020000 */
3937 #define ADC_CR2_EXTSEL_1                    (0x2UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00040000 */
3938 #define ADC_CR2_EXTSEL_2                    (0x4UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00080000 */
3939 
3940 #define ADC_CR2_EXTTRIG_Pos                 (20U)
3941 #define ADC_CR2_EXTTRIG_Msk                 (0x1UL << ADC_CR2_EXTTRIG_Pos)      /*!< 0x00100000 */
3942 #define ADC_CR2_EXTTRIG                     ADC_CR2_EXTTRIG_Msk                /*!< ADC group regular external trigger enable */
3943 #define ADC_CR2_JSWSTART_Pos                (21U)
3944 #define ADC_CR2_JSWSTART_Msk                (0x1UL << ADC_CR2_JSWSTART_Pos)     /*!< 0x00200000 */
3945 #define ADC_CR2_JSWSTART                    ADC_CR2_JSWSTART_Msk               /*!< ADC group injected conversion start */
3946 #define ADC_CR2_SWSTART_Pos                 (22U)
3947 #define ADC_CR2_SWSTART_Msk                 (0x1UL << ADC_CR2_SWSTART_Pos)      /*!< 0x00400000 */
3948 #define ADC_CR2_SWSTART                     ADC_CR2_SWSTART_Msk                /*!< ADC group regular conversion start */
3949 #define ADC_CR2_TSVREFE_Pos                 (23U)
3950 #define ADC_CR2_TSVREFE_Msk                 (0x1UL << ADC_CR2_TSVREFE_Pos)      /*!< 0x00800000 */
3951 #define ADC_CR2_TSVREFE                     ADC_CR2_TSVREFE_Msk                /*!< ADC internal path to VrefInt and temperature sensor enable */
3952 
3953 /******************  Bit definition for ADC_SMPR1 register  *******************/
3954 #define ADC_SMPR1_SMP10_Pos                 (0U)
3955 #define ADC_SMPR1_SMP10_Msk                 (0x7UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000007 */
3956 #define ADC_SMPR1_SMP10                     ADC_SMPR1_SMP10_Msk                /*!< ADC channel 10 sampling time selection  */
3957 #define ADC_SMPR1_SMP10_0                   (0x1UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000001 */
3958 #define ADC_SMPR1_SMP10_1                   (0x2UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000002 */
3959 #define ADC_SMPR1_SMP10_2                   (0x4UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000004 */
3960 
3961 #define ADC_SMPR1_SMP11_Pos                 (3U)
3962 #define ADC_SMPR1_SMP11_Msk                 (0x7UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000038 */
3963 #define ADC_SMPR1_SMP11                     ADC_SMPR1_SMP11_Msk                /*!< ADC channel 11 sampling time selection  */
3964 #define ADC_SMPR1_SMP11_0                   (0x1UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000008 */
3965 #define ADC_SMPR1_SMP11_1                   (0x2UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000010 */
3966 #define ADC_SMPR1_SMP11_2                   (0x4UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000020 */
3967 
3968 #define ADC_SMPR1_SMP12_Pos                 (6U)
3969 #define ADC_SMPR1_SMP12_Msk                 (0x7UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x000001C0 */
3970 #define ADC_SMPR1_SMP12                     ADC_SMPR1_SMP12_Msk                /*!< ADC channel 12 sampling time selection  */
3971 #define ADC_SMPR1_SMP12_0                   (0x1UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000040 */
3972 #define ADC_SMPR1_SMP12_1                   (0x2UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000080 */
3973 #define ADC_SMPR1_SMP12_2                   (0x4UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000100 */
3974 
3975 #define ADC_SMPR1_SMP13_Pos                 (9U)
3976 #define ADC_SMPR1_SMP13_Msk                 (0x7UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000E00 */
3977 #define ADC_SMPR1_SMP13                     ADC_SMPR1_SMP13_Msk                /*!< ADC channel 13 sampling time selection  */
3978 #define ADC_SMPR1_SMP13_0                   (0x1UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000200 */
3979 #define ADC_SMPR1_SMP13_1                   (0x2UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000400 */
3980 #define ADC_SMPR1_SMP13_2                   (0x4UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000800 */
3981 
3982 #define ADC_SMPR1_SMP14_Pos                 (12U)
3983 #define ADC_SMPR1_SMP14_Msk                 (0x7UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00007000 */
3984 #define ADC_SMPR1_SMP14                     ADC_SMPR1_SMP14_Msk                /*!< ADC channel 14 sampling time selection  */
3985 #define ADC_SMPR1_SMP14_0                   (0x1UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00001000 */
3986 #define ADC_SMPR1_SMP14_1                   (0x2UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00002000 */
3987 #define ADC_SMPR1_SMP14_2                   (0x4UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00004000 */
3988 
3989 #define ADC_SMPR1_SMP15_Pos                 (15U)
3990 #define ADC_SMPR1_SMP15_Msk                 (0x7UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00038000 */
3991 #define ADC_SMPR1_SMP15                     ADC_SMPR1_SMP15_Msk                /*!< ADC channel 15 sampling time selection  */
3992 #define ADC_SMPR1_SMP15_0                   (0x1UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00008000 */
3993 #define ADC_SMPR1_SMP15_1                   (0x2UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00010000 */
3994 #define ADC_SMPR1_SMP15_2                   (0x4UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00020000 */
3995 
3996 #define ADC_SMPR1_SMP16_Pos                 (18U)
3997 #define ADC_SMPR1_SMP16_Msk                 (0x7UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x001C0000 */
3998 #define ADC_SMPR1_SMP16                     ADC_SMPR1_SMP16_Msk                /*!< ADC channel 16 sampling time selection  */
3999 #define ADC_SMPR1_SMP16_0                   (0x1UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00040000 */
4000 #define ADC_SMPR1_SMP16_1                   (0x2UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00080000 */
4001 #define ADC_SMPR1_SMP16_2                   (0x4UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00100000 */
4002 
4003 #define ADC_SMPR1_SMP17_Pos                 (21U)
4004 #define ADC_SMPR1_SMP17_Msk                 (0x7UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00E00000 */
4005 #define ADC_SMPR1_SMP17                     ADC_SMPR1_SMP17_Msk                /*!< ADC channel 17 sampling time selection  */
4006 #define ADC_SMPR1_SMP17_0                   (0x1UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00200000 */
4007 #define ADC_SMPR1_SMP17_1                   (0x2UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00400000 */
4008 #define ADC_SMPR1_SMP17_2                   (0x4UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00800000 */
4009 
4010 /******************  Bit definition for ADC_SMPR2 register  *******************/
4011 #define ADC_SMPR2_SMP0_Pos                  (0U)
4012 #define ADC_SMPR2_SMP0_Msk                  (0x7UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000007 */
4013 #define ADC_SMPR2_SMP0                      ADC_SMPR2_SMP0_Msk                 /*!< ADC channel 0 sampling time selection  */
4014 #define ADC_SMPR2_SMP0_0                    (0x1UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000001 */
4015 #define ADC_SMPR2_SMP0_1                    (0x2UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000002 */
4016 #define ADC_SMPR2_SMP0_2                    (0x4UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000004 */
4017 
4018 #define ADC_SMPR2_SMP1_Pos                  (3U)
4019 #define ADC_SMPR2_SMP1_Msk                  (0x7UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000038 */
4020 #define ADC_SMPR2_SMP1                      ADC_SMPR2_SMP1_Msk                 /*!< ADC channel 1 sampling time selection  */
4021 #define ADC_SMPR2_SMP1_0                    (0x1UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000008 */
4022 #define ADC_SMPR2_SMP1_1                    (0x2UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000010 */
4023 #define ADC_SMPR2_SMP1_2                    (0x4UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000020 */
4024 
4025 #define ADC_SMPR2_SMP2_Pos                  (6U)
4026 #define ADC_SMPR2_SMP2_Msk                  (0x7UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x000001C0 */
4027 #define ADC_SMPR2_SMP2                      ADC_SMPR2_SMP2_Msk                 /*!< ADC channel 2 sampling time selection  */
4028 #define ADC_SMPR2_SMP2_0                    (0x1UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000040 */
4029 #define ADC_SMPR2_SMP2_1                    (0x2UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000080 */
4030 #define ADC_SMPR2_SMP2_2                    (0x4UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000100 */
4031 
4032 #define ADC_SMPR2_SMP3_Pos                  (9U)
4033 #define ADC_SMPR2_SMP3_Msk                  (0x7UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000E00 */
4034 #define ADC_SMPR2_SMP3                      ADC_SMPR2_SMP3_Msk                 /*!< ADC channel 3 sampling time selection  */
4035 #define ADC_SMPR2_SMP3_0                    (0x1UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000200 */
4036 #define ADC_SMPR2_SMP3_1                    (0x2UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000400 */
4037 #define ADC_SMPR2_SMP3_2                    (0x4UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000800 */
4038 
4039 #define ADC_SMPR2_SMP4_Pos                  (12U)
4040 #define ADC_SMPR2_SMP4_Msk                  (0x7UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00007000 */
4041 #define ADC_SMPR2_SMP4                      ADC_SMPR2_SMP4_Msk                 /*!< ADC channel 4 sampling time selection  */
4042 #define ADC_SMPR2_SMP4_0                    (0x1UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00001000 */
4043 #define ADC_SMPR2_SMP4_1                    (0x2UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00002000 */
4044 #define ADC_SMPR2_SMP4_2                    (0x4UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00004000 */
4045 
4046 #define ADC_SMPR2_SMP5_Pos                  (15U)
4047 #define ADC_SMPR2_SMP5_Msk                  (0x7UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00038000 */
4048 #define ADC_SMPR2_SMP5                      ADC_SMPR2_SMP5_Msk                 /*!< ADC channel 5 sampling time selection  */
4049 #define ADC_SMPR2_SMP5_0                    (0x1UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00008000 */
4050 #define ADC_SMPR2_SMP5_1                    (0x2UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00010000 */
4051 #define ADC_SMPR2_SMP5_2                    (0x4UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00020000 */
4052 
4053 #define ADC_SMPR2_SMP6_Pos                  (18U)
4054 #define ADC_SMPR2_SMP6_Msk                  (0x7UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x001C0000 */
4055 #define ADC_SMPR2_SMP6                      ADC_SMPR2_SMP6_Msk                 /*!< ADC channel 6 sampling time selection  */
4056 #define ADC_SMPR2_SMP6_0                    (0x1UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00040000 */
4057 #define ADC_SMPR2_SMP6_1                    (0x2UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00080000 */
4058 #define ADC_SMPR2_SMP6_2                    (0x4UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00100000 */
4059 
4060 #define ADC_SMPR2_SMP7_Pos                  (21U)
4061 #define ADC_SMPR2_SMP7_Msk                  (0x7UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00E00000 */
4062 #define ADC_SMPR2_SMP7                      ADC_SMPR2_SMP7_Msk                 /*!< ADC channel 7 sampling time selection  */
4063 #define ADC_SMPR2_SMP7_0                    (0x1UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00200000 */
4064 #define ADC_SMPR2_SMP7_1                    (0x2UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00400000 */
4065 #define ADC_SMPR2_SMP7_2                    (0x4UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00800000 */
4066 
4067 #define ADC_SMPR2_SMP8_Pos                  (24U)
4068 #define ADC_SMPR2_SMP8_Msk                  (0x7UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x07000000 */
4069 #define ADC_SMPR2_SMP8                      ADC_SMPR2_SMP8_Msk                 /*!< ADC channel 8 sampling time selection  */
4070 #define ADC_SMPR2_SMP8_0                    (0x1UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x01000000 */
4071 #define ADC_SMPR2_SMP8_1                    (0x2UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x02000000 */
4072 #define ADC_SMPR2_SMP8_2                    (0x4UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x04000000 */
4073 
4074 #define ADC_SMPR2_SMP9_Pos                  (27U)
4075 #define ADC_SMPR2_SMP9_Msk                  (0x7UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x38000000 */
4076 #define ADC_SMPR2_SMP9                      ADC_SMPR2_SMP9_Msk                 /*!< ADC channel 9 sampling time selection  */
4077 #define ADC_SMPR2_SMP9_0                    (0x1UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x08000000 */
4078 #define ADC_SMPR2_SMP9_1                    (0x2UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x10000000 */
4079 #define ADC_SMPR2_SMP9_2                    (0x4UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x20000000 */
4080 
4081 /******************  Bit definition for ADC_JOFR1 register  *******************/
4082 #define ADC_JOFR1_JOFFSET1_Pos              (0U)
4083 #define ADC_JOFR1_JOFFSET1_Msk              (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
4084 #define ADC_JOFR1_JOFFSET1                  ADC_JOFR1_JOFFSET1_Msk             /*!< ADC group injected sequencer rank 1 offset value */
4085 
4086 /******************  Bit definition for ADC_JOFR2 register  *******************/
4087 #define ADC_JOFR2_JOFFSET2_Pos              (0U)
4088 #define ADC_JOFR2_JOFFSET2_Msk              (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
4089 #define ADC_JOFR2_JOFFSET2                  ADC_JOFR2_JOFFSET2_Msk             /*!< ADC group injected sequencer rank 2 offset value */
4090 
4091 /******************  Bit definition for ADC_JOFR3 register  *******************/
4092 #define ADC_JOFR3_JOFFSET3_Pos              (0U)
4093 #define ADC_JOFR3_JOFFSET3_Msk              (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
4094 #define ADC_JOFR3_JOFFSET3                  ADC_JOFR3_JOFFSET3_Msk             /*!< ADC group injected sequencer rank 3 offset value */
4095 
4096 /******************  Bit definition for ADC_JOFR4 register  *******************/
4097 #define ADC_JOFR4_JOFFSET4_Pos              (0U)
4098 #define ADC_JOFR4_JOFFSET4_Msk              (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
4099 #define ADC_JOFR4_JOFFSET4                  ADC_JOFR4_JOFFSET4_Msk             /*!< ADC group injected sequencer rank 4 offset value */
4100 
4101 /*******************  Bit definition for ADC_HTR register  ********************/
4102 #define ADC_HTR_HT_Pos                      (0U)
4103 #define ADC_HTR_HT_Msk                      (0xFFFUL << ADC_HTR_HT_Pos)         /*!< 0x00000FFF */
4104 #define ADC_HTR_HT                          ADC_HTR_HT_Msk                     /*!< ADC analog watchdog 1 threshold high */
4105 
4106 /*******************  Bit definition for ADC_LTR register  ********************/
4107 #define ADC_LTR_LT_Pos                      (0U)
4108 #define ADC_LTR_LT_Msk                      (0xFFFUL << ADC_LTR_LT_Pos)         /*!< 0x00000FFF */
4109 #define ADC_LTR_LT                          ADC_LTR_LT_Msk                     /*!< ADC analog watchdog 1 threshold low */
4110 
4111 /*******************  Bit definition for ADC_SQR1 register  *******************/
4112 #define ADC_SQR1_SQ13_Pos                   (0U)
4113 #define ADC_SQR1_SQ13_Msk                   (0x1FUL << ADC_SQR1_SQ13_Pos)       /*!< 0x0000001F */
4114 #define ADC_SQR1_SQ13                       ADC_SQR1_SQ13_Msk                  /*!< ADC group regular sequencer rank 13 */
4115 #define ADC_SQR1_SQ13_0                     (0x01UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000001 */
4116 #define ADC_SQR1_SQ13_1                     (0x02UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000002 */
4117 #define ADC_SQR1_SQ13_2                     (0x04UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000004 */
4118 #define ADC_SQR1_SQ13_3                     (0x08UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000008 */
4119 #define ADC_SQR1_SQ13_4                     (0x10UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000010 */
4120 
4121 #define ADC_SQR1_SQ14_Pos                   (5U)
4122 #define ADC_SQR1_SQ14_Msk                   (0x1FUL << ADC_SQR1_SQ14_Pos)       /*!< 0x000003E0 */
4123 #define ADC_SQR1_SQ14                       ADC_SQR1_SQ14_Msk                  /*!< ADC group regular sequencer rank 14 */
4124 #define ADC_SQR1_SQ14_0                     (0x01UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000020 */
4125 #define ADC_SQR1_SQ14_1                     (0x02UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000040 */
4126 #define ADC_SQR1_SQ14_2                     (0x04UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000080 */
4127 #define ADC_SQR1_SQ14_3                     (0x08UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000100 */
4128 #define ADC_SQR1_SQ14_4                     (0x10UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000200 */
4129 
4130 #define ADC_SQR1_SQ15_Pos                   (10U)
4131 #define ADC_SQR1_SQ15_Msk                   (0x1FUL << ADC_SQR1_SQ15_Pos)       /*!< 0x00007C00 */
4132 #define ADC_SQR1_SQ15                       ADC_SQR1_SQ15_Msk                  /*!< ADC group regular sequencer rank 15 */
4133 #define ADC_SQR1_SQ15_0                     (0x01UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000400 */
4134 #define ADC_SQR1_SQ15_1                     (0x02UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000800 */
4135 #define ADC_SQR1_SQ15_2                     (0x04UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00001000 */
4136 #define ADC_SQR1_SQ15_3                     (0x08UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00002000 */
4137 #define ADC_SQR1_SQ15_4                     (0x10UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00004000 */
4138 
4139 #define ADC_SQR1_SQ16_Pos                   (15U)
4140 #define ADC_SQR1_SQ16_Msk                   (0x1FUL << ADC_SQR1_SQ16_Pos)       /*!< 0x000F8000 */
4141 #define ADC_SQR1_SQ16                       ADC_SQR1_SQ16_Msk                  /*!< ADC group regular sequencer rank 16 */
4142 #define ADC_SQR1_SQ16_0                     (0x01UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00008000 */
4143 #define ADC_SQR1_SQ16_1                     (0x02UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00010000 */
4144 #define ADC_SQR1_SQ16_2                     (0x04UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00020000 */
4145 #define ADC_SQR1_SQ16_3                     (0x08UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00040000 */
4146 #define ADC_SQR1_SQ16_4                     (0x10UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00080000 */
4147 
4148 #define ADC_SQR1_L_Pos                      (20U)
4149 #define ADC_SQR1_L_Msk                      (0xFUL << ADC_SQR1_L_Pos)           /*!< 0x00F00000 */
4150 #define ADC_SQR1_L                          ADC_SQR1_L_Msk                     /*!< ADC group regular sequencer scan length */
4151 #define ADC_SQR1_L_0                        (0x1UL << ADC_SQR1_L_Pos)           /*!< 0x00100000 */
4152 #define ADC_SQR1_L_1                        (0x2UL << ADC_SQR1_L_Pos)           /*!< 0x00200000 */
4153 #define ADC_SQR1_L_2                        (0x4UL << ADC_SQR1_L_Pos)           /*!< 0x00400000 */
4154 #define ADC_SQR1_L_3                        (0x8UL << ADC_SQR1_L_Pos)           /*!< 0x00800000 */
4155 
4156 /*******************  Bit definition for ADC_SQR2 register  *******************/
4157 #define ADC_SQR2_SQ7_Pos                    (0U)
4158 #define ADC_SQR2_SQ7_Msk                    (0x1FUL << ADC_SQR2_SQ7_Pos)        /*!< 0x0000001F */
4159 #define ADC_SQR2_SQ7                        ADC_SQR2_SQ7_Msk                   /*!< ADC group regular sequencer rank 7 */
4160 #define ADC_SQR2_SQ7_0                      (0x01UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000001 */
4161 #define ADC_SQR2_SQ7_1                      (0x02UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000002 */
4162 #define ADC_SQR2_SQ7_2                      (0x04UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000004 */
4163 #define ADC_SQR2_SQ7_3                      (0x08UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000008 */
4164 #define ADC_SQR2_SQ7_4                      (0x10UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000010 */
4165 
4166 #define ADC_SQR2_SQ8_Pos                    (5U)
4167 #define ADC_SQR2_SQ8_Msk                    (0x1FUL << ADC_SQR2_SQ8_Pos)        /*!< 0x000003E0 */
4168 #define ADC_SQR2_SQ8                        ADC_SQR2_SQ8_Msk                   /*!< ADC group regular sequencer rank 8 */
4169 #define ADC_SQR2_SQ8_0                      (0x01UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000020 */
4170 #define ADC_SQR2_SQ8_1                      (0x02UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000040 */
4171 #define ADC_SQR2_SQ8_2                      (0x04UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000080 */
4172 #define ADC_SQR2_SQ8_3                      (0x08UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000100 */
4173 #define ADC_SQR2_SQ8_4                      (0x10UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000200 */
4174 
4175 #define ADC_SQR2_SQ9_Pos                    (10U)
4176 #define ADC_SQR2_SQ9_Msk                    (0x1FUL << ADC_SQR2_SQ9_Pos)        /*!< 0x00007C00 */
4177 #define ADC_SQR2_SQ9                        ADC_SQR2_SQ9_Msk                   /*!< ADC group regular sequencer rank 9 */
4178 #define ADC_SQR2_SQ9_0                      (0x01UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000400 */
4179 #define ADC_SQR2_SQ9_1                      (0x02UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000800 */
4180 #define ADC_SQR2_SQ9_2                      (0x04UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00001000 */
4181 #define ADC_SQR2_SQ9_3                      (0x08UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00002000 */
4182 #define ADC_SQR2_SQ9_4                      (0x10UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00004000 */
4183 
4184 #define ADC_SQR2_SQ10_Pos                   (15U)
4185 #define ADC_SQR2_SQ10_Msk                   (0x1FUL << ADC_SQR2_SQ10_Pos)       /*!< 0x000F8000 */
4186 #define ADC_SQR2_SQ10                       ADC_SQR2_SQ10_Msk                  /*!< ADC group regular sequencer rank 10 */
4187 #define ADC_SQR2_SQ10_0                     (0x01UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00008000 */
4188 #define ADC_SQR2_SQ10_1                     (0x02UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00010000 */
4189 #define ADC_SQR2_SQ10_2                     (0x04UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00020000 */
4190 #define ADC_SQR2_SQ10_3                     (0x08UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00040000 */
4191 #define ADC_SQR2_SQ10_4                     (0x10UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00080000 */
4192 
4193 #define ADC_SQR2_SQ11_Pos                   (20U)
4194 #define ADC_SQR2_SQ11_Msk                   (0x1FUL << ADC_SQR2_SQ11_Pos)       /*!< 0x01F00000 */
4195 #define ADC_SQR2_SQ11                       ADC_SQR2_SQ11_Msk                  /*!< ADC group regular sequencer rank 1 */
4196 #define ADC_SQR2_SQ11_0                     (0x01UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00100000 */
4197 #define ADC_SQR2_SQ11_1                     (0x02UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00200000 */
4198 #define ADC_SQR2_SQ11_2                     (0x04UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00400000 */
4199 #define ADC_SQR2_SQ11_3                     (0x08UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00800000 */
4200 #define ADC_SQR2_SQ11_4                     (0x10UL << ADC_SQR2_SQ11_Pos)       /*!< 0x01000000 */
4201 
4202 #define ADC_SQR2_SQ12_Pos                   (25U)
4203 #define ADC_SQR2_SQ12_Msk                   (0x1FUL << ADC_SQR2_SQ12_Pos)       /*!< 0x3E000000 */
4204 #define ADC_SQR2_SQ12                       ADC_SQR2_SQ12_Msk                  /*!< ADC group regular sequencer rank 12 */
4205 #define ADC_SQR2_SQ12_0                     (0x01UL << ADC_SQR2_SQ12_Pos)       /*!< 0x02000000 */
4206 #define ADC_SQR2_SQ12_1                     (0x02UL << ADC_SQR2_SQ12_Pos)       /*!< 0x04000000 */
4207 #define ADC_SQR2_SQ12_2                     (0x04UL << ADC_SQR2_SQ12_Pos)       /*!< 0x08000000 */
4208 #define ADC_SQR2_SQ12_3                     (0x08UL << ADC_SQR2_SQ12_Pos)       /*!< 0x10000000 */
4209 #define ADC_SQR2_SQ12_4                     (0x10UL << ADC_SQR2_SQ12_Pos)       /*!< 0x20000000 */
4210 
4211 /*******************  Bit definition for ADC_SQR3 register  *******************/
4212 #define ADC_SQR3_SQ1_Pos                    (0U)
4213 #define ADC_SQR3_SQ1_Msk                    (0x1FUL << ADC_SQR3_SQ1_Pos)        /*!< 0x0000001F */
4214 #define ADC_SQR3_SQ1                        ADC_SQR3_SQ1_Msk                   /*!< ADC group regular sequencer rank 1 */
4215 #define ADC_SQR3_SQ1_0                      (0x01UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000001 */
4216 #define ADC_SQR3_SQ1_1                      (0x02UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000002 */
4217 #define ADC_SQR3_SQ1_2                      (0x04UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000004 */
4218 #define ADC_SQR3_SQ1_3                      (0x08UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000008 */
4219 #define ADC_SQR3_SQ1_4                      (0x10UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000010 */
4220 
4221 #define ADC_SQR3_SQ2_Pos                    (5U)
4222 #define ADC_SQR3_SQ2_Msk                    (0x1FUL << ADC_SQR3_SQ2_Pos)        /*!< 0x000003E0 */
4223 #define ADC_SQR3_SQ2                        ADC_SQR3_SQ2_Msk                   /*!< ADC group regular sequencer rank 2 */
4224 #define ADC_SQR3_SQ2_0                      (0x01UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000020 */
4225 #define ADC_SQR3_SQ2_1                      (0x02UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000040 */
4226 #define ADC_SQR3_SQ2_2                      (0x04UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000080 */
4227 #define ADC_SQR3_SQ2_3                      (0x08UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000100 */
4228 #define ADC_SQR3_SQ2_4                      (0x10UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000200 */
4229 
4230 #define ADC_SQR3_SQ3_Pos                    (10U)
4231 #define ADC_SQR3_SQ3_Msk                    (0x1FUL << ADC_SQR3_SQ3_Pos)        /*!< 0x00007C00 */
4232 #define ADC_SQR3_SQ3                        ADC_SQR3_SQ3_Msk                   /*!< ADC group regular sequencer rank 3 */
4233 #define ADC_SQR3_SQ3_0                      (0x01UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000400 */
4234 #define ADC_SQR3_SQ3_1                      (0x02UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000800 */
4235 #define ADC_SQR3_SQ3_2                      (0x04UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00001000 */
4236 #define ADC_SQR3_SQ3_3                      (0x08UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00002000 */
4237 #define ADC_SQR3_SQ3_4                      (0x10UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00004000 */
4238 
4239 #define ADC_SQR3_SQ4_Pos                    (15U)
4240 #define ADC_SQR3_SQ4_Msk                    (0x1FUL << ADC_SQR3_SQ4_Pos)        /*!< 0x000F8000 */
4241 #define ADC_SQR3_SQ4                        ADC_SQR3_SQ4_Msk                   /*!< ADC group regular sequencer rank 4 */
4242 #define ADC_SQR3_SQ4_0                      (0x01UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00008000 */
4243 #define ADC_SQR3_SQ4_1                      (0x02UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00010000 */
4244 #define ADC_SQR3_SQ4_2                      (0x04UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00020000 */
4245 #define ADC_SQR3_SQ4_3                      (0x08UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00040000 */
4246 #define ADC_SQR3_SQ4_4                      (0x10UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00080000 */
4247 
4248 #define ADC_SQR3_SQ5_Pos                    (20U)
4249 #define ADC_SQR3_SQ5_Msk                    (0x1FUL << ADC_SQR3_SQ5_Pos)        /*!< 0x01F00000 */
4250 #define ADC_SQR3_SQ5                        ADC_SQR3_SQ5_Msk                   /*!< ADC group regular sequencer rank 5 */
4251 #define ADC_SQR3_SQ5_0                      (0x01UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00100000 */
4252 #define ADC_SQR3_SQ5_1                      (0x02UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00200000 */
4253 #define ADC_SQR3_SQ5_2                      (0x04UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00400000 */
4254 #define ADC_SQR3_SQ5_3                      (0x08UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00800000 */
4255 #define ADC_SQR3_SQ5_4                      (0x10UL << ADC_SQR3_SQ5_Pos)        /*!< 0x01000000 */
4256 
4257 #define ADC_SQR3_SQ6_Pos                    (25U)
4258 #define ADC_SQR3_SQ6_Msk                    (0x1FUL << ADC_SQR3_SQ6_Pos)        /*!< 0x3E000000 */
4259 #define ADC_SQR3_SQ6                        ADC_SQR3_SQ6_Msk                   /*!< ADC group regular sequencer rank 6 */
4260 #define ADC_SQR3_SQ6_0                      (0x01UL << ADC_SQR3_SQ6_Pos)        /*!< 0x02000000 */
4261 #define ADC_SQR3_SQ6_1                      (0x02UL << ADC_SQR3_SQ6_Pos)        /*!< 0x04000000 */
4262 #define ADC_SQR3_SQ6_2                      (0x04UL << ADC_SQR3_SQ6_Pos)        /*!< 0x08000000 */
4263 #define ADC_SQR3_SQ6_3                      (0x08UL << ADC_SQR3_SQ6_Pos)        /*!< 0x10000000 */
4264 #define ADC_SQR3_SQ6_4                      (0x10UL << ADC_SQR3_SQ6_Pos)        /*!< 0x20000000 */
4265 
4266 /*******************  Bit definition for ADC_JSQR register  *******************/
4267 #define ADC_JSQR_JSQ1_Pos                   (0U)
4268 #define ADC_JSQR_JSQ1_Msk                   (0x1FUL << ADC_JSQR_JSQ1_Pos)       /*!< 0x0000001F */
4269 #define ADC_JSQR_JSQ1                       ADC_JSQR_JSQ1_Msk                  /*!< ADC group injected sequencer rank 1 */
4270 #define ADC_JSQR_JSQ1_0                     (0x01UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000001 */
4271 #define ADC_JSQR_JSQ1_1                     (0x02UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000002 */
4272 #define ADC_JSQR_JSQ1_2                     (0x04UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000004 */
4273 #define ADC_JSQR_JSQ1_3                     (0x08UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000008 */
4274 #define ADC_JSQR_JSQ1_4                     (0x10UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000010 */
4275 
4276 #define ADC_JSQR_JSQ2_Pos                   (5U)
4277 #define ADC_JSQR_JSQ2_Msk                   (0x1FUL << ADC_JSQR_JSQ2_Pos)       /*!< 0x000003E0 */
4278 #define ADC_JSQR_JSQ2                       ADC_JSQR_JSQ2_Msk                  /*!< ADC group injected sequencer rank 2 */
4279 #define ADC_JSQR_JSQ2_0                     (0x01UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000020 */
4280 #define ADC_JSQR_JSQ2_1                     (0x02UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000040 */
4281 #define ADC_JSQR_JSQ2_2                     (0x04UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000080 */
4282 #define ADC_JSQR_JSQ2_3                     (0x08UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000100 */
4283 #define ADC_JSQR_JSQ2_4                     (0x10UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000200 */
4284 
4285 #define ADC_JSQR_JSQ3_Pos                   (10U)
4286 #define ADC_JSQR_JSQ3_Msk                   (0x1FUL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00007C00 */
4287 #define ADC_JSQR_JSQ3                       ADC_JSQR_JSQ3_Msk                  /*!< ADC group injected sequencer rank 3 */
4288 #define ADC_JSQR_JSQ3_0                     (0x01UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000400 */
4289 #define ADC_JSQR_JSQ3_1                     (0x02UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000800 */
4290 #define ADC_JSQR_JSQ3_2                     (0x04UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00001000 */
4291 #define ADC_JSQR_JSQ3_3                     (0x08UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00002000 */
4292 #define ADC_JSQR_JSQ3_4                     (0x10UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00004000 */
4293 
4294 #define ADC_JSQR_JSQ4_Pos                   (15U)
4295 #define ADC_JSQR_JSQ4_Msk                   (0x1FUL << ADC_JSQR_JSQ4_Pos)       /*!< 0x000F8000 */
4296 #define ADC_JSQR_JSQ4                       ADC_JSQR_JSQ4_Msk                  /*!< ADC group injected sequencer rank 4 */
4297 #define ADC_JSQR_JSQ4_0                     (0x01UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00008000 */
4298 #define ADC_JSQR_JSQ4_1                     (0x02UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00010000 */
4299 #define ADC_JSQR_JSQ4_2                     (0x04UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00020000 */
4300 #define ADC_JSQR_JSQ4_3                     (0x08UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00040000 */
4301 #define ADC_JSQR_JSQ4_4                     (0x10UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00080000 */
4302 
4303 #define ADC_JSQR_JL_Pos                     (20U)
4304 #define ADC_JSQR_JL_Msk                     (0x3UL << ADC_JSQR_JL_Pos)          /*!< 0x00300000 */
4305 #define ADC_JSQR_JL                         ADC_JSQR_JL_Msk                    /*!< ADC group injected sequencer scan length */
4306 #define ADC_JSQR_JL_0                       (0x1UL << ADC_JSQR_JL_Pos)          /*!< 0x00100000 */
4307 #define ADC_JSQR_JL_1                       (0x2UL << ADC_JSQR_JL_Pos)          /*!< 0x00200000 */
4308 
4309 /*******************  Bit definition for ADC_JDR1 register  *******************/
4310 #define ADC_JDR1_JDATA_Pos                  (0U)
4311 #define ADC_JDR1_JDATA_Msk                  (0xFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0x0000FFFF */
4312 #define ADC_JDR1_JDATA                      ADC_JDR1_JDATA_Msk                 /*!< ADC group injected sequencer rank 1 conversion data */
4313 
4314 /*******************  Bit definition for ADC_JDR2 register  *******************/
4315 #define ADC_JDR2_JDATA_Pos                  (0U)
4316 #define ADC_JDR2_JDATA_Msk                  (0xFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0x0000FFFF */
4317 #define ADC_JDR2_JDATA                      ADC_JDR2_JDATA_Msk                 /*!< ADC group injected sequencer rank 2 conversion data */
4318 
4319 /*******************  Bit definition for ADC_JDR3 register  *******************/
4320 #define ADC_JDR3_JDATA_Pos                  (0U)
4321 #define ADC_JDR3_JDATA_Msk                  (0xFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0x0000FFFF */
4322 #define ADC_JDR3_JDATA                      ADC_JDR3_JDATA_Msk                 /*!< ADC group injected sequencer rank 3 conversion data */
4323 
4324 /*******************  Bit definition for ADC_JDR4 register  *******************/
4325 #define ADC_JDR4_JDATA_Pos                  (0U)
4326 #define ADC_JDR4_JDATA_Msk                  (0xFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0x0000FFFF */
4327 #define ADC_JDR4_JDATA                      ADC_JDR4_JDATA_Msk                 /*!< ADC group injected sequencer rank 4 conversion data */
4328 
4329 /********************  Bit definition for ADC_DR register  ********************/
4330 #define ADC_DR_DATA_Pos                     (0U)
4331 #define ADC_DR_DATA_Msk                     (0xFFFFUL << ADC_DR_DATA_Pos)       /*!< 0x0000FFFF */
4332 #define ADC_DR_DATA                         ADC_DR_DATA_Msk                    /*!< ADC group regular conversion data */
4333 #define ADC_DR_ADC2DATA_Pos                 (16U)
4334 #define ADC_DR_ADC2DATA_Msk                 (0xFFFFUL << ADC_DR_ADC2DATA_Pos)   /*!< 0xFFFF0000 */
4335 #define ADC_DR_ADC2DATA                     ADC_DR_ADC2DATA_Msk                /*!< ADC group regular conversion data for ADC slave, in multimode */
4336 /******************************************************************************/
4337 /*                                                                            */
4338 /*                      Digital to Analog Converter                           */
4339 /*                                                                            */
4340 /******************************************************************************/
4341 
4342 /********************  Bit definition for DAC_CR register  ********************/
4343 #define DAC_CR_EN1_Pos                      (0U)
4344 #define DAC_CR_EN1_Msk                      (0x1UL << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
4345 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!< DAC channel1 enable */
4346 #define DAC_CR_BOFF1_Pos                    (1U)
4347 #define DAC_CR_BOFF1_Msk                    (0x1UL << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
4348 #define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!< DAC channel1 output buffer disable */
4349 #define DAC_CR_TEN1_Pos                     (2U)
4350 #define DAC_CR_TEN1_Msk                     (0x1UL << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
4351 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!< DAC channel1 Trigger enable */
4352 
4353 #define DAC_CR_TSEL1_Pos                    (3U)
4354 #define DAC_CR_TSEL1_Msk                    (0x7UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
4355 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
4356 #define DAC_CR_TSEL1_0                      (0x1UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
4357 #define DAC_CR_TSEL1_1                      (0x2UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
4358 #define DAC_CR_TSEL1_2                      (0x4UL << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
4359 
4360 #define DAC_CR_WAVE1_Pos                    (6U)
4361 #define DAC_CR_WAVE1_Msk                    (0x3UL << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
4362 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
4363 #define DAC_CR_WAVE1_0                      (0x1UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
4364 #define DAC_CR_WAVE1_1                      (0x2UL << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
4365 
4366 #define DAC_CR_MAMP1_Pos                    (8U)
4367 #define DAC_CR_MAMP1_Msk                    (0xFUL << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
4368 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
4369 #define DAC_CR_MAMP1_0                      (0x1UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
4370 #define DAC_CR_MAMP1_1                      (0x2UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
4371 #define DAC_CR_MAMP1_2                      (0x4UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
4372 #define DAC_CR_MAMP1_3                      (0x8UL << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
4373 
4374 #define DAC_CR_DMAEN1_Pos                   (12U)
4375 #define DAC_CR_DMAEN1_Msk                   (0x1UL << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
4376 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!< DAC channel1 DMA enable */
4377 #define DAC_CR_EN2_Pos                      (16U)
4378 #define DAC_CR_EN2_Msk                      (0x1UL << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
4379 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!< DAC channel2 enable */
4380 #define DAC_CR_BOFF2_Pos                    (17U)
4381 #define DAC_CR_BOFF2_Msk                    (0x1UL << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
4382 #define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!< DAC channel2 output buffer disable */
4383 #define DAC_CR_TEN2_Pos                     (18U)
4384 #define DAC_CR_TEN2_Msk                     (0x1UL << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
4385 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!< DAC channel2 Trigger enable */
4386 
4387 #define DAC_CR_TSEL2_Pos                    (19U)
4388 #define DAC_CR_TSEL2_Msk                    (0x7UL << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
4389 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
4390 #define DAC_CR_TSEL2_0                      (0x1UL << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
4391 #define DAC_CR_TSEL2_1                      (0x2UL << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
4392 #define DAC_CR_TSEL2_2                      (0x4UL << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
4393 
4394 #define DAC_CR_WAVE2_Pos                    (22U)
4395 #define DAC_CR_WAVE2_Msk                    (0x3UL << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
4396 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
4397 #define DAC_CR_WAVE2_0                      (0x1UL << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
4398 #define DAC_CR_WAVE2_1                      (0x2UL << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
4399 
4400 #define DAC_CR_MAMP2_Pos                    (24U)
4401 #define DAC_CR_MAMP2_Msk                    (0xFUL << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
4402 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
4403 #define DAC_CR_MAMP2_0                      (0x1UL << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
4404 #define DAC_CR_MAMP2_1                      (0x2UL << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
4405 #define DAC_CR_MAMP2_2                      (0x4UL << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
4406 #define DAC_CR_MAMP2_3                      (0x8UL << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
4407 
4408 #define DAC_CR_DMAEN2_Pos                   (28U)
4409 #define DAC_CR_DMAEN2_Msk                   (0x1UL << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
4410 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!< DAC channel2 DMA enabled */
4411 
4412 
4413 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
4414 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
4415 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
4416 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!< DAC channel1 software trigger */
4417 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
4418 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
4419 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!< DAC channel2 software trigger */
4420 
4421 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
4422 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
4423 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
4424 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!< DAC channel1 12-bit Right aligned data */
4425 
4426 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
4427 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
4428 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
4429 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!< DAC channel1 12-bit Left aligned data */
4430 
4431 /******************  Bit definition for DAC_DHR8R1 register  ******************/
4432 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
4433 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
4434 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!< DAC channel1 8-bit Right aligned data */
4435 
4436 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
4437 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
4438 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
4439 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!< DAC channel2 12-bit Right aligned data */
4440 
4441 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
4442 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
4443 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
4444 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!< DAC channel2 12-bit Left aligned data */
4445 
4446 /******************  Bit definition for DAC_DHR8R2 register  ******************/
4447 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
4448 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
4449 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!< DAC channel2 8-bit Right aligned data */
4450 
4451 /*****************  Bit definition for DAC_DHR12RD register  ******************/
4452 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
4453 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
4454 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!< DAC channel1 12-bit Right aligned data */
4455 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
4456 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
4457 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!< DAC channel2 12-bit Right aligned data */
4458 
4459 /*****************  Bit definition for DAC_DHR12LD register  ******************/
4460 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
4461 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
4462 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!< DAC channel1 12-bit Left aligned data */
4463 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
4464 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
4465 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!< DAC channel2 12-bit Left aligned data */
4466 
4467 /******************  Bit definition for DAC_DHR8RD register  ******************/
4468 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
4469 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
4470 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!< DAC channel1 8-bit Right aligned data */
4471 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
4472 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
4473 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!< DAC channel2 8-bit Right aligned data */
4474 
4475 /*******************  Bit definition for DAC_DOR1 register  *******************/
4476 #define DAC_DOR1_DACC1DOR_Pos               (0U)
4477 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
4478 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!< DAC channel1 data output */
4479 
4480 /*******************  Bit definition for DAC_DOR2 register  *******************/
4481 #define DAC_DOR2_DACC2DOR_Pos               (0U)
4482 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
4483 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!< DAC channel2 data output */
4484 
4485 
4486 
4487 /*****************************************************************************/
4488 /*                                                                           */
4489 /*                               Timers (TIM)                                */
4490 /*                                                                           */
4491 /*****************************************************************************/
4492 /*******************  Bit definition for TIM_CR1 register  *******************/
4493 #define TIM_CR1_CEN_Pos                     (0U)
4494 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
4495 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
4496 #define TIM_CR1_UDIS_Pos                    (1U)
4497 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
4498 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
4499 #define TIM_CR1_URS_Pos                     (2U)
4500 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
4501 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
4502 #define TIM_CR1_OPM_Pos                     (3U)
4503 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
4504 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
4505 #define TIM_CR1_DIR_Pos                     (4U)
4506 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
4507 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
4508 
4509 #define TIM_CR1_CMS_Pos                     (5U)
4510 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
4511 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
4512 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
4513 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
4514 
4515 #define TIM_CR1_ARPE_Pos                    (7U)
4516 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
4517 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
4518 
4519 #define TIM_CR1_CKD_Pos                     (8U)
4520 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
4521 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
4522 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
4523 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
4524 
4525 /*******************  Bit definition for TIM_CR2 register  *******************/
4526 #define TIM_CR2_CCPC_Pos                    (0U)
4527 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)         /*!< 0x00000001 */
4528 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                   /*!<Capture/Compare Preloaded Control */
4529 #define TIM_CR2_CCUS_Pos                    (2U)
4530 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)         /*!< 0x00000004 */
4531 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                   /*!<Capture/Compare Control Update Selection */
4532 #define TIM_CR2_CCDS_Pos                    (3U)
4533 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
4534 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
4535 
4536 #define TIM_CR2_MMS_Pos                     (4U)
4537 #define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
4538 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
4539 #define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
4540 #define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
4541 #define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
4542 
4543 #define TIM_CR2_TI1S_Pos                    (7U)
4544 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
4545 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
4546 #define TIM_CR2_OIS1_Pos                    (8U)
4547 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)         /*!< 0x00000100 */
4548 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                   /*!<Output Idle state 1 (OC1 output) */
4549 #define TIM_CR2_OIS1N_Pos                   (9U)
4550 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)        /*!< 0x00000200 */
4551 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                  /*!<Output Idle state 1 (OC1N output) */
4552 #define TIM_CR2_OIS2_Pos                    (10U)
4553 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)         /*!< 0x00000400 */
4554 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                   /*!<Output Idle state 2 (OC2 output) */
4555 #define TIM_CR2_OIS2N_Pos                   (11U)
4556 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)        /*!< 0x00000800 */
4557 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                  /*!<Output Idle state 2 (OC2N output) */
4558 #define TIM_CR2_OIS3_Pos                    (12U)
4559 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)         /*!< 0x00001000 */
4560 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                   /*!<Output Idle state 3 (OC3 output) */
4561 #define TIM_CR2_OIS3N_Pos                   (13U)
4562 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)        /*!< 0x00002000 */
4563 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                  /*!<Output Idle state 3 (OC3N output) */
4564 #define TIM_CR2_OIS4_Pos                    (14U)
4565 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)         /*!< 0x00004000 */
4566 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                   /*!<Output Idle state 4 (OC4 output) */
4567 
4568 /*******************  Bit definition for TIM_SMCR register  ******************/
4569 #define TIM_SMCR_SMS_Pos                    (0U)
4570 #define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
4571 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
4572 #define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
4573 #define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
4574 #define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
4575 
4576 #define TIM_SMCR_TS_Pos                     (4U)
4577 #define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
4578 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
4579 #define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
4580 #define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
4581 #define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
4582 
4583 #define TIM_SMCR_MSM_Pos                    (7U)
4584 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
4585 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
4586 
4587 #define TIM_SMCR_ETF_Pos                    (8U)
4588 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
4589 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
4590 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
4591 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
4592 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
4593 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
4594 
4595 #define TIM_SMCR_ETPS_Pos                   (12U)
4596 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
4597 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
4598 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
4599 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
4600 
4601 #define TIM_SMCR_ECE_Pos                    (14U)
4602 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
4603 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
4604 #define TIM_SMCR_ETP_Pos                    (15U)
4605 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
4606 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
4607 
4608 /*******************  Bit definition for TIM_DIER register  ******************/
4609 #define TIM_DIER_UIE_Pos                    (0U)
4610 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
4611 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
4612 #define TIM_DIER_CC1IE_Pos                  (1U)
4613 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
4614 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
4615 #define TIM_DIER_CC2IE_Pos                  (2U)
4616 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
4617 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
4618 #define TIM_DIER_CC3IE_Pos                  (3U)
4619 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
4620 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
4621 #define TIM_DIER_CC4IE_Pos                  (4U)
4622 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
4623 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
4624 #define TIM_DIER_COMIE_Pos                  (5U)
4625 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)       /*!< 0x00000020 */
4626 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                 /*!<COM interrupt enable */
4627 #define TIM_DIER_TIE_Pos                    (6U)
4628 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
4629 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
4630 #define TIM_DIER_BIE_Pos                    (7U)
4631 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)         /*!< 0x00000080 */
4632 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                   /*!<Break interrupt enable */
4633 #define TIM_DIER_UDE_Pos                    (8U)
4634 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
4635 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
4636 #define TIM_DIER_CC1DE_Pos                  (9U)
4637 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
4638 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
4639 #define TIM_DIER_CC2DE_Pos                  (10U)
4640 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
4641 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
4642 #define TIM_DIER_CC3DE_Pos                  (11U)
4643 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
4644 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
4645 #define TIM_DIER_CC4DE_Pos                  (12U)
4646 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
4647 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
4648 #define TIM_DIER_COMDE_Pos                  (13U)
4649 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)       /*!< 0x00002000 */
4650 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                 /*!<COM DMA request enable */
4651 #define TIM_DIER_TDE_Pos                    (14U)
4652 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
4653 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
4654 
4655 /********************  Bit definition for TIM_SR register  *******************/
4656 #define TIM_SR_UIF_Pos                      (0U)
4657 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
4658 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
4659 #define TIM_SR_CC1IF_Pos                    (1U)
4660 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
4661 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
4662 #define TIM_SR_CC2IF_Pos                    (2U)
4663 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
4664 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
4665 #define TIM_SR_CC3IF_Pos                    (3U)
4666 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
4667 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
4668 #define TIM_SR_CC4IF_Pos                    (4U)
4669 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
4670 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
4671 #define TIM_SR_COMIF_Pos                    (5U)
4672 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)         /*!< 0x00000020 */
4673 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                   /*!<COM interrupt Flag */
4674 #define TIM_SR_TIF_Pos                      (6U)
4675 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
4676 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
4677 #define TIM_SR_BIF_Pos                      (7U)
4678 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)           /*!< 0x00000080 */
4679 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                     /*!<Break interrupt Flag */
4680 #define TIM_SR_CC1OF_Pos                    (9U)
4681 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
4682 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
4683 #define TIM_SR_CC2OF_Pos                    (10U)
4684 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
4685 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
4686 #define TIM_SR_CC3OF_Pos                    (11U)
4687 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
4688 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
4689 #define TIM_SR_CC4OF_Pos                    (12U)
4690 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
4691 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
4692 
4693 /*******************  Bit definition for TIM_EGR register  *******************/
4694 #define TIM_EGR_UG_Pos                      (0U)
4695 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
4696 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
4697 #define TIM_EGR_CC1G_Pos                    (1U)
4698 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
4699 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
4700 #define TIM_EGR_CC2G_Pos                    (2U)
4701 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
4702 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
4703 #define TIM_EGR_CC3G_Pos                    (3U)
4704 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
4705 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
4706 #define TIM_EGR_CC4G_Pos                    (4U)
4707 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
4708 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
4709 #define TIM_EGR_COMG_Pos                    (5U)
4710 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)         /*!< 0x00000020 */
4711 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                   /*!<Capture/Compare Control Update Generation */
4712 #define TIM_EGR_TG_Pos                      (6U)
4713 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
4714 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
4715 #define TIM_EGR_BG_Pos                      (7U)
4716 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)           /*!< 0x00000080 */
4717 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                     /*!<Break Generation */
4718 
4719 /******************  Bit definition for TIM_CCMR1 register  ******************/
4720 #define TIM_CCMR1_CC1S_Pos                  (0U)
4721 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
4722 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4723 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
4724 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
4725 
4726 #define TIM_CCMR1_OC1FE_Pos                 (2U)
4727 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
4728 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
4729 #define TIM_CCMR1_OC1PE_Pos                 (3U)
4730 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
4731 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
4732 
4733 #define TIM_CCMR1_OC1M_Pos                  (4U)
4734 #define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
4735 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4736 #define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
4737 #define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
4738 #define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
4739 
4740 #define TIM_CCMR1_OC1CE_Pos                 (7U)
4741 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
4742 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
4743 
4744 #define TIM_CCMR1_CC2S_Pos                  (8U)
4745 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
4746 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4747 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
4748 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
4749 
4750 #define TIM_CCMR1_OC2FE_Pos                 (10U)
4751 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
4752 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
4753 #define TIM_CCMR1_OC2PE_Pos                 (11U)
4754 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
4755 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
4756 
4757 #define TIM_CCMR1_OC2M_Pos                  (12U)
4758 #define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
4759 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4760 #define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
4761 #define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
4762 #define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
4763 
4764 #define TIM_CCMR1_OC2CE_Pos                 (15U)
4765 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
4766 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
4767 
4768 /*---------------------------------------------------------------------------*/
4769 
4770 #define TIM_CCMR1_IC1PSC_Pos                (2U)
4771 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
4772 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4773 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
4774 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
4775 
4776 #define TIM_CCMR1_IC1F_Pos                  (4U)
4777 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
4778 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4779 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
4780 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
4781 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
4782 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
4783 
4784 #define TIM_CCMR1_IC2PSC_Pos                (10U)
4785 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
4786 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4787 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
4788 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
4789 
4790 #define TIM_CCMR1_IC2F_Pos                  (12U)
4791 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
4792 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4793 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
4794 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
4795 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
4796 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
4797 
4798 /******************  Bit definition for TIM_CCMR2 register  ******************/
4799 #define TIM_CCMR2_CC3S_Pos                  (0U)
4800 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
4801 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4802 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
4803 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
4804 
4805 #define TIM_CCMR2_OC3FE_Pos                 (2U)
4806 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
4807 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
4808 #define TIM_CCMR2_OC3PE_Pos                 (3U)
4809 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
4810 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
4811 
4812 #define TIM_CCMR2_OC3M_Pos                  (4U)
4813 #define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
4814 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4815 #define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
4816 #define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
4817 #define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
4818 
4819 #define TIM_CCMR2_OC3CE_Pos                 (7U)
4820 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
4821 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
4822 
4823 #define TIM_CCMR2_CC4S_Pos                  (8U)
4824 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
4825 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4826 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
4827 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
4828 
4829 #define TIM_CCMR2_OC4FE_Pos                 (10U)
4830 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
4831 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
4832 #define TIM_CCMR2_OC4PE_Pos                 (11U)
4833 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
4834 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
4835 
4836 #define TIM_CCMR2_OC4M_Pos                  (12U)
4837 #define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
4838 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4839 #define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
4840 #define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
4841 #define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
4842 
4843 #define TIM_CCMR2_OC4CE_Pos                 (15U)
4844 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
4845 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
4846 
4847 /*---------------------------------------------------------------------------*/
4848 
4849 #define TIM_CCMR2_IC3PSC_Pos                (2U)
4850 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
4851 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4852 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
4853 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
4854 
4855 #define TIM_CCMR2_IC3F_Pos                  (4U)
4856 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
4857 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4858 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
4859 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
4860 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
4861 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
4862 
4863 #define TIM_CCMR2_IC4PSC_Pos                (10U)
4864 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
4865 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4866 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
4867 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
4868 
4869 #define TIM_CCMR2_IC4F_Pos                  (12U)
4870 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
4871 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4872 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
4873 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
4874 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
4875 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
4876 
4877 /*******************  Bit definition for TIM_CCER register  ******************/
4878 #define TIM_CCER_CC1E_Pos                   (0U)
4879 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
4880 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
4881 #define TIM_CCER_CC1P_Pos                   (1U)
4882 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
4883 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
4884 #define TIM_CCER_CC1NE_Pos                  (2U)
4885 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)       /*!< 0x00000004 */
4886 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                 /*!<Capture/Compare 1 Complementary output enable */
4887 #define TIM_CCER_CC1NP_Pos                  (3U)
4888 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
4889 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
4890 #define TIM_CCER_CC2E_Pos                   (4U)
4891 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
4892 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
4893 #define TIM_CCER_CC2P_Pos                   (5U)
4894 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
4895 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
4896 #define TIM_CCER_CC2NE_Pos                  (6U)
4897 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)       /*!< 0x00000040 */
4898 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                 /*!<Capture/Compare 2 Complementary output enable */
4899 #define TIM_CCER_CC2NP_Pos                  (7U)
4900 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
4901 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
4902 #define TIM_CCER_CC3E_Pos                   (8U)
4903 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
4904 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
4905 #define TIM_CCER_CC3P_Pos                   (9U)
4906 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
4907 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
4908 #define TIM_CCER_CC3NE_Pos                  (10U)
4909 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)       /*!< 0x00000400 */
4910 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                 /*!<Capture/Compare 3 Complementary output enable */
4911 #define TIM_CCER_CC3NP_Pos                  (11U)
4912 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
4913 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
4914 #define TIM_CCER_CC4E_Pos                   (12U)
4915 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
4916 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
4917 #define TIM_CCER_CC4P_Pos                   (13U)
4918 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
4919 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
4920 
4921 /*******************  Bit definition for TIM_CNT register  *******************/
4922 #define TIM_CNT_CNT_Pos                     (0U)
4923 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
4924 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
4925 
4926 /*******************  Bit definition for TIM_PSC register  *******************/
4927 #define TIM_PSC_PSC_Pos                     (0U)
4928 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
4929 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
4930 
4931 /*******************  Bit definition for TIM_ARR register  *******************/
4932 #define TIM_ARR_ARR_Pos                     (0U)
4933 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
4934 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
4935 
4936 /*******************  Bit definition for TIM_RCR register  *******************/
4937 #define TIM_RCR_REP_Pos                     (0U)
4938 #define TIM_RCR_REP_Msk                     (0xFFUL << TIM_RCR_REP_Pos)         /*!< 0x000000FF */
4939 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                    /*!<Repetition Counter Value */
4940 
4941 /*******************  Bit definition for TIM_CCR1 register  ******************/
4942 #define TIM_CCR1_CCR1_Pos                   (0U)
4943 #define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
4944 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
4945 
4946 /*******************  Bit definition for TIM_CCR2 register  ******************/
4947 #define TIM_CCR2_CCR2_Pos                   (0U)
4948 #define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
4949 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
4950 
4951 /*******************  Bit definition for TIM_CCR3 register  ******************/
4952 #define TIM_CCR3_CCR3_Pos                   (0U)
4953 #define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
4954 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
4955 
4956 /*******************  Bit definition for TIM_CCR4 register  ******************/
4957 #define TIM_CCR4_CCR4_Pos                   (0U)
4958 #define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
4959 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
4960 
4961 /*******************  Bit definition for TIM_BDTR register  ******************/
4962 #define TIM_BDTR_DTG_Pos                    (0U)
4963 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)        /*!< 0x000000FF */
4964 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                   /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4965 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000001 */
4966 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000002 */
4967 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000004 */
4968 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000008 */
4969 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000010 */
4970 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000020 */
4971 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000040 */
4972 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000080 */
4973 
4974 #define TIM_BDTR_LOCK_Pos                   (8U)
4975 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000300 */
4976 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                  /*!<LOCK[1:0] bits (Lock Configuration) */
4977 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000100 */
4978 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000200 */
4979 
4980 #define TIM_BDTR_OSSI_Pos                   (10U)
4981 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)        /*!< 0x00000400 */
4982 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                  /*!<Off-State Selection for Idle mode */
4983 #define TIM_BDTR_OSSR_Pos                   (11U)
4984 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)        /*!< 0x00000800 */
4985 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                  /*!<Off-State Selection for Run mode */
4986 #define TIM_BDTR_BKE_Pos                    (12U)
4987 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)         /*!< 0x00001000 */
4988 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                   /*!<Break enable */
4989 #define TIM_BDTR_BKP_Pos                    (13U)
4990 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)         /*!< 0x00002000 */
4991 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                   /*!<Break Polarity */
4992 #define TIM_BDTR_AOE_Pos                    (14U)
4993 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)         /*!< 0x00004000 */
4994 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                   /*!<Automatic Output enable */
4995 #define TIM_BDTR_MOE_Pos                    (15U)
4996 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)         /*!< 0x00008000 */
4997 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                   /*!<Main Output enable */
4998 
4999 /*******************  Bit definition for TIM_DCR register  *******************/
5000 #define TIM_DCR_DBA_Pos                     (0U)
5001 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
5002 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
5003 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
5004 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
5005 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
5006 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
5007 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
5008 
5009 #define TIM_DCR_DBL_Pos                     (8U)
5010 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
5011 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
5012 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
5013 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
5014 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
5015 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
5016 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
5017 
5018 /*******************  Bit definition for TIM_DMAR register  ******************/
5019 #define TIM_DMAR_DMAB_Pos                   (0U)
5020 #define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
5021 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
5022 
5023 /******************************************************************************/
5024 /*                                                                            */
5025 /*                             Real-Time Clock                                */
5026 /*                                                                            */
5027 /******************************************************************************/
5028 
5029 /*******************  Bit definition for RTC_CRH register  ********************/
5030 #define RTC_CRH_SECIE_Pos                   (0U)
5031 #define RTC_CRH_SECIE_Msk                   (0x1UL << RTC_CRH_SECIE_Pos)        /*!< 0x00000001 */
5032 #define RTC_CRH_SECIE                       RTC_CRH_SECIE_Msk                  /*!< Second Interrupt Enable */
5033 #define RTC_CRH_ALRIE_Pos                   (1U)
5034 #define RTC_CRH_ALRIE_Msk                   (0x1UL << RTC_CRH_ALRIE_Pos)        /*!< 0x00000002 */
5035 #define RTC_CRH_ALRIE                       RTC_CRH_ALRIE_Msk                  /*!< Alarm Interrupt Enable */
5036 #define RTC_CRH_OWIE_Pos                    (2U)
5037 #define RTC_CRH_OWIE_Msk                    (0x1UL << RTC_CRH_OWIE_Pos)         /*!< 0x00000004 */
5038 #define RTC_CRH_OWIE                        RTC_CRH_OWIE_Msk                   /*!< OverfloW Interrupt Enable */
5039 
5040 /*******************  Bit definition for RTC_CRL register  ********************/
5041 #define RTC_CRL_SECF_Pos                    (0U)
5042 #define RTC_CRL_SECF_Msk                    (0x1UL << RTC_CRL_SECF_Pos)         /*!< 0x00000001 */
5043 #define RTC_CRL_SECF                        RTC_CRL_SECF_Msk                   /*!< Second Flag */
5044 #define RTC_CRL_ALRF_Pos                    (1U)
5045 #define RTC_CRL_ALRF_Msk                    (0x1UL << RTC_CRL_ALRF_Pos)         /*!< 0x00000002 */
5046 #define RTC_CRL_ALRF                        RTC_CRL_ALRF_Msk                   /*!< Alarm Flag */
5047 #define RTC_CRL_OWF_Pos                     (2U)
5048 #define RTC_CRL_OWF_Msk                     (0x1UL << RTC_CRL_OWF_Pos)          /*!< 0x00000004 */
5049 #define RTC_CRL_OWF                         RTC_CRL_OWF_Msk                    /*!< OverfloW Flag */
5050 #define RTC_CRL_RSF_Pos                     (3U)
5051 #define RTC_CRL_RSF_Msk                     (0x1UL << RTC_CRL_RSF_Pos)          /*!< 0x00000008 */
5052 #define RTC_CRL_RSF                         RTC_CRL_RSF_Msk                    /*!< Registers Synchronized Flag */
5053 #define RTC_CRL_CNF_Pos                     (4U)
5054 #define RTC_CRL_CNF_Msk                     (0x1UL << RTC_CRL_CNF_Pos)          /*!< 0x00000010 */
5055 #define RTC_CRL_CNF                         RTC_CRL_CNF_Msk                    /*!< Configuration Flag */
5056 #define RTC_CRL_RTOFF_Pos                   (5U)
5057 #define RTC_CRL_RTOFF_Msk                   (0x1UL << RTC_CRL_RTOFF_Pos)        /*!< 0x00000020 */
5058 #define RTC_CRL_RTOFF                       RTC_CRL_RTOFF_Msk                  /*!< RTC operation OFF */
5059 
5060 /*******************  Bit definition for RTC_PRLH register  *******************/
5061 #define RTC_PRLH_PRL_Pos                    (0U)
5062 #define RTC_PRLH_PRL_Msk                    (0xFUL << RTC_PRLH_PRL_Pos)         /*!< 0x0000000F */
5063 #define RTC_PRLH_PRL                        RTC_PRLH_PRL_Msk                   /*!< RTC Prescaler Reload Value High */
5064 
5065 /*******************  Bit definition for RTC_PRLL register  *******************/
5066 #define RTC_PRLL_PRL_Pos                    (0U)
5067 #define RTC_PRLL_PRL_Msk                    (0xFFFFUL << RTC_PRLL_PRL_Pos)      /*!< 0x0000FFFF */
5068 #define RTC_PRLL_PRL                        RTC_PRLL_PRL_Msk                   /*!< RTC Prescaler Reload Value Low */
5069 
5070 /*******************  Bit definition for RTC_DIVH register  *******************/
5071 #define RTC_DIVH_RTC_DIV_Pos                (0U)
5072 #define RTC_DIVH_RTC_DIV_Msk                (0xFUL << RTC_DIVH_RTC_DIV_Pos)     /*!< 0x0000000F */
5073 #define RTC_DIVH_RTC_DIV                    RTC_DIVH_RTC_DIV_Msk               /*!< RTC Clock Divider High */
5074 
5075 /*******************  Bit definition for RTC_DIVL register  *******************/
5076 #define RTC_DIVL_RTC_DIV_Pos                (0U)
5077 #define RTC_DIVL_RTC_DIV_Msk                (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)  /*!< 0x0000FFFF */
5078 #define RTC_DIVL_RTC_DIV                    RTC_DIVL_RTC_DIV_Msk               /*!< RTC Clock Divider Low */
5079 
5080 /*******************  Bit definition for RTC_CNTH register  *******************/
5081 #define RTC_CNTH_RTC_CNT_Pos                (0U)
5082 #define RTC_CNTH_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)  /*!< 0x0000FFFF */
5083 #define RTC_CNTH_RTC_CNT                    RTC_CNTH_RTC_CNT_Msk               /*!< RTC Counter High */
5084 
5085 /*******************  Bit definition for RTC_CNTL register  *******************/
5086 #define RTC_CNTL_RTC_CNT_Pos                (0U)
5087 #define RTC_CNTL_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)  /*!< 0x0000FFFF */
5088 #define RTC_CNTL_RTC_CNT                    RTC_CNTL_RTC_CNT_Msk               /*!< RTC Counter Low */
5089 
5090 /*******************  Bit definition for RTC_ALRH register  *******************/
5091 #define RTC_ALRH_RTC_ALR_Pos                (0U)
5092 #define RTC_ALRH_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)  /*!< 0x0000FFFF */
5093 #define RTC_ALRH_RTC_ALR                    RTC_ALRH_RTC_ALR_Msk               /*!< RTC Alarm High */
5094 
5095 /*******************  Bit definition for RTC_ALRL register  *******************/
5096 #define RTC_ALRL_RTC_ALR_Pos                (0U)
5097 #define RTC_ALRL_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)  /*!< 0x0000FFFF */
5098 #define RTC_ALRL_RTC_ALR                    RTC_ALRL_RTC_ALR_Msk               /*!< RTC Alarm Low */
5099 
5100 /******************************************************************************/
5101 /*                                                                            */
5102 /*                        Independent WATCHDOG (IWDG)                         */
5103 /*                                                                            */
5104 /******************************************************************************/
5105 
5106 /*******************  Bit definition for IWDG_KR register  ********************/
5107 #define IWDG_KR_KEY_Pos                     (0U)
5108 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
5109 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
5110 
5111 /*******************  Bit definition for IWDG_PR register  ********************/
5112 #define IWDG_PR_PR_Pos                      (0U)
5113 #define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
5114 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
5115 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
5116 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
5117 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
5118 
5119 /*******************  Bit definition for IWDG_RLR register  *******************/
5120 #define IWDG_RLR_RL_Pos                     (0U)
5121 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
5122 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
5123 
5124 /*******************  Bit definition for IWDG_SR register  ********************/
5125 #define IWDG_SR_PVU_Pos                     (0U)
5126 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
5127 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
5128 #define IWDG_SR_RVU_Pos                     (1U)
5129 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
5130 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
5131 
5132 /******************************************************************************/
5133 /*                                                                            */
5134 /*                         Window WATCHDOG (WWDG)                             */
5135 /*                                                                            */
5136 /******************************************************************************/
5137 
5138 /*******************  Bit definition for WWDG_CR register  ********************/
5139 #define WWDG_CR_T_Pos                       (0U)
5140 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
5141 #define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
5142 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
5143 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
5144 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
5145 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
5146 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
5147 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
5148 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
5149 
5150 /* Legacy defines */
5151 #define  WWDG_CR_T0 WWDG_CR_T_0
5152 #define  WWDG_CR_T1 WWDG_CR_T_1
5153 #define  WWDG_CR_T2 WWDG_CR_T_2
5154 #define  WWDG_CR_T3 WWDG_CR_T_3
5155 #define  WWDG_CR_T4 WWDG_CR_T_4
5156 #define  WWDG_CR_T5 WWDG_CR_T_5
5157 #define  WWDG_CR_T6 WWDG_CR_T_6
5158 
5159 #define WWDG_CR_WDGA_Pos                    (7U)
5160 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
5161 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
5162 
5163 /*******************  Bit definition for WWDG_CFR register  *******************/
5164 #define WWDG_CFR_W_Pos                      (0U)
5165 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
5166 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
5167 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
5168 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
5169 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
5170 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
5171 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
5172 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
5173 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
5174 
5175 /* Legacy defines */
5176 #define  WWDG_CFR_W0 WWDG_CFR_W_0
5177 #define  WWDG_CFR_W1 WWDG_CFR_W_1
5178 #define  WWDG_CFR_W2 WWDG_CFR_W_2
5179 #define  WWDG_CFR_W3 WWDG_CFR_W_3
5180 #define  WWDG_CFR_W4 WWDG_CFR_W_4
5181 #define  WWDG_CFR_W5 WWDG_CFR_W_5
5182 #define  WWDG_CFR_W6 WWDG_CFR_W_6
5183 
5184 #define WWDG_CFR_WDGTB_Pos                  (7U)
5185 #define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
5186 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
5187 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
5188 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
5189 
5190 /* Legacy defines */
5191 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
5192 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
5193 
5194 #define WWDG_CFR_EWI_Pos                    (9U)
5195 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
5196 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
5197 
5198 /*******************  Bit definition for WWDG_SR register  ********************/
5199 #define WWDG_SR_EWIF_Pos                    (0U)
5200 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
5201 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
5202 
5203 /******************************************************************************/
5204 /*                                                                            */
5205 /*                       Flexible Static Memory Controller                    */
5206 /*                                                                            */
5207 /******************************************************************************/
5208 
5209 /******************  Bit definition for FSMC_BCRx (x=1..4) register  **********/
5210 #define FSMC_BCRx_MBKEN_Pos                 (0U)
5211 #define FSMC_BCRx_MBKEN_Msk                 (0x1UL << FSMC_BCRx_MBKEN_Pos)      /*!< 0x00000001 */
5212 #define FSMC_BCRx_MBKEN                     FSMC_BCRx_MBKEN_Msk                /*!< Memory bank enable bit */
5213 #define FSMC_BCRx_MUXEN_Pos                 (1U)
5214 #define FSMC_BCRx_MUXEN_Msk                 (0x1UL << FSMC_BCRx_MUXEN_Pos)      /*!< 0x00000002 */
5215 #define FSMC_BCRx_MUXEN                     FSMC_BCRx_MUXEN_Msk                /*!< Address/data multiplexing enable bit */
5216 
5217 #define FSMC_BCRx_MTYP_Pos                  (2U)
5218 #define FSMC_BCRx_MTYP_Msk                  (0x3UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x0000000C */
5219 #define FSMC_BCRx_MTYP                      FSMC_BCRx_MTYP_Msk                 /*!< MTYP[1:0] bits (Memory type) */
5220 #define FSMC_BCRx_MTYP_0                    (0x1UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000004 */
5221 #define FSMC_BCRx_MTYP_1                    (0x2UL << FSMC_BCRx_MTYP_Pos)       /*!< 0x00000008 */
5222 
5223 #define FSMC_BCRx_MWID_Pos                  (4U)
5224 #define FSMC_BCRx_MWID_Msk                  (0x3UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000030 */
5225 #define FSMC_BCRx_MWID                      FSMC_BCRx_MWID_Msk                 /*!< MWID[1:0] bits (Memory data bus width) */
5226 #define FSMC_BCRx_MWID_0                    (0x1UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000010 */
5227 #define FSMC_BCRx_MWID_1                    (0x2UL << FSMC_BCRx_MWID_Pos)       /*!< 0x00000020 */
5228 
5229 #define FSMC_BCRx_FACCEN_Pos                (6U)
5230 #define FSMC_BCRx_FACCEN_Msk                (0x1UL << FSMC_BCRx_FACCEN_Pos)     /*!< 0x00000040 */
5231 #define FSMC_BCRx_FACCEN                    FSMC_BCRx_FACCEN_Msk               /*!< Flash access enable */
5232 #define FSMC_BCRx_BURSTEN_Pos               (8U)
5233 #define FSMC_BCRx_BURSTEN_Msk               (0x1UL << FSMC_BCRx_BURSTEN_Pos)    /*!< 0x00000100 */
5234 #define FSMC_BCRx_BURSTEN                   FSMC_BCRx_BURSTEN_Msk              /*!< Burst enable bit */
5235 #define FSMC_BCRx_WAITPOL_Pos               (9U)
5236 #define FSMC_BCRx_WAITPOL_Msk               (0x1UL << FSMC_BCRx_WAITPOL_Pos)    /*!< 0x00000200 */
5237 #define FSMC_BCRx_WAITPOL                   FSMC_BCRx_WAITPOL_Msk              /*!< Wait signal polarity bit */
5238 #define FSMC_BCRx_WRAPMOD_Pos               (10U)
5239 #define FSMC_BCRx_WRAPMOD_Msk               (0x1UL << FSMC_BCRx_WRAPMOD_Pos)    /*!< 0x00000400 */
5240 #define FSMC_BCRx_WRAPMOD                   FSMC_BCRx_WRAPMOD_Msk              /*!< Wrapped burst mode support */
5241 #define FSMC_BCRx_WAITCFG_Pos               (11U)
5242 #define FSMC_BCRx_WAITCFG_Msk               (0x1UL << FSMC_BCRx_WAITCFG_Pos)    /*!< 0x00000800 */
5243 #define FSMC_BCRx_WAITCFG                   FSMC_BCRx_WAITCFG_Msk              /*!< Wait timing configuration */
5244 #define FSMC_BCRx_WREN_Pos                  (12U)
5245 #define FSMC_BCRx_WREN_Msk                  (0x1UL << FSMC_BCRx_WREN_Pos)       /*!< 0x00001000 */
5246 #define FSMC_BCRx_WREN                      FSMC_BCRx_WREN_Msk                 /*!< Write enable bit */
5247 #define FSMC_BCRx_WAITEN_Pos                (13U)
5248 #define FSMC_BCRx_WAITEN_Msk                (0x1UL << FSMC_BCRx_WAITEN_Pos)     /*!< 0x00002000 */
5249 #define FSMC_BCRx_WAITEN                    FSMC_BCRx_WAITEN_Msk               /*!< Wait enable bit */
5250 #define FSMC_BCRx_EXTMOD_Pos                (14U)
5251 #define FSMC_BCRx_EXTMOD_Msk                (0x1UL << FSMC_BCRx_EXTMOD_Pos)     /*!< 0x00004000 */
5252 #define FSMC_BCRx_EXTMOD                    FSMC_BCRx_EXTMOD_Msk               /*!< Extended mode enable */
5253 #define FSMC_BCRx_ASYNCWAIT_Pos             (15U)
5254 #define FSMC_BCRx_ASYNCWAIT_Msk             (0x1UL << FSMC_BCRx_ASYNCWAIT_Pos)  /*!< 0x00008000 */
5255 #define FSMC_BCRx_ASYNCWAIT                 FSMC_BCRx_ASYNCWAIT_Msk            /*!< Asynchronous wait */
5256 #define FSMC_BCRx_CBURSTRW_Pos              (19U)
5257 #define FSMC_BCRx_CBURSTRW_Msk              (0x1UL << FSMC_BCRx_CBURSTRW_Pos)   /*!< 0x00080000 */
5258 #define FSMC_BCRx_CBURSTRW                  FSMC_BCRx_CBURSTRW_Msk             /*!< Write burst enable */
5259 
5260 /******************  Bit definition for FSMC_BTRx (x=1..4) register  ******/
5261 #define FSMC_BTRx_ADDSET_Pos                (0U)
5262 #define FSMC_BTRx_ADDSET_Msk                (0xFUL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x0000000F */
5263 #define FSMC_BTRx_ADDSET                    FSMC_BTRx_ADDSET_Msk               /*!< ADDSET[3:0] bits (Address setup phase duration) */
5264 #define FSMC_BTRx_ADDSET_0                  (0x1UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000001 */
5265 #define FSMC_BTRx_ADDSET_1                  (0x2UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000002 */
5266 #define FSMC_BTRx_ADDSET_2                  (0x4UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000004 */
5267 #define FSMC_BTRx_ADDSET_3                  (0x8UL << FSMC_BTRx_ADDSET_Pos)     /*!< 0x00000008 */
5268 
5269 #define FSMC_BTRx_ADDHLD_Pos                (4U)
5270 #define FSMC_BTRx_ADDHLD_Msk                (0xFUL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x000000F0 */
5271 #define FSMC_BTRx_ADDHLD                    FSMC_BTRx_ADDHLD_Msk               /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
5272 #define FSMC_BTRx_ADDHLD_0                  (0x1UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000010 */
5273 #define FSMC_BTRx_ADDHLD_1                  (0x2UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000020 */
5274 #define FSMC_BTRx_ADDHLD_2                  (0x4UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000040 */
5275 #define FSMC_BTRx_ADDHLD_3                  (0x8UL << FSMC_BTRx_ADDHLD_Pos)     /*!< 0x00000080 */
5276 
5277 #define FSMC_BTRx_DATAST_Pos                (8U)
5278 #define FSMC_BTRx_DATAST_Msk                (0xFFUL << FSMC_BTRx_DATAST_Pos)    /*!< 0x0000FF00 */
5279 #define FSMC_BTRx_DATAST                    FSMC_BTRx_DATAST_Msk               /*!< DATAST [3:0] bits (Data-phase duration) */
5280 #define FSMC_BTRx_DATAST_0                  (0x01UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000100 */
5281 #define FSMC_BTRx_DATAST_1                  (0x02UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000200 */
5282 #define FSMC_BTRx_DATAST_2                  (0x04UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000400 */
5283 #define FSMC_BTRx_DATAST_3                  (0x08UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00000800 */
5284 #define FSMC_BTRx_DATAST_4                  (0x10UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00001000 */
5285 #define FSMC_BTRx_DATAST_5                  (0x20UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00002000 */
5286 #define FSMC_BTRx_DATAST_6                  (0x40UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00004000 */
5287 #define FSMC_BTRx_DATAST_7                  (0x80UL << FSMC_BTRx_DATAST_Pos)    /*!< 0x00008000 */
5288 
5289 #define FSMC_BTRx_BUSTURN_Pos               (16U)
5290 #define FSMC_BTRx_BUSTURN_Msk               (0xFUL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x000F0000 */
5291 #define FSMC_BTRx_BUSTURN                   FSMC_BTRx_BUSTURN_Msk              /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
5292 #define FSMC_BTRx_BUSTURN_0                 (0x1UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00010000 */
5293 #define FSMC_BTRx_BUSTURN_1                 (0x2UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00020000 */
5294 #define FSMC_BTRx_BUSTURN_2                 (0x4UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00040000 */
5295 #define FSMC_BTRx_BUSTURN_3                 (0x8UL << FSMC_BTRx_BUSTURN_Pos)    /*!< 0x00080000 */
5296 
5297 #define FSMC_BTRx_CLKDIV_Pos                (20U)
5298 #define FSMC_BTRx_CLKDIV_Msk                (0xFUL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00F00000 */
5299 #define FSMC_BTRx_CLKDIV                    FSMC_BTRx_CLKDIV_Msk               /*!< CLKDIV[3:0] bits (Clock divide ratio) */
5300 #define FSMC_BTRx_CLKDIV_0                  (0x1UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00100000 */
5301 #define FSMC_BTRx_CLKDIV_1                  (0x2UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00200000 */
5302 #define FSMC_BTRx_CLKDIV_2                  (0x4UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00400000 */
5303 #define FSMC_BTRx_CLKDIV_3                  (0x8UL << FSMC_BTRx_CLKDIV_Pos)     /*!< 0x00800000 */
5304 
5305 #define FSMC_BTRx_DATLAT_Pos                (24U)
5306 #define FSMC_BTRx_DATLAT_Msk                (0xFUL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x0F000000 */
5307 #define FSMC_BTRx_DATLAT                    FSMC_BTRx_DATLAT_Msk               /*!< DATLA[3:0] bits (Data latency) */
5308 #define FSMC_BTRx_DATLAT_0                  (0x1UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x01000000 */
5309 #define FSMC_BTRx_DATLAT_1                  (0x2UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x02000000 */
5310 #define FSMC_BTRx_DATLAT_2                  (0x4UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x04000000 */
5311 #define FSMC_BTRx_DATLAT_3                  (0x8UL << FSMC_BTRx_DATLAT_Pos)     /*!< 0x08000000 */
5312 
5313 #define FSMC_BTRx_ACCMOD_Pos                (28U)
5314 #define FSMC_BTRx_ACCMOD_Msk                (0x3UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x30000000 */
5315 #define FSMC_BTRx_ACCMOD                    FSMC_BTRx_ACCMOD_Msk               /*!< ACCMOD[1:0] bits (Access mode) */
5316 #define FSMC_BTRx_ACCMOD_0                  (0x1UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x10000000 */
5317 #define FSMC_BTRx_ACCMOD_1                  (0x2UL << FSMC_BTRx_ACCMOD_Pos)     /*!< 0x20000000 */
5318 
5319 /******************  Bit definition for FSMC_BWTRx (x=1..4) register  ******/
5320 #define FSMC_BWTRx_ADDSET_Pos               (0U)
5321 #define FSMC_BWTRx_ADDSET_Msk               (0xFUL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x0000000F */
5322 #define FSMC_BWTRx_ADDSET                   FSMC_BWTRx_ADDSET_Msk              /*!< ADDSET[3:0] bits (Address setup phase duration) */
5323 #define FSMC_BWTRx_ADDSET_0                 (0x1UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000001 */
5324 #define FSMC_BWTRx_ADDSET_1                 (0x2UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000002 */
5325 #define FSMC_BWTRx_ADDSET_2                 (0x4UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000004 */
5326 #define FSMC_BWTRx_ADDSET_3                 (0x8UL << FSMC_BWTRx_ADDSET_Pos)    /*!< 0x00000008 */
5327 
5328 #define FSMC_BWTRx_ADDHLD_Pos               (4U)
5329 #define FSMC_BWTRx_ADDHLD_Msk               (0xFUL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x000000F0 */
5330 #define FSMC_BWTRx_ADDHLD                   FSMC_BWTRx_ADDHLD_Msk              /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
5331 #define FSMC_BWTRx_ADDHLD_0                 (0x1UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000010 */
5332 #define FSMC_BWTRx_ADDHLD_1                 (0x2UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000020 */
5333 #define FSMC_BWTRx_ADDHLD_2                 (0x4UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000040 */
5334 #define FSMC_BWTRx_ADDHLD_3                 (0x8UL << FSMC_BWTRx_ADDHLD_Pos)    /*!< 0x00000080 */
5335 
5336 #define FSMC_BWTRx_DATAST_Pos               (8U)
5337 #define FSMC_BWTRx_DATAST_Msk               (0xFFUL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x0000FF00 */
5338 #define FSMC_BWTRx_DATAST                   FSMC_BWTRx_DATAST_Msk              /*!< DATAST [3:0] bits (Data-phase duration) */
5339 #define FSMC_BWTRx_DATAST_0                 (0x01UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000100 */
5340 #define FSMC_BWTRx_DATAST_1                 (0x02UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000200 */
5341 #define FSMC_BWTRx_DATAST_2                 (0x04UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000400 */
5342 #define FSMC_BWTRx_DATAST_3                 (0x08UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00000800 */
5343 #define FSMC_BWTRx_DATAST_4                 (0x10UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00001000 */
5344 #define FSMC_BWTRx_DATAST_5                 (0x20UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00002000 */
5345 #define FSMC_BWTRx_DATAST_6                 (0x40UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00004000 */
5346 #define FSMC_BWTRx_DATAST_7                 (0x80UL << FSMC_BWTRx_DATAST_Pos)   /*!< 0x00008000 */
5347 
5348 #define FSMC_BWTRx_BUSTURN_Pos              (16U)
5349 #define FSMC_BWTRx_BUSTURN_Msk              (0xFUL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x000F0000 */
5350 #define FSMC_BWTRx_BUSTURN                  FSMC_BWTRx_BUSTURN_Msk             /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
5351 #define FSMC_BWTRx_BUSTURN_0                (0x1UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00010000 */
5352 #define FSMC_BWTRx_BUSTURN_1                (0x2UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00020000 */
5353 #define FSMC_BWTRx_BUSTURN_2                (0x4UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00040000 */
5354 #define FSMC_BWTRx_BUSTURN_3                (0x8UL << FSMC_BWTRx_BUSTURN_Pos)   /*!< 0x00080000 */
5355 
5356 #define FSMC_BWTRx_ACCMOD_Pos               (28U)
5357 #define FSMC_BWTRx_ACCMOD_Msk               (0x3UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x30000000 */
5358 #define FSMC_BWTRx_ACCMOD                   FSMC_BWTRx_ACCMOD_Msk              /*!< ACCMOD[1:0] bits (Access mode) */
5359 #define FSMC_BWTRx_ACCMOD_0                 (0x1UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x10000000 */
5360 #define FSMC_BWTRx_ACCMOD_1                 (0x2UL << FSMC_BWTRx_ACCMOD_Pos)    /*!< 0x20000000 */
5361 
5362 /******************  Bit definition for FSMC_PCRx (x = 2 to 4) register  *******************/
5363 #define FSMC_PCRx_PWAITEN_Pos               (1U)
5364 #define FSMC_PCRx_PWAITEN_Msk               (0x1UL << FSMC_PCRx_PWAITEN_Pos)    /*!< 0x00000002 */
5365 #define FSMC_PCRx_PWAITEN                   FSMC_PCRx_PWAITEN_Msk              /*!< Wait feature enable bit */
5366 #define FSMC_PCRx_PBKEN_Pos                 (2U)
5367 #define FSMC_PCRx_PBKEN_Msk                 (0x1UL << FSMC_PCRx_PBKEN_Pos)      /*!< 0x00000004 */
5368 #define FSMC_PCRx_PBKEN                     FSMC_PCRx_PBKEN_Msk                /*!< PC Card/NAND Flash memory bank enable bit */
5369 #define FSMC_PCRx_PTYP_Pos                  (3U)
5370 #define FSMC_PCRx_PTYP_Msk                  (0x1UL << FSMC_PCRx_PTYP_Pos)       /*!< 0x00000008 */
5371 #define FSMC_PCRx_PTYP                      FSMC_PCRx_PTYP_Msk                 /*!< Memory type */
5372 
5373 #define FSMC_PCRx_PWID_Pos                  (4U)
5374 #define FSMC_PCRx_PWID_Msk                  (0x3UL << FSMC_PCRx_PWID_Pos)       /*!< 0x00000030 */
5375 #define FSMC_PCRx_PWID                      FSMC_PCRx_PWID_Msk                 /*!< PWID[1:0] bits (NAND Flash databus width) */
5376 #define FSMC_PCRx_PWID_0                    (0x1UL << FSMC_PCRx_PWID_Pos)       /*!< 0x00000010 */
5377 #define FSMC_PCRx_PWID_1                    (0x2UL << FSMC_PCRx_PWID_Pos)       /*!< 0x00000020 */
5378 
5379 #define FSMC_PCRx_ECCEN_Pos                 (6U)
5380 #define FSMC_PCRx_ECCEN_Msk                 (0x1UL << FSMC_PCRx_ECCEN_Pos)      /*!< 0x00000040 */
5381 #define FSMC_PCRx_ECCEN                     FSMC_PCRx_ECCEN_Msk                /*!< ECC computation logic enable bit */
5382 
5383 #define FSMC_PCRx_TCLR_Pos                  (9U)
5384 #define FSMC_PCRx_TCLR_Msk                  (0xFUL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00001E00 */
5385 #define FSMC_PCRx_TCLR                      FSMC_PCRx_TCLR_Msk                 /*!< TCLR[3:0] bits (CLE to RE delay) */
5386 #define FSMC_PCRx_TCLR_0                    (0x1UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00000200 */
5387 #define FSMC_PCRx_TCLR_1                    (0x2UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00000400 */
5388 #define FSMC_PCRx_TCLR_2                    (0x4UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00000800 */
5389 #define FSMC_PCRx_TCLR_3                    (0x8UL << FSMC_PCRx_TCLR_Pos)       /*!< 0x00001000 */
5390 
5391 #define FSMC_PCRx_TAR_Pos                   (13U)
5392 #define FSMC_PCRx_TAR_Msk                   (0xFUL << FSMC_PCRx_TAR_Pos)        /*!< 0x0001E000 */
5393 #define FSMC_PCRx_TAR                       FSMC_PCRx_TAR_Msk                  /*!< TAR[3:0] bits (ALE to RE delay) */
5394 #define FSMC_PCRx_TAR_0                     (0x1UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00002000 */
5395 #define FSMC_PCRx_TAR_1                     (0x2UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00004000 */
5396 #define FSMC_PCRx_TAR_2                     (0x4UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00008000 */
5397 #define FSMC_PCRx_TAR_3                     (0x8UL << FSMC_PCRx_TAR_Pos)        /*!< 0x00010000 */
5398 
5399 #define FSMC_PCRx_ECCPS_Pos                 (17U)
5400 #define FSMC_PCRx_ECCPS_Msk                 (0x7UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x000E0000 */
5401 #define FSMC_PCRx_ECCPS                     FSMC_PCRx_ECCPS_Msk                /*!< ECCPS[1:0] bits (ECC page size) */
5402 #define FSMC_PCRx_ECCPS_0                   (0x1UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x00020000 */
5403 #define FSMC_PCRx_ECCPS_1                   (0x2UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x00040000 */
5404 #define FSMC_PCRx_ECCPS_2                   (0x4UL << FSMC_PCRx_ECCPS_Pos)      /*!< 0x00080000 */
5405 
5406 /*******************  Bit definition for FSMC_SRx (x = 2 to 4) register  *******************/
5407 #define FSMC_SRx_IRS_Pos                    (0U)
5408 #define FSMC_SRx_IRS_Msk                    (0x1UL << FSMC_SRx_IRS_Pos)         /*!< 0x00000001 */
5409 #define FSMC_SRx_IRS                        FSMC_SRx_IRS_Msk                   /*!< Interrupt Rising Edge status */
5410 #define FSMC_SRx_ILS_Pos                    (1U)
5411 #define FSMC_SRx_ILS_Msk                    (0x1UL << FSMC_SRx_ILS_Pos)         /*!< 0x00000002 */
5412 #define FSMC_SRx_ILS                        FSMC_SRx_ILS_Msk                   /*!< Interrupt Level status */
5413 #define FSMC_SRx_IFS_Pos                    (2U)
5414 #define FSMC_SRx_IFS_Msk                    (0x1UL << FSMC_SRx_IFS_Pos)         /*!< 0x00000004 */
5415 #define FSMC_SRx_IFS                        FSMC_SRx_IFS_Msk                   /*!< Interrupt Falling Edge status */
5416 #define FSMC_SRx_IREN_Pos                   (3U)
5417 #define FSMC_SRx_IREN_Msk                   (0x1UL << FSMC_SRx_IREN_Pos)        /*!< 0x00000008 */
5418 #define FSMC_SRx_IREN                       FSMC_SRx_IREN_Msk                  /*!< Interrupt Rising Edge detection Enable bit */
5419 #define FSMC_SRx_ILEN_Pos                   (4U)
5420 #define FSMC_SRx_ILEN_Msk                   (0x1UL << FSMC_SRx_ILEN_Pos)        /*!< 0x00000010 */
5421 #define FSMC_SRx_ILEN                       FSMC_SRx_ILEN_Msk                  /*!< Interrupt Level detection Enable bit */
5422 #define FSMC_SRx_IFEN_Pos                   (5U)
5423 #define FSMC_SRx_IFEN_Msk                   (0x1UL << FSMC_SRx_IFEN_Pos)        /*!< 0x00000020 */
5424 #define FSMC_SRx_IFEN                       FSMC_SRx_IFEN_Msk                  /*!< Interrupt Falling Edge detection Enable bit */
5425 #define FSMC_SRx_FEMPT_Pos                  (6U)
5426 #define FSMC_SRx_FEMPT_Msk                  (0x1UL << FSMC_SRx_FEMPT_Pos)       /*!< 0x00000040 */
5427 #define FSMC_SRx_FEMPT                      FSMC_SRx_FEMPT_Msk                 /*!< FIFO empty */
5428 
5429 /******************  Bit definition for FSMC_PMEMx (x = 2 to 4) register  ******************/
5430 #define FSMC_PMEMx_MEMSETx_Pos              (0U)
5431 #define FSMC_PMEMx_MEMSETx_Msk              (0xFFUL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x000000FF */
5432 #define FSMC_PMEMx_MEMSETx                  FSMC_PMEMx_MEMSETx_Msk             /*!< MEMSETx[7:0] bits (Common memory x setup time) */
5433 #define FSMC_PMEMx_MEMSETx_0                (0x01UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000001 */
5434 #define FSMC_PMEMx_MEMSETx_1                (0x02UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000002 */
5435 #define FSMC_PMEMx_MEMSETx_2                (0x04UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000004 */
5436 #define FSMC_PMEMx_MEMSETx_3                (0x08UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000008 */
5437 #define FSMC_PMEMx_MEMSETx_4                (0x10UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000010 */
5438 #define FSMC_PMEMx_MEMSETx_5                (0x20UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000020 */
5439 #define FSMC_PMEMx_MEMSETx_6                (0x40UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000040 */
5440 #define FSMC_PMEMx_MEMSETx_7                (0x80UL << FSMC_PMEMx_MEMSETx_Pos)  /*!< 0x00000080 */
5441 
5442 #define FSMC_PMEMx_MEMWAITx_Pos             (8U)
5443 #define FSMC_PMEMx_MEMWAITx_Msk             (0xFFUL << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
5444 #define FSMC_PMEMx_MEMWAITx                 FSMC_PMEMx_MEMWAITx_Msk            /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
5445 #define FSMC_PMEMx_MEMWAIT2_0               0x00000100U                        /*!< Bit 0 */
5446 #define FSMC_PMEMx_MEMWAITx_1               0x00000200U                        /*!< Bit 1 */
5447 #define FSMC_PMEMx_MEMWAITx_2               0x00000400U                        /*!< Bit 2 */
5448 #define FSMC_PMEMx_MEMWAITx_3               0x00000800U                        /*!< Bit 3 */
5449 #define FSMC_PMEMx_MEMWAITx_4               0x00001000U                        /*!< Bit 4 */
5450 #define FSMC_PMEMx_MEMWAITx_5               0x00002000U                        /*!< Bit 5 */
5451 #define FSMC_PMEMx_MEMWAITx_6               0x00004000U                        /*!< Bit 6 */
5452 #define FSMC_PMEMx_MEMWAITx_7               0x00008000U                        /*!< Bit 7 */
5453 
5454 #define FSMC_PMEMx_MEMHOLDx_Pos             (16U)
5455 #define FSMC_PMEMx_MEMHOLDx_Msk             (0xFFUL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
5456 #define FSMC_PMEMx_MEMHOLDx                 FSMC_PMEMx_MEMHOLDx_Msk            /*!< MEMHOLDx[7:0] bits (Common memory x hold time) */
5457 #define FSMC_PMEMx_MEMHOLDx_0               (0x01UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00010000 */
5458 #define FSMC_PMEMx_MEMHOLDx_1               (0x02UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00020000 */
5459 #define FSMC_PMEMx_MEMHOLDx_2               (0x04UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00040000 */
5460 #define FSMC_PMEMx_MEMHOLDx_3               (0x08UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00080000 */
5461 #define FSMC_PMEMx_MEMHOLDx_4               (0x10UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00100000 */
5462 #define FSMC_PMEMx_MEMHOLDx_5               (0x20UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00200000 */
5463 #define FSMC_PMEMx_MEMHOLDx_6               (0x40UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00400000 */
5464 #define FSMC_PMEMx_MEMHOLDx_7               (0x80UL << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00800000 */
5465 
5466 #define FSMC_PMEMx_MEMHIZx_Pos              (24U)
5467 #define FSMC_PMEMx_MEMHIZx_Msk              (0xFFUL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0xFF000000 */
5468 #define FSMC_PMEMx_MEMHIZx                  FSMC_PMEMx_MEMHIZx_Msk             /*!< MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
5469 #define FSMC_PMEMx_MEMHIZx_0                (0x01UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x01000000 */
5470 #define FSMC_PMEMx_MEMHIZx_1                (0x02UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x02000000 */
5471 #define FSMC_PMEMx_MEMHIZx_2                (0x04UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x04000000 */
5472 #define FSMC_PMEMx_MEMHIZx_3                (0x08UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x08000000 */
5473 #define FSMC_PMEMx_MEMHIZx_4                (0x10UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x10000000 */
5474 #define FSMC_PMEMx_MEMHIZx_5                (0x20UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x20000000 */
5475 #define FSMC_PMEMx_MEMHIZx_6                (0x40UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x40000000 */
5476 #define FSMC_PMEMx_MEMHIZx_7                (0x80UL << FSMC_PMEMx_MEMHIZx_Pos)  /*!< 0x80000000 */
5477 
5478 /******************  Bit definition for FSMC_PATTx (x = 2 to 4) register  ******************/
5479 #define FSMC_PATTx_ATTSETx_Pos              (0U)
5480 #define FSMC_PATTx_ATTSETx_Msk              (0xFFUL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x000000FF */
5481 #define FSMC_PATTx_ATTSETx                  FSMC_PATTx_ATTSETx_Msk             /*!< ATTSETx[7:0] bits (Attribute memory x setup time) */
5482 #define FSMC_PATTx_ATTSETx_0                (0x01UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000001 */
5483 #define FSMC_PATTx_ATTSETx_1                (0x02UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000002 */
5484 #define FSMC_PATTx_ATTSETx_2                (0x04UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000004 */
5485 #define FSMC_PATTx_ATTSETx_3                (0x08UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000008 */
5486 #define FSMC_PATTx_ATTSETx_4                (0x10UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000010 */
5487 #define FSMC_PATTx_ATTSETx_5                (0x20UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000020 */
5488 #define FSMC_PATTx_ATTSETx_6                (0x40UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000040 */
5489 #define FSMC_PATTx_ATTSETx_7                (0x80UL << FSMC_PATTx_ATTSETx_Pos)  /*!< 0x00000080 */
5490 
5491 #define FSMC_PATTx_ATTWAITx_Pos             (8U)
5492 #define FSMC_PATTx_ATTWAITx_Msk             (0xFFUL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x0000FF00 */
5493 #define FSMC_PATTx_ATTWAITx                 FSMC_PATTx_ATTWAITx_Msk            /*!< ATTWAITx[7:0] bits (Attribute memory x wait time) */
5494 #define FSMC_PATTx_ATTWAITx_0               (0x01UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000100 */
5495 #define FSMC_PATTx_ATTWAITx_1               (0x02UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000200 */
5496 #define FSMC_PATTx_ATTWAITx_2               (0x04UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000400 */
5497 #define FSMC_PATTx_ATTWAITx_3               (0x08UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00000800 */
5498 #define FSMC_PATTx_ATTWAITx_4               (0x10UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00001000 */
5499 #define FSMC_PATTx_ATTWAITx_5               (0x20UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00002000 */
5500 #define FSMC_PATTx_ATTWAITx_6               (0x40UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00004000 */
5501 #define FSMC_PATTx_ATTWAITx_7               (0x80UL << FSMC_PATTx_ATTWAITx_Pos) /*!< 0x00008000 */
5502 
5503 #define FSMC_PATTx_ATTHOLDx_Pos             (16U)
5504 #define FSMC_PATTx_ATTHOLDx_Msk             (0xFFUL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00FF0000 */
5505 #define FSMC_PATTx_ATTHOLDx                 FSMC_PATTx_ATTHOLDx_Msk            /*!< ATTHOLDx[7:0] bits (Attribute memory x hold time) */
5506 #define FSMC_PATTx_ATTHOLDx_0               (0x01UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00010000 */
5507 #define FSMC_PATTx_ATTHOLDx_1               (0x02UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00020000 */
5508 #define FSMC_PATTx_ATTHOLDx_2               (0x04UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00040000 */
5509 #define FSMC_PATTx_ATTHOLDx_3               (0x08UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00080000 */
5510 #define FSMC_PATTx_ATTHOLDx_4               (0x10UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00100000 */
5511 #define FSMC_PATTx_ATTHOLDx_5               (0x20UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00200000 */
5512 #define FSMC_PATTx_ATTHOLDx_6               (0x40UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00400000 */
5513 #define FSMC_PATTx_ATTHOLDx_7               (0x80UL << FSMC_PATTx_ATTHOLDx_Pos) /*!< 0x00800000 */
5514 
5515 #define FSMC_PATTx_ATTHIZx_Pos              (24U)
5516 #define FSMC_PATTx_ATTHIZx_Msk              (0xFFUL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0xFF000000 */
5517 #define FSMC_PATTx_ATTHIZx                  FSMC_PATTx_ATTHIZx_Msk             /*!< ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
5518 #define FSMC_PATTx_ATTHIZx_0                (0x01UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x01000000 */
5519 #define FSMC_PATTx_ATTHIZx_1                (0x02UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x02000000 */
5520 #define FSMC_PATTx_ATTHIZx_2                (0x04UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x04000000 */
5521 #define FSMC_PATTx_ATTHIZx_3                (0x08UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x08000000 */
5522 #define FSMC_PATTx_ATTHIZx_4                (0x10UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x10000000 */
5523 #define FSMC_PATTx_ATTHIZx_5                (0x20UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x20000000 */
5524 #define FSMC_PATTx_ATTHIZx_6                (0x40UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x40000000 */
5525 #define FSMC_PATTx_ATTHIZx_7                (0x80UL << FSMC_PATTx_ATTHIZx_Pos)  /*!< 0x80000000 */
5526 
5527 /******************  Bit definition for FSMC_PIO4 register  *******************/
5528 #define FSMC_PIO4_IOSET4_Pos                (0U)
5529 #define FSMC_PIO4_IOSET4_Msk                (0xFFUL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x000000FF */
5530 #define FSMC_PIO4_IOSET4                    FSMC_PIO4_IOSET4_Msk               /*!< IOSET4[7:0] bits (I/O 4 setup time) */
5531 #define FSMC_PIO4_IOSET4_0                  (0x01UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000001 */
5532 #define FSMC_PIO4_IOSET4_1                  (0x02UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000002 */
5533 #define FSMC_PIO4_IOSET4_2                  (0x04UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000004 */
5534 #define FSMC_PIO4_IOSET4_3                  (0x08UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000008 */
5535 #define FSMC_PIO4_IOSET4_4                  (0x10UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000010 */
5536 #define FSMC_PIO4_IOSET4_5                  (0x20UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000020 */
5537 #define FSMC_PIO4_IOSET4_6                  (0x40UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000040 */
5538 #define FSMC_PIO4_IOSET4_7                  (0x80UL << FSMC_PIO4_IOSET4_Pos)    /*!< 0x00000080 */
5539 
5540 #define FSMC_PIO4_IOWAIT4_Pos               (8U)
5541 #define FSMC_PIO4_IOWAIT4_Msk               (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x0000FF00 */
5542 #define FSMC_PIO4_IOWAIT4                   FSMC_PIO4_IOWAIT4_Msk              /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
5543 #define FSMC_PIO4_IOWAIT4_0                 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000100 */
5544 #define FSMC_PIO4_IOWAIT4_1                 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000200 */
5545 #define FSMC_PIO4_IOWAIT4_2                 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000400 */
5546 #define FSMC_PIO4_IOWAIT4_3                 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00000800 */
5547 #define FSMC_PIO4_IOWAIT4_4                 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00001000 */
5548 #define FSMC_PIO4_IOWAIT4_5                 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00002000 */
5549 #define FSMC_PIO4_IOWAIT4_6                 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00004000 */
5550 #define FSMC_PIO4_IOWAIT4_7                 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)   /*!< 0x00008000 */
5551 
5552 #define FSMC_PIO4_IOHOLD4_Pos               (16U)
5553 #define FSMC_PIO4_IOHOLD4_Msk               (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00FF0000 */
5554 #define FSMC_PIO4_IOHOLD4                   FSMC_PIO4_IOHOLD4_Msk              /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
5555 #define FSMC_PIO4_IOHOLD4_0                 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00010000 */
5556 #define FSMC_PIO4_IOHOLD4_1                 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00020000 */
5557 #define FSMC_PIO4_IOHOLD4_2                 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00040000 */
5558 #define FSMC_PIO4_IOHOLD4_3                 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00080000 */
5559 #define FSMC_PIO4_IOHOLD4_4                 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00100000 */
5560 #define FSMC_PIO4_IOHOLD4_5                 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00200000 */
5561 #define FSMC_PIO4_IOHOLD4_6                 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00400000 */
5562 #define FSMC_PIO4_IOHOLD4_7                 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)   /*!< 0x00800000 */
5563 
5564 #define FSMC_PIO4_IOHIZ4_Pos                (24U)
5565 #define FSMC_PIO4_IOHIZ4_Msk                (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0xFF000000 */
5566 #define FSMC_PIO4_IOHIZ4                    FSMC_PIO4_IOHIZ4_Msk               /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
5567 #define FSMC_PIO4_IOHIZ4_0                  (0x01UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x01000000 */
5568 #define FSMC_PIO4_IOHIZ4_1                  (0x02UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x02000000 */
5569 #define FSMC_PIO4_IOHIZ4_2                  (0x04UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x04000000 */
5570 #define FSMC_PIO4_IOHIZ4_3                  (0x08UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x08000000 */
5571 #define FSMC_PIO4_IOHIZ4_4                  (0x10UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x10000000 */
5572 #define FSMC_PIO4_IOHIZ4_5                  (0x20UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x20000000 */
5573 #define FSMC_PIO4_IOHIZ4_6                  (0x40UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x40000000 */
5574 #define FSMC_PIO4_IOHIZ4_7                  (0x80UL << FSMC_PIO4_IOHIZ4_Pos)    /*!< 0x80000000 */
5575 
5576 /******************  Bit definition for FSMC_ECCR2 register  ******************/
5577 #define FSMC_ECCR2_ECC2_Pos                 (0U)
5578 #define FSMC_ECCR2_ECC2_Msk                 (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
5579 #define FSMC_ECCR2_ECC2                     FSMC_ECCR2_ECC2_Msk                /*!< ECC result */
5580 
5581 /******************  Bit definition for FSMC_ECCR3 register  ******************/
5582 #define FSMC_ECCR3_ECC3_Pos                 (0U)
5583 #define FSMC_ECCR3_ECC3_Msk                 (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
5584 #define FSMC_ECCR3_ECC3                     FSMC_ECCR3_ECC3_Msk                /*!< ECC result */
5585 
5586 /******************************************************************************/
5587 /*                                                                            */
5588 /*                          SD host Interface                                 */
5589 /*                                                                            */
5590 /******************************************************************************/
5591 
5592 /******************  Bit definition for SDIO_POWER register  ******************/
5593 #define SDIO_POWER_PWRCTRL_Pos              (0U)
5594 #define SDIO_POWER_PWRCTRL_Msk              (0x3UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x00000003 */
5595 #define SDIO_POWER_PWRCTRL                  SDIO_POWER_PWRCTRL_Msk             /*!< PWRCTRL[1:0] bits (Power supply control bits) */
5596 #define SDIO_POWER_PWRCTRL_0                (0x1UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x01 */
5597 #define SDIO_POWER_PWRCTRL_1                (0x2UL << SDIO_POWER_PWRCTRL_Pos)   /*!< 0x02 */
5598 
5599 /******************  Bit definition for SDIO_CLKCR register  ******************/
5600 #define SDIO_CLKCR_CLKDIV_Pos               (0U)
5601 #define SDIO_CLKCR_CLKDIV_Msk               (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)   /*!< 0x000000FF */
5602 #define SDIO_CLKCR_CLKDIV                   SDIO_CLKCR_CLKDIV_Msk              /*!< Clock divide factor */
5603 #define SDIO_CLKCR_CLKEN_Pos                (8U)
5604 #define SDIO_CLKCR_CLKEN_Msk                (0x1UL << SDIO_CLKCR_CLKEN_Pos)     /*!< 0x00000100 */
5605 #define SDIO_CLKCR_CLKEN                    SDIO_CLKCR_CLKEN_Msk               /*!< Clock enable bit */
5606 #define SDIO_CLKCR_PWRSAV_Pos               (9U)
5607 #define SDIO_CLKCR_PWRSAV_Msk               (0x1UL << SDIO_CLKCR_PWRSAV_Pos)    /*!< 0x00000200 */
5608 #define SDIO_CLKCR_PWRSAV                   SDIO_CLKCR_PWRSAV_Msk              /*!< Power saving configuration bit */
5609 #define SDIO_CLKCR_BYPASS_Pos               (10U)
5610 #define SDIO_CLKCR_BYPASS_Msk               (0x1UL << SDIO_CLKCR_BYPASS_Pos)    /*!< 0x00000400 */
5611 #define SDIO_CLKCR_BYPASS                   SDIO_CLKCR_BYPASS_Msk              /*!< Clock divider bypass enable bit */
5612 
5613 #define SDIO_CLKCR_WIDBUS_Pos               (11U)
5614 #define SDIO_CLKCR_WIDBUS_Msk               (0x3UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x00001800 */
5615 #define SDIO_CLKCR_WIDBUS                   SDIO_CLKCR_WIDBUS_Msk              /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
5616 #define SDIO_CLKCR_WIDBUS_0                 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x0800 */
5617 #define SDIO_CLKCR_WIDBUS_1                 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)    /*!< 0x1000 */
5618 
5619 #define SDIO_CLKCR_NEGEDGE_Pos              (13U)
5620 #define SDIO_CLKCR_NEGEDGE_Msk              (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)   /*!< 0x00002000 */
5621 #define SDIO_CLKCR_NEGEDGE                  SDIO_CLKCR_NEGEDGE_Msk             /*!< SDIO_CK dephasing selection bit */
5622 #define SDIO_CLKCR_HWFC_EN_Pos              (14U)
5623 #define SDIO_CLKCR_HWFC_EN_Msk              (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)   /*!< 0x00004000 */
5624 #define SDIO_CLKCR_HWFC_EN                  SDIO_CLKCR_HWFC_EN_Msk             /*!< HW Flow Control enable */
5625 
5626 /*******************  Bit definition for SDIO_ARG register  *******************/
5627 #define SDIO_ARG_CMDARG_Pos                 (0U)
5628 #define SDIO_ARG_CMDARG_Msk                 (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
5629 #define SDIO_ARG_CMDARG                     SDIO_ARG_CMDARG_Msk                /*!< Command argument */
5630 
5631 /*******************  Bit definition for SDIO_CMD register  *******************/
5632 #define SDIO_CMD_CMDINDEX_Pos               (0U)
5633 #define SDIO_CMD_CMDINDEX_Msk               (0x3FUL << SDIO_CMD_CMDINDEX_Pos)   /*!< 0x0000003F */
5634 #define SDIO_CMD_CMDINDEX                   SDIO_CMD_CMDINDEX_Msk              /*!< Command Index */
5635 
5636 #define SDIO_CMD_WAITRESP_Pos               (6U)
5637 #define SDIO_CMD_WAITRESP_Msk               (0x3UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x000000C0 */
5638 #define SDIO_CMD_WAITRESP                   SDIO_CMD_WAITRESP_Msk              /*!< WAITRESP[1:0] bits (Wait for response bits) */
5639 #define SDIO_CMD_WAITRESP_0                 (0x1UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0040 */
5640 #define SDIO_CMD_WAITRESP_1                 (0x2UL << SDIO_CMD_WAITRESP_Pos)    /*!< 0x0080 */
5641 
5642 #define SDIO_CMD_WAITINT_Pos                (8U)
5643 #define SDIO_CMD_WAITINT_Msk                (0x1UL << SDIO_CMD_WAITINT_Pos)     /*!< 0x00000100 */
5644 #define SDIO_CMD_WAITINT                    SDIO_CMD_WAITINT_Msk               /*!< CPSM Waits for Interrupt Request */
5645 #define SDIO_CMD_WAITPEND_Pos               (9U)
5646 #define SDIO_CMD_WAITPEND_Msk               (0x1UL << SDIO_CMD_WAITPEND_Pos)    /*!< 0x00000200 */
5647 #define SDIO_CMD_WAITPEND                   SDIO_CMD_WAITPEND_Msk              /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
5648 #define SDIO_CMD_CPSMEN_Pos                 (10U)
5649 #define SDIO_CMD_CPSMEN_Msk                 (0x1UL << SDIO_CMD_CPSMEN_Pos)      /*!< 0x00000400 */
5650 #define SDIO_CMD_CPSMEN                     SDIO_CMD_CPSMEN_Msk                /*!< Command path state machine (CPSM) Enable bit */
5651 #define SDIO_CMD_SDIOSUSPEND_Pos            (11U)
5652 #define SDIO_CMD_SDIOSUSPEND_Msk            (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
5653 #define SDIO_CMD_SDIOSUSPEND                SDIO_CMD_SDIOSUSPEND_Msk           /*!< SD I/O suspend command */
5654 #define SDIO_CMD_ENCMDCOMPL_Pos             (12U)
5655 #define SDIO_CMD_ENCMDCOMPL_Msk             (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)  /*!< 0x00001000 */
5656 #define SDIO_CMD_ENCMDCOMPL                 SDIO_CMD_ENCMDCOMPL_Msk            /*!< Enable CMD completion */
5657 #define SDIO_CMD_NIEN_Pos                   (13U)
5658 #define SDIO_CMD_NIEN_Msk                   (0x1UL << SDIO_CMD_NIEN_Pos)        /*!< 0x00002000 */
5659 #define SDIO_CMD_NIEN                       SDIO_CMD_NIEN_Msk                  /*!< Not Interrupt Enable */
5660 #define SDIO_CMD_CEATACMD_Pos               (14U)
5661 #define SDIO_CMD_CEATACMD_Msk               (0x1UL << SDIO_CMD_CEATACMD_Pos)    /*!< 0x00004000 */
5662 #define SDIO_CMD_CEATACMD                   SDIO_CMD_CEATACMD_Msk              /*!< CE-ATA command */
5663 
5664 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
5665 #define SDIO_RESPCMD_RESPCMD_Pos            (0U)
5666 #define SDIO_RESPCMD_RESPCMD_Msk            (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
5667 #define SDIO_RESPCMD_RESPCMD                SDIO_RESPCMD_RESPCMD_Msk           /*!< Response command index */
5668 
5669 /******************  Bit definition for SDIO_RESP0 register  ******************/
5670 #define SDIO_RESP0_CARDSTATUS0_Pos          (0U)
5671 #define SDIO_RESP0_CARDSTATUS0_Msk          (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
5672 #define SDIO_RESP0_CARDSTATUS0              SDIO_RESP0_CARDSTATUS0_Msk         /*!< Card Status */
5673 
5674 /******************  Bit definition for SDIO_RESP1 register  ******************/
5675 #define SDIO_RESP1_CARDSTATUS1_Pos          (0U)
5676 #define SDIO_RESP1_CARDSTATUS1_Msk          (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
5677 #define SDIO_RESP1_CARDSTATUS1              SDIO_RESP1_CARDSTATUS1_Msk         /*!< Card Status */
5678 
5679 /******************  Bit definition for SDIO_RESP2 register  ******************/
5680 #define SDIO_RESP2_CARDSTATUS2_Pos          (0U)
5681 #define SDIO_RESP2_CARDSTATUS2_Msk          (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
5682 #define SDIO_RESP2_CARDSTATUS2              SDIO_RESP2_CARDSTATUS2_Msk         /*!< Card Status */
5683 
5684 /******************  Bit definition for SDIO_RESP3 register  ******************/
5685 #define SDIO_RESP3_CARDSTATUS3_Pos          (0U)
5686 #define SDIO_RESP3_CARDSTATUS3_Msk          (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
5687 #define SDIO_RESP3_CARDSTATUS3              SDIO_RESP3_CARDSTATUS3_Msk         /*!< Card Status */
5688 
5689 /******************  Bit definition for SDIO_RESP4 register  ******************/
5690 #define SDIO_RESP4_CARDSTATUS4_Pos          (0U)
5691 #define SDIO_RESP4_CARDSTATUS4_Msk          (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
5692 #define SDIO_RESP4_CARDSTATUS4              SDIO_RESP4_CARDSTATUS4_Msk         /*!< Card Status */
5693 
5694 /******************  Bit definition for SDIO_DTIMER register  *****************/
5695 #define SDIO_DTIMER_DATATIME_Pos            (0U)
5696 #define SDIO_DTIMER_DATATIME_Msk            (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
5697 #define SDIO_DTIMER_DATATIME                SDIO_DTIMER_DATATIME_Msk           /*!< Data timeout period. */
5698 
5699 /******************  Bit definition for SDIO_DLEN register  *******************/
5700 #define SDIO_DLEN_DATALENGTH_Pos            (0U)
5701 #define SDIO_DLEN_DATALENGTH_Msk            (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
5702 #define SDIO_DLEN_DATALENGTH                SDIO_DLEN_DATALENGTH_Msk           /*!< Data length value */
5703 
5704 /******************  Bit definition for SDIO_DCTRL register  ******************/
5705 #define SDIO_DCTRL_DTEN_Pos                 (0U)
5706 #define SDIO_DCTRL_DTEN_Msk                 (0x1UL << SDIO_DCTRL_DTEN_Pos)      /*!< 0x00000001 */
5707 #define SDIO_DCTRL_DTEN                     SDIO_DCTRL_DTEN_Msk                /*!< Data transfer enabled bit */
5708 #define SDIO_DCTRL_DTDIR_Pos                (1U)
5709 #define SDIO_DCTRL_DTDIR_Msk                (0x1UL << SDIO_DCTRL_DTDIR_Pos)     /*!< 0x00000002 */
5710 #define SDIO_DCTRL_DTDIR                    SDIO_DCTRL_DTDIR_Msk               /*!< Data transfer direction selection */
5711 #define SDIO_DCTRL_DTMODE_Pos               (2U)
5712 #define SDIO_DCTRL_DTMODE_Msk               (0x1UL << SDIO_DCTRL_DTMODE_Pos)    /*!< 0x00000004 */
5713 #define SDIO_DCTRL_DTMODE                   SDIO_DCTRL_DTMODE_Msk              /*!< Data transfer mode selection */
5714 #define SDIO_DCTRL_DMAEN_Pos                (3U)
5715 #define SDIO_DCTRL_DMAEN_Msk                (0x1UL << SDIO_DCTRL_DMAEN_Pos)     /*!< 0x00000008 */
5716 #define SDIO_DCTRL_DMAEN                    SDIO_DCTRL_DMAEN_Msk               /*!< DMA enabled bit */
5717 
5718 #define SDIO_DCTRL_DBLOCKSIZE_Pos           (4U)
5719 #define SDIO_DCTRL_DBLOCKSIZE_Msk           (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
5720 #define SDIO_DCTRL_DBLOCKSIZE               SDIO_DCTRL_DBLOCKSIZE_Msk          /*!< DBLOCKSIZE[3:0] bits (Data block size) */
5721 #define SDIO_DCTRL_DBLOCKSIZE_0             (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
5722 #define SDIO_DCTRL_DBLOCKSIZE_1             (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
5723 #define SDIO_DCTRL_DBLOCKSIZE_2             (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
5724 #define SDIO_DCTRL_DBLOCKSIZE_3             (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
5725 
5726 #define SDIO_DCTRL_RWSTART_Pos              (8U)
5727 #define SDIO_DCTRL_RWSTART_Msk              (0x1UL << SDIO_DCTRL_RWSTART_Pos)   /*!< 0x00000100 */
5728 #define SDIO_DCTRL_RWSTART                  SDIO_DCTRL_RWSTART_Msk             /*!< Read wait start */
5729 #define SDIO_DCTRL_RWSTOP_Pos               (9U)
5730 #define SDIO_DCTRL_RWSTOP_Msk               (0x1UL << SDIO_DCTRL_RWSTOP_Pos)    /*!< 0x00000200 */
5731 #define SDIO_DCTRL_RWSTOP                   SDIO_DCTRL_RWSTOP_Msk              /*!< Read wait stop */
5732 #define SDIO_DCTRL_RWMOD_Pos                (10U)
5733 #define SDIO_DCTRL_RWMOD_Msk                (0x1UL << SDIO_DCTRL_RWMOD_Pos)     /*!< 0x00000400 */
5734 #define SDIO_DCTRL_RWMOD                    SDIO_DCTRL_RWMOD_Msk               /*!< Read wait mode */
5735 #define SDIO_DCTRL_SDIOEN_Pos               (11U)
5736 #define SDIO_DCTRL_SDIOEN_Msk               (0x1UL << SDIO_DCTRL_SDIOEN_Pos)    /*!< 0x00000800 */
5737 #define SDIO_DCTRL_SDIOEN                   SDIO_DCTRL_SDIOEN_Msk              /*!< SD I/O enable functions */
5738 
5739 /******************  Bit definition for SDIO_DCOUNT register  *****************/
5740 #define SDIO_DCOUNT_DATACOUNT_Pos           (0U)
5741 #define SDIO_DCOUNT_DATACOUNT_Msk           (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
5742 #define SDIO_DCOUNT_DATACOUNT               SDIO_DCOUNT_DATACOUNT_Msk          /*!< Data count value */
5743 
5744 /******************  Bit definition for SDIO_STA register  ********************/
5745 #define SDIO_STA_CCRCFAIL_Pos               (0U)
5746 #define SDIO_STA_CCRCFAIL_Msk               (0x1UL << SDIO_STA_CCRCFAIL_Pos)    /*!< 0x00000001 */
5747 #define SDIO_STA_CCRCFAIL                   SDIO_STA_CCRCFAIL_Msk              /*!< Command response received (CRC check failed) */
5748 #define SDIO_STA_DCRCFAIL_Pos               (1U)
5749 #define SDIO_STA_DCRCFAIL_Msk               (0x1UL << SDIO_STA_DCRCFAIL_Pos)    /*!< 0x00000002 */
5750 #define SDIO_STA_DCRCFAIL                   SDIO_STA_DCRCFAIL_Msk              /*!< Data block sent/received (CRC check failed) */
5751 #define SDIO_STA_CTIMEOUT_Pos               (2U)
5752 #define SDIO_STA_CTIMEOUT_Msk               (0x1UL << SDIO_STA_CTIMEOUT_Pos)    /*!< 0x00000004 */
5753 #define SDIO_STA_CTIMEOUT                   SDIO_STA_CTIMEOUT_Msk              /*!< Command response timeout */
5754 #define SDIO_STA_DTIMEOUT_Pos               (3U)
5755 #define SDIO_STA_DTIMEOUT_Msk               (0x1UL << SDIO_STA_DTIMEOUT_Pos)    /*!< 0x00000008 */
5756 #define SDIO_STA_DTIMEOUT                   SDIO_STA_DTIMEOUT_Msk              /*!< Data timeout */
5757 #define SDIO_STA_TXUNDERR_Pos               (4U)
5758 #define SDIO_STA_TXUNDERR_Msk               (0x1UL << SDIO_STA_TXUNDERR_Pos)    /*!< 0x00000010 */
5759 #define SDIO_STA_TXUNDERR                   SDIO_STA_TXUNDERR_Msk              /*!< Transmit FIFO underrun error */
5760 #define SDIO_STA_RXOVERR_Pos                (5U)
5761 #define SDIO_STA_RXOVERR_Msk                (0x1UL << SDIO_STA_RXOVERR_Pos)     /*!< 0x00000020 */
5762 #define SDIO_STA_RXOVERR                    SDIO_STA_RXOVERR_Msk               /*!< Received FIFO overrun error */
5763 #define SDIO_STA_CMDREND_Pos                (6U)
5764 #define SDIO_STA_CMDREND_Msk                (0x1UL << SDIO_STA_CMDREND_Pos)     /*!< 0x00000040 */
5765 #define SDIO_STA_CMDREND                    SDIO_STA_CMDREND_Msk               /*!< Command response received (CRC check passed) */
5766 #define SDIO_STA_CMDSENT_Pos                (7U)
5767 #define SDIO_STA_CMDSENT_Msk                (0x1UL << SDIO_STA_CMDSENT_Pos)     /*!< 0x00000080 */
5768 #define SDIO_STA_CMDSENT                    SDIO_STA_CMDSENT_Msk               /*!< Command sent (no response required) */
5769 #define SDIO_STA_DATAEND_Pos                (8U)
5770 #define SDIO_STA_DATAEND_Msk                (0x1UL << SDIO_STA_DATAEND_Pos)     /*!< 0x00000100 */
5771 #define SDIO_STA_DATAEND                    SDIO_STA_DATAEND_Msk               /*!< Data end (data counter, SDIDCOUNT, is zero) */
5772 #define SDIO_STA_STBITERR_Pos               (9U)
5773 #define SDIO_STA_STBITERR_Msk               (0x1UL << SDIO_STA_STBITERR_Pos)    /*!< 0x00000200 */
5774 #define SDIO_STA_STBITERR                   SDIO_STA_STBITERR_Msk              /*!< Start bit not detected on all data signals in wide bus mode */
5775 #define SDIO_STA_DBCKEND_Pos                (10U)
5776 #define SDIO_STA_DBCKEND_Msk                (0x1UL << SDIO_STA_DBCKEND_Pos)     /*!< 0x00000400 */
5777 #define SDIO_STA_DBCKEND                    SDIO_STA_DBCKEND_Msk               /*!< Data block sent/received (CRC check passed) */
5778 #define SDIO_STA_CMDACT_Pos                 (11U)
5779 #define SDIO_STA_CMDACT_Msk                 (0x1UL << SDIO_STA_CMDACT_Pos)      /*!< 0x00000800 */
5780 #define SDIO_STA_CMDACT                     SDIO_STA_CMDACT_Msk                /*!< Command transfer in progress */
5781 #define SDIO_STA_TXACT_Pos                  (12U)
5782 #define SDIO_STA_TXACT_Msk                  (0x1UL << SDIO_STA_TXACT_Pos)       /*!< 0x00001000 */
5783 #define SDIO_STA_TXACT                      SDIO_STA_TXACT_Msk                 /*!< Data transmit in progress */
5784 #define SDIO_STA_RXACT_Pos                  (13U)
5785 #define SDIO_STA_RXACT_Msk                  (0x1UL << SDIO_STA_RXACT_Pos)       /*!< 0x00002000 */
5786 #define SDIO_STA_RXACT                      SDIO_STA_RXACT_Msk                 /*!< Data receive in progress */
5787 #define SDIO_STA_TXFIFOHE_Pos               (14U)
5788 #define SDIO_STA_TXFIFOHE_Msk               (0x1UL << SDIO_STA_TXFIFOHE_Pos)    /*!< 0x00004000 */
5789 #define SDIO_STA_TXFIFOHE                   SDIO_STA_TXFIFOHE_Msk              /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5790 #define SDIO_STA_RXFIFOHF_Pos               (15U)
5791 #define SDIO_STA_RXFIFOHF_Msk               (0x1UL << SDIO_STA_RXFIFOHF_Pos)    /*!< 0x00008000 */
5792 #define SDIO_STA_RXFIFOHF                   SDIO_STA_RXFIFOHF_Msk              /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
5793 #define SDIO_STA_TXFIFOF_Pos                (16U)
5794 #define SDIO_STA_TXFIFOF_Msk                (0x1UL << SDIO_STA_TXFIFOF_Pos)     /*!< 0x00010000 */
5795 #define SDIO_STA_TXFIFOF                    SDIO_STA_TXFIFOF_Msk               /*!< Transmit FIFO full */
5796 #define SDIO_STA_RXFIFOF_Pos                (17U)
5797 #define SDIO_STA_RXFIFOF_Msk                (0x1UL << SDIO_STA_RXFIFOF_Pos)     /*!< 0x00020000 */
5798 #define SDIO_STA_RXFIFOF                    SDIO_STA_RXFIFOF_Msk               /*!< Receive FIFO full */
5799 #define SDIO_STA_TXFIFOE_Pos                (18U)
5800 #define SDIO_STA_TXFIFOE_Msk                (0x1UL << SDIO_STA_TXFIFOE_Pos)     /*!< 0x00040000 */
5801 #define SDIO_STA_TXFIFOE                    SDIO_STA_TXFIFOE_Msk               /*!< Transmit FIFO empty */
5802 #define SDIO_STA_RXFIFOE_Pos                (19U)
5803 #define SDIO_STA_RXFIFOE_Msk                (0x1UL << SDIO_STA_RXFIFOE_Pos)     /*!< 0x00080000 */
5804 #define SDIO_STA_RXFIFOE                    SDIO_STA_RXFIFOE_Msk               /*!< Receive FIFO empty */
5805 #define SDIO_STA_TXDAVL_Pos                 (20U)
5806 #define SDIO_STA_TXDAVL_Msk                 (0x1UL << SDIO_STA_TXDAVL_Pos)      /*!< 0x00100000 */
5807 #define SDIO_STA_TXDAVL                     SDIO_STA_TXDAVL_Msk                /*!< Data available in transmit FIFO */
5808 #define SDIO_STA_RXDAVL_Pos                 (21U)
5809 #define SDIO_STA_RXDAVL_Msk                 (0x1UL << SDIO_STA_RXDAVL_Pos)      /*!< 0x00200000 */
5810 #define SDIO_STA_RXDAVL                     SDIO_STA_RXDAVL_Msk                /*!< Data available in receive FIFO */
5811 #define SDIO_STA_SDIOIT_Pos                 (22U)
5812 #define SDIO_STA_SDIOIT_Msk                 (0x1UL << SDIO_STA_SDIOIT_Pos)      /*!< 0x00400000 */
5813 #define SDIO_STA_SDIOIT                     SDIO_STA_SDIOIT_Msk                /*!< SDIO interrupt received */
5814 #define SDIO_STA_CEATAEND_Pos               (23U)
5815 #define SDIO_STA_CEATAEND_Msk               (0x1UL << SDIO_STA_CEATAEND_Pos)    /*!< 0x00800000 */
5816 #define SDIO_STA_CEATAEND                   SDIO_STA_CEATAEND_Msk              /*!< CE-ATA command completion signal received for CMD61 */
5817 
5818 /*******************  Bit definition for SDIO_ICR register  *******************/
5819 #define SDIO_ICR_CCRCFAILC_Pos              (0U)
5820 #define SDIO_ICR_CCRCFAILC_Msk              (0x1UL << SDIO_ICR_CCRCFAILC_Pos)   /*!< 0x00000001 */
5821 #define SDIO_ICR_CCRCFAILC                  SDIO_ICR_CCRCFAILC_Msk             /*!< CCRCFAIL flag clear bit */
5822 #define SDIO_ICR_DCRCFAILC_Pos              (1U)
5823 #define SDIO_ICR_DCRCFAILC_Msk              (0x1UL << SDIO_ICR_DCRCFAILC_Pos)   /*!< 0x00000002 */
5824 #define SDIO_ICR_DCRCFAILC                  SDIO_ICR_DCRCFAILC_Msk             /*!< DCRCFAIL flag clear bit */
5825 #define SDIO_ICR_CTIMEOUTC_Pos              (2U)
5826 #define SDIO_ICR_CTIMEOUTC_Msk              (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)   /*!< 0x00000004 */
5827 #define SDIO_ICR_CTIMEOUTC                  SDIO_ICR_CTIMEOUTC_Msk             /*!< CTIMEOUT flag clear bit */
5828 #define SDIO_ICR_DTIMEOUTC_Pos              (3U)
5829 #define SDIO_ICR_DTIMEOUTC_Msk              (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)   /*!< 0x00000008 */
5830 #define SDIO_ICR_DTIMEOUTC                  SDIO_ICR_DTIMEOUTC_Msk             /*!< DTIMEOUT flag clear bit */
5831 #define SDIO_ICR_TXUNDERRC_Pos              (4U)
5832 #define SDIO_ICR_TXUNDERRC_Msk              (0x1UL << SDIO_ICR_TXUNDERRC_Pos)   /*!< 0x00000010 */
5833 #define SDIO_ICR_TXUNDERRC                  SDIO_ICR_TXUNDERRC_Msk             /*!< TXUNDERR flag clear bit */
5834 #define SDIO_ICR_RXOVERRC_Pos               (5U)
5835 #define SDIO_ICR_RXOVERRC_Msk               (0x1UL << SDIO_ICR_RXOVERRC_Pos)    /*!< 0x00000020 */
5836 #define SDIO_ICR_RXOVERRC                   SDIO_ICR_RXOVERRC_Msk              /*!< RXOVERR flag clear bit */
5837 #define SDIO_ICR_CMDRENDC_Pos               (6U)
5838 #define SDIO_ICR_CMDRENDC_Msk               (0x1UL << SDIO_ICR_CMDRENDC_Pos)    /*!< 0x00000040 */
5839 #define SDIO_ICR_CMDRENDC                   SDIO_ICR_CMDRENDC_Msk              /*!< CMDREND flag clear bit */
5840 #define SDIO_ICR_CMDSENTC_Pos               (7U)
5841 #define SDIO_ICR_CMDSENTC_Msk               (0x1UL << SDIO_ICR_CMDSENTC_Pos)    /*!< 0x00000080 */
5842 #define SDIO_ICR_CMDSENTC                   SDIO_ICR_CMDSENTC_Msk              /*!< CMDSENT flag clear bit */
5843 #define SDIO_ICR_DATAENDC_Pos               (8U)
5844 #define SDIO_ICR_DATAENDC_Msk               (0x1UL << SDIO_ICR_DATAENDC_Pos)    /*!< 0x00000100 */
5845 #define SDIO_ICR_DATAENDC                   SDIO_ICR_DATAENDC_Msk              /*!< DATAEND flag clear bit */
5846 #define SDIO_ICR_STBITERRC_Pos              (9U)
5847 #define SDIO_ICR_STBITERRC_Msk              (0x1UL << SDIO_ICR_STBITERRC_Pos)   /*!< 0x00000200 */
5848 #define SDIO_ICR_STBITERRC                  SDIO_ICR_STBITERRC_Msk             /*!< STBITERR flag clear bit */
5849 #define SDIO_ICR_DBCKENDC_Pos               (10U)
5850 #define SDIO_ICR_DBCKENDC_Msk               (0x1UL << SDIO_ICR_DBCKENDC_Pos)    /*!< 0x00000400 */
5851 #define SDIO_ICR_DBCKENDC                   SDIO_ICR_DBCKENDC_Msk              /*!< DBCKEND flag clear bit */
5852 #define SDIO_ICR_SDIOITC_Pos                (22U)
5853 #define SDIO_ICR_SDIOITC_Msk                (0x1UL << SDIO_ICR_SDIOITC_Pos)     /*!< 0x00400000 */
5854 #define SDIO_ICR_SDIOITC                    SDIO_ICR_SDIOITC_Msk               /*!< SDIOIT flag clear bit */
5855 #define SDIO_ICR_CEATAENDC_Pos              (23U)
5856 #define SDIO_ICR_CEATAENDC_Msk              (0x1UL << SDIO_ICR_CEATAENDC_Pos)   /*!< 0x00800000 */
5857 #define SDIO_ICR_CEATAENDC                  SDIO_ICR_CEATAENDC_Msk             /*!< CEATAEND flag clear bit */
5858 
5859 /******************  Bit definition for SDIO_MASK register  *******************/
5860 #define SDIO_MASK_CCRCFAILIE_Pos            (0U)
5861 #define SDIO_MASK_CCRCFAILIE_Msk            (0x1UL << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
5862 #define SDIO_MASK_CCRCFAILIE                SDIO_MASK_CCRCFAILIE_Msk           /*!< Command CRC Fail Interrupt Enable */
5863 #define SDIO_MASK_DCRCFAILIE_Pos            (1U)
5864 #define SDIO_MASK_DCRCFAILIE_Msk            (0x1UL << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
5865 #define SDIO_MASK_DCRCFAILIE                SDIO_MASK_DCRCFAILIE_Msk           /*!< Data CRC Fail Interrupt Enable */
5866 #define SDIO_MASK_CTIMEOUTIE_Pos            (2U)
5867 #define SDIO_MASK_CTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
5868 #define SDIO_MASK_CTIMEOUTIE                SDIO_MASK_CTIMEOUTIE_Msk           /*!< Command TimeOut Interrupt Enable */
5869 #define SDIO_MASK_DTIMEOUTIE_Pos            (3U)
5870 #define SDIO_MASK_DTIMEOUTIE_Msk            (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
5871 #define SDIO_MASK_DTIMEOUTIE                SDIO_MASK_DTIMEOUTIE_Msk           /*!< Data TimeOut Interrupt Enable */
5872 #define SDIO_MASK_TXUNDERRIE_Pos            (4U)
5873 #define SDIO_MASK_TXUNDERRIE_Msk            (0x1UL << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
5874 #define SDIO_MASK_TXUNDERRIE                SDIO_MASK_TXUNDERRIE_Msk           /*!< Tx FIFO UnderRun Error Interrupt Enable */
5875 #define SDIO_MASK_RXOVERRIE_Pos             (5U)
5876 #define SDIO_MASK_RXOVERRIE_Msk             (0x1UL << SDIO_MASK_RXOVERRIE_Pos)  /*!< 0x00000020 */
5877 #define SDIO_MASK_RXOVERRIE                 SDIO_MASK_RXOVERRIE_Msk            /*!< Rx FIFO OverRun Error Interrupt Enable */
5878 #define SDIO_MASK_CMDRENDIE_Pos             (6U)
5879 #define SDIO_MASK_CMDRENDIE_Msk             (0x1UL << SDIO_MASK_CMDRENDIE_Pos)  /*!< 0x00000040 */
5880 #define SDIO_MASK_CMDRENDIE                 SDIO_MASK_CMDRENDIE_Msk            /*!< Command Response Received Interrupt Enable */
5881 #define SDIO_MASK_CMDSENTIE_Pos             (7U)
5882 #define SDIO_MASK_CMDSENTIE_Msk             (0x1UL << SDIO_MASK_CMDSENTIE_Pos)  /*!< 0x00000080 */
5883 #define SDIO_MASK_CMDSENTIE                 SDIO_MASK_CMDSENTIE_Msk            /*!< Command Sent Interrupt Enable */
5884 #define SDIO_MASK_DATAENDIE_Pos             (8U)
5885 #define SDIO_MASK_DATAENDIE_Msk             (0x1UL << SDIO_MASK_DATAENDIE_Pos)  /*!< 0x00000100 */
5886 #define SDIO_MASK_DATAENDIE                 SDIO_MASK_DATAENDIE_Msk            /*!< Data End Interrupt Enable */
5887 #define SDIO_MASK_STBITERRIE_Pos            (9U)
5888 #define SDIO_MASK_STBITERRIE_Msk            (0x1UL << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
5889 #define SDIO_MASK_STBITERRIE                SDIO_MASK_STBITERRIE_Msk           /*!< Start Bit Error Interrupt Enable */
5890 #define SDIO_MASK_DBCKENDIE_Pos             (10U)
5891 #define SDIO_MASK_DBCKENDIE_Msk             (0x1UL << SDIO_MASK_DBCKENDIE_Pos)  /*!< 0x00000400 */
5892 #define SDIO_MASK_DBCKENDIE                 SDIO_MASK_DBCKENDIE_Msk            /*!< Data Block End Interrupt Enable */
5893 #define SDIO_MASK_CMDACTIE_Pos              (11U)
5894 #define SDIO_MASK_CMDACTIE_Msk              (0x1UL << SDIO_MASK_CMDACTIE_Pos)   /*!< 0x00000800 */
5895 #define SDIO_MASK_CMDACTIE                  SDIO_MASK_CMDACTIE_Msk             /*!< Command Acting Interrupt Enable */
5896 #define SDIO_MASK_TXACTIE_Pos               (12U)
5897 #define SDIO_MASK_TXACTIE_Msk               (0x1UL << SDIO_MASK_TXACTIE_Pos)    /*!< 0x00001000 */
5898 #define SDIO_MASK_TXACTIE                   SDIO_MASK_TXACTIE_Msk              /*!< Data Transmit Acting Interrupt Enable */
5899 #define SDIO_MASK_RXACTIE_Pos               (13U)
5900 #define SDIO_MASK_RXACTIE_Msk               (0x1UL << SDIO_MASK_RXACTIE_Pos)    /*!< 0x00002000 */
5901 #define SDIO_MASK_RXACTIE                   SDIO_MASK_RXACTIE_Msk              /*!< Data receive acting interrupt enabled */
5902 #define SDIO_MASK_TXFIFOHEIE_Pos            (14U)
5903 #define SDIO_MASK_TXFIFOHEIE_Msk            (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
5904 #define SDIO_MASK_TXFIFOHEIE                SDIO_MASK_TXFIFOHEIE_Msk           /*!< Tx FIFO Half Empty interrupt Enable */
5905 #define SDIO_MASK_RXFIFOHFIE_Pos            (15U)
5906 #define SDIO_MASK_RXFIFOHFIE_Msk            (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
5907 #define SDIO_MASK_RXFIFOHFIE                SDIO_MASK_RXFIFOHFIE_Msk           /*!< Rx FIFO Half Full interrupt Enable */
5908 #define SDIO_MASK_TXFIFOFIE_Pos             (16U)
5909 #define SDIO_MASK_TXFIFOFIE_Msk             (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)  /*!< 0x00010000 */
5910 #define SDIO_MASK_TXFIFOFIE                 SDIO_MASK_TXFIFOFIE_Msk            /*!< Tx FIFO Full interrupt Enable */
5911 #define SDIO_MASK_RXFIFOFIE_Pos             (17U)
5912 #define SDIO_MASK_RXFIFOFIE_Msk             (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)  /*!< 0x00020000 */
5913 #define SDIO_MASK_RXFIFOFIE                 SDIO_MASK_RXFIFOFIE_Msk            /*!< Rx FIFO Full interrupt Enable */
5914 #define SDIO_MASK_TXFIFOEIE_Pos             (18U)
5915 #define SDIO_MASK_TXFIFOEIE_Msk             (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)  /*!< 0x00040000 */
5916 #define SDIO_MASK_TXFIFOEIE                 SDIO_MASK_TXFIFOEIE_Msk            /*!< Tx FIFO Empty interrupt Enable */
5917 #define SDIO_MASK_RXFIFOEIE_Pos             (19U)
5918 #define SDIO_MASK_RXFIFOEIE_Msk             (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)  /*!< 0x00080000 */
5919 #define SDIO_MASK_RXFIFOEIE                 SDIO_MASK_RXFIFOEIE_Msk            /*!< Rx FIFO Empty interrupt Enable */
5920 #define SDIO_MASK_TXDAVLIE_Pos              (20U)
5921 #define SDIO_MASK_TXDAVLIE_Msk              (0x1UL << SDIO_MASK_TXDAVLIE_Pos)   /*!< 0x00100000 */
5922 #define SDIO_MASK_TXDAVLIE                  SDIO_MASK_TXDAVLIE_Msk             /*!< Data available in Tx FIFO interrupt Enable */
5923 #define SDIO_MASK_RXDAVLIE_Pos              (21U)
5924 #define SDIO_MASK_RXDAVLIE_Msk              (0x1UL << SDIO_MASK_RXDAVLIE_Pos)   /*!< 0x00200000 */
5925 #define SDIO_MASK_RXDAVLIE                  SDIO_MASK_RXDAVLIE_Msk             /*!< Data available in Rx FIFO interrupt Enable */
5926 #define SDIO_MASK_SDIOITIE_Pos              (22U)
5927 #define SDIO_MASK_SDIOITIE_Msk              (0x1UL << SDIO_MASK_SDIOITIE_Pos)   /*!< 0x00400000 */
5928 #define SDIO_MASK_SDIOITIE                  SDIO_MASK_SDIOITIE_Msk             /*!< SDIO Mode Interrupt Received interrupt Enable */
5929 #define SDIO_MASK_CEATAENDIE_Pos            (23U)
5930 #define SDIO_MASK_CEATAENDIE_Msk            (0x1UL << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
5931 #define SDIO_MASK_CEATAENDIE                SDIO_MASK_CEATAENDIE_Msk           /*!< CE-ATA command completion signal received Interrupt Enable */
5932 
5933 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
5934 #define SDIO_FIFOCNT_FIFOCOUNT_Pos          (0U)
5935 #define SDIO_FIFOCNT_FIFOCOUNT_Msk          (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
5936 #define SDIO_FIFOCNT_FIFOCOUNT              SDIO_FIFOCNT_FIFOCOUNT_Msk         /*!< Remaining number of words to be written to or read from the FIFO */
5937 
5938 /******************  Bit definition for SDIO_FIFO register  *******************/
5939 #define SDIO_FIFO_FIFODATA_Pos              (0U)
5940 #define SDIO_FIFO_FIFODATA_Msk              (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
5941 #define SDIO_FIFO_FIFODATA                  SDIO_FIFO_FIFODATA_Msk             /*!< Receive and transmit FIFO data */
5942 
5943 /******************************************************************************/
5944 /*                                                                            */
5945 /*                                   USB Device FS                            */
5946 /*                                                                            */
5947 /******************************************************************************/
5948 
5949 /*!< Endpoint-specific registers */
5950 #define  USB_EP0R                            USB_BASE                      /*!< Endpoint 0 register address */
5951 #define  USB_EP1R                            (USB_BASE + 0x00000004)       /*!< Endpoint 1 register address */
5952 #define  USB_EP2R                            (USB_BASE + 0x00000008)       /*!< Endpoint 2 register address */
5953 #define  USB_EP3R                            (USB_BASE + 0x0000000C)       /*!< Endpoint 3 register address */
5954 #define  USB_EP4R                            (USB_BASE + 0x00000010)       /*!< Endpoint 4 register address */
5955 #define  USB_EP5R                            (USB_BASE + 0x00000014)       /*!< Endpoint 5 register address */
5956 #define  USB_EP6R                            (USB_BASE + 0x00000018)       /*!< Endpoint 6 register address */
5957 #define  USB_EP7R                            (USB_BASE + 0x0000001C)       /*!< Endpoint 7 register address */
5958 
5959 /* bit positions */
5960 #define USB_EP_CTR_RX_Pos                       (15U)
5961 #define USB_EP_CTR_RX_Msk                       (0x1UL << USB_EP_CTR_RX_Pos)    /*!< 0x00008000 */
5962 #define USB_EP_CTR_RX                           USB_EP_CTR_RX_Msk              /*!< EndPoint Correct TRansfer RX */
5963 #define USB_EP_DTOG_RX_Pos                      (14U)
5964 #define USB_EP_DTOG_RX_Msk                      (0x1UL << USB_EP_DTOG_RX_Pos)   /*!< 0x00004000 */
5965 #define USB_EP_DTOG_RX                          USB_EP_DTOG_RX_Msk             /*!< EndPoint Data TOGGLE RX */
5966 #define USB_EPRX_STAT_Pos                       (12U)
5967 #define USB_EPRX_STAT_Msk                       (0x3UL << USB_EPRX_STAT_Pos)    /*!< 0x00003000 */
5968 #define USB_EPRX_STAT                           USB_EPRX_STAT_Msk              /*!< EndPoint RX STATus bit field */
5969 #define USB_EP_SETUP_Pos                        (11U)
5970 #define USB_EP_SETUP_Msk                        (0x1UL << USB_EP_SETUP_Pos)     /*!< 0x00000800 */
5971 #define USB_EP_SETUP                            USB_EP_SETUP_Msk               /*!< EndPoint SETUP */
5972 #define USB_EP_T_FIELD_Pos                      (9U)
5973 #define USB_EP_T_FIELD_Msk                      (0x3UL << USB_EP_T_FIELD_Pos)   /*!< 0x00000600 */
5974 #define USB_EP_T_FIELD                          USB_EP_T_FIELD_Msk             /*!< EndPoint TYPE */
5975 #define USB_EP_KIND_Pos                         (8U)
5976 #define USB_EP_KIND_Msk                         (0x1UL << USB_EP_KIND_Pos)      /*!< 0x00000100 */
5977 #define USB_EP_KIND                             USB_EP_KIND_Msk                /*!< EndPoint KIND */
5978 #define USB_EP_CTR_TX_Pos                       (7U)
5979 #define USB_EP_CTR_TX_Msk                       (0x1UL << USB_EP_CTR_TX_Pos)    /*!< 0x00000080 */
5980 #define USB_EP_CTR_TX                           USB_EP_CTR_TX_Msk              /*!< EndPoint Correct TRansfer TX */
5981 #define USB_EP_DTOG_TX_Pos                      (6U)
5982 #define USB_EP_DTOG_TX_Msk                      (0x1UL << USB_EP_DTOG_TX_Pos)   /*!< 0x00000040 */
5983 #define USB_EP_DTOG_TX                          USB_EP_DTOG_TX_Msk             /*!< EndPoint Data TOGGLE TX */
5984 #define USB_EPTX_STAT_Pos                       (4U)
5985 #define USB_EPTX_STAT_Msk                       (0x3UL << USB_EPTX_STAT_Pos)    /*!< 0x00000030 */
5986 #define USB_EPTX_STAT                           USB_EPTX_STAT_Msk              /*!< EndPoint TX STATus bit field */
5987 #define USB_EPADDR_FIELD_Pos                    (0U)
5988 #define USB_EPADDR_FIELD_Msk                    (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
5989 #define USB_EPADDR_FIELD                        USB_EPADDR_FIELD_Msk           /*!< EndPoint ADDRess FIELD */
5990 
5991 /* EndPoint REGister MASK (no toggle fields) */
5992 #define  USB_EPREG_MASK                      (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
5993                                                                            /*!< EP_TYPE[1:0] EndPoint TYPE */
5994 #define USB_EP_TYPE_MASK_Pos                    (9U)
5995 #define USB_EP_TYPE_MASK_Msk                    (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
5996 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */
5997 #define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */
5998 #define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */
5999 #define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */
6000 #define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */
6001 #define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)
6002 
6003 #define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */
6004                                                                                /*!< STAT_TX[1:0] STATus for TX transfer */
6005 #define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */
6006 #define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */
6007 #define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */
6008 #define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */
6009 #define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */
6010 #define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */
6011 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
6012                                                                                /*!< STAT_RX[1:0] STATus for RX transfer */
6013 #define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */
6014 #define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */
6015 #define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */
6016 #define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */
6017 #define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */
6018 #define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */
6019 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
6020 
6021 /*******************  Bit definition for USB_EP0R register  *******************/
6022 #define USB_EP0R_EA_Pos                         (0U)
6023 #define USB_EP0R_EA_Msk                         (0xFUL << USB_EP0R_EA_Pos)      /*!< 0x0000000F */
6024 #define USB_EP0R_EA                             USB_EP0R_EA_Msk                /*!< Endpoint Address */
6025 
6026 #define USB_EP0R_STAT_TX_Pos                    (4U)
6027 #define USB_EP0R_STAT_TX_Msk                    (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
6028 #define USB_EP0R_STAT_TX                        USB_EP0R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6029 #define USB_EP0R_STAT_TX_0                      (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
6030 #define USB_EP0R_STAT_TX_1                      (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
6031 
6032 #define USB_EP0R_DTOG_TX_Pos                    (6U)
6033 #define USB_EP0R_DTOG_TX_Msk                    (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
6034 #define USB_EP0R_DTOG_TX                        USB_EP0R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6035 #define USB_EP0R_CTR_TX_Pos                     (7U)
6036 #define USB_EP0R_CTR_TX_Msk                     (0x1UL << USB_EP0R_CTR_TX_Pos)  /*!< 0x00000080 */
6037 #define USB_EP0R_CTR_TX                         USB_EP0R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6038 #define USB_EP0R_EP_KIND_Pos                    (8U)
6039 #define USB_EP0R_EP_KIND_Msk                    (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
6040 #define USB_EP0R_EP_KIND                        USB_EP0R_EP_KIND_Msk           /*!< Endpoint Kind */
6041 
6042 #define USB_EP0R_EP_TYPE_Pos                    (9U)
6043 #define USB_EP0R_EP_TYPE_Msk                    (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
6044 #define USB_EP0R_EP_TYPE                        USB_EP0R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6045 #define USB_EP0R_EP_TYPE_0                      (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
6046 #define USB_EP0R_EP_TYPE_1                      (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
6047 
6048 #define USB_EP0R_SETUP_Pos                      (11U)
6049 #define USB_EP0R_SETUP_Msk                      (0x1UL << USB_EP0R_SETUP_Pos)   /*!< 0x00000800 */
6050 #define USB_EP0R_SETUP                          USB_EP0R_SETUP_Msk             /*!< Setup transaction completed */
6051 
6052 #define USB_EP0R_STAT_RX_Pos                    (12U)
6053 #define USB_EP0R_STAT_RX_Msk                    (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
6054 #define USB_EP0R_STAT_RX                        USB_EP0R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6055 #define USB_EP0R_STAT_RX_0                      (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
6056 #define USB_EP0R_STAT_RX_1                      (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
6057 
6058 #define USB_EP0R_DTOG_RX_Pos                    (14U)
6059 #define USB_EP0R_DTOG_RX_Msk                    (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
6060 #define USB_EP0R_DTOG_RX                        USB_EP0R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6061 #define USB_EP0R_CTR_RX_Pos                     (15U)
6062 #define USB_EP0R_CTR_RX_Msk                     (0x1UL << USB_EP0R_CTR_RX_Pos)  /*!< 0x00008000 */
6063 #define USB_EP0R_CTR_RX                         USB_EP0R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6064 
6065 /*******************  Bit definition for USB_EP1R register  *******************/
6066 #define USB_EP1R_EA_Pos                         (0U)
6067 #define USB_EP1R_EA_Msk                         (0xFUL << USB_EP1R_EA_Pos)      /*!< 0x0000000F */
6068 #define USB_EP1R_EA                             USB_EP1R_EA_Msk                /*!< Endpoint Address */
6069 
6070 #define USB_EP1R_STAT_TX_Pos                    (4U)
6071 #define USB_EP1R_STAT_TX_Msk                    (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
6072 #define USB_EP1R_STAT_TX                        USB_EP1R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6073 #define USB_EP1R_STAT_TX_0                      (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
6074 #define USB_EP1R_STAT_TX_1                      (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
6075 
6076 #define USB_EP1R_DTOG_TX_Pos                    (6U)
6077 #define USB_EP1R_DTOG_TX_Msk                    (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
6078 #define USB_EP1R_DTOG_TX                        USB_EP1R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6079 #define USB_EP1R_CTR_TX_Pos                     (7U)
6080 #define USB_EP1R_CTR_TX_Msk                     (0x1UL << USB_EP1R_CTR_TX_Pos)  /*!< 0x00000080 */
6081 #define USB_EP1R_CTR_TX                         USB_EP1R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6082 #define USB_EP1R_EP_KIND_Pos                    (8U)
6083 #define USB_EP1R_EP_KIND_Msk                    (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
6084 #define USB_EP1R_EP_KIND                        USB_EP1R_EP_KIND_Msk           /*!< Endpoint Kind */
6085 
6086 #define USB_EP1R_EP_TYPE_Pos                    (9U)
6087 #define USB_EP1R_EP_TYPE_Msk                    (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
6088 #define USB_EP1R_EP_TYPE                        USB_EP1R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6089 #define USB_EP1R_EP_TYPE_0                      (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
6090 #define USB_EP1R_EP_TYPE_1                      (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
6091 
6092 #define USB_EP1R_SETUP_Pos                      (11U)
6093 #define USB_EP1R_SETUP_Msk                      (0x1UL << USB_EP1R_SETUP_Pos)   /*!< 0x00000800 */
6094 #define USB_EP1R_SETUP                          USB_EP1R_SETUP_Msk             /*!< Setup transaction completed */
6095 
6096 #define USB_EP1R_STAT_RX_Pos                    (12U)
6097 #define USB_EP1R_STAT_RX_Msk                    (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
6098 #define USB_EP1R_STAT_RX                        USB_EP1R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6099 #define USB_EP1R_STAT_RX_0                      (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
6100 #define USB_EP1R_STAT_RX_1                      (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
6101 
6102 #define USB_EP1R_DTOG_RX_Pos                    (14U)
6103 #define USB_EP1R_DTOG_RX_Msk                    (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
6104 #define USB_EP1R_DTOG_RX                        USB_EP1R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6105 #define USB_EP1R_CTR_RX_Pos                     (15U)
6106 #define USB_EP1R_CTR_RX_Msk                     (0x1UL << USB_EP1R_CTR_RX_Pos)  /*!< 0x00008000 */
6107 #define USB_EP1R_CTR_RX                         USB_EP1R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6108 
6109 /*******************  Bit definition for USB_EP2R register  *******************/
6110 #define USB_EP2R_EA_Pos                         (0U)
6111 #define USB_EP2R_EA_Msk                         (0xFUL << USB_EP2R_EA_Pos)      /*!< 0x0000000F */
6112 #define USB_EP2R_EA                             USB_EP2R_EA_Msk                /*!< Endpoint Address */
6113 
6114 #define USB_EP2R_STAT_TX_Pos                    (4U)
6115 #define USB_EP2R_STAT_TX_Msk                    (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
6116 #define USB_EP2R_STAT_TX                        USB_EP2R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6117 #define USB_EP2R_STAT_TX_0                      (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
6118 #define USB_EP2R_STAT_TX_1                      (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
6119 
6120 #define USB_EP2R_DTOG_TX_Pos                    (6U)
6121 #define USB_EP2R_DTOG_TX_Msk                    (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
6122 #define USB_EP2R_DTOG_TX                        USB_EP2R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6123 #define USB_EP2R_CTR_TX_Pos                     (7U)
6124 #define USB_EP2R_CTR_TX_Msk                     (0x1UL << USB_EP2R_CTR_TX_Pos)  /*!< 0x00000080 */
6125 #define USB_EP2R_CTR_TX                         USB_EP2R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6126 #define USB_EP2R_EP_KIND_Pos                    (8U)
6127 #define USB_EP2R_EP_KIND_Msk                    (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
6128 #define USB_EP2R_EP_KIND                        USB_EP2R_EP_KIND_Msk           /*!< Endpoint Kind */
6129 
6130 #define USB_EP2R_EP_TYPE_Pos                    (9U)
6131 #define USB_EP2R_EP_TYPE_Msk                    (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
6132 #define USB_EP2R_EP_TYPE                        USB_EP2R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6133 #define USB_EP2R_EP_TYPE_0                      (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
6134 #define USB_EP2R_EP_TYPE_1                      (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
6135 
6136 #define USB_EP2R_SETUP_Pos                      (11U)
6137 #define USB_EP2R_SETUP_Msk                      (0x1UL << USB_EP2R_SETUP_Pos)   /*!< 0x00000800 */
6138 #define USB_EP2R_SETUP                          USB_EP2R_SETUP_Msk             /*!< Setup transaction completed */
6139 
6140 #define USB_EP2R_STAT_RX_Pos                    (12U)
6141 #define USB_EP2R_STAT_RX_Msk                    (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
6142 #define USB_EP2R_STAT_RX                        USB_EP2R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6143 #define USB_EP2R_STAT_RX_0                      (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
6144 #define USB_EP2R_STAT_RX_1                      (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
6145 
6146 #define USB_EP2R_DTOG_RX_Pos                    (14U)
6147 #define USB_EP2R_DTOG_RX_Msk                    (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
6148 #define USB_EP2R_DTOG_RX                        USB_EP2R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6149 #define USB_EP2R_CTR_RX_Pos                     (15U)
6150 #define USB_EP2R_CTR_RX_Msk                     (0x1UL << USB_EP2R_CTR_RX_Pos)  /*!< 0x00008000 */
6151 #define USB_EP2R_CTR_RX                         USB_EP2R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6152 
6153 /*******************  Bit definition for USB_EP3R register  *******************/
6154 #define USB_EP3R_EA_Pos                         (0U)
6155 #define USB_EP3R_EA_Msk                         (0xFUL << USB_EP3R_EA_Pos)      /*!< 0x0000000F */
6156 #define USB_EP3R_EA                             USB_EP3R_EA_Msk                /*!< Endpoint Address */
6157 
6158 #define USB_EP3R_STAT_TX_Pos                    (4U)
6159 #define USB_EP3R_STAT_TX_Msk                    (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
6160 #define USB_EP3R_STAT_TX                        USB_EP3R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6161 #define USB_EP3R_STAT_TX_0                      (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
6162 #define USB_EP3R_STAT_TX_1                      (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
6163 
6164 #define USB_EP3R_DTOG_TX_Pos                    (6U)
6165 #define USB_EP3R_DTOG_TX_Msk                    (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
6166 #define USB_EP3R_DTOG_TX                        USB_EP3R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6167 #define USB_EP3R_CTR_TX_Pos                     (7U)
6168 #define USB_EP3R_CTR_TX_Msk                     (0x1UL << USB_EP3R_CTR_TX_Pos)  /*!< 0x00000080 */
6169 #define USB_EP3R_CTR_TX                         USB_EP3R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6170 #define USB_EP3R_EP_KIND_Pos                    (8U)
6171 #define USB_EP3R_EP_KIND_Msk                    (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
6172 #define USB_EP3R_EP_KIND                        USB_EP3R_EP_KIND_Msk           /*!< Endpoint Kind */
6173 
6174 #define USB_EP3R_EP_TYPE_Pos                    (9U)
6175 #define USB_EP3R_EP_TYPE_Msk                    (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
6176 #define USB_EP3R_EP_TYPE                        USB_EP3R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6177 #define USB_EP3R_EP_TYPE_0                      (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
6178 #define USB_EP3R_EP_TYPE_1                      (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
6179 
6180 #define USB_EP3R_SETUP_Pos                      (11U)
6181 #define USB_EP3R_SETUP_Msk                      (0x1UL << USB_EP3R_SETUP_Pos)   /*!< 0x00000800 */
6182 #define USB_EP3R_SETUP                          USB_EP3R_SETUP_Msk             /*!< Setup transaction completed */
6183 
6184 #define USB_EP3R_STAT_RX_Pos                    (12U)
6185 #define USB_EP3R_STAT_RX_Msk                    (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
6186 #define USB_EP3R_STAT_RX                        USB_EP3R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6187 #define USB_EP3R_STAT_RX_0                      (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
6188 #define USB_EP3R_STAT_RX_1                      (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
6189 
6190 #define USB_EP3R_DTOG_RX_Pos                    (14U)
6191 #define USB_EP3R_DTOG_RX_Msk                    (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
6192 #define USB_EP3R_DTOG_RX                        USB_EP3R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6193 #define USB_EP3R_CTR_RX_Pos                     (15U)
6194 #define USB_EP3R_CTR_RX_Msk                     (0x1UL << USB_EP3R_CTR_RX_Pos)  /*!< 0x00008000 */
6195 #define USB_EP3R_CTR_RX                         USB_EP3R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6196 
6197 /*******************  Bit definition for USB_EP4R register  *******************/
6198 #define USB_EP4R_EA_Pos                         (0U)
6199 #define USB_EP4R_EA_Msk                         (0xFUL << USB_EP4R_EA_Pos)      /*!< 0x0000000F */
6200 #define USB_EP4R_EA                             USB_EP4R_EA_Msk                /*!< Endpoint Address */
6201 
6202 #define USB_EP4R_STAT_TX_Pos                    (4U)
6203 #define USB_EP4R_STAT_TX_Msk                    (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
6204 #define USB_EP4R_STAT_TX                        USB_EP4R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6205 #define USB_EP4R_STAT_TX_0                      (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
6206 #define USB_EP4R_STAT_TX_1                      (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
6207 
6208 #define USB_EP4R_DTOG_TX_Pos                    (6U)
6209 #define USB_EP4R_DTOG_TX_Msk                    (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
6210 #define USB_EP4R_DTOG_TX                        USB_EP4R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6211 #define USB_EP4R_CTR_TX_Pos                     (7U)
6212 #define USB_EP4R_CTR_TX_Msk                     (0x1UL << USB_EP4R_CTR_TX_Pos)  /*!< 0x00000080 */
6213 #define USB_EP4R_CTR_TX                         USB_EP4R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6214 #define USB_EP4R_EP_KIND_Pos                    (8U)
6215 #define USB_EP4R_EP_KIND_Msk                    (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
6216 #define USB_EP4R_EP_KIND                        USB_EP4R_EP_KIND_Msk           /*!< Endpoint Kind */
6217 
6218 #define USB_EP4R_EP_TYPE_Pos                    (9U)
6219 #define USB_EP4R_EP_TYPE_Msk                    (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
6220 #define USB_EP4R_EP_TYPE                        USB_EP4R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6221 #define USB_EP4R_EP_TYPE_0                      (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
6222 #define USB_EP4R_EP_TYPE_1                      (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
6223 
6224 #define USB_EP4R_SETUP_Pos                      (11U)
6225 #define USB_EP4R_SETUP_Msk                      (0x1UL << USB_EP4R_SETUP_Pos)   /*!< 0x00000800 */
6226 #define USB_EP4R_SETUP                          USB_EP4R_SETUP_Msk             /*!< Setup transaction completed */
6227 
6228 #define USB_EP4R_STAT_RX_Pos                    (12U)
6229 #define USB_EP4R_STAT_RX_Msk                    (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
6230 #define USB_EP4R_STAT_RX                        USB_EP4R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6231 #define USB_EP4R_STAT_RX_0                      (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
6232 #define USB_EP4R_STAT_RX_1                      (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
6233 
6234 #define USB_EP4R_DTOG_RX_Pos                    (14U)
6235 #define USB_EP4R_DTOG_RX_Msk                    (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
6236 #define USB_EP4R_DTOG_RX                        USB_EP4R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6237 #define USB_EP4R_CTR_RX_Pos                     (15U)
6238 #define USB_EP4R_CTR_RX_Msk                     (0x1UL << USB_EP4R_CTR_RX_Pos)  /*!< 0x00008000 */
6239 #define USB_EP4R_CTR_RX                         USB_EP4R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6240 
6241 /*******************  Bit definition for USB_EP5R register  *******************/
6242 #define USB_EP5R_EA_Pos                         (0U)
6243 #define USB_EP5R_EA_Msk                         (0xFUL << USB_EP5R_EA_Pos)      /*!< 0x0000000F */
6244 #define USB_EP5R_EA                             USB_EP5R_EA_Msk                /*!< Endpoint Address */
6245 
6246 #define USB_EP5R_STAT_TX_Pos                    (4U)
6247 #define USB_EP5R_STAT_TX_Msk                    (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
6248 #define USB_EP5R_STAT_TX                        USB_EP5R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6249 #define USB_EP5R_STAT_TX_0                      (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
6250 #define USB_EP5R_STAT_TX_1                      (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
6251 
6252 #define USB_EP5R_DTOG_TX_Pos                    (6U)
6253 #define USB_EP5R_DTOG_TX_Msk                    (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
6254 #define USB_EP5R_DTOG_TX                        USB_EP5R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6255 #define USB_EP5R_CTR_TX_Pos                     (7U)
6256 #define USB_EP5R_CTR_TX_Msk                     (0x1UL << USB_EP5R_CTR_TX_Pos)  /*!< 0x00000080 */
6257 #define USB_EP5R_CTR_TX                         USB_EP5R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6258 #define USB_EP5R_EP_KIND_Pos                    (8U)
6259 #define USB_EP5R_EP_KIND_Msk                    (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
6260 #define USB_EP5R_EP_KIND                        USB_EP5R_EP_KIND_Msk           /*!< Endpoint Kind */
6261 
6262 #define USB_EP5R_EP_TYPE_Pos                    (9U)
6263 #define USB_EP5R_EP_TYPE_Msk                    (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
6264 #define USB_EP5R_EP_TYPE                        USB_EP5R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6265 #define USB_EP5R_EP_TYPE_0                      (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
6266 #define USB_EP5R_EP_TYPE_1                      (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
6267 
6268 #define USB_EP5R_SETUP_Pos                      (11U)
6269 #define USB_EP5R_SETUP_Msk                      (0x1UL << USB_EP5R_SETUP_Pos)   /*!< 0x00000800 */
6270 #define USB_EP5R_SETUP                          USB_EP5R_SETUP_Msk             /*!< Setup transaction completed */
6271 
6272 #define USB_EP5R_STAT_RX_Pos                    (12U)
6273 #define USB_EP5R_STAT_RX_Msk                    (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
6274 #define USB_EP5R_STAT_RX                        USB_EP5R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6275 #define USB_EP5R_STAT_RX_0                      (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
6276 #define USB_EP5R_STAT_RX_1                      (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
6277 
6278 #define USB_EP5R_DTOG_RX_Pos                    (14U)
6279 #define USB_EP5R_DTOG_RX_Msk                    (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
6280 #define USB_EP5R_DTOG_RX                        USB_EP5R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6281 #define USB_EP5R_CTR_RX_Pos                     (15U)
6282 #define USB_EP5R_CTR_RX_Msk                     (0x1UL << USB_EP5R_CTR_RX_Pos)  /*!< 0x00008000 */
6283 #define USB_EP5R_CTR_RX                         USB_EP5R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6284 
6285 /*******************  Bit definition for USB_EP6R register  *******************/
6286 #define USB_EP6R_EA_Pos                         (0U)
6287 #define USB_EP6R_EA_Msk                         (0xFUL << USB_EP6R_EA_Pos)      /*!< 0x0000000F */
6288 #define USB_EP6R_EA                             USB_EP6R_EA_Msk                /*!< Endpoint Address */
6289 
6290 #define USB_EP6R_STAT_TX_Pos                    (4U)
6291 #define USB_EP6R_STAT_TX_Msk                    (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
6292 #define USB_EP6R_STAT_TX                        USB_EP6R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6293 #define USB_EP6R_STAT_TX_0                      (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
6294 #define USB_EP6R_STAT_TX_1                      (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
6295 
6296 #define USB_EP6R_DTOG_TX_Pos                    (6U)
6297 #define USB_EP6R_DTOG_TX_Msk                    (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
6298 #define USB_EP6R_DTOG_TX                        USB_EP6R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6299 #define USB_EP6R_CTR_TX_Pos                     (7U)
6300 #define USB_EP6R_CTR_TX_Msk                     (0x1UL << USB_EP6R_CTR_TX_Pos)  /*!< 0x00000080 */
6301 #define USB_EP6R_CTR_TX                         USB_EP6R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6302 #define USB_EP6R_EP_KIND_Pos                    (8U)
6303 #define USB_EP6R_EP_KIND_Msk                    (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
6304 #define USB_EP6R_EP_KIND                        USB_EP6R_EP_KIND_Msk           /*!< Endpoint Kind */
6305 
6306 #define USB_EP6R_EP_TYPE_Pos                    (9U)
6307 #define USB_EP6R_EP_TYPE_Msk                    (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
6308 #define USB_EP6R_EP_TYPE                        USB_EP6R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6309 #define USB_EP6R_EP_TYPE_0                      (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
6310 #define USB_EP6R_EP_TYPE_1                      (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
6311 
6312 #define USB_EP6R_SETUP_Pos                      (11U)
6313 #define USB_EP6R_SETUP_Msk                      (0x1UL << USB_EP6R_SETUP_Pos)   /*!< 0x00000800 */
6314 #define USB_EP6R_SETUP                          USB_EP6R_SETUP_Msk             /*!< Setup transaction completed */
6315 
6316 #define USB_EP6R_STAT_RX_Pos                    (12U)
6317 #define USB_EP6R_STAT_RX_Msk                    (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
6318 #define USB_EP6R_STAT_RX                        USB_EP6R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6319 #define USB_EP6R_STAT_RX_0                      (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
6320 #define USB_EP6R_STAT_RX_1                      (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
6321 
6322 #define USB_EP6R_DTOG_RX_Pos                    (14U)
6323 #define USB_EP6R_DTOG_RX_Msk                    (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
6324 #define USB_EP6R_DTOG_RX                        USB_EP6R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6325 #define USB_EP6R_CTR_RX_Pos                     (15U)
6326 #define USB_EP6R_CTR_RX_Msk                     (0x1UL << USB_EP6R_CTR_RX_Pos)  /*!< 0x00008000 */
6327 #define USB_EP6R_CTR_RX                         USB_EP6R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6328 
6329 /*******************  Bit definition for USB_EP7R register  *******************/
6330 #define USB_EP7R_EA_Pos                         (0U)
6331 #define USB_EP7R_EA_Msk                         (0xFUL << USB_EP7R_EA_Pos)      /*!< 0x0000000F */
6332 #define USB_EP7R_EA                             USB_EP7R_EA_Msk                /*!< Endpoint Address */
6333 
6334 #define USB_EP7R_STAT_TX_Pos                    (4U)
6335 #define USB_EP7R_STAT_TX_Msk                    (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
6336 #define USB_EP7R_STAT_TX                        USB_EP7R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
6337 #define USB_EP7R_STAT_TX_0                      (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
6338 #define USB_EP7R_STAT_TX_1                      (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
6339 
6340 #define USB_EP7R_DTOG_TX_Pos                    (6U)
6341 #define USB_EP7R_DTOG_TX_Msk                    (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
6342 #define USB_EP7R_DTOG_TX                        USB_EP7R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
6343 #define USB_EP7R_CTR_TX_Pos                     (7U)
6344 #define USB_EP7R_CTR_TX_Msk                     (0x1UL << USB_EP7R_CTR_TX_Pos)  /*!< 0x00000080 */
6345 #define USB_EP7R_CTR_TX                         USB_EP7R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
6346 #define USB_EP7R_EP_KIND_Pos                    (8U)
6347 #define USB_EP7R_EP_KIND_Msk                    (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
6348 #define USB_EP7R_EP_KIND                        USB_EP7R_EP_KIND_Msk           /*!< Endpoint Kind */
6349 
6350 #define USB_EP7R_EP_TYPE_Pos                    (9U)
6351 #define USB_EP7R_EP_TYPE_Msk                    (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
6352 #define USB_EP7R_EP_TYPE                        USB_EP7R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
6353 #define USB_EP7R_EP_TYPE_0                      (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
6354 #define USB_EP7R_EP_TYPE_1                      (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
6355 
6356 #define USB_EP7R_SETUP_Pos                      (11U)
6357 #define USB_EP7R_SETUP_Msk                      (0x1UL << USB_EP7R_SETUP_Pos)   /*!< 0x00000800 */
6358 #define USB_EP7R_SETUP                          USB_EP7R_SETUP_Msk             /*!< Setup transaction completed */
6359 
6360 #define USB_EP7R_STAT_RX_Pos                    (12U)
6361 #define USB_EP7R_STAT_RX_Msk                    (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
6362 #define USB_EP7R_STAT_RX                        USB_EP7R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
6363 #define USB_EP7R_STAT_RX_0                      (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
6364 #define USB_EP7R_STAT_RX_1                      (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
6365 
6366 #define USB_EP7R_DTOG_RX_Pos                    (14U)
6367 #define USB_EP7R_DTOG_RX_Msk                    (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
6368 #define USB_EP7R_DTOG_RX                        USB_EP7R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
6369 #define USB_EP7R_CTR_RX_Pos                     (15U)
6370 #define USB_EP7R_CTR_RX_Msk                     (0x1UL << USB_EP7R_CTR_RX_Pos)  /*!< 0x00008000 */
6371 #define USB_EP7R_CTR_RX                         USB_EP7R_CTR_RX_Msk            /*!< Correct Transfer for reception */
6372 
6373 /*!< Common registers */
6374 /*******************  Bit definition for USB_CNTR register  *******************/
6375 #define USB_CNTR_FRES_Pos                       (0U)
6376 #define USB_CNTR_FRES_Msk                       (0x1UL << USB_CNTR_FRES_Pos)    /*!< 0x00000001 */
6377 #define USB_CNTR_FRES                           USB_CNTR_FRES_Msk              /*!< Force USB Reset */
6378 #define USB_CNTR_PDWN_Pos                       (1U)
6379 #define USB_CNTR_PDWN_Msk                       (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
6380 #define USB_CNTR_PDWN                           USB_CNTR_PDWN_Msk              /*!< Power down */
6381 #define USB_CNTR_LP_MODE_Pos                    (2U)
6382 #define USB_CNTR_LP_MODE_Msk                    (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
6383 #define USB_CNTR_LP_MODE                        USB_CNTR_LP_MODE_Msk           /*!< Low-power mode */
6384 #define USB_CNTR_FSUSP_Pos                      (3U)
6385 #define USB_CNTR_FSUSP_Msk                      (0x1UL << USB_CNTR_FSUSP_Pos)   /*!< 0x00000008 */
6386 #define USB_CNTR_FSUSP                          USB_CNTR_FSUSP_Msk             /*!< Force suspend */
6387 #define USB_CNTR_RESUME_Pos                     (4U)
6388 #define USB_CNTR_RESUME_Msk                     (0x1UL << USB_CNTR_RESUME_Pos)  /*!< 0x00000010 */
6389 #define USB_CNTR_RESUME                         USB_CNTR_RESUME_Msk            /*!< Resume request */
6390 #define USB_CNTR_ESOFM_Pos                      (8U)
6391 #define USB_CNTR_ESOFM_Msk                      (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
6392 #define USB_CNTR_ESOFM                          USB_CNTR_ESOFM_Msk             /*!< Expected Start Of Frame Interrupt Mask */
6393 #define USB_CNTR_SOFM_Pos                       (9U)
6394 #define USB_CNTR_SOFM_Msk                       (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
6395 #define USB_CNTR_SOFM                           USB_CNTR_SOFM_Msk              /*!< Start Of Frame Interrupt Mask */
6396 #define USB_CNTR_RESETM_Pos                     (10U)
6397 #define USB_CNTR_RESETM_Msk                     (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
6398 #define USB_CNTR_RESETM                         USB_CNTR_RESETM_Msk            /*!< RESET Interrupt Mask */
6399 #define USB_CNTR_SUSPM_Pos                      (11U)
6400 #define USB_CNTR_SUSPM_Msk                      (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
6401 #define USB_CNTR_SUSPM                          USB_CNTR_SUSPM_Msk             /*!< Suspend mode Interrupt Mask */
6402 #define USB_CNTR_WKUPM_Pos                      (12U)
6403 #define USB_CNTR_WKUPM_Msk                      (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
6404 #define USB_CNTR_WKUPM                          USB_CNTR_WKUPM_Msk             /*!< Wakeup Interrupt Mask */
6405 #define USB_CNTR_ERRM_Pos                       (13U)
6406 #define USB_CNTR_ERRM_Msk                       (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
6407 #define USB_CNTR_ERRM                           USB_CNTR_ERRM_Msk              /*!< Error Interrupt Mask */
6408 #define USB_CNTR_PMAOVRM_Pos                    (14U)
6409 #define USB_CNTR_PMAOVRM_Msk                    (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
6410 #define USB_CNTR_PMAOVRM                        USB_CNTR_PMAOVRM_Msk           /*!< Packet Memory Area Over / Underrun Interrupt Mask */
6411 #define USB_CNTR_CTRM_Pos                       (15U)
6412 #define USB_CNTR_CTRM_Msk                       (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
6413 #define USB_CNTR_CTRM                           USB_CNTR_CTRM_Msk              /*!< Correct Transfer Interrupt Mask */
6414 
6415 /*******************  Bit definition for USB_ISTR register  *******************/
6416 #define USB_ISTR_EP_ID_Pos                      (0U)
6417 #define USB_ISTR_EP_ID_Msk                      (0xFUL << USB_ISTR_EP_ID_Pos)   /*!< 0x0000000F */
6418 #define USB_ISTR_EP_ID                          USB_ISTR_EP_ID_Msk             /*!< Endpoint Identifier */
6419 #define USB_ISTR_DIR_Pos                        (4U)
6420 #define USB_ISTR_DIR_Msk                        (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
6421 #define USB_ISTR_DIR                            USB_ISTR_DIR_Msk               /*!< Direction of transaction */
6422 #define USB_ISTR_ESOF_Pos                       (8U)
6423 #define USB_ISTR_ESOF_Msk                       (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
6424 #define USB_ISTR_ESOF                           USB_ISTR_ESOF_Msk              /*!< Expected Start Of Frame */
6425 #define USB_ISTR_SOF_Pos                        (9U)
6426 #define USB_ISTR_SOF_Msk                        (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
6427 #define USB_ISTR_SOF                            USB_ISTR_SOF_Msk               /*!< Start Of Frame */
6428 #define USB_ISTR_RESET_Pos                      (10U)
6429 #define USB_ISTR_RESET_Msk                      (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
6430 #define USB_ISTR_RESET                          USB_ISTR_RESET_Msk             /*!< USB RESET request */
6431 #define USB_ISTR_SUSP_Pos                       (11U)
6432 #define USB_ISTR_SUSP_Msk                       (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
6433 #define USB_ISTR_SUSP                           USB_ISTR_SUSP_Msk              /*!< Suspend mode request */
6434 #define USB_ISTR_WKUP_Pos                       (12U)
6435 #define USB_ISTR_WKUP_Msk                       (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
6436 #define USB_ISTR_WKUP                           USB_ISTR_WKUP_Msk              /*!< Wake up */
6437 #define USB_ISTR_ERR_Pos                        (13U)
6438 #define USB_ISTR_ERR_Msk                        (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
6439 #define USB_ISTR_ERR                            USB_ISTR_ERR_Msk               /*!< Error */
6440 #define USB_ISTR_PMAOVR_Pos                     (14U)
6441 #define USB_ISTR_PMAOVR_Msk                     (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
6442 #define USB_ISTR_PMAOVR                         USB_ISTR_PMAOVR_Msk            /*!< Packet Memory Area Over / Underrun */
6443 #define USB_ISTR_CTR_Pos                        (15U)
6444 #define USB_ISTR_CTR_Msk                        (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
6445 #define USB_ISTR_CTR                            USB_ISTR_CTR_Msk               /*!< Correct Transfer */
6446 
6447 /*******************  Bit definition for USB_FNR register  ********************/
6448 #define USB_FNR_FN_Pos                          (0U)
6449 #define USB_FNR_FN_Msk                          (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
6450 #define USB_FNR_FN                              USB_FNR_FN_Msk                 /*!< Frame Number */
6451 #define USB_FNR_LSOF_Pos                        (11U)
6452 #define USB_FNR_LSOF_Msk                        (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
6453 #define USB_FNR_LSOF                            USB_FNR_LSOF_Msk               /*!< Lost SOF */
6454 #define USB_FNR_LCK_Pos                         (13U)
6455 #define USB_FNR_LCK_Msk                         (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
6456 #define USB_FNR_LCK                             USB_FNR_LCK_Msk                /*!< Locked */
6457 #define USB_FNR_RXDM_Pos                        (14U)
6458 #define USB_FNR_RXDM_Msk                        (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
6459 #define USB_FNR_RXDM                            USB_FNR_RXDM_Msk               /*!< Receive Data - Line Status */
6460 #define USB_FNR_RXDP_Pos                        (15U)
6461 #define USB_FNR_RXDP_Msk                        (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
6462 #define USB_FNR_RXDP                            USB_FNR_RXDP_Msk               /*!< Receive Data + Line Status */
6463 
6464 /******************  Bit definition for USB_DADDR register  *******************/
6465 #define USB_DADDR_ADD_Pos                       (0U)
6466 #define USB_DADDR_ADD_Msk                       (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
6467 #define USB_DADDR_ADD                           USB_DADDR_ADD_Msk              /*!< ADD[6:0] bits (Device Address) */
6468 #define USB_DADDR_ADD0_Pos                      (0U)
6469 #define USB_DADDR_ADD0_Msk                      (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
6470 #define USB_DADDR_ADD0                          USB_DADDR_ADD0_Msk             /*!< Bit 0 */
6471 #define USB_DADDR_ADD1_Pos                      (1U)
6472 #define USB_DADDR_ADD1_Msk                      (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
6473 #define USB_DADDR_ADD1                          USB_DADDR_ADD1_Msk             /*!< Bit 1 */
6474 #define USB_DADDR_ADD2_Pos                      (2U)
6475 #define USB_DADDR_ADD2_Msk                      (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
6476 #define USB_DADDR_ADD2                          USB_DADDR_ADD2_Msk             /*!< Bit 2 */
6477 #define USB_DADDR_ADD3_Pos                      (3U)
6478 #define USB_DADDR_ADD3_Msk                      (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
6479 #define USB_DADDR_ADD3                          USB_DADDR_ADD3_Msk             /*!< Bit 3 */
6480 #define USB_DADDR_ADD4_Pos                      (4U)
6481 #define USB_DADDR_ADD4_Msk                      (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
6482 #define USB_DADDR_ADD4                          USB_DADDR_ADD4_Msk             /*!< Bit 4 */
6483 #define USB_DADDR_ADD5_Pos                      (5U)
6484 #define USB_DADDR_ADD5_Msk                      (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
6485 #define USB_DADDR_ADD5                          USB_DADDR_ADD5_Msk             /*!< Bit 5 */
6486 #define USB_DADDR_ADD6_Pos                      (6U)
6487 #define USB_DADDR_ADD6_Msk                      (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
6488 #define USB_DADDR_ADD6                          USB_DADDR_ADD6_Msk             /*!< Bit 6 */
6489 
6490 #define USB_DADDR_EF_Pos                        (7U)
6491 #define USB_DADDR_EF_Msk                        (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
6492 #define USB_DADDR_EF                            USB_DADDR_EF_Msk               /*!< Enable Function */
6493 
6494 /******************  Bit definition for USB_BTABLE register  ******************/
6495 #define USB_BTABLE_BTABLE_Pos                   (3U)
6496 #define USB_BTABLE_BTABLE_Msk                   (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
6497 #define USB_BTABLE_BTABLE                       USB_BTABLE_BTABLE_Msk          /*!< Buffer Table */
6498 
6499 /*!< Buffer descriptor table */
6500 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
6501 #define USB_ADDR0_TX_ADDR0_TX_Pos               (1U)
6502 #define USB_ADDR0_TX_ADDR0_TX_Msk               (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
6503 #define USB_ADDR0_TX_ADDR0_TX                   USB_ADDR0_TX_ADDR0_TX_Msk      /*!< Transmission Buffer Address 0 */
6504 
6505 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
6506 #define USB_ADDR1_TX_ADDR1_TX_Pos               (1U)
6507 #define USB_ADDR1_TX_ADDR1_TX_Msk               (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
6508 #define USB_ADDR1_TX_ADDR1_TX                   USB_ADDR1_TX_ADDR1_TX_Msk      /*!< Transmission Buffer Address 1 */
6509 
6510 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
6511 #define USB_ADDR2_TX_ADDR2_TX_Pos               (1U)
6512 #define USB_ADDR2_TX_ADDR2_TX_Msk               (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
6513 #define USB_ADDR2_TX_ADDR2_TX                   USB_ADDR2_TX_ADDR2_TX_Msk      /*!< Transmission Buffer Address 2 */
6514 
6515 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
6516 #define USB_ADDR3_TX_ADDR3_TX_Pos               (1U)
6517 #define USB_ADDR3_TX_ADDR3_TX_Msk               (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
6518 #define USB_ADDR3_TX_ADDR3_TX                   USB_ADDR3_TX_ADDR3_TX_Msk      /*!< Transmission Buffer Address 3 */
6519 
6520 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
6521 #define USB_ADDR4_TX_ADDR4_TX_Pos               (1U)
6522 #define USB_ADDR4_TX_ADDR4_TX_Msk               (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
6523 #define USB_ADDR4_TX_ADDR4_TX                   USB_ADDR4_TX_ADDR4_TX_Msk      /*!< Transmission Buffer Address 4 */
6524 
6525 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
6526 #define USB_ADDR5_TX_ADDR5_TX_Pos               (1U)
6527 #define USB_ADDR5_TX_ADDR5_TX_Msk               (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
6528 #define USB_ADDR5_TX_ADDR5_TX                   USB_ADDR5_TX_ADDR5_TX_Msk      /*!< Transmission Buffer Address 5 */
6529 
6530 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
6531 #define USB_ADDR6_TX_ADDR6_TX_Pos               (1U)
6532 #define USB_ADDR6_TX_ADDR6_TX_Msk               (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
6533 #define USB_ADDR6_TX_ADDR6_TX                   USB_ADDR6_TX_ADDR6_TX_Msk      /*!< Transmission Buffer Address 6 */
6534 
6535 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
6536 #define USB_ADDR7_TX_ADDR7_TX_Pos               (1U)
6537 #define USB_ADDR7_TX_ADDR7_TX_Msk               (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
6538 #define USB_ADDR7_TX_ADDR7_TX                   USB_ADDR7_TX_ADDR7_TX_Msk      /*!< Transmission Buffer Address 7 */
6539 
6540 /*----------------------------------------------------------------------------*/
6541 
6542 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
6543 #define USB_COUNT0_TX_COUNT0_TX_Pos             (0U)
6544 #define USB_COUNT0_TX_COUNT0_TX_Msk             (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
6545 #define USB_COUNT0_TX_COUNT0_TX                 USB_COUNT0_TX_COUNT0_TX_Msk    /*!< Transmission Byte Count 0 */
6546 
6547 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
6548 #define USB_COUNT1_TX_COUNT1_TX_Pos             (0U)
6549 #define USB_COUNT1_TX_COUNT1_TX_Msk             (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
6550 #define USB_COUNT1_TX_COUNT1_TX                 USB_COUNT1_TX_COUNT1_TX_Msk    /*!< Transmission Byte Count 1 */
6551 
6552 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
6553 #define USB_COUNT2_TX_COUNT2_TX_Pos             (0U)
6554 #define USB_COUNT2_TX_COUNT2_TX_Msk             (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
6555 #define USB_COUNT2_TX_COUNT2_TX                 USB_COUNT2_TX_COUNT2_TX_Msk    /*!< Transmission Byte Count 2 */
6556 
6557 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
6558 #define USB_COUNT3_TX_COUNT3_TX_Pos             (0U)
6559 #define USB_COUNT3_TX_COUNT3_TX_Msk             (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
6560 #define USB_COUNT3_TX_COUNT3_TX                 USB_COUNT3_TX_COUNT3_TX_Msk    /*!< Transmission Byte Count 3 */
6561 
6562 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
6563 #define USB_COUNT4_TX_COUNT4_TX_Pos             (0U)
6564 #define USB_COUNT4_TX_COUNT4_TX_Msk             (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
6565 #define USB_COUNT4_TX_COUNT4_TX                 USB_COUNT4_TX_COUNT4_TX_Msk    /*!< Transmission Byte Count 4 */
6566 
6567 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
6568 #define USB_COUNT5_TX_COUNT5_TX_Pos             (0U)
6569 #define USB_COUNT5_TX_COUNT5_TX_Msk             (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
6570 #define USB_COUNT5_TX_COUNT5_TX                 USB_COUNT5_TX_COUNT5_TX_Msk    /*!< Transmission Byte Count 5 */
6571 
6572 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
6573 #define USB_COUNT6_TX_COUNT6_TX_Pos             (0U)
6574 #define USB_COUNT6_TX_COUNT6_TX_Msk             (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
6575 #define USB_COUNT6_TX_COUNT6_TX                 USB_COUNT6_TX_COUNT6_TX_Msk    /*!< Transmission Byte Count 6 */
6576 
6577 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
6578 #define USB_COUNT7_TX_COUNT7_TX_Pos             (0U)
6579 #define USB_COUNT7_TX_COUNT7_TX_Msk             (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
6580 #define USB_COUNT7_TX_COUNT7_TX                 USB_COUNT7_TX_COUNT7_TX_Msk    /*!< Transmission Byte Count 7 */
6581 
6582 /*----------------------------------------------------------------------------*/
6583 
6584 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
6585 #define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */
6586 
6587 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
6588 #define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */
6589 
6590 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
6591 #define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */
6592 
6593 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
6594 #define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */
6595 
6596 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
6597 #define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */
6598 
6599 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
6600 #define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */
6601 
6602 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
6603 #define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */
6604 
6605 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
6606 #define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */
6607 
6608 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
6609 #define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */
6610 
6611 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
6612 #define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */
6613 
6614 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
6615 #define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */
6616 
6617 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
6618 #define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */
6619 
6620 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
6621 #define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */
6622 
6623 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
6624 #define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */
6625 
6626 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
6627 #define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */
6628 
6629 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
6630 #define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */
6631 
6632 /*----------------------------------------------------------------------------*/
6633 
6634 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
6635 #define USB_ADDR0_RX_ADDR0_RX_Pos               (1U)
6636 #define USB_ADDR0_RX_ADDR0_RX_Msk               (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
6637 #define USB_ADDR0_RX_ADDR0_RX                   USB_ADDR0_RX_ADDR0_RX_Msk      /*!< Reception Buffer Address 0 */
6638 
6639 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
6640 #define USB_ADDR1_RX_ADDR1_RX_Pos               (1U)
6641 #define USB_ADDR1_RX_ADDR1_RX_Msk               (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
6642 #define USB_ADDR1_RX_ADDR1_RX                   USB_ADDR1_RX_ADDR1_RX_Msk      /*!< Reception Buffer Address 1 */
6643 
6644 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
6645 #define USB_ADDR2_RX_ADDR2_RX_Pos               (1U)
6646 #define USB_ADDR2_RX_ADDR2_RX_Msk               (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
6647 #define USB_ADDR2_RX_ADDR2_RX                   USB_ADDR2_RX_ADDR2_RX_Msk      /*!< Reception Buffer Address 2 */
6648 
6649 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
6650 #define USB_ADDR3_RX_ADDR3_RX_Pos               (1U)
6651 #define USB_ADDR3_RX_ADDR3_RX_Msk               (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
6652 #define USB_ADDR3_RX_ADDR3_RX                   USB_ADDR3_RX_ADDR3_RX_Msk      /*!< Reception Buffer Address 3 */
6653 
6654 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
6655 #define USB_ADDR4_RX_ADDR4_RX_Pos               (1U)
6656 #define USB_ADDR4_RX_ADDR4_RX_Msk               (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
6657 #define USB_ADDR4_RX_ADDR4_RX                   USB_ADDR4_RX_ADDR4_RX_Msk      /*!< Reception Buffer Address 4 */
6658 
6659 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
6660 #define USB_ADDR5_RX_ADDR5_RX_Pos               (1U)
6661 #define USB_ADDR5_RX_ADDR5_RX_Msk               (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
6662 #define USB_ADDR5_RX_ADDR5_RX                   USB_ADDR5_RX_ADDR5_RX_Msk      /*!< Reception Buffer Address 5 */
6663 
6664 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
6665 #define USB_ADDR6_RX_ADDR6_RX_Pos               (1U)
6666 #define USB_ADDR6_RX_ADDR6_RX_Msk               (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
6667 #define USB_ADDR6_RX_ADDR6_RX                   USB_ADDR6_RX_ADDR6_RX_Msk      /*!< Reception Buffer Address 6 */
6668 
6669 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
6670 #define USB_ADDR7_RX_ADDR7_RX_Pos               (1U)
6671 #define USB_ADDR7_RX_ADDR7_RX_Msk               (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
6672 #define USB_ADDR7_RX_ADDR7_RX                   USB_ADDR7_RX_ADDR7_RX_Msk      /*!< Reception Buffer Address 7 */
6673 
6674 /*----------------------------------------------------------------------------*/
6675 
6676 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
6677 #define USB_COUNT0_RX_COUNT0_RX_Pos             (0U)
6678 #define USB_COUNT0_RX_COUNT0_RX_Msk             (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
6679 #define USB_COUNT0_RX_COUNT0_RX                 USB_COUNT0_RX_COUNT0_RX_Msk    /*!< Reception Byte Count */
6680 
6681 #define USB_COUNT0_RX_NUM_BLOCK_Pos             (10U)
6682 #define USB_COUNT0_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6683 #define USB_COUNT0_RX_NUM_BLOCK                 USB_COUNT0_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6684 #define USB_COUNT0_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6685 #define USB_COUNT0_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6686 #define USB_COUNT0_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6687 #define USB_COUNT0_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6688 #define USB_COUNT0_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6689 
6690 #define USB_COUNT0_RX_BLSIZE_Pos                (15U)
6691 #define USB_COUNT0_RX_BLSIZE_Msk                (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
6692 #define USB_COUNT0_RX_BLSIZE                    USB_COUNT0_RX_BLSIZE_Msk       /*!< BLock SIZE */
6693 
6694 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
6695 #define USB_COUNT1_RX_COUNT1_RX_Pos             (0U)
6696 #define USB_COUNT1_RX_COUNT1_RX_Msk             (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
6697 #define USB_COUNT1_RX_COUNT1_RX                 USB_COUNT1_RX_COUNT1_RX_Msk    /*!< Reception Byte Count */
6698 
6699 #define USB_COUNT1_RX_NUM_BLOCK_Pos             (10U)
6700 #define USB_COUNT1_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6701 #define USB_COUNT1_RX_NUM_BLOCK                 USB_COUNT1_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6702 #define USB_COUNT1_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6703 #define USB_COUNT1_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6704 #define USB_COUNT1_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6705 #define USB_COUNT1_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6706 #define USB_COUNT1_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6707 
6708 #define USB_COUNT1_RX_BLSIZE_Pos                (15U)
6709 #define USB_COUNT1_RX_BLSIZE_Msk                (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
6710 #define USB_COUNT1_RX_BLSIZE                    USB_COUNT1_RX_BLSIZE_Msk       /*!< BLock SIZE */
6711 
6712 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
6713 #define USB_COUNT2_RX_COUNT2_RX_Pos             (0U)
6714 #define USB_COUNT2_RX_COUNT2_RX_Msk             (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
6715 #define USB_COUNT2_RX_COUNT2_RX                 USB_COUNT2_RX_COUNT2_RX_Msk    /*!< Reception Byte Count */
6716 
6717 #define USB_COUNT2_RX_NUM_BLOCK_Pos             (10U)
6718 #define USB_COUNT2_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6719 #define USB_COUNT2_RX_NUM_BLOCK                 USB_COUNT2_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6720 #define USB_COUNT2_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6721 #define USB_COUNT2_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6722 #define USB_COUNT2_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6723 #define USB_COUNT2_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6724 #define USB_COUNT2_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6725 
6726 #define USB_COUNT2_RX_BLSIZE_Pos                (15U)
6727 #define USB_COUNT2_RX_BLSIZE_Msk                (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
6728 #define USB_COUNT2_RX_BLSIZE                    USB_COUNT2_RX_BLSIZE_Msk       /*!< BLock SIZE */
6729 
6730 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
6731 #define USB_COUNT3_RX_COUNT3_RX_Pos             (0U)
6732 #define USB_COUNT3_RX_COUNT3_RX_Msk             (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
6733 #define USB_COUNT3_RX_COUNT3_RX                 USB_COUNT3_RX_COUNT3_RX_Msk    /*!< Reception Byte Count */
6734 
6735 #define USB_COUNT3_RX_NUM_BLOCK_Pos             (10U)
6736 #define USB_COUNT3_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6737 #define USB_COUNT3_RX_NUM_BLOCK                 USB_COUNT3_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6738 #define USB_COUNT3_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6739 #define USB_COUNT3_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6740 #define USB_COUNT3_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6741 #define USB_COUNT3_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6742 #define USB_COUNT3_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6743 
6744 #define USB_COUNT3_RX_BLSIZE_Pos                (15U)
6745 #define USB_COUNT3_RX_BLSIZE_Msk                (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
6746 #define USB_COUNT3_RX_BLSIZE                    USB_COUNT3_RX_BLSIZE_Msk       /*!< BLock SIZE */
6747 
6748 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
6749 #define USB_COUNT4_RX_COUNT4_RX_Pos             (0U)
6750 #define USB_COUNT4_RX_COUNT4_RX_Msk             (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
6751 #define USB_COUNT4_RX_COUNT4_RX                 USB_COUNT4_RX_COUNT4_RX_Msk    /*!< Reception Byte Count */
6752 
6753 #define USB_COUNT4_RX_NUM_BLOCK_Pos             (10U)
6754 #define USB_COUNT4_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6755 #define USB_COUNT4_RX_NUM_BLOCK                 USB_COUNT4_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6756 #define USB_COUNT4_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6757 #define USB_COUNT4_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6758 #define USB_COUNT4_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6759 #define USB_COUNT4_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6760 #define USB_COUNT4_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6761 
6762 #define USB_COUNT4_RX_BLSIZE_Pos                (15U)
6763 #define USB_COUNT4_RX_BLSIZE_Msk                (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
6764 #define USB_COUNT4_RX_BLSIZE                    USB_COUNT4_RX_BLSIZE_Msk       /*!< BLock SIZE */
6765 
6766 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
6767 #define USB_COUNT5_RX_COUNT5_RX_Pos             (0U)
6768 #define USB_COUNT5_RX_COUNT5_RX_Msk             (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
6769 #define USB_COUNT5_RX_COUNT5_RX                 USB_COUNT5_RX_COUNT5_RX_Msk    /*!< Reception Byte Count */
6770 
6771 #define USB_COUNT5_RX_NUM_BLOCK_Pos             (10U)
6772 #define USB_COUNT5_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6773 #define USB_COUNT5_RX_NUM_BLOCK                 USB_COUNT5_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6774 #define USB_COUNT5_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6775 #define USB_COUNT5_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6776 #define USB_COUNT5_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6777 #define USB_COUNT5_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6778 #define USB_COUNT5_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6779 
6780 #define USB_COUNT5_RX_BLSIZE_Pos                (15U)
6781 #define USB_COUNT5_RX_BLSIZE_Msk                (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
6782 #define USB_COUNT5_RX_BLSIZE                    USB_COUNT5_RX_BLSIZE_Msk       /*!< BLock SIZE */
6783 
6784 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
6785 #define USB_COUNT6_RX_COUNT6_RX_Pos             (0U)
6786 #define USB_COUNT6_RX_COUNT6_RX_Msk             (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
6787 #define USB_COUNT6_RX_COUNT6_RX                 USB_COUNT6_RX_COUNT6_RX_Msk    /*!< Reception Byte Count */
6788 
6789 #define USB_COUNT6_RX_NUM_BLOCK_Pos             (10U)
6790 #define USB_COUNT6_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6791 #define USB_COUNT6_RX_NUM_BLOCK                 USB_COUNT6_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6792 #define USB_COUNT6_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6793 #define USB_COUNT6_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6794 #define USB_COUNT6_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6795 #define USB_COUNT6_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6796 #define USB_COUNT6_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6797 
6798 #define USB_COUNT6_RX_BLSIZE_Pos                (15U)
6799 #define USB_COUNT6_RX_BLSIZE_Msk                (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
6800 #define USB_COUNT6_RX_BLSIZE                    USB_COUNT6_RX_BLSIZE_Msk       /*!< BLock SIZE */
6801 
6802 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
6803 #define USB_COUNT7_RX_COUNT7_RX_Pos             (0U)
6804 #define USB_COUNT7_RX_COUNT7_RX_Msk             (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
6805 #define USB_COUNT7_RX_COUNT7_RX                 USB_COUNT7_RX_COUNT7_RX_Msk    /*!< Reception Byte Count */
6806 
6807 #define USB_COUNT7_RX_NUM_BLOCK_Pos             (10U)
6808 #define USB_COUNT7_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
6809 #define USB_COUNT7_RX_NUM_BLOCK                 USB_COUNT7_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
6810 #define USB_COUNT7_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
6811 #define USB_COUNT7_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
6812 #define USB_COUNT7_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
6813 #define USB_COUNT7_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
6814 #define USB_COUNT7_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
6815 
6816 #define USB_COUNT7_RX_BLSIZE_Pos                (15U)
6817 #define USB_COUNT7_RX_BLSIZE_Msk                (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
6818 #define USB_COUNT7_RX_BLSIZE                    USB_COUNT7_RX_BLSIZE_Msk       /*!< BLock SIZE */
6819 
6820 /*----------------------------------------------------------------------------*/
6821 
6822 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
6823 #define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6824 
6825 #define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6826 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6827 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6828 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6829 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6830 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6831 
6832 #define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6833 
6834 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
6835 #define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6836 
6837 #define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6838 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */
6839 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6840 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6841 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6842 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6843 
6844 #define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6845 
6846 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
6847 #define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6848 
6849 #define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6850 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6851 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6852 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6853 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6854 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6855 
6856 #define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6857 
6858 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
6859 #define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6860 
6861 #define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6862 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6863 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6864 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6865 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6866 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6867 
6868 #define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6869 
6870 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
6871 #define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6872 
6873 #define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6874 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6875 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6876 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6877 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6878 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6879 
6880 #define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6881 
6882 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
6883 #define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6884 
6885 #define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6886 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6887 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6888 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6889 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6890 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6891 
6892 #define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6893 
6894 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
6895 #define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6896 
6897 #define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6898 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6899 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6900 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6901 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6902 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6903 
6904 #define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6905 
6906 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
6907 #define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6908 
6909 #define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6910 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6911 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6912 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6913 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6914 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6915 
6916 #define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6917 
6918 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
6919 #define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6920 
6921 #define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6922 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6923 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6924 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6925 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6926 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6927 
6928 #define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6929 
6930 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
6931 #define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6932 
6933 #define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6934 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6935 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6936 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6937 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6938 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6939 
6940 #define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6941 
6942 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
6943 #define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6944 
6945 #define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6946 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6947 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6948 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6949 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6950 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6951 
6952 #define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6953 
6954 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
6955 #define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
6956 
6957 #define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6958 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
6959 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
6960 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
6961 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
6962 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
6963 
6964 #define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
6965 
6966 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
6967 #define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6968 
6969 #define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6970 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6971 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6972 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6973 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6974 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6975 
6976 #define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
6977 
6978 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
6979 #define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */
6980 
6981 #define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6982 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */
6983 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */
6984 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */
6985 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */
6986 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */
6987 
6988 #define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */
6989 
6990 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
6991 #define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
6992 
6993 #define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6994 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
6995 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
6996 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
6997 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
6998 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
6999 
7000 #define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
7001 
7002 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
7003 #define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
7004 
7005 #define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
7006 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
7007 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
7008 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
7009 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
7010 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
7011 
7012 #define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
7013 
7014 /******************************************************************************/
7015 /*                                                                            */
7016 /*                         Controller Area Network                            */
7017 /*                                                                            */
7018 /******************************************************************************/
7019 
7020 /*!< CAN control and status registers */
7021 /*******************  Bit definition for CAN_MCR register  ********************/
7022 #define CAN_MCR_INRQ_Pos                     (0U)
7023 #define CAN_MCR_INRQ_Msk                     (0x1UL << CAN_MCR_INRQ_Pos)        /*!< 0x00000001 */
7024 #define CAN_MCR_INRQ                         CAN_MCR_INRQ_Msk                  /*!< Initialization Request */
7025 #define CAN_MCR_SLEEP_Pos                    (1U)
7026 #define CAN_MCR_SLEEP_Msk                    (0x1UL << CAN_MCR_SLEEP_Pos)       /*!< 0x00000002 */
7027 #define CAN_MCR_SLEEP                        CAN_MCR_SLEEP_Msk                 /*!< Sleep Mode Request */
7028 #define CAN_MCR_TXFP_Pos                     (2U)
7029 #define CAN_MCR_TXFP_Msk                     (0x1UL << CAN_MCR_TXFP_Pos)        /*!< 0x00000004 */
7030 #define CAN_MCR_TXFP                         CAN_MCR_TXFP_Msk                  /*!< Transmit FIFO Priority */
7031 #define CAN_MCR_RFLM_Pos                     (3U)
7032 #define CAN_MCR_RFLM_Msk                     (0x1UL << CAN_MCR_RFLM_Pos)        /*!< 0x00000008 */
7033 #define CAN_MCR_RFLM                         CAN_MCR_RFLM_Msk                  /*!< Receive FIFO Locked Mode */
7034 #define CAN_MCR_NART_Pos                     (4U)
7035 #define CAN_MCR_NART_Msk                     (0x1UL << CAN_MCR_NART_Pos)        /*!< 0x00000010 */
7036 #define CAN_MCR_NART                         CAN_MCR_NART_Msk                  /*!< No Automatic Retransmission */
7037 #define CAN_MCR_AWUM_Pos                     (5U)
7038 #define CAN_MCR_AWUM_Msk                     (0x1UL << CAN_MCR_AWUM_Pos)        /*!< 0x00000020 */
7039 #define CAN_MCR_AWUM                         CAN_MCR_AWUM_Msk                  /*!< Automatic Wakeup Mode */
7040 #define CAN_MCR_ABOM_Pos                     (6U)
7041 #define CAN_MCR_ABOM_Msk                     (0x1UL << CAN_MCR_ABOM_Pos)        /*!< 0x00000040 */
7042 #define CAN_MCR_ABOM                         CAN_MCR_ABOM_Msk                  /*!< Automatic Bus-Off Management */
7043 #define CAN_MCR_TTCM_Pos                     (7U)
7044 #define CAN_MCR_TTCM_Msk                     (0x1UL << CAN_MCR_TTCM_Pos)        /*!< 0x00000080 */
7045 #define CAN_MCR_TTCM                         CAN_MCR_TTCM_Msk                  /*!< Time Triggered Communication Mode */
7046 #define CAN_MCR_RESET_Pos                    (15U)
7047 #define CAN_MCR_RESET_Msk                    (0x1UL << CAN_MCR_RESET_Pos)       /*!< 0x00008000 */
7048 #define CAN_MCR_RESET                        CAN_MCR_RESET_Msk                 /*!< CAN software master reset */
7049 #define CAN_MCR_DBF_Pos                      (16U)
7050 #define CAN_MCR_DBF_Msk                      (0x1UL << CAN_MCR_DBF_Pos)         /*!< 0x00010000 */
7051 #define CAN_MCR_DBF                          CAN_MCR_DBF_Msk                   /*!< CAN Debug freeze */
7052 
7053 /*******************  Bit definition for CAN_MSR register  ********************/
7054 #define CAN_MSR_INAK_Pos                     (0U)
7055 #define CAN_MSR_INAK_Msk                     (0x1UL << CAN_MSR_INAK_Pos)        /*!< 0x00000001 */
7056 #define CAN_MSR_INAK                         CAN_MSR_INAK_Msk                  /*!< Initialization Acknowledge */
7057 #define CAN_MSR_SLAK_Pos                     (1U)
7058 #define CAN_MSR_SLAK_Msk                     (0x1UL << CAN_MSR_SLAK_Pos)        /*!< 0x00000002 */
7059 #define CAN_MSR_SLAK                         CAN_MSR_SLAK_Msk                  /*!< Sleep Acknowledge */
7060 #define CAN_MSR_ERRI_Pos                     (2U)
7061 #define CAN_MSR_ERRI_Msk                     (0x1UL << CAN_MSR_ERRI_Pos)        /*!< 0x00000004 */
7062 #define CAN_MSR_ERRI                         CAN_MSR_ERRI_Msk                  /*!< Error Interrupt */
7063 #define CAN_MSR_WKUI_Pos                     (3U)
7064 #define CAN_MSR_WKUI_Msk                     (0x1UL << CAN_MSR_WKUI_Pos)        /*!< 0x00000008 */
7065 #define CAN_MSR_WKUI                         CAN_MSR_WKUI_Msk                  /*!< Wakeup Interrupt */
7066 #define CAN_MSR_SLAKI_Pos                    (4U)
7067 #define CAN_MSR_SLAKI_Msk                    (0x1UL << CAN_MSR_SLAKI_Pos)       /*!< 0x00000010 */
7068 #define CAN_MSR_SLAKI                        CAN_MSR_SLAKI_Msk                 /*!< Sleep Acknowledge Interrupt */
7069 #define CAN_MSR_TXM_Pos                      (8U)
7070 #define CAN_MSR_TXM_Msk                      (0x1UL << CAN_MSR_TXM_Pos)         /*!< 0x00000100 */
7071 #define CAN_MSR_TXM                          CAN_MSR_TXM_Msk                   /*!< Transmit Mode */
7072 #define CAN_MSR_RXM_Pos                      (9U)
7073 #define CAN_MSR_RXM_Msk                      (0x1UL << CAN_MSR_RXM_Pos)         /*!< 0x00000200 */
7074 #define CAN_MSR_RXM                          CAN_MSR_RXM_Msk                   /*!< Receive Mode */
7075 #define CAN_MSR_SAMP_Pos                     (10U)
7076 #define CAN_MSR_SAMP_Msk                     (0x1UL << CAN_MSR_SAMP_Pos)        /*!< 0x00000400 */
7077 #define CAN_MSR_SAMP                         CAN_MSR_SAMP_Msk                  /*!< Last Sample Point */
7078 #define CAN_MSR_RX_Pos                       (11U)
7079 #define CAN_MSR_RX_Msk                       (0x1UL << CAN_MSR_RX_Pos)          /*!< 0x00000800 */
7080 #define CAN_MSR_RX                           CAN_MSR_RX_Msk                    /*!< CAN Rx Signal */
7081 
7082 /*******************  Bit definition for CAN_TSR register  ********************/
7083 #define CAN_TSR_RQCP0_Pos                    (0U)
7084 #define CAN_TSR_RQCP0_Msk                    (0x1UL << CAN_TSR_RQCP0_Pos)       /*!< 0x00000001 */
7085 #define CAN_TSR_RQCP0                        CAN_TSR_RQCP0_Msk                 /*!< Request Completed Mailbox0 */
7086 #define CAN_TSR_TXOK0_Pos                    (1U)
7087 #define CAN_TSR_TXOK0_Msk                    (0x1UL << CAN_TSR_TXOK0_Pos)       /*!< 0x00000002 */
7088 #define CAN_TSR_TXOK0                        CAN_TSR_TXOK0_Msk                 /*!< Transmission OK of Mailbox0 */
7089 #define CAN_TSR_ALST0_Pos                    (2U)
7090 #define CAN_TSR_ALST0_Msk                    (0x1UL << CAN_TSR_ALST0_Pos)       /*!< 0x00000004 */
7091 #define CAN_TSR_ALST0                        CAN_TSR_ALST0_Msk                 /*!< Arbitration Lost for Mailbox0 */
7092 #define CAN_TSR_TERR0_Pos                    (3U)
7093 #define CAN_TSR_TERR0_Msk                    (0x1UL << CAN_TSR_TERR0_Pos)       /*!< 0x00000008 */
7094 #define CAN_TSR_TERR0                        CAN_TSR_TERR0_Msk                 /*!< Transmission Error of Mailbox0 */
7095 #define CAN_TSR_ABRQ0_Pos                    (7U)
7096 #define CAN_TSR_ABRQ0_Msk                    (0x1UL << CAN_TSR_ABRQ0_Pos)       /*!< 0x00000080 */
7097 #define CAN_TSR_ABRQ0                        CAN_TSR_ABRQ0_Msk                 /*!< Abort Request for Mailbox0 */
7098 #define CAN_TSR_RQCP1_Pos                    (8U)
7099 #define CAN_TSR_RQCP1_Msk                    (0x1UL << CAN_TSR_RQCP1_Pos)       /*!< 0x00000100 */
7100 #define CAN_TSR_RQCP1                        CAN_TSR_RQCP1_Msk                 /*!< Request Completed Mailbox1 */
7101 #define CAN_TSR_TXOK1_Pos                    (9U)
7102 #define CAN_TSR_TXOK1_Msk                    (0x1UL << CAN_TSR_TXOK1_Pos)       /*!< 0x00000200 */
7103 #define CAN_TSR_TXOK1                        CAN_TSR_TXOK1_Msk                 /*!< Transmission OK of Mailbox1 */
7104 #define CAN_TSR_ALST1_Pos                    (10U)
7105 #define CAN_TSR_ALST1_Msk                    (0x1UL << CAN_TSR_ALST1_Pos)       /*!< 0x00000400 */
7106 #define CAN_TSR_ALST1                        CAN_TSR_ALST1_Msk                 /*!< Arbitration Lost for Mailbox1 */
7107 #define CAN_TSR_TERR1_Pos                    (11U)
7108 #define CAN_TSR_TERR1_Msk                    (0x1UL << CAN_TSR_TERR1_Pos)       /*!< 0x00000800 */
7109 #define CAN_TSR_TERR1                        CAN_TSR_TERR1_Msk                 /*!< Transmission Error of Mailbox1 */
7110 #define CAN_TSR_ABRQ1_Pos                    (15U)
7111 #define CAN_TSR_ABRQ1_Msk                    (0x1UL << CAN_TSR_ABRQ1_Pos)       /*!< 0x00008000 */
7112 #define CAN_TSR_ABRQ1                        CAN_TSR_ABRQ1_Msk                 /*!< Abort Request for Mailbox 1 */
7113 #define CAN_TSR_RQCP2_Pos                    (16U)
7114 #define CAN_TSR_RQCP2_Msk                    (0x1UL << CAN_TSR_RQCP2_Pos)       /*!< 0x00010000 */
7115 #define CAN_TSR_RQCP2                        CAN_TSR_RQCP2_Msk                 /*!< Request Completed Mailbox2 */
7116 #define CAN_TSR_TXOK2_Pos                    (17U)
7117 #define CAN_TSR_TXOK2_Msk                    (0x1UL << CAN_TSR_TXOK2_Pos)       /*!< 0x00020000 */
7118 #define CAN_TSR_TXOK2                        CAN_TSR_TXOK2_Msk                 /*!< Transmission OK of Mailbox 2 */
7119 #define CAN_TSR_ALST2_Pos                    (18U)
7120 #define CAN_TSR_ALST2_Msk                    (0x1UL << CAN_TSR_ALST2_Pos)       /*!< 0x00040000 */
7121 #define CAN_TSR_ALST2                        CAN_TSR_ALST2_Msk                 /*!< Arbitration Lost for mailbox 2 */
7122 #define CAN_TSR_TERR2_Pos                    (19U)
7123 #define CAN_TSR_TERR2_Msk                    (0x1UL << CAN_TSR_TERR2_Pos)       /*!< 0x00080000 */
7124 #define CAN_TSR_TERR2                        CAN_TSR_TERR2_Msk                 /*!< Transmission Error of Mailbox 2 */
7125 #define CAN_TSR_ABRQ2_Pos                    (23U)
7126 #define CAN_TSR_ABRQ2_Msk                    (0x1UL << CAN_TSR_ABRQ2_Pos)       /*!< 0x00800000 */
7127 #define CAN_TSR_ABRQ2                        CAN_TSR_ABRQ2_Msk                 /*!< Abort Request for Mailbox 2 */
7128 #define CAN_TSR_CODE_Pos                     (24U)
7129 #define CAN_TSR_CODE_Msk                     (0x3UL << CAN_TSR_CODE_Pos)        /*!< 0x03000000 */
7130 #define CAN_TSR_CODE                         CAN_TSR_CODE_Msk                  /*!< Mailbox Code */
7131 
7132 #define CAN_TSR_TME_Pos                      (26U)
7133 #define CAN_TSR_TME_Msk                      (0x7UL << CAN_TSR_TME_Pos)         /*!< 0x1C000000 */
7134 #define CAN_TSR_TME                          CAN_TSR_TME_Msk                   /*!< TME[2:0] bits */
7135 #define CAN_TSR_TME0_Pos                     (26U)
7136 #define CAN_TSR_TME0_Msk                     (0x1UL << CAN_TSR_TME0_Pos)        /*!< 0x04000000 */
7137 #define CAN_TSR_TME0                         CAN_TSR_TME0_Msk                  /*!< Transmit Mailbox 0 Empty */
7138 #define CAN_TSR_TME1_Pos                     (27U)
7139 #define CAN_TSR_TME1_Msk                     (0x1UL << CAN_TSR_TME1_Pos)        /*!< 0x08000000 */
7140 #define CAN_TSR_TME1                         CAN_TSR_TME1_Msk                  /*!< Transmit Mailbox 1 Empty */
7141 #define CAN_TSR_TME2_Pos                     (28U)
7142 #define CAN_TSR_TME2_Msk                     (0x1UL << CAN_TSR_TME2_Pos)        /*!< 0x10000000 */
7143 #define CAN_TSR_TME2                         CAN_TSR_TME2_Msk                  /*!< Transmit Mailbox 2 Empty */
7144 
7145 #define CAN_TSR_LOW_Pos                      (29U)
7146 #define CAN_TSR_LOW_Msk                      (0x7UL << CAN_TSR_LOW_Pos)         /*!< 0xE0000000 */
7147 #define CAN_TSR_LOW                          CAN_TSR_LOW_Msk                   /*!< LOW[2:0] bits */
7148 #define CAN_TSR_LOW0_Pos                     (29U)
7149 #define CAN_TSR_LOW0_Msk                     (0x1UL << CAN_TSR_LOW0_Pos)        /*!< 0x20000000 */
7150 #define CAN_TSR_LOW0                         CAN_TSR_LOW0_Msk                  /*!< Lowest Priority Flag for Mailbox 0 */
7151 #define CAN_TSR_LOW1_Pos                     (30U)
7152 #define CAN_TSR_LOW1_Msk                     (0x1UL << CAN_TSR_LOW1_Pos)        /*!< 0x40000000 */
7153 #define CAN_TSR_LOW1                         CAN_TSR_LOW1_Msk                  /*!< Lowest Priority Flag for Mailbox 1 */
7154 #define CAN_TSR_LOW2_Pos                     (31U)
7155 #define CAN_TSR_LOW2_Msk                     (0x1UL << CAN_TSR_LOW2_Pos)        /*!< 0x80000000 */
7156 #define CAN_TSR_LOW2                         CAN_TSR_LOW2_Msk                  /*!< Lowest Priority Flag for Mailbox 2 */
7157 
7158 /*******************  Bit definition for CAN_RF0R register  *******************/
7159 #define CAN_RF0R_FMP0_Pos                    (0U)
7160 #define CAN_RF0R_FMP0_Msk                    (0x3UL << CAN_RF0R_FMP0_Pos)       /*!< 0x00000003 */
7161 #define CAN_RF0R_FMP0                        CAN_RF0R_FMP0_Msk                 /*!< FIFO 0 Message Pending */
7162 #define CAN_RF0R_FULL0_Pos                   (3U)
7163 #define CAN_RF0R_FULL0_Msk                   (0x1UL << CAN_RF0R_FULL0_Pos)      /*!< 0x00000008 */
7164 #define CAN_RF0R_FULL0                       CAN_RF0R_FULL0_Msk                /*!< FIFO 0 Full */
7165 #define CAN_RF0R_FOVR0_Pos                   (4U)
7166 #define CAN_RF0R_FOVR0_Msk                   (0x1UL << CAN_RF0R_FOVR0_Pos)      /*!< 0x00000010 */
7167 #define CAN_RF0R_FOVR0                       CAN_RF0R_FOVR0_Msk                /*!< FIFO 0 Overrun */
7168 #define CAN_RF0R_RFOM0_Pos                   (5U)
7169 #define CAN_RF0R_RFOM0_Msk                   (0x1UL << CAN_RF0R_RFOM0_Pos)      /*!< 0x00000020 */
7170 #define CAN_RF0R_RFOM0                       CAN_RF0R_RFOM0_Msk                /*!< Release FIFO 0 Output Mailbox */
7171 
7172 /*******************  Bit definition for CAN_RF1R register  *******************/
7173 #define CAN_RF1R_FMP1_Pos                    (0U)
7174 #define CAN_RF1R_FMP1_Msk                    (0x3UL << CAN_RF1R_FMP1_Pos)       /*!< 0x00000003 */
7175 #define CAN_RF1R_FMP1                        CAN_RF1R_FMP1_Msk                 /*!< FIFO 1 Message Pending */
7176 #define CAN_RF1R_FULL1_Pos                   (3U)
7177 #define CAN_RF1R_FULL1_Msk                   (0x1UL << CAN_RF1R_FULL1_Pos)      /*!< 0x00000008 */
7178 #define CAN_RF1R_FULL1                       CAN_RF1R_FULL1_Msk                /*!< FIFO 1 Full */
7179 #define CAN_RF1R_FOVR1_Pos                   (4U)
7180 #define CAN_RF1R_FOVR1_Msk                   (0x1UL << CAN_RF1R_FOVR1_Pos)      /*!< 0x00000010 */
7181 #define CAN_RF1R_FOVR1                       CAN_RF1R_FOVR1_Msk                /*!< FIFO 1 Overrun */
7182 #define CAN_RF1R_RFOM1_Pos                   (5U)
7183 #define CAN_RF1R_RFOM1_Msk                   (0x1UL << CAN_RF1R_RFOM1_Pos)      /*!< 0x00000020 */
7184 #define CAN_RF1R_RFOM1                       CAN_RF1R_RFOM1_Msk                /*!< Release FIFO 1 Output Mailbox */
7185 
7186 /********************  Bit definition for CAN_IER register  *******************/
7187 #define CAN_IER_TMEIE_Pos                    (0U)
7188 #define CAN_IER_TMEIE_Msk                    (0x1UL << CAN_IER_TMEIE_Pos)       /*!< 0x00000001 */
7189 #define CAN_IER_TMEIE                        CAN_IER_TMEIE_Msk                 /*!< Transmit Mailbox Empty Interrupt Enable */
7190 #define CAN_IER_FMPIE0_Pos                   (1U)
7191 #define CAN_IER_FMPIE0_Msk                   (0x1UL << CAN_IER_FMPIE0_Pos)      /*!< 0x00000002 */
7192 #define CAN_IER_FMPIE0                       CAN_IER_FMPIE0_Msk                /*!< FIFO Message Pending Interrupt Enable */
7193 #define CAN_IER_FFIE0_Pos                    (2U)
7194 #define CAN_IER_FFIE0_Msk                    (0x1UL << CAN_IER_FFIE0_Pos)       /*!< 0x00000004 */
7195 #define CAN_IER_FFIE0                        CAN_IER_FFIE0_Msk                 /*!< FIFO Full Interrupt Enable */
7196 #define CAN_IER_FOVIE0_Pos                   (3U)
7197 #define CAN_IER_FOVIE0_Msk                   (0x1UL << CAN_IER_FOVIE0_Pos)      /*!< 0x00000008 */
7198 #define CAN_IER_FOVIE0                       CAN_IER_FOVIE0_Msk                /*!< FIFO Overrun Interrupt Enable */
7199 #define CAN_IER_FMPIE1_Pos                   (4U)
7200 #define CAN_IER_FMPIE1_Msk                   (0x1UL << CAN_IER_FMPIE1_Pos)      /*!< 0x00000010 */
7201 #define CAN_IER_FMPIE1                       CAN_IER_FMPIE1_Msk                /*!< FIFO Message Pending Interrupt Enable */
7202 #define CAN_IER_FFIE1_Pos                    (5U)
7203 #define CAN_IER_FFIE1_Msk                    (0x1UL << CAN_IER_FFIE1_Pos)       /*!< 0x00000020 */
7204 #define CAN_IER_FFIE1                        CAN_IER_FFIE1_Msk                 /*!< FIFO Full Interrupt Enable */
7205 #define CAN_IER_FOVIE1_Pos                   (6U)
7206 #define CAN_IER_FOVIE1_Msk                   (0x1UL << CAN_IER_FOVIE1_Pos)      /*!< 0x00000040 */
7207 #define CAN_IER_FOVIE1                       CAN_IER_FOVIE1_Msk                /*!< FIFO Overrun Interrupt Enable */
7208 #define CAN_IER_EWGIE_Pos                    (8U)
7209 #define CAN_IER_EWGIE_Msk                    (0x1UL << CAN_IER_EWGIE_Pos)       /*!< 0x00000100 */
7210 #define CAN_IER_EWGIE                        CAN_IER_EWGIE_Msk                 /*!< Error Warning Interrupt Enable */
7211 #define CAN_IER_EPVIE_Pos                    (9U)
7212 #define CAN_IER_EPVIE_Msk                    (0x1UL << CAN_IER_EPVIE_Pos)       /*!< 0x00000200 */
7213 #define CAN_IER_EPVIE                        CAN_IER_EPVIE_Msk                 /*!< Error Passive Interrupt Enable */
7214 #define CAN_IER_BOFIE_Pos                    (10U)
7215 #define CAN_IER_BOFIE_Msk                    (0x1UL << CAN_IER_BOFIE_Pos)       /*!< 0x00000400 */
7216 #define CAN_IER_BOFIE                        CAN_IER_BOFIE_Msk                 /*!< Bus-Off Interrupt Enable */
7217 #define CAN_IER_LECIE_Pos                    (11U)
7218 #define CAN_IER_LECIE_Msk                    (0x1UL << CAN_IER_LECIE_Pos)       /*!< 0x00000800 */
7219 #define CAN_IER_LECIE                        CAN_IER_LECIE_Msk                 /*!< Last Error Code Interrupt Enable */
7220 #define CAN_IER_ERRIE_Pos                    (15U)
7221 #define CAN_IER_ERRIE_Msk                    (0x1UL << CAN_IER_ERRIE_Pos)       /*!< 0x00008000 */
7222 #define CAN_IER_ERRIE                        CAN_IER_ERRIE_Msk                 /*!< Error Interrupt Enable */
7223 #define CAN_IER_WKUIE_Pos                    (16U)
7224 #define CAN_IER_WKUIE_Msk                    (0x1UL << CAN_IER_WKUIE_Pos)       /*!< 0x00010000 */
7225 #define CAN_IER_WKUIE                        CAN_IER_WKUIE_Msk                 /*!< Wakeup Interrupt Enable */
7226 #define CAN_IER_SLKIE_Pos                    (17U)
7227 #define CAN_IER_SLKIE_Msk                    (0x1UL << CAN_IER_SLKIE_Pos)       /*!< 0x00020000 */
7228 #define CAN_IER_SLKIE                        CAN_IER_SLKIE_Msk                 /*!< Sleep Interrupt Enable */
7229 
7230 /********************  Bit definition for CAN_ESR register  *******************/
7231 #define CAN_ESR_EWGF_Pos                     (0U)
7232 #define CAN_ESR_EWGF_Msk                     (0x1UL << CAN_ESR_EWGF_Pos)        /*!< 0x00000001 */
7233 #define CAN_ESR_EWGF                         CAN_ESR_EWGF_Msk                  /*!< Error Warning Flag */
7234 #define CAN_ESR_EPVF_Pos                     (1U)
7235 #define CAN_ESR_EPVF_Msk                     (0x1UL << CAN_ESR_EPVF_Pos)        /*!< 0x00000002 */
7236 #define CAN_ESR_EPVF                         CAN_ESR_EPVF_Msk                  /*!< Error Passive Flag */
7237 #define CAN_ESR_BOFF_Pos                     (2U)
7238 #define CAN_ESR_BOFF_Msk                     (0x1UL << CAN_ESR_BOFF_Pos)        /*!< 0x00000004 */
7239 #define CAN_ESR_BOFF                         CAN_ESR_BOFF_Msk                  /*!< Bus-Off Flag */
7240 
7241 #define CAN_ESR_LEC_Pos                      (4U)
7242 #define CAN_ESR_LEC_Msk                      (0x7UL << CAN_ESR_LEC_Pos)         /*!< 0x00000070 */
7243 #define CAN_ESR_LEC                          CAN_ESR_LEC_Msk                   /*!< LEC[2:0] bits (Last Error Code) */
7244 #define CAN_ESR_LEC_0                        (0x1UL << CAN_ESR_LEC_Pos)         /*!< 0x00000010 */
7245 #define CAN_ESR_LEC_1                        (0x2UL << CAN_ESR_LEC_Pos)         /*!< 0x00000020 */
7246 #define CAN_ESR_LEC_2                        (0x4UL << CAN_ESR_LEC_Pos)         /*!< 0x00000040 */
7247 
7248 #define CAN_ESR_TEC_Pos                      (16U)
7249 #define CAN_ESR_TEC_Msk                      (0xFFUL << CAN_ESR_TEC_Pos)        /*!< 0x00FF0000 */
7250 #define CAN_ESR_TEC                          CAN_ESR_TEC_Msk                   /*!< Least significant byte of the 9-bit Transmit Error Counter */
7251 #define CAN_ESR_REC_Pos                      (24U)
7252 #define CAN_ESR_REC_Msk                      (0xFFUL << CAN_ESR_REC_Pos)        /*!< 0xFF000000 */
7253 #define CAN_ESR_REC                          CAN_ESR_REC_Msk                   /*!< Receive Error Counter */
7254 
7255 /*******************  Bit definition for CAN_BTR register  ********************/
7256 #define CAN_BTR_BRP_Pos                      (0U)
7257 #define CAN_BTR_BRP_Msk                      (0x3FFUL << CAN_BTR_BRP_Pos)       /*!< 0x000003FF */
7258 #define CAN_BTR_BRP                          CAN_BTR_BRP_Msk                   /*!<Baud Rate Prescaler */
7259 #define CAN_BTR_TS1_Pos                      (16U)
7260 #define CAN_BTR_TS1_Msk                      (0xFUL << CAN_BTR_TS1_Pos)         /*!< 0x000F0000 */
7261 #define CAN_BTR_TS1                          CAN_BTR_TS1_Msk                   /*!<Time Segment 1 */
7262 #define CAN_BTR_TS1_0                        (0x1UL << CAN_BTR_TS1_Pos)         /*!< 0x00010000 */
7263 #define CAN_BTR_TS1_1                        (0x2UL << CAN_BTR_TS1_Pos)         /*!< 0x00020000 */
7264 #define CAN_BTR_TS1_2                        (0x4UL << CAN_BTR_TS1_Pos)         /*!< 0x00040000 */
7265 #define CAN_BTR_TS1_3                        (0x8UL << CAN_BTR_TS1_Pos)         /*!< 0x00080000 */
7266 #define CAN_BTR_TS2_Pos                      (20U)
7267 #define CAN_BTR_TS2_Msk                      (0x7UL << CAN_BTR_TS2_Pos)         /*!< 0x00700000 */
7268 #define CAN_BTR_TS2                          CAN_BTR_TS2_Msk                   /*!<Time Segment 2 */
7269 #define CAN_BTR_TS2_0                        (0x1UL << CAN_BTR_TS2_Pos)         /*!< 0x00100000 */
7270 #define CAN_BTR_TS2_1                        (0x2UL << CAN_BTR_TS2_Pos)         /*!< 0x00200000 */
7271 #define CAN_BTR_TS2_2                        (0x4UL << CAN_BTR_TS2_Pos)         /*!< 0x00400000 */
7272 #define CAN_BTR_SJW_Pos                      (24U)
7273 #define CAN_BTR_SJW_Msk                      (0x3UL << CAN_BTR_SJW_Pos)         /*!< 0x03000000 */
7274 #define CAN_BTR_SJW                          CAN_BTR_SJW_Msk                   /*!<Resynchronization Jump Width */
7275 #define CAN_BTR_SJW_0                        (0x1UL << CAN_BTR_SJW_Pos)         /*!< 0x01000000 */
7276 #define CAN_BTR_SJW_1                        (0x2UL << CAN_BTR_SJW_Pos)         /*!< 0x02000000 */
7277 #define CAN_BTR_LBKM_Pos                     (30U)
7278 #define CAN_BTR_LBKM_Msk                     (0x1UL << CAN_BTR_LBKM_Pos)        /*!< 0x40000000 */
7279 #define CAN_BTR_LBKM                         CAN_BTR_LBKM_Msk                  /*!<Loop Back Mode (Debug) */
7280 #define CAN_BTR_SILM_Pos                     (31U)
7281 #define CAN_BTR_SILM_Msk                     (0x1UL << CAN_BTR_SILM_Pos)        /*!< 0x80000000 */
7282 #define CAN_BTR_SILM                         CAN_BTR_SILM_Msk                  /*!<Silent Mode */
7283 
7284 /*!< Mailbox registers */
7285 /******************  Bit definition for CAN_TI0R register  ********************/
7286 #define CAN_TI0R_TXRQ_Pos                    (0U)
7287 #define CAN_TI0R_TXRQ_Msk                    (0x1UL << CAN_TI0R_TXRQ_Pos)       /*!< 0x00000001 */
7288 #define CAN_TI0R_TXRQ                        CAN_TI0R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
7289 #define CAN_TI0R_RTR_Pos                     (1U)
7290 #define CAN_TI0R_RTR_Msk                     (0x1UL << CAN_TI0R_RTR_Pos)        /*!< 0x00000002 */
7291 #define CAN_TI0R_RTR                         CAN_TI0R_RTR_Msk                  /*!< Remote Transmission Request */
7292 #define CAN_TI0R_IDE_Pos                     (2U)
7293 #define CAN_TI0R_IDE_Msk                     (0x1UL << CAN_TI0R_IDE_Pos)        /*!< 0x00000004 */
7294 #define CAN_TI0R_IDE                         CAN_TI0R_IDE_Msk                  /*!< Identifier Extension */
7295 #define CAN_TI0R_EXID_Pos                    (3U)
7296 #define CAN_TI0R_EXID_Msk                    (0x3FFFFUL << CAN_TI0R_EXID_Pos)   /*!< 0x001FFFF8 */
7297 #define CAN_TI0R_EXID                        CAN_TI0R_EXID_Msk                 /*!< Extended Identifier */
7298 #define CAN_TI0R_STID_Pos                    (21U)
7299 #define CAN_TI0R_STID_Msk                    (0x7FFUL << CAN_TI0R_STID_Pos)     /*!< 0xFFE00000 */
7300 #define CAN_TI0R_STID                        CAN_TI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7301 
7302 /******************  Bit definition for CAN_TDT0R register  *******************/
7303 #define CAN_TDT0R_DLC_Pos                    (0U)
7304 #define CAN_TDT0R_DLC_Msk                    (0xFUL << CAN_TDT0R_DLC_Pos)       /*!< 0x0000000F */
7305 #define CAN_TDT0R_DLC                        CAN_TDT0R_DLC_Msk                 /*!< Data Length Code */
7306 #define CAN_TDT0R_TGT_Pos                    (8U)
7307 #define CAN_TDT0R_TGT_Msk                    (0x1UL << CAN_TDT0R_TGT_Pos)       /*!< 0x00000100 */
7308 #define CAN_TDT0R_TGT                        CAN_TDT0R_TGT_Msk                 /*!< Transmit Global Time */
7309 #define CAN_TDT0R_TIME_Pos                   (16U)
7310 #define CAN_TDT0R_TIME_Msk                   (0xFFFFUL << CAN_TDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
7311 #define CAN_TDT0R_TIME                       CAN_TDT0R_TIME_Msk                /*!< Message Time Stamp */
7312 
7313 /******************  Bit definition for CAN_TDL0R register  *******************/
7314 #define CAN_TDL0R_DATA0_Pos                  (0U)
7315 #define CAN_TDL0R_DATA0_Msk                  (0xFFUL << CAN_TDL0R_DATA0_Pos)    /*!< 0x000000FF */
7316 #define CAN_TDL0R_DATA0                      CAN_TDL0R_DATA0_Msk               /*!< Data byte 0 */
7317 #define CAN_TDL0R_DATA1_Pos                  (8U)
7318 #define CAN_TDL0R_DATA1_Msk                  (0xFFUL << CAN_TDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
7319 #define CAN_TDL0R_DATA1                      CAN_TDL0R_DATA1_Msk               /*!< Data byte 1 */
7320 #define CAN_TDL0R_DATA2_Pos                  (16U)
7321 #define CAN_TDL0R_DATA2_Msk                  (0xFFUL << CAN_TDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
7322 #define CAN_TDL0R_DATA2                      CAN_TDL0R_DATA2_Msk               /*!< Data byte 2 */
7323 #define CAN_TDL0R_DATA3_Pos                  (24U)
7324 #define CAN_TDL0R_DATA3_Msk                  (0xFFUL << CAN_TDL0R_DATA3_Pos)    /*!< 0xFF000000 */
7325 #define CAN_TDL0R_DATA3                      CAN_TDL0R_DATA3_Msk               /*!< Data byte 3 */
7326 
7327 /******************  Bit definition for CAN_TDH0R register  *******************/
7328 #define CAN_TDH0R_DATA4_Pos                  (0U)
7329 #define CAN_TDH0R_DATA4_Msk                  (0xFFUL << CAN_TDH0R_DATA4_Pos)    /*!< 0x000000FF */
7330 #define CAN_TDH0R_DATA4                      CAN_TDH0R_DATA4_Msk               /*!< Data byte 4 */
7331 #define CAN_TDH0R_DATA5_Pos                  (8U)
7332 #define CAN_TDH0R_DATA5_Msk                  (0xFFUL << CAN_TDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
7333 #define CAN_TDH0R_DATA5                      CAN_TDH0R_DATA5_Msk               /*!< Data byte 5 */
7334 #define CAN_TDH0R_DATA6_Pos                  (16U)
7335 #define CAN_TDH0R_DATA6_Msk                  (0xFFUL << CAN_TDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
7336 #define CAN_TDH0R_DATA6                      CAN_TDH0R_DATA6_Msk               /*!< Data byte 6 */
7337 #define CAN_TDH0R_DATA7_Pos                  (24U)
7338 #define CAN_TDH0R_DATA7_Msk                  (0xFFUL << CAN_TDH0R_DATA7_Pos)    /*!< 0xFF000000 */
7339 #define CAN_TDH0R_DATA7                      CAN_TDH0R_DATA7_Msk               /*!< Data byte 7 */
7340 
7341 /*******************  Bit definition for CAN_TI1R register  *******************/
7342 #define CAN_TI1R_TXRQ_Pos                    (0U)
7343 #define CAN_TI1R_TXRQ_Msk                    (0x1UL << CAN_TI1R_TXRQ_Pos)       /*!< 0x00000001 */
7344 #define CAN_TI1R_TXRQ                        CAN_TI1R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
7345 #define CAN_TI1R_RTR_Pos                     (1U)
7346 #define CAN_TI1R_RTR_Msk                     (0x1UL << CAN_TI1R_RTR_Pos)        /*!< 0x00000002 */
7347 #define CAN_TI1R_RTR                         CAN_TI1R_RTR_Msk                  /*!< Remote Transmission Request */
7348 #define CAN_TI1R_IDE_Pos                     (2U)
7349 #define CAN_TI1R_IDE_Msk                     (0x1UL << CAN_TI1R_IDE_Pos)        /*!< 0x00000004 */
7350 #define CAN_TI1R_IDE                         CAN_TI1R_IDE_Msk                  /*!< Identifier Extension */
7351 #define CAN_TI1R_EXID_Pos                    (3U)
7352 #define CAN_TI1R_EXID_Msk                    (0x3FFFFUL << CAN_TI1R_EXID_Pos)   /*!< 0x001FFFF8 */
7353 #define CAN_TI1R_EXID                        CAN_TI1R_EXID_Msk                 /*!< Extended Identifier */
7354 #define CAN_TI1R_STID_Pos                    (21U)
7355 #define CAN_TI1R_STID_Msk                    (0x7FFUL << CAN_TI1R_STID_Pos)     /*!< 0xFFE00000 */
7356 #define CAN_TI1R_STID                        CAN_TI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7357 
7358 /*******************  Bit definition for CAN_TDT1R register  ******************/
7359 #define CAN_TDT1R_DLC_Pos                    (0U)
7360 #define CAN_TDT1R_DLC_Msk                    (0xFUL << CAN_TDT1R_DLC_Pos)       /*!< 0x0000000F */
7361 #define CAN_TDT1R_DLC                        CAN_TDT1R_DLC_Msk                 /*!< Data Length Code */
7362 #define CAN_TDT1R_TGT_Pos                    (8U)
7363 #define CAN_TDT1R_TGT_Msk                    (0x1UL << CAN_TDT1R_TGT_Pos)       /*!< 0x00000100 */
7364 #define CAN_TDT1R_TGT                        CAN_TDT1R_TGT_Msk                 /*!< Transmit Global Time */
7365 #define CAN_TDT1R_TIME_Pos                   (16U)
7366 #define CAN_TDT1R_TIME_Msk                   (0xFFFFUL << CAN_TDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
7367 #define CAN_TDT1R_TIME                       CAN_TDT1R_TIME_Msk                /*!< Message Time Stamp */
7368 
7369 /*******************  Bit definition for CAN_TDL1R register  ******************/
7370 #define CAN_TDL1R_DATA0_Pos                  (0U)
7371 #define CAN_TDL1R_DATA0_Msk                  (0xFFUL << CAN_TDL1R_DATA0_Pos)    /*!< 0x000000FF */
7372 #define CAN_TDL1R_DATA0                      CAN_TDL1R_DATA0_Msk               /*!< Data byte 0 */
7373 #define CAN_TDL1R_DATA1_Pos                  (8U)
7374 #define CAN_TDL1R_DATA1_Msk                  (0xFFUL << CAN_TDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
7375 #define CAN_TDL1R_DATA1                      CAN_TDL1R_DATA1_Msk               /*!< Data byte 1 */
7376 #define CAN_TDL1R_DATA2_Pos                  (16U)
7377 #define CAN_TDL1R_DATA2_Msk                  (0xFFUL << CAN_TDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
7378 #define CAN_TDL1R_DATA2                      CAN_TDL1R_DATA2_Msk               /*!< Data byte 2 */
7379 #define CAN_TDL1R_DATA3_Pos                  (24U)
7380 #define CAN_TDL1R_DATA3_Msk                  (0xFFUL << CAN_TDL1R_DATA3_Pos)    /*!< 0xFF000000 */
7381 #define CAN_TDL1R_DATA3                      CAN_TDL1R_DATA3_Msk               /*!< Data byte 3 */
7382 
7383 /*******************  Bit definition for CAN_TDH1R register  ******************/
7384 #define CAN_TDH1R_DATA4_Pos                  (0U)
7385 #define CAN_TDH1R_DATA4_Msk                  (0xFFUL << CAN_TDH1R_DATA4_Pos)    /*!< 0x000000FF */
7386 #define CAN_TDH1R_DATA4                      CAN_TDH1R_DATA4_Msk               /*!< Data byte 4 */
7387 #define CAN_TDH1R_DATA5_Pos                  (8U)
7388 #define CAN_TDH1R_DATA5_Msk                  (0xFFUL << CAN_TDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
7389 #define CAN_TDH1R_DATA5                      CAN_TDH1R_DATA5_Msk               /*!< Data byte 5 */
7390 #define CAN_TDH1R_DATA6_Pos                  (16U)
7391 #define CAN_TDH1R_DATA6_Msk                  (0xFFUL << CAN_TDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
7392 #define CAN_TDH1R_DATA6                      CAN_TDH1R_DATA6_Msk               /*!< Data byte 6 */
7393 #define CAN_TDH1R_DATA7_Pos                  (24U)
7394 #define CAN_TDH1R_DATA7_Msk                  (0xFFUL << CAN_TDH1R_DATA7_Pos)    /*!< 0xFF000000 */
7395 #define CAN_TDH1R_DATA7                      CAN_TDH1R_DATA7_Msk               /*!< Data byte 7 */
7396 
7397 /*******************  Bit definition for CAN_TI2R register  *******************/
7398 #define CAN_TI2R_TXRQ_Pos                    (0U)
7399 #define CAN_TI2R_TXRQ_Msk                    (0x1UL << CAN_TI2R_TXRQ_Pos)       /*!< 0x00000001 */
7400 #define CAN_TI2R_TXRQ                        CAN_TI2R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
7401 #define CAN_TI2R_RTR_Pos                     (1U)
7402 #define CAN_TI2R_RTR_Msk                     (0x1UL << CAN_TI2R_RTR_Pos)        /*!< 0x00000002 */
7403 #define CAN_TI2R_RTR                         CAN_TI2R_RTR_Msk                  /*!< Remote Transmission Request */
7404 #define CAN_TI2R_IDE_Pos                     (2U)
7405 #define CAN_TI2R_IDE_Msk                     (0x1UL << CAN_TI2R_IDE_Pos)        /*!< 0x00000004 */
7406 #define CAN_TI2R_IDE                         CAN_TI2R_IDE_Msk                  /*!< Identifier Extension */
7407 #define CAN_TI2R_EXID_Pos                    (3U)
7408 #define CAN_TI2R_EXID_Msk                    (0x3FFFFUL << CAN_TI2R_EXID_Pos)   /*!< 0x001FFFF8 */
7409 #define CAN_TI2R_EXID                        CAN_TI2R_EXID_Msk                 /*!< Extended identifier */
7410 #define CAN_TI2R_STID_Pos                    (21U)
7411 #define CAN_TI2R_STID_Msk                    (0x7FFUL << CAN_TI2R_STID_Pos)     /*!< 0xFFE00000 */
7412 #define CAN_TI2R_STID                        CAN_TI2R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7413 
7414 /*******************  Bit definition for CAN_TDT2R register  ******************/
7415 #define CAN_TDT2R_DLC_Pos                    (0U)
7416 #define CAN_TDT2R_DLC_Msk                    (0xFUL << CAN_TDT2R_DLC_Pos)       /*!< 0x0000000F */
7417 #define CAN_TDT2R_DLC                        CAN_TDT2R_DLC_Msk                 /*!< Data Length Code */
7418 #define CAN_TDT2R_TGT_Pos                    (8U)
7419 #define CAN_TDT2R_TGT_Msk                    (0x1UL << CAN_TDT2R_TGT_Pos)       /*!< 0x00000100 */
7420 #define CAN_TDT2R_TGT                        CAN_TDT2R_TGT_Msk                 /*!< Transmit Global Time */
7421 #define CAN_TDT2R_TIME_Pos                   (16U)
7422 #define CAN_TDT2R_TIME_Msk                   (0xFFFFUL << CAN_TDT2R_TIME_Pos)   /*!< 0xFFFF0000 */
7423 #define CAN_TDT2R_TIME                       CAN_TDT2R_TIME_Msk                /*!< Message Time Stamp */
7424 
7425 /*******************  Bit definition for CAN_TDL2R register  ******************/
7426 #define CAN_TDL2R_DATA0_Pos                  (0U)
7427 #define CAN_TDL2R_DATA0_Msk                  (0xFFUL << CAN_TDL2R_DATA0_Pos)    /*!< 0x000000FF */
7428 #define CAN_TDL2R_DATA0                      CAN_TDL2R_DATA0_Msk               /*!< Data byte 0 */
7429 #define CAN_TDL2R_DATA1_Pos                  (8U)
7430 #define CAN_TDL2R_DATA1_Msk                  (0xFFUL << CAN_TDL2R_DATA1_Pos)    /*!< 0x0000FF00 */
7431 #define CAN_TDL2R_DATA1                      CAN_TDL2R_DATA1_Msk               /*!< Data byte 1 */
7432 #define CAN_TDL2R_DATA2_Pos                  (16U)
7433 #define CAN_TDL2R_DATA2_Msk                  (0xFFUL << CAN_TDL2R_DATA2_Pos)    /*!< 0x00FF0000 */
7434 #define CAN_TDL2R_DATA2                      CAN_TDL2R_DATA2_Msk               /*!< Data byte 2 */
7435 #define CAN_TDL2R_DATA3_Pos                  (24U)
7436 #define CAN_TDL2R_DATA3_Msk                  (0xFFUL << CAN_TDL2R_DATA3_Pos)    /*!< 0xFF000000 */
7437 #define CAN_TDL2R_DATA3                      CAN_TDL2R_DATA3_Msk               /*!< Data byte 3 */
7438 
7439 /*******************  Bit definition for CAN_TDH2R register  ******************/
7440 #define CAN_TDH2R_DATA4_Pos                  (0U)
7441 #define CAN_TDH2R_DATA4_Msk                  (0xFFUL << CAN_TDH2R_DATA4_Pos)    /*!< 0x000000FF */
7442 #define CAN_TDH2R_DATA4                      CAN_TDH2R_DATA4_Msk               /*!< Data byte 4 */
7443 #define CAN_TDH2R_DATA5_Pos                  (8U)
7444 #define CAN_TDH2R_DATA5_Msk                  (0xFFUL << CAN_TDH2R_DATA5_Pos)    /*!< 0x0000FF00 */
7445 #define CAN_TDH2R_DATA5                      CAN_TDH2R_DATA5_Msk               /*!< Data byte 5 */
7446 #define CAN_TDH2R_DATA6_Pos                  (16U)
7447 #define CAN_TDH2R_DATA6_Msk                  (0xFFUL << CAN_TDH2R_DATA6_Pos)    /*!< 0x00FF0000 */
7448 #define CAN_TDH2R_DATA6                      CAN_TDH2R_DATA6_Msk               /*!< Data byte 6 */
7449 #define CAN_TDH2R_DATA7_Pos                  (24U)
7450 #define CAN_TDH2R_DATA7_Msk                  (0xFFUL << CAN_TDH2R_DATA7_Pos)    /*!< 0xFF000000 */
7451 #define CAN_TDH2R_DATA7                      CAN_TDH2R_DATA7_Msk               /*!< Data byte 7 */
7452 
7453 /*******************  Bit definition for CAN_RI0R register  *******************/
7454 #define CAN_RI0R_RTR_Pos                     (1U)
7455 #define CAN_RI0R_RTR_Msk                     (0x1UL << CAN_RI0R_RTR_Pos)        /*!< 0x00000002 */
7456 #define CAN_RI0R_RTR                         CAN_RI0R_RTR_Msk                  /*!< Remote Transmission Request */
7457 #define CAN_RI0R_IDE_Pos                     (2U)
7458 #define CAN_RI0R_IDE_Msk                     (0x1UL << CAN_RI0R_IDE_Pos)        /*!< 0x00000004 */
7459 #define CAN_RI0R_IDE                         CAN_RI0R_IDE_Msk                  /*!< Identifier Extension */
7460 #define CAN_RI0R_EXID_Pos                    (3U)
7461 #define CAN_RI0R_EXID_Msk                    (0x3FFFFUL << CAN_RI0R_EXID_Pos)   /*!< 0x001FFFF8 */
7462 #define CAN_RI0R_EXID                        CAN_RI0R_EXID_Msk                 /*!< Extended Identifier */
7463 #define CAN_RI0R_STID_Pos                    (21U)
7464 #define CAN_RI0R_STID_Msk                    (0x7FFUL << CAN_RI0R_STID_Pos)     /*!< 0xFFE00000 */
7465 #define CAN_RI0R_STID                        CAN_RI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7466 
7467 /*******************  Bit definition for CAN_RDT0R register  ******************/
7468 #define CAN_RDT0R_DLC_Pos                    (0U)
7469 #define CAN_RDT0R_DLC_Msk                    (0xFUL << CAN_RDT0R_DLC_Pos)       /*!< 0x0000000F */
7470 #define CAN_RDT0R_DLC                        CAN_RDT0R_DLC_Msk                 /*!< Data Length Code */
7471 #define CAN_RDT0R_FMI_Pos                    (8U)
7472 #define CAN_RDT0R_FMI_Msk                    (0xFFUL << CAN_RDT0R_FMI_Pos)      /*!< 0x0000FF00 */
7473 #define CAN_RDT0R_FMI                        CAN_RDT0R_FMI_Msk                 /*!< Filter Match Index */
7474 #define CAN_RDT0R_TIME_Pos                   (16U)
7475 #define CAN_RDT0R_TIME_Msk                   (0xFFFFUL << CAN_RDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
7476 #define CAN_RDT0R_TIME                       CAN_RDT0R_TIME_Msk                /*!< Message Time Stamp */
7477 
7478 /*******************  Bit definition for CAN_RDL0R register  ******************/
7479 #define CAN_RDL0R_DATA0_Pos                  (0U)
7480 #define CAN_RDL0R_DATA0_Msk                  (0xFFUL << CAN_RDL0R_DATA0_Pos)    /*!< 0x000000FF */
7481 #define CAN_RDL0R_DATA0                      CAN_RDL0R_DATA0_Msk               /*!< Data byte 0 */
7482 #define CAN_RDL0R_DATA1_Pos                  (8U)
7483 #define CAN_RDL0R_DATA1_Msk                  (0xFFUL << CAN_RDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
7484 #define CAN_RDL0R_DATA1                      CAN_RDL0R_DATA1_Msk               /*!< Data byte 1 */
7485 #define CAN_RDL0R_DATA2_Pos                  (16U)
7486 #define CAN_RDL0R_DATA2_Msk                  (0xFFUL << CAN_RDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
7487 #define CAN_RDL0R_DATA2                      CAN_RDL0R_DATA2_Msk               /*!< Data byte 2 */
7488 #define CAN_RDL0R_DATA3_Pos                  (24U)
7489 #define CAN_RDL0R_DATA3_Msk                  (0xFFUL << CAN_RDL0R_DATA3_Pos)    /*!< 0xFF000000 */
7490 #define CAN_RDL0R_DATA3                      CAN_RDL0R_DATA3_Msk               /*!< Data byte 3 */
7491 
7492 /*******************  Bit definition for CAN_RDH0R register  ******************/
7493 #define CAN_RDH0R_DATA4_Pos                  (0U)
7494 #define CAN_RDH0R_DATA4_Msk                  (0xFFUL << CAN_RDH0R_DATA4_Pos)    /*!< 0x000000FF */
7495 #define CAN_RDH0R_DATA4                      CAN_RDH0R_DATA4_Msk               /*!< Data byte 4 */
7496 #define CAN_RDH0R_DATA5_Pos                  (8U)
7497 #define CAN_RDH0R_DATA5_Msk                  (0xFFUL << CAN_RDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
7498 #define CAN_RDH0R_DATA5                      CAN_RDH0R_DATA5_Msk               /*!< Data byte 5 */
7499 #define CAN_RDH0R_DATA6_Pos                  (16U)
7500 #define CAN_RDH0R_DATA6_Msk                  (0xFFUL << CAN_RDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
7501 #define CAN_RDH0R_DATA6                      CAN_RDH0R_DATA6_Msk               /*!< Data byte 6 */
7502 #define CAN_RDH0R_DATA7_Pos                  (24U)
7503 #define CAN_RDH0R_DATA7_Msk                  (0xFFUL << CAN_RDH0R_DATA7_Pos)    /*!< 0xFF000000 */
7504 #define CAN_RDH0R_DATA7                      CAN_RDH0R_DATA7_Msk               /*!< Data byte 7 */
7505 
7506 /*******************  Bit definition for CAN_RI1R register  *******************/
7507 #define CAN_RI1R_RTR_Pos                     (1U)
7508 #define CAN_RI1R_RTR_Msk                     (0x1UL << CAN_RI1R_RTR_Pos)        /*!< 0x00000002 */
7509 #define CAN_RI1R_RTR                         CAN_RI1R_RTR_Msk                  /*!< Remote Transmission Request */
7510 #define CAN_RI1R_IDE_Pos                     (2U)
7511 #define CAN_RI1R_IDE_Msk                     (0x1UL << CAN_RI1R_IDE_Pos)        /*!< 0x00000004 */
7512 #define CAN_RI1R_IDE                         CAN_RI1R_IDE_Msk                  /*!< Identifier Extension */
7513 #define CAN_RI1R_EXID_Pos                    (3U)
7514 #define CAN_RI1R_EXID_Msk                    (0x3FFFFUL << CAN_RI1R_EXID_Pos)   /*!< 0x001FFFF8 */
7515 #define CAN_RI1R_EXID                        CAN_RI1R_EXID_Msk                 /*!< Extended identifier */
7516 #define CAN_RI1R_STID_Pos                    (21U)
7517 #define CAN_RI1R_STID_Msk                    (0x7FFUL << CAN_RI1R_STID_Pos)     /*!< 0xFFE00000 */
7518 #define CAN_RI1R_STID                        CAN_RI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
7519 
7520 /*******************  Bit definition for CAN_RDT1R register  ******************/
7521 #define CAN_RDT1R_DLC_Pos                    (0U)
7522 #define CAN_RDT1R_DLC_Msk                    (0xFUL << CAN_RDT1R_DLC_Pos)       /*!< 0x0000000F */
7523 #define CAN_RDT1R_DLC                        CAN_RDT1R_DLC_Msk                 /*!< Data Length Code */
7524 #define CAN_RDT1R_FMI_Pos                    (8U)
7525 #define CAN_RDT1R_FMI_Msk                    (0xFFUL << CAN_RDT1R_FMI_Pos)      /*!< 0x0000FF00 */
7526 #define CAN_RDT1R_FMI                        CAN_RDT1R_FMI_Msk                 /*!< Filter Match Index */
7527 #define CAN_RDT1R_TIME_Pos                   (16U)
7528 #define CAN_RDT1R_TIME_Msk                   (0xFFFFUL << CAN_RDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
7529 #define CAN_RDT1R_TIME                       CAN_RDT1R_TIME_Msk                /*!< Message Time Stamp */
7530 
7531 /*******************  Bit definition for CAN_RDL1R register  ******************/
7532 #define CAN_RDL1R_DATA0_Pos                  (0U)
7533 #define CAN_RDL1R_DATA0_Msk                  (0xFFUL << CAN_RDL1R_DATA0_Pos)    /*!< 0x000000FF */
7534 #define CAN_RDL1R_DATA0                      CAN_RDL1R_DATA0_Msk               /*!< Data byte 0 */
7535 #define CAN_RDL1R_DATA1_Pos                  (8U)
7536 #define CAN_RDL1R_DATA1_Msk                  (0xFFUL << CAN_RDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
7537 #define CAN_RDL1R_DATA1                      CAN_RDL1R_DATA1_Msk               /*!< Data byte 1 */
7538 #define CAN_RDL1R_DATA2_Pos                  (16U)
7539 #define CAN_RDL1R_DATA2_Msk                  (0xFFUL << CAN_RDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
7540 #define CAN_RDL1R_DATA2                      CAN_RDL1R_DATA2_Msk               /*!< Data byte 2 */
7541 #define CAN_RDL1R_DATA3_Pos                  (24U)
7542 #define CAN_RDL1R_DATA3_Msk                  (0xFFUL << CAN_RDL1R_DATA3_Pos)    /*!< 0xFF000000 */
7543 #define CAN_RDL1R_DATA3                      CAN_RDL1R_DATA3_Msk               /*!< Data byte 3 */
7544 
7545 /*******************  Bit definition for CAN_RDH1R register  ******************/
7546 #define CAN_RDH1R_DATA4_Pos                  (0U)
7547 #define CAN_RDH1R_DATA4_Msk                  (0xFFUL << CAN_RDH1R_DATA4_Pos)    /*!< 0x000000FF */
7548 #define CAN_RDH1R_DATA4                      CAN_RDH1R_DATA4_Msk               /*!< Data byte 4 */
7549 #define CAN_RDH1R_DATA5_Pos                  (8U)
7550 #define CAN_RDH1R_DATA5_Msk                  (0xFFUL << CAN_RDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
7551 #define CAN_RDH1R_DATA5                      CAN_RDH1R_DATA5_Msk               /*!< Data byte 5 */
7552 #define CAN_RDH1R_DATA6_Pos                  (16U)
7553 #define CAN_RDH1R_DATA6_Msk                  (0xFFUL << CAN_RDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
7554 #define CAN_RDH1R_DATA6                      CAN_RDH1R_DATA6_Msk               /*!< Data byte 6 */
7555 #define CAN_RDH1R_DATA7_Pos                  (24U)
7556 #define CAN_RDH1R_DATA7_Msk                  (0xFFUL << CAN_RDH1R_DATA7_Pos)    /*!< 0xFF000000 */
7557 #define CAN_RDH1R_DATA7                      CAN_RDH1R_DATA7_Msk               /*!< Data byte 7 */
7558 
7559 /*!< CAN filter registers */
7560 /*******************  Bit definition for CAN_FMR register  ********************/
7561 #define CAN_FMR_FINIT_Pos                    (0U)
7562 #define CAN_FMR_FINIT_Msk                    (0x1UL << CAN_FMR_FINIT_Pos)       /*!< 0x00000001 */
7563 #define CAN_FMR_FINIT                        CAN_FMR_FINIT_Msk                 /*!< Filter Init Mode */
7564 #define CAN_FMR_CAN2SB_Pos                   (8U)
7565 #define CAN_FMR_CAN2SB_Msk                   (0x3FUL << CAN_FMR_CAN2SB_Pos)     /*!< 0x00003F00 */
7566 #define CAN_FMR_CAN2SB                       CAN_FMR_CAN2SB_Msk                /*!< CAN2 start bank */
7567 
7568 /*******************  Bit definition for CAN_FM1R register  *******************/
7569 #define CAN_FM1R_FBM_Pos                     (0U)
7570 #define CAN_FM1R_FBM_Msk                     (0x3FFFUL << CAN_FM1R_FBM_Pos)     /*!< 0x00003FFF */
7571 #define CAN_FM1R_FBM                         CAN_FM1R_FBM_Msk                  /*!< Filter Mode */
7572 #define CAN_FM1R_FBM0_Pos                    (0U)
7573 #define CAN_FM1R_FBM0_Msk                    (0x1UL << CAN_FM1R_FBM0_Pos)       /*!< 0x00000001 */
7574 #define CAN_FM1R_FBM0                        CAN_FM1R_FBM0_Msk                 /*!< Filter Init Mode for filter 0 */
7575 #define CAN_FM1R_FBM1_Pos                    (1U)
7576 #define CAN_FM1R_FBM1_Msk                    (0x1UL << CAN_FM1R_FBM1_Pos)       /*!< 0x00000002 */
7577 #define CAN_FM1R_FBM1                        CAN_FM1R_FBM1_Msk                 /*!< Filter Init Mode for filter 1 */
7578 #define CAN_FM1R_FBM2_Pos                    (2U)
7579 #define CAN_FM1R_FBM2_Msk                    (0x1UL << CAN_FM1R_FBM2_Pos)       /*!< 0x00000004 */
7580 #define CAN_FM1R_FBM2                        CAN_FM1R_FBM2_Msk                 /*!< Filter Init Mode for filter 2 */
7581 #define CAN_FM1R_FBM3_Pos                    (3U)
7582 #define CAN_FM1R_FBM3_Msk                    (0x1UL << CAN_FM1R_FBM3_Pos)       /*!< 0x00000008 */
7583 #define CAN_FM1R_FBM3                        CAN_FM1R_FBM3_Msk                 /*!< Filter Init Mode for filter 3 */
7584 #define CAN_FM1R_FBM4_Pos                    (4U)
7585 #define CAN_FM1R_FBM4_Msk                    (0x1UL << CAN_FM1R_FBM4_Pos)       /*!< 0x00000010 */
7586 #define CAN_FM1R_FBM4                        CAN_FM1R_FBM4_Msk                 /*!< Filter Init Mode for filter 4 */
7587 #define CAN_FM1R_FBM5_Pos                    (5U)
7588 #define CAN_FM1R_FBM5_Msk                    (0x1UL << CAN_FM1R_FBM5_Pos)       /*!< 0x00000020 */
7589 #define CAN_FM1R_FBM5                        CAN_FM1R_FBM5_Msk                 /*!< Filter Init Mode for filter 5 */
7590 #define CAN_FM1R_FBM6_Pos                    (6U)
7591 #define CAN_FM1R_FBM6_Msk                    (0x1UL << CAN_FM1R_FBM6_Pos)       /*!< 0x00000040 */
7592 #define CAN_FM1R_FBM6                        CAN_FM1R_FBM6_Msk                 /*!< Filter Init Mode for filter 6 */
7593 #define CAN_FM1R_FBM7_Pos                    (7U)
7594 #define CAN_FM1R_FBM7_Msk                    (0x1UL << CAN_FM1R_FBM7_Pos)       /*!< 0x00000080 */
7595 #define CAN_FM1R_FBM7                        CAN_FM1R_FBM7_Msk                 /*!< Filter Init Mode for filter 7 */
7596 #define CAN_FM1R_FBM8_Pos                    (8U)
7597 #define CAN_FM1R_FBM8_Msk                    (0x1UL << CAN_FM1R_FBM8_Pos)       /*!< 0x00000100 */
7598 #define CAN_FM1R_FBM8                        CAN_FM1R_FBM8_Msk                 /*!< Filter Init Mode for filter 8 */
7599 #define CAN_FM1R_FBM9_Pos                    (9U)
7600 #define CAN_FM1R_FBM9_Msk                    (0x1UL << CAN_FM1R_FBM9_Pos)       /*!< 0x00000200 */
7601 #define CAN_FM1R_FBM9                        CAN_FM1R_FBM9_Msk                 /*!< Filter Init Mode for filter 9 */
7602 #define CAN_FM1R_FBM10_Pos                   (10U)
7603 #define CAN_FM1R_FBM10_Msk                   (0x1UL << CAN_FM1R_FBM10_Pos)      /*!< 0x00000400 */
7604 #define CAN_FM1R_FBM10                       CAN_FM1R_FBM10_Msk                /*!< Filter Init Mode for filter 10 */
7605 #define CAN_FM1R_FBM11_Pos                   (11U)
7606 #define CAN_FM1R_FBM11_Msk                   (0x1UL << CAN_FM1R_FBM11_Pos)      /*!< 0x00000800 */
7607 #define CAN_FM1R_FBM11                       CAN_FM1R_FBM11_Msk                /*!< Filter Init Mode for filter 11 */
7608 #define CAN_FM1R_FBM12_Pos                   (12U)
7609 #define CAN_FM1R_FBM12_Msk                   (0x1UL << CAN_FM1R_FBM12_Pos)      /*!< 0x00001000 */
7610 #define CAN_FM1R_FBM12                       CAN_FM1R_FBM12_Msk                /*!< Filter Init Mode for filter 12 */
7611 #define CAN_FM1R_FBM13_Pos                   (13U)
7612 #define CAN_FM1R_FBM13_Msk                   (0x1UL << CAN_FM1R_FBM13_Pos)      /*!< 0x00002000 */
7613 #define CAN_FM1R_FBM13                       CAN_FM1R_FBM13_Msk                /*!< Filter Init Mode for filter 13 */
7614 
7615 /*******************  Bit definition for CAN_FS1R register  *******************/
7616 #define CAN_FS1R_FSC_Pos                     (0U)
7617 #define CAN_FS1R_FSC_Msk                     (0x3FFFUL << CAN_FS1R_FSC_Pos)     /*!< 0x00003FFF */
7618 #define CAN_FS1R_FSC                         CAN_FS1R_FSC_Msk                  /*!< Filter Scale Configuration */
7619 #define CAN_FS1R_FSC0_Pos                    (0U)
7620 #define CAN_FS1R_FSC0_Msk                    (0x1UL << CAN_FS1R_FSC0_Pos)       /*!< 0x00000001 */
7621 #define CAN_FS1R_FSC0                        CAN_FS1R_FSC0_Msk                 /*!< Filter Scale Configuration for filter 0 */
7622 #define CAN_FS1R_FSC1_Pos                    (1U)
7623 #define CAN_FS1R_FSC1_Msk                    (0x1UL << CAN_FS1R_FSC1_Pos)       /*!< 0x00000002 */
7624 #define CAN_FS1R_FSC1                        CAN_FS1R_FSC1_Msk                 /*!< Filter Scale Configuration for filter 1 */
7625 #define CAN_FS1R_FSC2_Pos                    (2U)
7626 #define CAN_FS1R_FSC2_Msk                    (0x1UL << CAN_FS1R_FSC2_Pos)       /*!< 0x00000004 */
7627 #define CAN_FS1R_FSC2                        CAN_FS1R_FSC2_Msk                 /*!< Filter Scale Configuration for filter 2 */
7628 #define CAN_FS1R_FSC3_Pos                    (3U)
7629 #define CAN_FS1R_FSC3_Msk                    (0x1UL << CAN_FS1R_FSC3_Pos)       /*!< 0x00000008 */
7630 #define CAN_FS1R_FSC3                        CAN_FS1R_FSC3_Msk                 /*!< Filter Scale Configuration for filter 3 */
7631 #define CAN_FS1R_FSC4_Pos                    (4U)
7632 #define CAN_FS1R_FSC4_Msk                    (0x1UL << CAN_FS1R_FSC4_Pos)       /*!< 0x00000010 */
7633 #define CAN_FS1R_FSC4                        CAN_FS1R_FSC4_Msk                 /*!< Filter Scale Configuration for filter 4 */
7634 #define CAN_FS1R_FSC5_Pos                    (5U)
7635 #define CAN_FS1R_FSC5_Msk                    (0x1UL << CAN_FS1R_FSC5_Pos)       /*!< 0x00000020 */
7636 #define CAN_FS1R_FSC5                        CAN_FS1R_FSC5_Msk                 /*!< Filter Scale Configuration for filter 5 */
7637 #define CAN_FS1R_FSC6_Pos                    (6U)
7638 #define CAN_FS1R_FSC6_Msk                    (0x1UL << CAN_FS1R_FSC6_Pos)       /*!< 0x00000040 */
7639 #define CAN_FS1R_FSC6                        CAN_FS1R_FSC6_Msk                 /*!< Filter Scale Configuration for filter 6 */
7640 #define CAN_FS1R_FSC7_Pos                    (7U)
7641 #define CAN_FS1R_FSC7_Msk                    (0x1UL << CAN_FS1R_FSC7_Pos)       /*!< 0x00000080 */
7642 #define CAN_FS1R_FSC7                        CAN_FS1R_FSC7_Msk                 /*!< Filter Scale Configuration for filter 7 */
7643 #define CAN_FS1R_FSC8_Pos                    (8U)
7644 #define CAN_FS1R_FSC8_Msk                    (0x1UL << CAN_FS1R_FSC8_Pos)       /*!< 0x00000100 */
7645 #define CAN_FS1R_FSC8                        CAN_FS1R_FSC8_Msk                 /*!< Filter Scale Configuration for filter 8 */
7646 #define CAN_FS1R_FSC9_Pos                    (9U)
7647 #define CAN_FS1R_FSC9_Msk                    (0x1UL << CAN_FS1R_FSC9_Pos)       /*!< 0x00000200 */
7648 #define CAN_FS1R_FSC9                        CAN_FS1R_FSC9_Msk                 /*!< Filter Scale Configuration for filter 9 */
7649 #define CAN_FS1R_FSC10_Pos                   (10U)
7650 #define CAN_FS1R_FSC10_Msk                   (0x1UL << CAN_FS1R_FSC10_Pos)      /*!< 0x00000400 */
7651 #define CAN_FS1R_FSC10                       CAN_FS1R_FSC10_Msk                /*!< Filter Scale Configuration for filter 10 */
7652 #define CAN_FS1R_FSC11_Pos                   (11U)
7653 #define CAN_FS1R_FSC11_Msk                   (0x1UL << CAN_FS1R_FSC11_Pos)      /*!< 0x00000800 */
7654 #define CAN_FS1R_FSC11                       CAN_FS1R_FSC11_Msk                /*!< Filter Scale Configuration for filter 11 */
7655 #define CAN_FS1R_FSC12_Pos                   (12U)
7656 #define CAN_FS1R_FSC12_Msk                   (0x1UL << CAN_FS1R_FSC12_Pos)      /*!< 0x00001000 */
7657 #define CAN_FS1R_FSC12                       CAN_FS1R_FSC12_Msk                /*!< Filter Scale Configuration for filter 12 */
7658 #define CAN_FS1R_FSC13_Pos                   (13U)
7659 #define CAN_FS1R_FSC13_Msk                   (0x1UL << CAN_FS1R_FSC13_Pos)      /*!< 0x00002000 */
7660 #define CAN_FS1R_FSC13                       CAN_FS1R_FSC13_Msk                /*!< Filter Scale Configuration for filter 13 */
7661 
7662 /******************  Bit definition for CAN_FFA1R register  *******************/
7663 #define CAN_FFA1R_FFA_Pos                    (0U)
7664 #define CAN_FFA1R_FFA_Msk                    (0x3FFFUL << CAN_FFA1R_FFA_Pos)    /*!< 0x00003FFF */
7665 #define CAN_FFA1R_FFA                        CAN_FFA1R_FFA_Msk                 /*!< Filter FIFO Assignment */
7666 #define CAN_FFA1R_FFA0_Pos                   (0U)
7667 #define CAN_FFA1R_FFA0_Msk                   (0x1UL << CAN_FFA1R_FFA0_Pos)      /*!< 0x00000001 */
7668 #define CAN_FFA1R_FFA0                       CAN_FFA1R_FFA0_Msk                /*!< Filter FIFO Assignment for filter 0 */
7669 #define CAN_FFA1R_FFA1_Pos                   (1U)
7670 #define CAN_FFA1R_FFA1_Msk                   (0x1UL << CAN_FFA1R_FFA1_Pos)      /*!< 0x00000002 */
7671 #define CAN_FFA1R_FFA1                       CAN_FFA1R_FFA1_Msk                /*!< Filter FIFO Assignment for filter 1 */
7672 #define CAN_FFA1R_FFA2_Pos                   (2U)
7673 #define CAN_FFA1R_FFA2_Msk                   (0x1UL << CAN_FFA1R_FFA2_Pos)      /*!< 0x00000004 */
7674 #define CAN_FFA1R_FFA2                       CAN_FFA1R_FFA2_Msk                /*!< Filter FIFO Assignment for filter 2 */
7675 #define CAN_FFA1R_FFA3_Pos                   (3U)
7676 #define CAN_FFA1R_FFA3_Msk                   (0x1UL << CAN_FFA1R_FFA3_Pos)      /*!< 0x00000008 */
7677 #define CAN_FFA1R_FFA3                       CAN_FFA1R_FFA3_Msk                /*!< Filter FIFO Assignment for filter 3 */
7678 #define CAN_FFA1R_FFA4_Pos                   (4U)
7679 #define CAN_FFA1R_FFA4_Msk                   (0x1UL << CAN_FFA1R_FFA4_Pos)      /*!< 0x00000010 */
7680 #define CAN_FFA1R_FFA4                       CAN_FFA1R_FFA4_Msk                /*!< Filter FIFO Assignment for filter 4 */
7681 #define CAN_FFA1R_FFA5_Pos                   (5U)
7682 #define CAN_FFA1R_FFA5_Msk                   (0x1UL << CAN_FFA1R_FFA5_Pos)      /*!< 0x00000020 */
7683 #define CAN_FFA1R_FFA5                       CAN_FFA1R_FFA5_Msk                /*!< Filter FIFO Assignment for filter 5 */
7684 #define CAN_FFA1R_FFA6_Pos                   (6U)
7685 #define CAN_FFA1R_FFA6_Msk                   (0x1UL << CAN_FFA1R_FFA6_Pos)      /*!< 0x00000040 */
7686 #define CAN_FFA1R_FFA6                       CAN_FFA1R_FFA6_Msk                /*!< Filter FIFO Assignment for filter 6 */
7687 #define CAN_FFA1R_FFA7_Pos                   (7U)
7688 #define CAN_FFA1R_FFA7_Msk                   (0x1UL << CAN_FFA1R_FFA7_Pos)      /*!< 0x00000080 */
7689 #define CAN_FFA1R_FFA7                       CAN_FFA1R_FFA7_Msk                /*!< Filter FIFO Assignment for filter 7 */
7690 #define CAN_FFA1R_FFA8_Pos                   (8U)
7691 #define CAN_FFA1R_FFA8_Msk                   (0x1UL << CAN_FFA1R_FFA8_Pos)      /*!< 0x00000100 */
7692 #define CAN_FFA1R_FFA8                       CAN_FFA1R_FFA8_Msk                /*!< Filter FIFO Assignment for filter 8 */
7693 #define CAN_FFA1R_FFA9_Pos                   (9U)
7694 #define CAN_FFA1R_FFA9_Msk                   (0x1UL << CAN_FFA1R_FFA9_Pos)      /*!< 0x00000200 */
7695 #define CAN_FFA1R_FFA9                       CAN_FFA1R_FFA9_Msk                /*!< Filter FIFO Assignment for filter 9 */
7696 #define CAN_FFA1R_FFA10_Pos                  (10U)
7697 #define CAN_FFA1R_FFA10_Msk                  (0x1UL << CAN_FFA1R_FFA10_Pos)     /*!< 0x00000400 */
7698 #define CAN_FFA1R_FFA10                      CAN_FFA1R_FFA10_Msk               /*!< Filter FIFO Assignment for filter 10 */
7699 #define CAN_FFA1R_FFA11_Pos                  (11U)
7700 #define CAN_FFA1R_FFA11_Msk                  (0x1UL << CAN_FFA1R_FFA11_Pos)     /*!< 0x00000800 */
7701 #define CAN_FFA1R_FFA11                      CAN_FFA1R_FFA11_Msk               /*!< Filter FIFO Assignment for filter 11 */
7702 #define CAN_FFA1R_FFA12_Pos                  (12U)
7703 #define CAN_FFA1R_FFA12_Msk                  (0x1UL << CAN_FFA1R_FFA12_Pos)     /*!< 0x00001000 */
7704 #define CAN_FFA1R_FFA12                      CAN_FFA1R_FFA12_Msk               /*!< Filter FIFO Assignment for filter 12 */
7705 #define CAN_FFA1R_FFA13_Pos                  (13U)
7706 #define CAN_FFA1R_FFA13_Msk                  (0x1UL << CAN_FFA1R_FFA13_Pos)     /*!< 0x00002000 */
7707 #define CAN_FFA1R_FFA13                      CAN_FFA1R_FFA13_Msk               /*!< Filter FIFO Assignment for filter 13 */
7708 
7709 /*******************  Bit definition for CAN_FA1R register  *******************/
7710 #define CAN_FA1R_FACT_Pos                    (0U)
7711 #define CAN_FA1R_FACT_Msk                    (0x3FFFUL << CAN_FA1R_FACT_Pos)    /*!< 0x00003FFF */
7712 #define CAN_FA1R_FACT                        CAN_FA1R_FACT_Msk                 /*!< Filter Active */
7713 #define CAN_FA1R_FACT0_Pos                   (0U)
7714 #define CAN_FA1R_FACT0_Msk                   (0x1UL << CAN_FA1R_FACT0_Pos)      /*!< 0x00000001 */
7715 #define CAN_FA1R_FACT0                       CAN_FA1R_FACT0_Msk                /*!< Filter 0 Active */
7716 #define CAN_FA1R_FACT1_Pos                   (1U)
7717 #define CAN_FA1R_FACT1_Msk                   (0x1UL << CAN_FA1R_FACT1_Pos)      /*!< 0x00000002 */
7718 #define CAN_FA1R_FACT1                       CAN_FA1R_FACT1_Msk                /*!< Filter 1 Active */
7719 #define CAN_FA1R_FACT2_Pos                   (2U)
7720 #define CAN_FA1R_FACT2_Msk                   (0x1UL << CAN_FA1R_FACT2_Pos)      /*!< 0x00000004 */
7721 #define CAN_FA1R_FACT2                       CAN_FA1R_FACT2_Msk                /*!< Filter 2 Active */
7722 #define CAN_FA1R_FACT3_Pos                   (3U)
7723 #define CAN_FA1R_FACT3_Msk                   (0x1UL << CAN_FA1R_FACT3_Pos)      /*!< 0x00000008 */
7724 #define CAN_FA1R_FACT3                       CAN_FA1R_FACT3_Msk                /*!< Filter 3 Active */
7725 #define CAN_FA1R_FACT4_Pos                   (4U)
7726 #define CAN_FA1R_FACT4_Msk                   (0x1UL << CAN_FA1R_FACT4_Pos)      /*!< 0x00000010 */
7727 #define CAN_FA1R_FACT4                       CAN_FA1R_FACT4_Msk                /*!< Filter 4 Active */
7728 #define CAN_FA1R_FACT5_Pos                   (5U)
7729 #define CAN_FA1R_FACT5_Msk                   (0x1UL << CAN_FA1R_FACT5_Pos)      /*!< 0x00000020 */
7730 #define CAN_FA1R_FACT5                       CAN_FA1R_FACT5_Msk                /*!< Filter 5 Active */
7731 #define CAN_FA1R_FACT6_Pos                   (6U)
7732 #define CAN_FA1R_FACT6_Msk                   (0x1UL << CAN_FA1R_FACT6_Pos)      /*!< 0x00000040 */
7733 #define CAN_FA1R_FACT6                       CAN_FA1R_FACT6_Msk                /*!< Filter 6 Active */
7734 #define CAN_FA1R_FACT7_Pos                   (7U)
7735 #define CAN_FA1R_FACT7_Msk                   (0x1UL << CAN_FA1R_FACT7_Pos)      /*!< 0x00000080 */
7736 #define CAN_FA1R_FACT7                       CAN_FA1R_FACT7_Msk                /*!< Filter 7 Active */
7737 #define CAN_FA1R_FACT8_Pos                   (8U)
7738 #define CAN_FA1R_FACT8_Msk                   (0x1UL << CAN_FA1R_FACT8_Pos)      /*!< 0x00000100 */
7739 #define CAN_FA1R_FACT8                       CAN_FA1R_FACT8_Msk                /*!< Filter 8 Active */
7740 #define CAN_FA1R_FACT9_Pos                   (9U)
7741 #define CAN_FA1R_FACT9_Msk                   (0x1UL << CAN_FA1R_FACT9_Pos)      /*!< 0x00000200 */
7742 #define CAN_FA1R_FACT9                       CAN_FA1R_FACT9_Msk                /*!< Filter 9 Active */
7743 #define CAN_FA1R_FACT10_Pos                  (10U)
7744 #define CAN_FA1R_FACT10_Msk                  (0x1UL << CAN_FA1R_FACT10_Pos)     /*!< 0x00000400 */
7745 #define CAN_FA1R_FACT10                      CAN_FA1R_FACT10_Msk               /*!< Filter 10 Active */
7746 #define CAN_FA1R_FACT11_Pos                  (11U)
7747 #define CAN_FA1R_FACT11_Msk                  (0x1UL << CAN_FA1R_FACT11_Pos)     /*!< 0x00000800 */
7748 #define CAN_FA1R_FACT11                      CAN_FA1R_FACT11_Msk               /*!< Filter 11 Active */
7749 #define CAN_FA1R_FACT12_Pos                  (12U)
7750 #define CAN_FA1R_FACT12_Msk                  (0x1UL << CAN_FA1R_FACT12_Pos)     /*!< 0x00001000 */
7751 #define CAN_FA1R_FACT12                      CAN_FA1R_FACT12_Msk               /*!< Filter 12 Active */
7752 #define CAN_FA1R_FACT13_Pos                  (13U)
7753 #define CAN_FA1R_FACT13_Msk                  (0x1UL << CAN_FA1R_FACT13_Pos)     /*!< 0x00002000 */
7754 #define CAN_FA1R_FACT13                      CAN_FA1R_FACT13_Msk               /*!< Filter 13 Active */
7755 
7756 /*******************  Bit definition for CAN_F0R1 register  *******************/
7757 #define CAN_F0R1_FB0_Pos                     (0U)
7758 #define CAN_F0R1_FB0_Msk                     (0x1UL << CAN_F0R1_FB0_Pos)        /*!< 0x00000001 */
7759 #define CAN_F0R1_FB0                         CAN_F0R1_FB0_Msk                  /*!< Filter bit 0 */
7760 #define CAN_F0R1_FB1_Pos                     (1U)
7761 #define CAN_F0R1_FB1_Msk                     (0x1UL << CAN_F0R1_FB1_Pos)        /*!< 0x00000002 */
7762 #define CAN_F0R1_FB1                         CAN_F0R1_FB1_Msk                  /*!< Filter bit 1 */
7763 #define CAN_F0R1_FB2_Pos                     (2U)
7764 #define CAN_F0R1_FB2_Msk                     (0x1UL << CAN_F0R1_FB2_Pos)        /*!< 0x00000004 */
7765 #define CAN_F0R1_FB2                         CAN_F0R1_FB2_Msk                  /*!< Filter bit 2 */
7766 #define CAN_F0R1_FB3_Pos                     (3U)
7767 #define CAN_F0R1_FB3_Msk                     (0x1UL << CAN_F0R1_FB3_Pos)        /*!< 0x00000008 */
7768 #define CAN_F0R1_FB3                         CAN_F0R1_FB3_Msk                  /*!< Filter bit 3 */
7769 #define CAN_F0R1_FB4_Pos                     (4U)
7770 #define CAN_F0R1_FB4_Msk                     (0x1UL << CAN_F0R1_FB4_Pos)        /*!< 0x00000010 */
7771 #define CAN_F0R1_FB4                         CAN_F0R1_FB4_Msk                  /*!< Filter bit 4 */
7772 #define CAN_F0R1_FB5_Pos                     (5U)
7773 #define CAN_F0R1_FB5_Msk                     (0x1UL << CAN_F0R1_FB5_Pos)        /*!< 0x00000020 */
7774 #define CAN_F0R1_FB5                         CAN_F0R1_FB5_Msk                  /*!< Filter bit 5 */
7775 #define CAN_F0R1_FB6_Pos                     (6U)
7776 #define CAN_F0R1_FB6_Msk                     (0x1UL << CAN_F0R1_FB6_Pos)        /*!< 0x00000040 */
7777 #define CAN_F0R1_FB6                         CAN_F0R1_FB6_Msk                  /*!< Filter bit 6 */
7778 #define CAN_F0R1_FB7_Pos                     (7U)
7779 #define CAN_F0R1_FB7_Msk                     (0x1UL << CAN_F0R1_FB7_Pos)        /*!< 0x00000080 */
7780 #define CAN_F0R1_FB7                         CAN_F0R1_FB7_Msk                  /*!< Filter bit 7 */
7781 #define CAN_F0R1_FB8_Pos                     (8U)
7782 #define CAN_F0R1_FB8_Msk                     (0x1UL << CAN_F0R1_FB8_Pos)        /*!< 0x00000100 */
7783 #define CAN_F0R1_FB8                         CAN_F0R1_FB8_Msk                  /*!< Filter bit 8 */
7784 #define CAN_F0R1_FB9_Pos                     (9U)
7785 #define CAN_F0R1_FB9_Msk                     (0x1UL << CAN_F0R1_FB9_Pos)        /*!< 0x00000200 */
7786 #define CAN_F0R1_FB9                         CAN_F0R1_FB9_Msk                  /*!< Filter bit 9 */
7787 #define CAN_F0R1_FB10_Pos                    (10U)
7788 #define CAN_F0R1_FB10_Msk                    (0x1UL << CAN_F0R1_FB10_Pos)       /*!< 0x00000400 */
7789 #define CAN_F0R1_FB10                        CAN_F0R1_FB10_Msk                 /*!< Filter bit 10 */
7790 #define CAN_F0R1_FB11_Pos                    (11U)
7791 #define CAN_F0R1_FB11_Msk                    (0x1UL << CAN_F0R1_FB11_Pos)       /*!< 0x00000800 */
7792 #define CAN_F0R1_FB11                        CAN_F0R1_FB11_Msk                 /*!< Filter bit 11 */
7793 #define CAN_F0R1_FB12_Pos                    (12U)
7794 #define CAN_F0R1_FB12_Msk                    (0x1UL << CAN_F0R1_FB12_Pos)       /*!< 0x00001000 */
7795 #define CAN_F0R1_FB12                        CAN_F0R1_FB12_Msk                 /*!< Filter bit 12 */
7796 #define CAN_F0R1_FB13_Pos                    (13U)
7797 #define CAN_F0R1_FB13_Msk                    (0x1UL << CAN_F0R1_FB13_Pos)       /*!< 0x00002000 */
7798 #define CAN_F0R1_FB13                        CAN_F0R1_FB13_Msk                 /*!< Filter bit 13 */
7799 #define CAN_F0R1_FB14_Pos                    (14U)
7800 #define CAN_F0R1_FB14_Msk                    (0x1UL << CAN_F0R1_FB14_Pos)       /*!< 0x00004000 */
7801 #define CAN_F0R1_FB14                        CAN_F0R1_FB14_Msk                 /*!< Filter bit 14 */
7802 #define CAN_F0R1_FB15_Pos                    (15U)
7803 #define CAN_F0R1_FB15_Msk                    (0x1UL << CAN_F0R1_FB15_Pos)       /*!< 0x00008000 */
7804 #define CAN_F0R1_FB15                        CAN_F0R1_FB15_Msk                 /*!< Filter bit 15 */
7805 #define CAN_F0R1_FB16_Pos                    (16U)
7806 #define CAN_F0R1_FB16_Msk                    (0x1UL << CAN_F0R1_FB16_Pos)       /*!< 0x00010000 */
7807 #define CAN_F0R1_FB16                        CAN_F0R1_FB16_Msk                 /*!< Filter bit 16 */
7808 #define CAN_F0R1_FB17_Pos                    (17U)
7809 #define CAN_F0R1_FB17_Msk                    (0x1UL << CAN_F0R1_FB17_Pos)       /*!< 0x00020000 */
7810 #define CAN_F0R1_FB17                        CAN_F0R1_FB17_Msk                 /*!< Filter bit 17 */
7811 #define CAN_F0R1_FB18_Pos                    (18U)
7812 #define CAN_F0R1_FB18_Msk                    (0x1UL << CAN_F0R1_FB18_Pos)       /*!< 0x00040000 */
7813 #define CAN_F0R1_FB18                        CAN_F0R1_FB18_Msk                 /*!< Filter bit 18 */
7814 #define CAN_F0R1_FB19_Pos                    (19U)
7815 #define CAN_F0R1_FB19_Msk                    (0x1UL << CAN_F0R1_FB19_Pos)       /*!< 0x00080000 */
7816 #define CAN_F0R1_FB19                        CAN_F0R1_FB19_Msk                 /*!< Filter bit 19 */
7817 #define CAN_F0R1_FB20_Pos                    (20U)
7818 #define CAN_F0R1_FB20_Msk                    (0x1UL << CAN_F0R1_FB20_Pos)       /*!< 0x00100000 */
7819 #define CAN_F0R1_FB20                        CAN_F0R1_FB20_Msk                 /*!< Filter bit 20 */
7820 #define CAN_F0R1_FB21_Pos                    (21U)
7821 #define CAN_F0R1_FB21_Msk                    (0x1UL << CAN_F0R1_FB21_Pos)       /*!< 0x00200000 */
7822 #define CAN_F0R1_FB21                        CAN_F0R1_FB21_Msk                 /*!< Filter bit 21 */
7823 #define CAN_F0R1_FB22_Pos                    (22U)
7824 #define CAN_F0R1_FB22_Msk                    (0x1UL << CAN_F0R1_FB22_Pos)       /*!< 0x00400000 */
7825 #define CAN_F0R1_FB22                        CAN_F0R1_FB22_Msk                 /*!< Filter bit 22 */
7826 #define CAN_F0R1_FB23_Pos                    (23U)
7827 #define CAN_F0R1_FB23_Msk                    (0x1UL << CAN_F0R1_FB23_Pos)       /*!< 0x00800000 */
7828 #define CAN_F0R1_FB23                        CAN_F0R1_FB23_Msk                 /*!< Filter bit 23 */
7829 #define CAN_F0R1_FB24_Pos                    (24U)
7830 #define CAN_F0R1_FB24_Msk                    (0x1UL << CAN_F0R1_FB24_Pos)       /*!< 0x01000000 */
7831 #define CAN_F0R1_FB24                        CAN_F0R1_FB24_Msk                 /*!< Filter bit 24 */
7832 #define CAN_F0R1_FB25_Pos                    (25U)
7833 #define CAN_F0R1_FB25_Msk                    (0x1UL << CAN_F0R1_FB25_Pos)       /*!< 0x02000000 */
7834 #define CAN_F0R1_FB25                        CAN_F0R1_FB25_Msk                 /*!< Filter bit 25 */
7835 #define CAN_F0R1_FB26_Pos                    (26U)
7836 #define CAN_F0R1_FB26_Msk                    (0x1UL << CAN_F0R1_FB26_Pos)       /*!< 0x04000000 */
7837 #define CAN_F0R1_FB26                        CAN_F0R1_FB26_Msk                 /*!< Filter bit 26 */
7838 #define CAN_F0R1_FB27_Pos                    (27U)
7839 #define CAN_F0R1_FB27_Msk                    (0x1UL << CAN_F0R1_FB27_Pos)       /*!< 0x08000000 */
7840 #define CAN_F0R1_FB27                        CAN_F0R1_FB27_Msk                 /*!< Filter bit 27 */
7841 #define CAN_F0R1_FB28_Pos                    (28U)
7842 #define CAN_F0R1_FB28_Msk                    (0x1UL << CAN_F0R1_FB28_Pos)       /*!< 0x10000000 */
7843 #define CAN_F0R1_FB28                        CAN_F0R1_FB28_Msk                 /*!< Filter bit 28 */
7844 #define CAN_F0R1_FB29_Pos                    (29U)
7845 #define CAN_F0R1_FB29_Msk                    (0x1UL << CAN_F0R1_FB29_Pos)       /*!< 0x20000000 */
7846 #define CAN_F0R1_FB29                        CAN_F0R1_FB29_Msk                 /*!< Filter bit 29 */
7847 #define CAN_F0R1_FB30_Pos                    (30U)
7848 #define CAN_F0R1_FB30_Msk                    (0x1UL << CAN_F0R1_FB30_Pos)       /*!< 0x40000000 */
7849 #define CAN_F0R1_FB30                        CAN_F0R1_FB30_Msk                 /*!< Filter bit 30 */
7850 #define CAN_F0R1_FB31_Pos                    (31U)
7851 #define CAN_F0R1_FB31_Msk                    (0x1UL << CAN_F0R1_FB31_Pos)       /*!< 0x80000000 */
7852 #define CAN_F0R1_FB31                        CAN_F0R1_FB31_Msk                 /*!< Filter bit 31 */
7853 
7854 /*******************  Bit definition for CAN_F1R1 register  *******************/
7855 #define CAN_F1R1_FB0_Pos                     (0U)
7856 #define CAN_F1R1_FB0_Msk                     (0x1UL << CAN_F1R1_FB0_Pos)        /*!< 0x00000001 */
7857 #define CAN_F1R1_FB0                         CAN_F1R1_FB0_Msk                  /*!< Filter bit 0 */
7858 #define CAN_F1R1_FB1_Pos                     (1U)
7859 #define CAN_F1R1_FB1_Msk                     (0x1UL << CAN_F1R1_FB1_Pos)        /*!< 0x00000002 */
7860 #define CAN_F1R1_FB1                         CAN_F1R1_FB1_Msk                  /*!< Filter bit 1 */
7861 #define CAN_F1R1_FB2_Pos                     (2U)
7862 #define CAN_F1R1_FB2_Msk                     (0x1UL << CAN_F1R1_FB2_Pos)        /*!< 0x00000004 */
7863 #define CAN_F1R1_FB2                         CAN_F1R1_FB2_Msk                  /*!< Filter bit 2 */
7864 #define CAN_F1R1_FB3_Pos                     (3U)
7865 #define CAN_F1R1_FB3_Msk                     (0x1UL << CAN_F1R1_FB3_Pos)        /*!< 0x00000008 */
7866 #define CAN_F1R1_FB3                         CAN_F1R1_FB3_Msk                  /*!< Filter bit 3 */
7867 #define CAN_F1R1_FB4_Pos                     (4U)
7868 #define CAN_F1R1_FB4_Msk                     (0x1UL << CAN_F1R1_FB4_Pos)        /*!< 0x00000010 */
7869 #define CAN_F1R1_FB4                         CAN_F1R1_FB4_Msk                  /*!< Filter bit 4 */
7870 #define CAN_F1R1_FB5_Pos                     (5U)
7871 #define CAN_F1R1_FB5_Msk                     (0x1UL << CAN_F1R1_FB5_Pos)        /*!< 0x00000020 */
7872 #define CAN_F1R1_FB5                         CAN_F1R1_FB5_Msk                  /*!< Filter bit 5 */
7873 #define CAN_F1R1_FB6_Pos                     (6U)
7874 #define CAN_F1R1_FB6_Msk                     (0x1UL << CAN_F1R1_FB6_Pos)        /*!< 0x00000040 */
7875 #define CAN_F1R1_FB6                         CAN_F1R1_FB6_Msk                  /*!< Filter bit 6 */
7876 #define CAN_F1R1_FB7_Pos                     (7U)
7877 #define CAN_F1R1_FB7_Msk                     (0x1UL << CAN_F1R1_FB7_Pos)        /*!< 0x00000080 */
7878 #define CAN_F1R1_FB7                         CAN_F1R1_FB7_Msk                  /*!< Filter bit 7 */
7879 #define CAN_F1R1_FB8_Pos                     (8U)
7880 #define CAN_F1R1_FB8_Msk                     (0x1UL << CAN_F1R1_FB8_Pos)        /*!< 0x00000100 */
7881 #define CAN_F1R1_FB8                         CAN_F1R1_FB8_Msk                  /*!< Filter bit 8 */
7882 #define CAN_F1R1_FB9_Pos                     (9U)
7883 #define CAN_F1R1_FB9_Msk                     (0x1UL << CAN_F1R1_FB9_Pos)        /*!< 0x00000200 */
7884 #define CAN_F1R1_FB9                         CAN_F1R1_FB9_Msk                  /*!< Filter bit 9 */
7885 #define CAN_F1R1_FB10_Pos                    (10U)
7886 #define CAN_F1R1_FB10_Msk                    (0x1UL << CAN_F1R1_FB10_Pos)       /*!< 0x00000400 */
7887 #define CAN_F1R1_FB10                        CAN_F1R1_FB10_Msk                 /*!< Filter bit 10 */
7888 #define CAN_F1R1_FB11_Pos                    (11U)
7889 #define CAN_F1R1_FB11_Msk                    (0x1UL << CAN_F1R1_FB11_Pos)       /*!< 0x00000800 */
7890 #define CAN_F1R1_FB11                        CAN_F1R1_FB11_Msk                 /*!< Filter bit 11 */
7891 #define CAN_F1R1_FB12_Pos                    (12U)
7892 #define CAN_F1R1_FB12_Msk                    (0x1UL << CAN_F1R1_FB12_Pos)       /*!< 0x00001000 */
7893 #define CAN_F1R1_FB12                        CAN_F1R1_FB12_Msk                 /*!< Filter bit 12 */
7894 #define CAN_F1R1_FB13_Pos                    (13U)
7895 #define CAN_F1R1_FB13_Msk                    (0x1UL << CAN_F1R1_FB13_Pos)       /*!< 0x00002000 */
7896 #define CAN_F1R1_FB13                        CAN_F1R1_FB13_Msk                 /*!< Filter bit 13 */
7897 #define CAN_F1R1_FB14_Pos                    (14U)
7898 #define CAN_F1R1_FB14_Msk                    (0x1UL << CAN_F1R1_FB14_Pos)       /*!< 0x00004000 */
7899 #define CAN_F1R1_FB14                        CAN_F1R1_FB14_Msk                 /*!< Filter bit 14 */
7900 #define CAN_F1R1_FB15_Pos                    (15U)
7901 #define CAN_F1R1_FB15_Msk                    (0x1UL << CAN_F1R1_FB15_Pos)       /*!< 0x00008000 */
7902 #define CAN_F1R1_FB15                        CAN_F1R1_FB15_Msk                 /*!< Filter bit 15 */
7903 #define CAN_F1R1_FB16_Pos                    (16U)
7904 #define CAN_F1R1_FB16_Msk                    (0x1UL << CAN_F1R1_FB16_Pos)       /*!< 0x00010000 */
7905 #define CAN_F1R1_FB16                        CAN_F1R1_FB16_Msk                 /*!< Filter bit 16 */
7906 #define CAN_F1R1_FB17_Pos                    (17U)
7907 #define CAN_F1R1_FB17_Msk                    (0x1UL << CAN_F1R1_FB17_Pos)       /*!< 0x00020000 */
7908 #define CAN_F1R1_FB17                        CAN_F1R1_FB17_Msk                 /*!< Filter bit 17 */
7909 #define CAN_F1R1_FB18_Pos                    (18U)
7910 #define CAN_F1R1_FB18_Msk                    (0x1UL << CAN_F1R1_FB18_Pos)       /*!< 0x00040000 */
7911 #define CAN_F1R1_FB18                        CAN_F1R1_FB18_Msk                 /*!< Filter bit 18 */
7912 #define CAN_F1R1_FB19_Pos                    (19U)
7913 #define CAN_F1R1_FB19_Msk                    (0x1UL << CAN_F1R1_FB19_Pos)       /*!< 0x00080000 */
7914 #define CAN_F1R1_FB19                        CAN_F1R1_FB19_Msk                 /*!< Filter bit 19 */
7915 #define CAN_F1R1_FB20_Pos                    (20U)
7916 #define CAN_F1R1_FB20_Msk                    (0x1UL << CAN_F1R1_FB20_Pos)       /*!< 0x00100000 */
7917 #define CAN_F1R1_FB20                        CAN_F1R1_FB20_Msk                 /*!< Filter bit 20 */
7918 #define CAN_F1R1_FB21_Pos                    (21U)
7919 #define CAN_F1R1_FB21_Msk                    (0x1UL << CAN_F1R1_FB21_Pos)       /*!< 0x00200000 */
7920 #define CAN_F1R1_FB21                        CAN_F1R1_FB21_Msk                 /*!< Filter bit 21 */
7921 #define CAN_F1R1_FB22_Pos                    (22U)
7922 #define CAN_F1R1_FB22_Msk                    (0x1UL << CAN_F1R1_FB22_Pos)       /*!< 0x00400000 */
7923 #define CAN_F1R1_FB22                        CAN_F1R1_FB22_Msk                 /*!< Filter bit 22 */
7924 #define CAN_F1R1_FB23_Pos                    (23U)
7925 #define CAN_F1R1_FB23_Msk                    (0x1UL << CAN_F1R1_FB23_Pos)       /*!< 0x00800000 */
7926 #define CAN_F1R1_FB23                        CAN_F1R1_FB23_Msk                 /*!< Filter bit 23 */
7927 #define CAN_F1R1_FB24_Pos                    (24U)
7928 #define CAN_F1R1_FB24_Msk                    (0x1UL << CAN_F1R1_FB24_Pos)       /*!< 0x01000000 */
7929 #define CAN_F1R1_FB24                        CAN_F1R1_FB24_Msk                 /*!< Filter bit 24 */
7930 #define CAN_F1R1_FB25_Pos                    (25U)
7931 #define CAN_F1R1_FB25_Msk                    (0x1UL << CAN_F1R1_FB25_Pos)       /*!< 0x02000000 */
7932 #define CAN_F1R1_FB25                        CAN_F1R1_FB25_Msk                 /*!< Filter bit 25 */
7933 #define CAN_F1R1_FB26_Pos                    (26U)
7934 #define CAN_F1R1_FB26_Msk                    (0x1UL << CAN_F1R1_FB26_Pos)       /*!< 0x04000000 */
7935 #define CAN_F1R1_FB26                        CAN_F1R1_FB26_Msk                 /*!< Filter bit 26 */
7936 #define CAN_F1R1_FB27_Pos                    (27U)
7937 #define CAN_F1R1_FB27_Msk                    (0x1UL << CAN_F1R1_FB27_Pos)       /*!< 0x08000000 */
7938 #define CAN_F1R1_FB27                        CAN_F1R1_FB27_Msk                 /*!< Filter bit 27 */
7939 #define CAN_F1R1_FB28_Pos                    (28U)
7940 #define CAN_F1R1_FB28_Msk                    (0x1UL << CAN_F1R1_FB28_Pos)       /*!< 0x10000000 */
7941 #define CAN_F1R1_FB28                        CAN_F1R1_FB28_Msk                 /*!< Filter bit 28 */
7942 #define CAN_F1R1_FB29_Pos                    (29U)
7943 #define CAN_F1R1_FB29_Msk                    (0x1UL << CAN_F1R1_FB29_Pos)       /*!< 0x20000000 */
7944 #define CAN_F1R1_FB29                        CAN_F1R1_FB29_Msk                 /*!< Filter bit 29 */
7945 #define CAN_F1R1_FB30_Pos                    (30U)
7946 #define CAN_F1R1_FB30_Msk                    (0x1UL << CAN_F1R1_FB30_Pos)       /*!< 0x40000000 */
7947 #define CAN_F1R1_FB30                        CAN_F1R1_FB30_Msk                 /*!< Filter bit 30 */
7948 #define CAN_F1R1_FB31_Pos                    (31U)
7949 #define CAN_F1R1_FB31_Msk                    (0x1UL << CAN_F1R1_FB31_Pos)       /*!< 0x80000000 */
7950 #define CAN_F1R1_FB31                        CAN_F1R1_FB31_Msk                 /*!< Filter bit 31 */
7951 
7952 /*******************  Bit definition for CAN_F2R1 register  *******************/
7953 #define CAN_F2R1_FB0_Pos                     (0U)
7954 #define CAN_F2R1_FB0_Msk                     (0x1UL << CAN_F2R1_FB0_Pos)        /*!< 0x00000001 */
7955 #define CAN_F2R1_FB0                         CAN_F2R1_FB0_Msk                  /*!< Filter bit 0 */
7956 #define CAN_F2R1_FB1_Pos                     (1U)
7957 #define CAN_F2R1_FB1_Msk                     (0x1UL << CAN_F2R1_FB1_Pos)        /*!< 0x00000002 */
7958 #define CAN_F2R1_FB1                         CAN_F2R1_FB1_Msk                  /*!< Filter bit 1 */
7959 #define CAN_F2R1_FB2_Pos                     (2U)
7960 #define CAN_F2R1_FB2_Msk                     (0x1UL << CAN_F2R1_FB2_Pos)        /*!< 0x00000004 */
7961 #define CAN_F2R1_FB2                         CAN_F2R1_FB2_Msk                  /*!< Filter bit 2 */
7962 #define CAN_F2R1_FB3_Pos                     (3U)
7963 #define CAN_F2R1_FB3_Msk                     (0x1UL << CAN_F2R1_FB3_Pos)        /*!< 0x00000008 */
7964 #define CAN_F2R1_FB3                         CAN_F2R1_FB3_Msk                  /*!< Filter bit 3 */
7965 #define CAN_F2R1_FB4_Pos                     (4U)
7966 #define CAN_F2R1_FB4_Msk                     (0x1UL << CAN_F2R1_FB4_Pos)        /*!< 0x00000010 */
7967 #define CAN_F2R1_FB4                         CAN_F2R1_FB4_Msk                  /*!< Filter bit 4 */
7968 #define CAN_F2R1_FB5_Pos                     (5U)
7969 #define CAN_F2R1_FB5_Msk                     (0x1UL << CAN_F2R1_FB5_Pos)        /*!< 0x00000020 */
7970 #define CAN_F2R1_FB5                         CAN_F2R1_FB5_Msk                  /*!< Filter bit 5 */
7971 #define CAN_F2R1_FB6_Pos                     (6U)
7972 #define CAN_F2R1_FB6_Msk                     (0x1UL << CAN_F2R1_FB6_Pos)        /*!< 0x00000040 */
7973 #define CAN_F2R1_FB6                         CAN_F2R1_FB6_Msk                  /*!< Filter bit 6 */
7974 #define CAN_F2R1_FB7_Pos                     (7U)
7975 #define CAN_F2R1_FB7_Msk                     (0x1UL << CAN_F2R1_FB7_Pos)        /*!< 0x00000080 */
7976 #define CAN_F2R1_FB7                         CAN_F2R1_FB7_Msk                  /*!< Filter bit 7 */
7977 #define CAN_F2R1_FB8_Pos                     (8U)
7978 #define CAN_F2R1_FB8_Msk                     (0x1UL << CAN_F2R1_FB8_Pos)        /*!< 0x00000100 */
7979 #define CAN_F2R1_FB8                         CAN_F2R1_FB8_Msk                  /*!< Filter bit 8 */
7980 #define CAN_F2R1_FB9_Pos                     (9U)
7981 #define CAN_F2R1_FB9_Msk                     (0x1UL << CAN_F2R1_FB9_Pos)        /*!< 0x00000200 */
7982 #define CAN_F2R1_FB9                         CAN_F2R1_FB9_Msk                  /*!< Filter bit 9 */
7983 #define CAN_F2R1_FB10_Pos                    (10U)
7984 #define CAN_F2R1_FB10_Msk                    (0x1UL << CAN_F2R1_FB10_Pos)       /*!< 0x00000400 */
7985 #define CAN_F2R1_FB10                        CAN_F2R1_FB10_Msk                 /*!< Filter bit 10 */
7986 #define CAN_F2R1_FB11_Pos                    (11U)
7987 #define CAN_F2R1_FB11_Msk                    (0x1UL << CAN_F2R1_FB11_Pos)       /*!< 0x00000800 */
7988 #define CAN_F2R1_FB11                        CAN_F2R1_FB11_Msk                 /*!< Filter bit 11 */
7989 #define CAN_F2R1_FB12_Pos                    (12U)
7990 #define CAN_F2R1_FB12_Msk                    (0x1UL << CAN_F2R1_FB12_Pos)       /*!< 0x00001000 */
7991 #define CAN_F2R1_FB12                        CAN_F2R1_FB12_Msk                 /*!< Filter bit 12 */
7992 #define CAN_F2R1_FB13_Pos                    (13U)
7993 #define CAN_F2R1_FB13_Msk                    (0x1UL << CAN_F2R1_FB13_Pos)       /*!< 0x00002000 */
7994 #define CAN_F2R1_FB13                        CAN_F2R1_FB13_Msk                 /*!< Filter bit 13 */
7995 #define CAN_F2R1_FB14_Pos                    (14U)
7996 #define CAN_F2R1_FB14_Msk                    (0x1UL << CAN_F2R1_FB14_Pos)       /*!< 0x00004000 */
7997 #define CAN_F2R1_FB14                        CAN_F2R1_FB14_Msk                 /*!< Filter bit 14 */
7998 #define CAN_F2R1_FB15_Pos                    (15U)
7999 #define CAN_F2R1_FB15_Msk                    (0x1UL << CAN_F2R1_FB15_Pos)       /*!< 0x00008000 */
8000 #define CAN_F2R1_FB15                        CAN_F2R1_FB15_Msk                 /*!< Filter bit 15 */
8001 #define CAN_F2R1_FB16_Pos                    (16U)
8002 #define CAN_F2R1_FB16_Msk                    (0x1UL << CAN_F2R1_FB16_Pos)       /*!< 0x00010000 */
8003 #define CAN_F2R1_FB16                        CAN_F2R1_FB16_Msk                 /*!< Filter bit 16 */
8004 #define CAN_F2R1_FB17_Pos                    (17U)
8005 #define CAN_F2R1_FB17_Msk                    (0x1UL << CAN_F2R1_FB17_Pos)       /*!< 0x00020000 */
8006 #define CAN_F2R1_FB17                        CAN_F2R1_FB17_Msk                 /*!< Filter bit 17 */
8007 #define CAN_F2R1_FB18_Pos                    (18U)
8008 #define CAN_F2R1_FB18_Msk                    (0x1UL << CAN_F2R1_FB18_Pos)       /*!< 0x00040000 */
8009 #define CAN_F2R1_FB18                        CAN_F2R1_FB18_Msk                 /*!< Filter bit 18 */
8010 #define CAN_F2R1_FB19_Pos                    (19U)
8011 #define CAN_F2R1_FB19_Msk                    (0x1UL << CAN_F2R1_FB19_Pos)       /*!< 0x00080000 */
8012 #define CAN_F2R1_FB19                        CAN_F2R1_FB19_Msk                 /*!< Filter bit 19 */
8013 #define CAN_F2R1_FB20_Pos                    (20U)
8014 #define CAN_F2R1_FB20_Msk                    (0x1UL << CAN_F2R1_FB20_Pos)       /*!< 0x00100000 */
8015 #define CAN_F2R1_FB20                        CAN_F2R1_FB20_Msk                 /*!< Filter bit 20 */
8016 #define CAN_F2R1_FB21_Pos                    (21U)
8017 #define CAN_F2R1_FB21_Msk                    (0x1UL << CAN_F2R1_FB21_Pos)       /*!< 0x00200000 */
8018 #define CAN_F2R1_FB21                        CAN_F2R1_FB21_Msk                 /*!< Filter bit 21 */
8019 #define CAN_F2R1_FB22_Pos                    (22U)
8020 #define CAN_F2R1_FB22_Msk                    (0x1UL << CAN_F2R1_FB22_Pos)       /*!< 0x00400000 */
8021 #define CAN_F2R1_FB22                        CAN_F2R1_FB22_Msk                 /*!< Filter bit 22 */
8022 #define CAN_F2R1_FB23_Pos                    (23U)
8023 #define CAN_F2R1_FB23_Msk                    (0x1UL << CAN_F2R1_FB23_Pos)       /*!< 0x00800000 */
8024 #define CAN_F2R1_FB23                        CAN_F2R1_FB23_Msk                 /*!< Filter bit 23 */
8025 #define CAN_F2R1_FB24_Pos                    (24U)
8026 #define CAN_F2R1_FB24_Msk                    (0x1UL << CAN_F2R1_FB24_Pos)       /*!< 0x01000000 */
8027 #define CAN_F2R1_FB24                        CAN_F2R1_FB24_Msk                 /*!< Filter bit 24 */
8028 #define CAN_F2R1_FB25_Pos                    (25U)
8029 #define CAN_F2R1_FB25_Msk                    (0x1UL << CAN_F2R1_FB25_Pos)       /*!< 0x02000000 */
8030 #define CAN_F2R1_FB25                        CAN_F2R1_FB25_Msk                 /*!< Filter bit 25 */
8031 #define CAN_F2R1_FB26_Pos                    (26U)
8032 #define CAN_F2R1_FB26_Msk                    (0x1UL << CAN_F2R1_FB26_Pos)       /*!< 0x04000000 */
8033 #define CAN_F2R1_FB26                        CAN_F2R1_FB26_Msk                 /*!< Filter bit 26 */
8034 #define CAN_F2R1_FB27_Pos                    (27U)
8035 #define CAN_F2R1_FB27_Msk                    (0x1UL << CAN_F2R1_FB27_Pos)       /*!< 0x08000000 */
8036 #define CAN_F2R1_FB27                        CAN_F2R1_FB27_Msk                 /*!< Filter bit 27 */
8037 #define CAN_F2R1_FB28_Pos                    (28U)
8038 #define CAN_F2R1_FB28_Msk                    (0x1UL << CAN_F2R1_FB28_Pos)       /*!< 0x10000000 */
8039 #define CAN_F2R1_FB28                        CAN_F2R1_FB28_Msk                 /*!< Filter bit 28 */
8040 #define CAN_F2R1_FB29_Pos                    (29U)
8041 #define CAN_F2R1_FB29_Msk                    (0x1UL << CAN_F2R1_FB29_Pos)       /*!< 0x20000000 */
8042 #define CAN_F2R1_FB29                        CAN_F2R1_FB29_Msk                 /*!< Filter bit 29 */
8043 #define CAN_F2R1_FB30_Pos                    (30U)
8044 #define CAN_F2R1_FB30_Msk                    (0x1UL << CAN_F2R1_FB30_Pos)       /*!< 0x40000000 */
8045 #define CAN_F2R1_FB30                        CAN_F2R1_FB30_Msk                 /*!< Filter bit 30 */
8046 #define CAN_F2R1_FB31_Pos                    (31U)
8047 #define CAN_F2R1_FB31_Msk                    (0x1UL << CAN_F2R1_FB31_Pos)       /*!< 0x80000000 */
8048 #define CAN_F2R1_FB31                        CAN_F2R1_FB31_Msk                 /*!< Filter bit 31 */
8049 
8050 /*******************  Bit definition for CAN_F3R1 register  *******************/
8051 #define CAN_F3R1_FB0_Pos                     (0U)
8052 #define CAN_F3R1_FB0_Msk                     (0x1UL << CAN_F3R1_FB0_Pos)        /*!< 0x00000001 */
8053 #define CAN_F3R1_FB0                         CAN_F3R1_FB0_Msk                  /*!< Filter bit 0 */
8054 #define CAN_F3R1_FB1_Pos                     (1U)
8055 #define CAN_F3R1_FB1_Msk                     (0x1UL << CAN_F3R1_FB1_Pos)        /*!< 0x00000002 */
8056 #define CAN_F3R1_FB1                         CAN_F3R1_FB1_Msk                  /*!< Filter bit 1 */
8057 #define CAN_F3R1_FB2_Pos                     (2U)
8058 #define CAN_F3R1_FB2_Msk                     (0x1UL << CAN_F3R1_FB2_Pos)        /*!< 0x00000004 */
8059 #define CAN_F3R1_FB2                         CAN_F3R1_FB2_Msk                  /*!< Filter bit 2 */
8060 #define CAN_F3R1_FB3_Pos                     (3U)
8061 #define CAN_F3R1_FB3_Msk                     (0x1UL << CAN_F3R1_FB3_Pos)        /*!< 0x00000008 */
8062 #define CAN_F3R1_FB3                         CAN_F3R1_FB3_Msk                  /*!< Filter bit 3 */
8063 #define CAN_F3R1_FB4_Pos                     (4U)
8064 #define CAN_F3R1_FB4_Msk                     (0x1UL << CAN_F3R1_FB4_Pos)        /*!< 0x00000010 */
8065 #define CAN_F3R1_FB4                         CAN_F3R1_FB4_Msk                  /*!< Filter bit 4 */
8066 #define CAN_F3R1_FB5_Pos                     (5U)
8067 #define CAN_F3R1_FB5_Msk                     (0x1UL << CAN_F3R1_FB5_Pos)        /*!< 0x00000020 */
8068 #define CAN_F3R1_FB5                         CAN_F3R1_FB5_Msk                  /*!< Filter bit 5 */
8069 #define CAN_F3R1_FB6_Pos                     (6U)
8070 #define CAN_F3R1_FB6_Msk                     (0x1UL << CAN_F3R1_FB6_Pos)        /*!< 0x00000040 */
8071 #define CAN_F3R1_FB6                         CAN_F3R1_FB6_Msk                  /*!< Filter bit 6 */
8072 #define CAN_F3R1_FB7_Pos                     (7U)
8073 #define CAN_F3R1_FB7_Msk                     (0x1UL << CAN_F3R1_FB7_Pos)        /*!< 0x00000080 */
8074 #define CAN_F3R1_FB7                         CAN_F3R1_FB7_Msk                  /*!< Filter bit 7 */
8075 #define CAN_F3R1_FB8_Pos                     (8U)
8076 #define CAN_F3R1_FB8_Msk                     (0x1UL << CAN_F3R1_FB8_Pos)        /*!< 0x00000100 */
8077 #define CAN_F3R1_FB8                         CAN_F3R1_FB8_Msk                  /*!< Filter bit 8 */
8078 #define CAN_F3R1_FB9_Pos                     (9U)
8079 #define CAN_F3R1_FB9_Msk                     (0x1UL << CAN_F3R1_FB9_Pos)        /*!< 0x00000200 */
8080 #define CAN_F3R1_FB9                         CAN_F3R1_FB9_Msk                  /*!< Filter bit 9 */
8081 #define CAN_F3R1_FB10_Pos                    (10U)
8082 #define CAN_F3R1_FB10_Msk                    (0x1UL << CAN_F3R1_FB10_Pos)       /*!< 0x00000400 */
8083 #define CAN_F3R1_FB10                        CAN_F3R1_FB10_Msk                 /*!< Filter bit 10 */
8084 #define CAN_F3R1_FB11_Pos                    (11U)
8085 #define CAN_F3R1_FB11_Msk                    (0x1UL << CAN_F3R1_FB11_Pos)       /*!< 0x00000800 */
8086 #define CAN_F3R1_FB11                        CAN_F3R1_FB11_Msk                 /*!< Filter bit 11 */
8087 #define CAN_F3R1_FB12_Pos                    (12U)
8088 #define CAN_F3R1_FB12_Msk                    (0x1UL << CAN_F3R1_FB12_Pos)       /*!< 0x00001000 */
8089 #define CAN_F3R1_FB12                        CAN_F3R1_FB12_Msk                 /*!< Filter bit 12 */
8090 #define CAN_F3R1_FB13_Pos                    (13U)
8091 #define CAN_F3R1_FB13_Msk                    (0x1UL << CAN_F3R1_FB13_Pos)       /*!< 0x00002000 */
8092 #define CAN_F3R1_FB13                        CAN_F3R1_FB13_Msk                 /*!< Filter bit 13 */
8093 #define CAN_F3R1_FB14_Pos                    (14U)
8094 #define CAN_F3R1_FB14_Msk                    (0x1UL << CAN_F3R1_FB14_Pos)       /*!< 0x00004000 */
8095 #define CAN_F3R1_FB14                        CAN_F3R1_FB14_Msk                 /*!< Filter bit 14 */
8096 #define CAN_F3R1_FB15_Pos                    (15U)
8097 #define CAN_F3R1_FB15_Msk                    (0x1UL << CAN_F3R1_FB15_Pos)       /*!< 0x00008000 */
8098 #define CAN_F3R1_FB15                        CAN_F3R1_FB15_Msk                 /*!< Filter bit 15 */
8099 #define CAN_F3R1_FB16_Pos                    (16U)
8100 #define CAN_F3R1_FB16_Msk                    (0x1UL << CAN_F3R1_FB16_Pos)       /*!< 0x00010000 */
8101 #define CAN_F3R1_FB16                        CAN_F3R1_FB16_Msk                 /*!< Filter bit 16 */
8102 #define CAN_F3R1_FB17_Pos                    (17U)
8103 #define CAN_F3R1_FB17_Msk                    (0x1UL << CAN_F3R1_FB17_Pos)       /*!< 0x00020000 */
8104 #define CAN_F3R1_FB17                        CAN_F3R1_FB17_Msk                 /*!< Filter bit 17 */
8105 #define CAN_F3R1_FB18_Pos                    (18U)
8106 #define CAN_F3R1_FB18_Msk                    (0x1UL << CAN_F3R1_FB18_Pos)       /*!< 0x00040000 */
8107 #define CAN_F3R1_FB18                        CAN_F3R1_FB18_Msk                 /*!< Filter bit 18 */
8108 #define CAN_F3R1_FB19_Pos                    (19U)
8109 #define CAN_F3R1_FB19_Msk                    (0x1UL << CAN_F3R1_FB19_Pos)       /*!< 0x00080000 */
8110 #define CAN_F3R1_FB19                        CAN_F3R1_FB19_Msk                 /*!< Filter bit 19 */
8111 #define CAN_F3R1_FB20_Pos                    (20U)
8112 #define CAN_F3R1_FB20_Msk                    (0x1UL << CAN_F3R1_FB20_Pos)       /*!< 0x00100000 */
8113 #define CAN_F3R1_FB20                        CAN_F3R1_FB20_Msk                 /*!< Filter bit 20 */
8114 #define CAN_F3R1_FB21_Pos                    (21U)
8115 #define CAN_F3R1_FB21_Msk                    (0x1UL << CAN_F3R1_FB21_Pos)       /*!< 0x00200000 */
8116 #define CAN_F3R1_FB21                        CAN_F3R1_FB21_Msk                 /*!< Filter bit 21 */
8117 #define CAN_F3R1_FB22_Pos                    (22U)
8118 #define CAN_F3R1_FB22_Msk                    (0x1UL << CAN_F3R1_FB22_Pos)       /*!< 0x00400000 */
8119 #define CAN_F3R1_FB22                        CAN_F3R1_FB22_Msk                 /*!< Filter bit 22 */
8120 #define CAN_F3R1_FB23_Pos                    (23U)
8121 #define CAN_F3R1_FB23_Msk                    (0x1UL << CAN_F3R1_FB23_Pos)       /*!< 0x00800000 */
8122 #define CAN_F3R1_FB23                        CAN_F3R1_FB23_Msk                 /*!< Filter bit 23 */
8123 #define CAN_F3R1_FB24_Pos                    (24U)
8124 #define CAN_F3R1_FB24_Msk                    (0x1UL << CAN_F3R1_FB24_Pos)       /*!< 0x01000000 */
8125 #define CAN_F3R1_FB24                        CAN_F3R1_FB24_Msk                 /*!< Filter bit 24 */
8126 #define CAN_F3R1_FB25_Pos                    (25U)
8127 #define CAN_F3R1_FB25_Msk                    (0x1UL << CAN_F3R1_FB25_Pos)       /*!< 0x02000000 */
8128 #define CAN_F3R1_FB25                        CAN_F3R1_FB25_Msk                 /*!< Filter bit 25 */
8129 #define CAN_F3R1_FB26_Pos                    (26U)
8130 #define CAN_F3R1_FB26_Msk                    (0x1UL << CAN_F3R1_FB26_Pos)       /*!< 0x04000000 */
8131 #define CAN_F3R1_FB26                        CAN_F3R1_FB26_Msk                 /*!< Filter bit 26 */
8132 #define CAN_F3R1_FB27_Pos                    (27U)
8133 #define CAN_F3R1_FB27_Msk                    (0x1UL << CAN_F3R1_FB27_Pos)       /*!< 0x08000000 */
8134 #define CAN_F3R1_FB27                        CAN_F3R1_FB27_Msk                 /*!< Filter bit 27 */
8135 #define CAN_F3R1_FB28_Pos                    (28U)
8136 #define CAN_F3R1_FB28_Msk                    (0x1UL << CAN_F3R1_FB28_Pos)       /*!< 0x10000000 */
8137 #define CAN_F3R1_FB28                        CAN_F3R1_FB28_Msk                 /*!< Filter bit 28 */
8138 #define CAN_F3R1_FB29_Pos                    (29U)
8139 #define CAN_F3R1_FB29_Msk                    (0x1UL << CAN_F3R1_FB29_Pos)       /*!< 0x20000000 */
8140 #define CAN_F3R1_FB29                        CAN_F3R1_FB29_Msk                 /*!< Filter bit 29 */
8141 #define CAN_F3R1_FB30_Pos                    (30U)
8142 #define CAN_F3R1_FB30_Msk                    (0x1UL << CAN_F3R1_FB30_Pos)       /*!< 0x40000000 */
8143 #define CAN_F3R1_FB30                        CAN_F3R1_FB30_Msk                 /*!< Filter bit 30 */
8144 #define CAN_F3R1_FB31_Pos                    (31U)
8145 #define CAN_F3R1_FB31_Msk                    (0x1UL << CAN_F3R1_FB31_Pos)       /*!< 0x80000000 */
8146 #define CAN_F3R1_FB31                        CAN_F3R1_FB31_Msk                 /*!< Filter bit 31 */
8147 
8148 /*******************  Bit definition for CAN_F4R1 register  *******************/
8149 #define CAN_F4R1_FB0_Pos                     (0U)
8150 #define CAN_F4R1_FB0_Msk                     (0x1UL << CAN_F4R1_FB0_Pos)        /*!< 0x00000001 */
8151 #define CAN_F4R1_FB0                         CAN_F4R1_FB0_Msk                  /*!< Filter bit 0 */
8152 #define CAN_F4R1_FB1_Pos                     (1U)
8153 #define CAN_F4R1_FB1_Msk                     (0x1UL << CAN_F4R1_FB1_Pos)        /*!< 0x00000002 */
8154 #define CAN_F4R1_FB1                         CAN_F4R1_FB1_Msk                  /*!< Filter bit 1 */
8155 #define CAN_F4R1_FB2_Pos                     (2U)
8156 #define CAN_F4R1_FB2_Msk                     (0x1UL << CAN_F4R1_FB2_Pos)        /*!< 0x00000004 */
8157 #define CAN_F4R1_FB2                         CAN_F4R1_FB2_Msk                  /*!< Filter bit 2 */
8158 #define CAN_F4R1_FB3_Pos                     (3U)
8159 #define CAN_F4R1_FB3_Msk                     (0x1UL << CAN_F4R1_FB3_Pos)        /*!< 0x00000008 */
8160 #define CAN_F4R1_FB3                         CAN_F4R1_FB3_Msk                  /*!< Filter bit 3 */
8161 #define CAN_F4R1_FB4_Pos                     (4U)
8162 #define CAN_F4R1_FB4_Msk                     (0x1UL << CAN_F4R1_FB4_Pos)        /*!< 0x00000010 */
8163 #define CAN_F4R1_FB4                         CAN_F4R1_FB4_Msk                  /*!< Filter bit 4 */
8164 #define CAN_F4R1_FB5_Pos                     (5U)
8165 #define CAN_F4R1_FB5_Msk                     (0x1UL << CAN_F4R1_FB5_Pos)        /*!< 0x00000020 */
8166 #define CAN_F4R1_FB5                         CAN_F4R1_FB5_Msk                  /*!< Filter bit 5 */
8167 #define CAN_F4R1_FB6_Pos                     (6U)
8168 #define CAN_F4R1_FB6_Msk                     (0x1UL << CAN_F4R1_FB6_Pos)        /*!< 0x00000040 */
8169 #define CAN_F4R1_FB6                         CAN_F4R1_FB6_Msk                  /*!< Filter bit 6 */
8170 #define CAN_F4R1_FB7_Pos                     (7U)
8171 #define CAN_F4R1_FB7_Msk                     (0x1UL << CAN_F4R1_FB7_Pos)        /*!< 0x00000080 */
8172 #define CAN_F4R1_FB7                         CAN_F4R1_FB7_Msk                  /*!< Filter bit 7 */
8173 #define CAN_F4R1_FB8_Pos                     (8U)
8174 #define CAN_F4R1_FB8_Msk                     (0x1UL << CAN_F4R1_FB8_Pos)        /*!< 0x00000100 */
8175 #define CAN_F4R1_FB8                         CAN_F4R1_FB8_Msk                  /*!< Filter bit 8 */
8176 #define CAN_F4R1_FB9_Pos                     (9U)
8177 #define CAN_F4R1_FB9_Msk                     (0x1UL << CAN_F4R1_FB9_Pos)        /*!< 0x00000200 */
8178 #define CAN_F4R1_FB9                         CAN_F4R1_FB9_Msk                  /*!< Filter bit 9 */
8179 #define CAN_F4R1_FB10_Pos                    (10U)
8180 #define CAN_F4R1_FB10_Msk                    (0x1UL << CAN_F4R1_FB10_Pos)       /*!< 0x00000400 */
8181 #define CAN_F4R1_FB10                        CAN_F4R1_FB10_Msk                 /*!< Filter bit 10 */
8182 #define CAN_F4R1_FB11_Pos                    (11U)
8183 #define CAN_F4R1_FB11_Msk                    (0x1UL << CAN_F4R1_FB11_Pos)       /*!< 0x00000800 */
8184 #define CAN_F4R1_FB11                        CAN_F4R1_FB11_Msk                 /*!< Filter bit 11 */
8185 #define CAN_F4R1_FB12_Pos                    (12U)
8186 #define CAN_F4R1_FB12_Msk                    (0x1UL << CAN_F4R1_FB12_Pos)       /*!< 0x00001000 */
8187 #define CAN_F4R1_FB12                        CAN_F4R1_FB12_Msk                 /*!< Filter bit 12 */
8188 #define CAN_F4R1_FB13_Pos                    (13U)
8189 #define CAN_F4R1_FB13_Msk                    (0x1UL << CAN_F4R1_FB13_Pos)       /*!< 0x00002000 */
8190 #define CAN_F4R1_FB13                        CAN_F4R1_FB13_Msk                 /*!< Filter bit 13 */
8191 #define CAN_F4R1_FB14_Pos                    (14U)
8192 #define CAN_F4R1_FB14_Msk                    (0x1UL << CAN_F4R1_FB14_Pos)       /*!< 0x00004000 */
8193 #define CAN_F4R1_FB14                        CAN_F4R1_FB14_Msk                 /*!< Filter bit 14 */
8194 #define CAN_F4R1_FB15_Pos                    (15U)
8195 #define CAN_F4R1_FB15_Msk                    (0x1UL << CAN_F4R1_FB15_Pos)       /*!< 0x00008000 */
8196 #define CAN_F4R1_FB15                        CAN_F4R1_FB15_Msk                 /*!< Filter bit 15 */
8197 #define CAN_F4R1_FB16_Pos                    (16U)
8198 #define CAN_F4R1_FB16_Msk                    (0x1UL << CAN_F4R1_FB16_Pos)       /*!< 0x00010000 */
8199 #define CAN_F4R1_FB16                        CAN_F4R1_FB16_Msk                 /*!< Filter bit 16 */
8200 #define CAN_F4R1_FB17_Pos                    (17U)
8201 #define CAN_F4R1_FB17_Msk                    (0x1UL << CAN_F4R1_FB17_Pos)       /*!< 0x00020000 */
8202 #define CAN_F4R1_FB17                        CAN_F4R1_FB17_Msk                 /*!< Filter bit 17 */
8203 #define CAN_F4R1_FB18_Pos                    (18U)
8204 #define CAN_F4R1_FB18_Msk                    (0x1UL << CAN_F4R1_FB18_Pos)       /*!< 0x00040000 */
8205 #define CAN_F4R1_FB18                        CAN_F4R1_FB18_Msk                 /*!< Filter bit 18 */
8206 #define CAN_F4R1_FB19_Pos                    (19U)
8207 #define CAN_F4R1_FB19_Msk                    (0x1UL << CAN_F4R1_FB19_Pos)       /*!< 0x00080000 */
8208 #define CAN_F4R1_FB19                        CAN_F4R1_FB19_Msk                 /*!< Filter bit 19 */
8209 #define CAN_F4R1_FB20_Pos                    (20U)
8210 #define CAN_F4R1_FB20_Msk                    (0x1UL << CAN_F4R1_FB20_Pos)       /*!< 0x00100000 */
8211 #define CAN_F4R1_FB20                        CAN_F4R1_FB20_Msk                 /*!< Filter bit 20 */
8212 #define CAN_F4R1_FB21_Pos                    (21U)
8213 #define CAN_F4R1_FB21_Msk                    (0x1UL << CAN_F4R1_FB21_Pos)       /*!< 0x00200000 */
8214 #define CAN_F4R1_FB21                        CAN_F4R1_FB21_Msk                 /*!< Filter bit 21 */
8215 #define CAN_F4R1_FB22_Pos                    (22U)
8216 #define CAN_F4R1_FB22_Msk                    (0x1UL << CAN_F4R1_FB22_Pos)       /*!< 0x00400000 */
8217 #define CAN_F4R1_FB22                        CAN_F4R1_FB22_Msk                 /*!< Filter bit 22 */
8218 #define CAN_F4R1_FB23_Pos                    (23U)
8219 #define CAN_F4R1_FB23_Msk                    (0x1UL << CAN_F4R1_FB23_Pos)       /*!< 0x00800000 */
8220 #define CAN_F4R1_FB23                        CAN_F4R1_FB23_Msk                 /*!< Filter bit 23 */
8221 #define CAN_F4R1_FB24_Pos                    (24U)
8222 #define CAN_F4R1_FB24_Msk                    (0x1UL << CAN_F4R1_FB24_Pos)       /*!< 0x01000000 */
8223 #define CAN_F4R1_FB24                        CAN_F4R1_FB24_Msk                 /*!< Filter bit 24 */
8224 #define CAN_F4R1_FB25_Pos                    (25U)
8225 #define CAN_F4R1_FB25_Msk                    (0x1UL << CAN_F4R1_FB25_Pos)       /*!< 0x02000000 */
8226 #define CAN_F4R1_FB25                        CAN_F4R1_FB25_Msk                 /*!< Filter bit 25 */
8227 #define CAN_F4R1_FB26_Pos                    (26U)
8228 #define CAN_F4R1_FB26_Msk                    (0x1UL << CAN_F4R1_FB26_Pos)       /*!< 0x04000000 */
8229 #define CAN_F4R1_FB26                        CAN_F4R1_FB26_Msk                 /*!< Filter bit 26 */
8230 #define CAN_F4R1_FB27_Pos                    (27U)
8231 #define CAN_F4R1_FB27_Msk                    (0x1UL << CAN_F4R1_FB27_Pos)       /*!< 0x08000000 */
8232 #define CAN_F4R1_FB27                        CAN_F4R1_FB27_Msk                 /*!< Filter bit 27 */
8233 #define CAN_F4R1_FB28_Pos                    (28U)
8234 #define CAN_F4R1_FB28_Msk                    (0x1UL << CAN_F4R1_FB28_Pos)       /*!< 0x10000000 */
8235 #define CAN_F4R1_FB28                        CAN_F4R1_FB28_Msk                 /*!< Filter bit 28 */
8236 #define CAN_F4R1_FB29_Pos                    (29U)
8237 #define CAN_F4R1_FB29_Msk                    (0x1UL << CAN_F4R1_FB29_Pos)       /*!< 0x20000000 */
8238 #define CAN_F4R1_FB29                        CAN_F4R1_FB29_Msk                 /*!< Filter bit 29 */
8239 #define CAN_F4R1_FB30_Pos                    (30U)
8240 #define CAN_F4R1_FB30_Msk                    (0x1UL << CAN_F4R1_FB30_Pos)       /*!< 0x40000000 */
8241 #define CAN_F4R1_FB30                        CAN_F4R1_FB30_Msk                 /*!< Filter bit 30 */
8242 #define CAN_F4R1_FB31_Pos                    (31U)
8243 #define CAN_F4R1_FB31_Msk                    (0x1UL << CAN_F4R1_FB31_Pos)       /*!< 0x80000000 */
8244 #define CAN_F4R1_FB31                        CAN_F4R1_FB31_Msk                 /*!< Filter bit 31 */
8245 
8246 /*******************  Bit definition for CAN_F5R1 register  *******************/
8247 #define CAN_F5R1_FB0_Pos                     (0U)
8248 #define CAN_F5R1_FB0_Msk                     (0x1UL << CAN_F5R1_FB0_Pos)        /*!< 0x00000001 */
8249 #define CAN_F5R1_FB0                         CAN_F5R1_FB0_Msk                  /*!< Filter bit 0 */
8250 #define CAN_F5R1_FB1_Pos                     (1U)
8251 #define CAN_F5R1_FB1_Msk                     (0x1UL << CAN_F5R1_FB1_Pos)        /*!< 0x00000002 */
8252 #define CAN_F5R1_FB1                         CAN_F5R1_FB1_Msk                  /*!< Filter bit 1 */
8253 #define CAN_F5R1_FB2_Pos                     (2U)
8254 #define CAN_F5R1_FB2_Msk                     (0x1UL << CAN_F5R1_FB2_Pos)        /*!< 0x00000004 */
8255 #define CAN_F5R1_FB2                         CAN_F5R1_FB2_Msk                  /*!< Filter bit 2 */
8256 #define CAN_F5R1_FB3_Pos                     (3U)
8257 #define CAN_F5R1_FB3_Msk                     (0x1UL << CAN_F5R1_FB3_Pos)        /*!< 0x00000008 */
8258 #define CAN_F5R1_FB3                         CAN_F5R1_FB3_Msk                  /*!< Filter bit 3 */
8259 #define CAN_F5R1_FB4_Pos                     (4U)
8260 #define CAN_F5R1_FB4_Msk                     (0x1UL << CAN_F5R1_FB4_Pos)        /*!< 0x00000010 */
8261 #define CAN_F5R1_FB4                         CAN_F5R1_FB4_Msk                  /*!< Filter bit 4 */
8262 #define CAN_F5R1_FB5_Pos                     (5U)
8263 #define CAN_F5R1_FB5_Msk                     (0x1UL << CAN_F5R1_FB5_Pos)        /*!< 0x00000020 */
8264 #define CAN_F5R1_FB5                         CAN_F5R1_FB5_Msk                  /*!< Filter bit 5 */
8265 #define CAN_F5R1_FB6_Pos                     (6U)
8266 #define CAN_F5R1_FB6_Msk                     (0x1UL << CAN_F5R1_FB6_Pos)        /*!< 0x00000040 */
8267 #define CAN_F5R1_FB6                         CAN_F5R1_FB6_Msk                  /*!< Filter bit 6 */
8268 #define CAN_F5R1_FB7_Pos                     (7U)
8269 #define CAN_F5R1_FB7_Msk                     (0x1UL << CAN_F5R1_FB7_Pos)        /*!< 0x00000080 */
8270 #define CAN_F5R1_FB7                         CAN_F5R1_FB7_Msk                  /*!< Filter bit 7 */
8271 #define CAN_F5R1_FB8_Pos                     (8U)
8272 #define CAN_F5R1_FB8_Msk                     (0x1UL << CAN_F5R1_FB8_Pos)        /*!< 0x00000100 */
8273 #define CAN_F5R1_FB8                         CAN_F5R1_FB8_Msk                  /*!< Filter bit 8 */
8274 #define CAN_F5R1_FB9_Pos                     (9U)
8275 #define CAN_F5R1_FB9_Msk                     (0x1UL << CAN_F5R1_FB9_Pos)        /*!< 0x00000200 */
8276 #define CAN_F5R1_FB9                         CAN_F5R1_FB9_Msk                  /*!< Filter bit 9 */
8277 #define CAN_F5R1_FB10_Pos                    (10U)
8278 #define CAN_F5R1_FB10_Msk                    (0x1UL << CAN_F5R1_FB10_Pos)       /*!< 0x00000400 */
8279 #define CAN_F5R1_FB10                        CAN_F5R1_FB10_Msk                 /*!< Filter bit 10 */
8280 #define CAN_F5R1_FB11_Pos                    (11U)
8281 #define CAN_F5R1_FB11_Msk                    (0x1UL << CAN_F5R1_FB11_Pos)       /*!< 0x00000800 */
8282 #define CAN_F5R1_FB11                        CAN_F5R1_FB11_Msk                 /*!< Filter bit 11 */
8283 #define CAN_F5R1_FB12_Pos                    (12U)
8284 #define CAN_F5R1_FB12_Msk                    (0x1UL << CAN_F5R1_FB12_Pos)       /*!< 0x00001000 */
8285 #define CAN_F5R1_FB12                        CAN_F5R1_FB12_Msk                 /*!< Filter bit 12 */
8286 #define CAN_F5R1_FB13_Pos                    (13U)
8287 #define CAN_F5R1_FB13_Msk                    (0x1UL << CAN_F5R1_FB13_Pos)       /*!< 0x00002000 */
8288 #define CAN_F5R1_FB13                        CAN_F5R1_FB13_Msk                 /*!< Filter bit 13 */
8289 #define CAN_F5R1_FB14_Pos                    (14U)
8290 #define CAN_F5R1_FB14_Msk                    (0x1UL << CAN_F5R1_FB14_Pos)       /*!< 0x00004000 */
8291 #define CAN_F5R1_FB14                        CAN_F5R1_FB14_Msk                 /*!< Filter bit 14 */
8292 #define CAN_F5R1_FB15_Pos                    (15U)
8293 #define CAN_F5R1_FB15_Msk                    (0x1UL << CAN_F5R1_FB15_Pos)       /*!< 0x00008000 */
8294 #define CAN_F5R1_FB15                        CAN_F5R1_FB15_Msk                 /*!< Filter bit 15 */
8295 #define CAN_F5R1_FB16_Pos                    (16U)
8296 #define CAN_F5R1_FB16_Msk                    (0x1UL << CAN_F5R1_FB16_Pos)       /*!< 0x00010000 */
8297 #define CAN_F5R1_FB16                        CAN_F5R1_FB16_Msk                 /*!< Filter bit 16 */
8298 #define CAN_F5R1_FB17_Pos                    (17U)
8299 #define CAN_F5R1_FB17_Msk                    (0x1UL << CAN_F5R1_FB17_Pos)       /*!< 0x00020000 */
8300 #define CAN_F5R1_FB17                        CAN_F5R1_FB17_Msk                 /*!< Filter bit 17 */
8301 #define CAN_F5R1_FB18_Pos                    (18U)
8302 #define CAN_F5R1_FB18_Msk                    (0x1UL << CAN_F5R1_FB18_Pos)       /*!< 0x00040000 */
8303 #define CAN_F5R1_FB18                        CAN_F5R1_FB18_Msk                 /*!< Filter bit 18 */
8304 #define CAN_F5R1_FB19_Pos                    (19U)
8305 #define CAN_F5R1_FB19_Msk                    (0x1UL << CAN_F5R1_FB19_Pos)       /*!< 0x00080000 */
8306 #define CAN_F5R1_FB19                        CAN_F5R1_FB19_Msk                 /*!< Filter bit 19 */
8307 #define CAN_F5R1_FB20_Pos                    (20U)
8308 #define CAN_F5R1_FB20_Msk                    (0x1UL << CAN_F5R1_FB20_Pos)       /*!< 0x00100000 */
8309 #define CAN_F5R1_FB20                        CAN_F5R1_FB20_Msk                 /*!< Filter bit 20 */
8310 #define CAN_F5R1_FB21_Pos                    (21U)
8311 #define CAN_F5R1_FB21_Msk                    (0x1UL << CAN_F5R1_FB21_Pos)       /*!< 0x00200000 */
8312 #define CAN_F5R1_FB21                        CAN_F5R1_FB21_Msk                 /*!< Filter bit 21 */
8313 #define CAN_F5R1_FB22_Pos                    (22U)
8314 #define CAN_F5R1_FB22_Msk                    (0x1UL << CAN_F5R1_FB22_Pos)       /*!< 0x00400000 */
8315 #define CAN_F5R1_FB22                        CAN_F5R1_FB22_Msk                 /*!< Filter bit 22 */
8316 #define CAN_F5R1_FB23_Pos                    (23U)
8317 #define CAN_F5R1_FB23_Msk                    (0x1UL << CAN_F5R1_FB23_Pos)       /*!< 0x00800000 */
8318 #define CAN_F5R1_FB23                        CAN_F5R1_FB23_Msk                 /*!< Filter bit 23 */
8319 #define CAN_F5R1_FB24_Pos                    (24U)
8320 #define CAN_F5R1_FB24_Msk                    (0x1UL << CAN_F5R1_FB24_Pos)       /*!< 0x01000000 */
8321 #define CAN_F5R1_FB24                        CAN_F5R1_FB24_Msk                 /*!< Filter bit 24 */
8322 #define CAN_F5R1_FB25_Pos                    (25U)
8323 #define CAN_F5R1_FB25_Msk                    (0x1UL << CAN_F5R1_FB25_Pos)       /*!< 0x02000000 */
8324 #define CAN_F5R1_FB25                        CAN_F5R1_FB25_Msk                 /*!< Filter bit 25 */
8325 #define CAN_F5R1_FB26_Pos                    (26U)
8326 #define CAN_F5R1_FB26_Msk                    (0x1UL << CAN_F5R1_FB26_Pos)       /*!< 0x04000000 */
8327 #define CAN_F5R1_FB26                        CAN_F5R1_FB26_Msk                 /*!< Filter bit 26 */
8328 #define CAN_F5R1_FB27_Pos                    (27U)
8329 #define CAN_F5R1_FB27_Msk                    (0x1UL << CAN_F5R1_FB27_Pos)       /*!< 0x08000000 */
8330 #define CAN_F5R1_FB27                        CAN_F5R1_FB27_Msk                 /*!< Filter bit 27 */
8331 #define CAN_F5R1_FB28_Pos                    (28U)
8332 #define CAN_F5R1_FB28_Msk                    (0x1UL << CAN_F5R1_FB28_Pos)       /*!< 0x10000000 */
8333 #define CAN_F5R1_FB28                        CAN_F5R1_FB28_Msk                 /*!< Filter bit 28 */
8334 #define CAN_F5R1_FB29_Pos                    (29U)
8335 #define CAN_F5R1_FB29_Msk                    (0x1UL << CAN_F5R1_FB29_Pos)       /*!< 0x20000000 */
8336 #define CAN_F5R1_FB29                        CAN_F5R1_FB29_Msk                 /*!< Filter bit 29 */
8337 #define CAN_F5R1_FB30_Pos                    (30U)
8338 #define CAN_F5R1_FB30_Msk                    (0x1UL << CAN_F5R1_FB30_Pos)       /*!< 0x40000000 */
8339 #define CAN_F5R1_FB30                        CAN_F5R1_FB30_Msk                 /*!< Filter bit 30 */
8340 #define CAN_F5R1_FB31_Pos                    (31U)
8341 #define CAN_F5R1_FB31_Msk                    (0x1UL << CAN_F5R1_FB31_Pos)       /*!< 0x80000000 */
8342 #define CAN_F5R1_FB31                        CAN_F5R1_FB31_Msk                 /*!< Filter bit 31 */
8343 
8344 /*******************  Bit definition for CAN_F6R1 register  *******************/
8345 #define CAN_F6R1_FB0_Pos                     (0U)
8346 #define CAN_F6R1_FB0_Msk                     (0x1UL << CAN_F6R1_FB0_Pos)        /*!< 0x00000001 */
8347 #define CAN_F6R1_FB0                         CAN_F6R1_FB0_Msk                  /*!< Filter bit 0 */
8348 #define CAN_F6R1_FB1_Pos                     (1U)
8349 #define CAN_F6R1_FB1_Msk                     (0x1UL << CAN_F6R1_FB1_Pos)        /*!< 0x00000002 */
8350 #define CAN_F6R1_FB1                         CAN_F6R1_FB1_Msk                  /*!< Filter bit 1 */
8351 #define CAN_F6R1_FB2_Pos                     (2U)
8352 #define CAN_F6R1_FB2_Msk                     (0x1UL << CAN_F6R1_FB2_Pos)        /*!< 0x00000004 */
8353 #define CAN_F6R1_FB2                         CAN_F6R1_FB2_Msk                  /*!< Filter bit 2 */
8354 #define CAN_F6R1_FB3_Pos                     (3U)
8355 #define CAN_F6R1_FB3_Msk                     (0x1UL << CAN_F6R1_FB3_Pos)        /*!< 0x00000008 */
8356 #define CAN_F6R1_FB3                         CAN_F6R1_FB3_Msk                  /*!< Filter bit 3 */
8357 #define CAN_F6R1_FB4_Pos                     (4U)
8358 #define CAN_F6R1_FB4_Msk                     (0x1UL << CAN_F6R1_FB4_Pos)        /*!< 0x00000010 */
8359 #define CAN_F6R1_FB4                         CAN_F6R1_FB4_Msk                  /*!< Filter bit 4 */
8360 #define CAN_F6R1_FB5_Pos                     (5U)
8361 #define CAN_F6R1_FB5_Msk                     (0x1UL << CAN_F6R1_FB5_Pos)        /*!< 0x00000020 */
8362 #define CAN_F6R1_FB5                         CAN_F6R1_FB5_Msk                  /*!< Filter bit 5 */
8363 #define CAN_F6R1_FB6_Pos                     (6U)
8364 #define CAN_F6R1_FB6_Msk                     (0x1UL << CAN_F6R1_FB6_Pos)        /*!< 0x00000040 */
8365 #define CAN_F6R1_FB6                         CAN_F6R1_FB6_Msk                  /*!< Filter bit 6 */
8366 #define CAN_F6R1_FB7_Pos                     (7U)
8367 #define CAN_F6R1_FB7_Msk                     (0x1UL << CAN_F6R1_FB7_Pos)        /*!< 0x00000080 */
8368 #define CAN_F6R1_FB7                         CAN_F6R1_FB7_Msk                  /*!< Filter bit 7 */
8369 #define CAN_F6R1_FB8_Pos                     (8U)
8370 #define CAN_F6R1_FB8_Msk                     (0x1UL << CAN_F6R1_FB8_Pos)        /*!< 0x00000100 */
8371 #define CAN_F6R1_FB8                         CAN_F6R1_FB8_Msk                  /*!< Filter bit 8 */
8372 #define CAN_F6R1_FB9_Pos                     (9U)
8373 #define CAN_F6R1_FB9_Msk                     (0x1UL << CAN_F6R1_FB9_Pos)        /*!< 0x00000200 */
8374 #define CAN_F6R1_FB9                         CAN_F6R1_FB9_Msk                  /*!< Filter bit 9 */
8375 #define CAN_F6R1_FB10_Pos                    (10U)
8376 #define CAN_F6R1_FB10_Msk                    (0x1UL << CAN_F6R1_FB10_Pos)       /*!< 0x00000400 */
8377 #define CAN_F6R1_FB10                        CAN_F6R1_FB10_Msk                 /*!< Filter bit 10 */
8378 #define CAN_F6R1_FB11_Pos                    (11U)
8379 #define CAN_F6R1_FB11_Msk                    (0x1UL << CAN_F6R1_FB11_Pos)       /*!< 0x00000800 */
8380 #define CAN_F6R1_FB11                        CAN_F6R1_FB11_Msk                 /*!< Filter bit 11 */
8381 #define CAN_F6R1_FB12_Pos                    (12U)
8382 #define CAN_F6R1_FB12_Msk                    (0x1UL << CAN_F6R1_FB12_Pos)       /*!< 0x00001000 */
8383 #define CAN_F6R1_FB12                        CAN_F6R1_FB12_Msk                 /*!< Filter bit 12 */
8384 #define CAN_F6R1_FB13_Pos                    (13U)
8385 #define CAN_F6R1_FB13_Msk                    (0x1UL << CAN_F6R1_FB13_Pos)       /*!< 0x00002000 */
8386 #define CAN_F6R1_FB13                        CAN_F6R1_FB13_Msk                 /*!< Filter bit 13 */
8387 #define CAN_F6R1_FB14_Pos                    (14U)
8388 #define CAN_F6R1_FB14_Msk                    (0x1UL << CAN_F6R1_FB14_Pos)       /*!< 0x00004000 */
8389 #define CAN_F6R1_FB14                        CAN_F6R1_FB14_Msk                 /*!< Filter bit 14 */
8390 #define CAN_F6R1_FB15_Pos                    (15U)
8391 #define CAN_F6R1_FB15_Msk                    (0x1UL << CAN_F6R1_FB15_Pos)       /*!< 0x00008000 */
8392 #define CAN_F6R1_FB15                        CAN_F6R1_FB15_Msk                 /*!< Filter bit 15 */
8393 #define CAN_F6R1_FB16_Pos                    (16U)
8394 #define CAN_F6R1_FB16_Msk                    (0x1UL << CAN_F6R1_FB16_Pos)       /*!< 0x00010000 */
8395 #define CAN_F6R1_FB16                        CAN_F6R1_FB16_Msk                 /*!< Filter bit 16 */
8396 #define CAN_F6R1_FB17_Pos                    (17U)
8397 #define CAN_F6R1_FB17_Msk                    (0x1UL << CAN_F6R1_FB17_Pos)       /*!< 0x00020000 */
8398 #define CAN_F6R1_FB17                        CAN_F6R1_FB17_Msk                 /*!< Filter bit 17 */
8399 #define CAN_F6R1_FB18_Pos                    (18U)
8400 #define CAN_F6R1_FB18_Msk                    (0x1UL << CAN_F6R1_FB18_Pos)       /*!< 0x00040000 */
8401 #define CAN_F6R1_FB18                        CAN_F6R1_FB18_Msk                 /*!< Filter bit 18 */
8402 #define CAN_F6R1_FB19_Pos                    (19U)
8403 #define CAN_F6R1_FB19_Msk                    (0x1UL << CAN_F6R1_FB19_Pos)       /*!< 0x00080000 */
8404 #define CAN_F6R1_FB19                        CAN_F6R1_FB19_Msk                 /*!< Filter bit 19 */
8405 #define CAN_F6R1_FB20_Pos                    (20U)
8406 #define CAN_F6R1_FB20_Msk                    (0x1UL << CAN_F6R1_FB20_Pos)       /*!< 0x00100000 */
8407 #define CAN_F6R1_FB20                        CAN_F6R1_FB20_Msk                 /*!< Filter bit 20 */
8408 #define CAN_F6R1_FB21_Pos                    (21U)
8409 #define CAN_F6R1_FB21_Msk                    (0x1UL << CAN_F6R1_FB21_Pos)       /*!< 0x00200000 */
8410 #define CAN_F6R1_FB21                        CAN_F6R1_FB21_Msk                 /*!< Filter bit 21 */
8411 #define CAN_F6R1_FB22_Pos                    (22U)
8412 #define CAN_F6R1_FB22_Msk                    (0x1UL << CAN_F6R1_FB22_Pos)       /*!< 0x00400000 */
8413 #define CAN_F6R1_FB22                        CAN_F6R1_FB22_Msk                 /*!< Filter bit 22 */
8414 #define CAN_F6R1_FB23_Pos                    (23U)
8415 #define CAN_F6R1_FB23_Msk                    (0x1UL << CAN_F6R1_FB23_Pos)       /*!< 0x00800000 */
8416 #define CAN_F6R1_FB23                        CAN_F6R1_FB23_Msk                 /*!< Filter bit 23 */
8417 #define CAN_F6R1_FB24_Pos                    (24U)
8418 #define CAN_F6R1_FB24_Msk                    (0x1UL << CAN_F6R1_FB24_Pos)       /*!< 0x01000000 */
8419 #define CAN_F6R1_FB24                        CAN_F6R1_FB24_Msk                 /*!< Filter bit 24 */
8420 #define CAN_F6R1_FB25_Pos                    (25U)
8421 #define CAN_F6R1_FB25_Msk                    (0x1UL << CAN_F6R1_FB25_Pos)       /*!< 0x02000000 */
8422 #define CAN_F6R1_FB25                        CAN_F6R1_FB25_Msk                 /*!< Filter bit 25 */
8423 #define CAN_F6R1_FB26_Pos                    (26U)
8424 #define CAN_F6R1_FB26_Msk                    (0x1UL << CAN_F6R1_FB26_Pos)       /*!< 0x04000000 */
8425 #define CAN_F6R1_FB26                        CAN_F6R1_FB26_Msk                 /*!< Filter bit 26 */
8426 #define CAN_F6R1_FB27_Pos                    (27U)
8427 #define CAN_F6R1_FB27_Msk                    (0x1UL << CAN_F6R1_FB27_Pos)       /*!< 0x08000000 */
8428 #define CAN_F6R1_FB27                        CAN_F6R1_FB27_Msk                 /*!< Filter bit 27 */
8429 #define CAN_F6R1_FB28_Pos                    (28U)
8430 #define CAN_F6R1_FB28_Msk                    (0x1UL << CAN_F6R1_FB28_Pos)       /*!< 0x10000000 */
8431 #define CAN_F6R1_FB28                        CAN_F6R1_FB28_Msk                 /*!< Filter bit 28 */
8432 #define CAN_F6R1_FB29_Pos                    (29U)
8433 #define CAN_F6R1_FB29_Msk                    (0x1UL << CAN_F6R1_FB29_Pos)       /*!< 0x20000000 */
8434 #define CAN_F6R1_FB29                        CAN_F6R1_FB29_Msk                 /*!< Filter bit 29 */
8435 #define CAN_F6R1_FB30_Pos                    (30U)
8436 #define CAN_F6R1_FB30_Msk                    (0x1UL << CAN_F6R1_FB30_Pos)       /*!< 0x40000000 */
8437 #define CAN_F6R1_FB30                        CAN_F6R1_FB30_Msk                 /*!< Filter bit 30 */
8438 #define CAN_F6R1_FB31_Pos                    (31U)
8439 #define CAN_F6R1_FB31_Msk                    (0x1UL << CAN_F6R1_FB31_Pos)       /*!< 0x80000000 */
8440 #define CAN_F6R1_FB31                        CAN_F6R1_FB31_Msk                 /*!< Filter bit 31 */
8441 
8442 /*******************  Bit definition for CAN_F7R1 register  *******************/
8443 #define CAN_F7R1_FB0_Pos                     (0U)
8444 #define CAN_F7R1_FB0_Msk                     (0x1UL << CAN_F7R1_FB0_Pos)        /*!< 0x00000001 */
8445 #define CAN_F7R1_FB0                         CAN_F7R1_FB0_Msk                  /*!< Filter bit 0 */
8446 #define CAN_F7R1_FB1_Pos                     (1U)
8447 #define CAN_F7R1_FB1_Msk                     (0x1UL << CAN_F7R1_FB1_Pos)        /*!< 0x00000002 */
8448 #define CAN_F7R1_FB1                         CAN_F7R1_FB1_Msk                  /*!< Filter bit 1 */
8449 #define CAN_F7R1_FB2_Pos                     (2U)
8450 #define CAN_F7R1_FB2_Msk                     (0x1UL << CAN_F7R1_FB2_Pos)        /*!< 0x00000004 */
8451 #define CAN_F7R1_FB2                         CAN_F7R1_FB2_Msk                  /*!< Filter bit 2 */
8452 #define CAN_F7R1_FB3_Pos                     (3U)
8453 #define CAN_F7R1_FB3_Msk                     (0x1UL << CAN_F7R1_FB3_Pos)        /*!< 0x00000008 */
8454 #define CAN_F7R1_FB3                         CAN_F7R1_FB3_Msk                  /*!< Filter bit 3 */
8455 #define CAN_F7R1_FB4_Pos                     (4U)
8456 #define CAN_F7R1_FB4_Msk                     (0x1UL << CAN_F7R1_FB4_Pos)        /*!< 0x00000010 */
8457 #define CAN_F7R1_FB4                         CAN_F7R1_FB4_Msk                  /*!< Filter bit 4 */
8458 #define CAN_F7R1_FB5_Pos                     (5U)
8459 #define CAN_F7R1_FB5_Msk                     (0x1UL << CAN_F7R1_FB5_Pos)        /*!< 0x00000020 */
8460 #define CAN_F7R1_FB5                         CAN_F7R1_FB5_Msk                  /*!< Filter bit 5 */
8461 #define CAN_F7R1_FB6_Pos                     (6U)
8462 #define CAN_F7R1_FB6_Msk                     (0x1UL << CAN_F7R1_FB6_Pos)        /*!< 0x00000040 */
8463 #define CAN_F7R1_FB6                         CAN_F7R1_FB6_Msk                  /*!< Filter bit 6 */
8464 #define CAN_F7R1_FB7_Pos                     (7U)
8465 #define CAN_F7R1_FB7_Msk                     (0x1UL << CAN_F7R1_FB7_Pos)        /*!< 0x00000080 */
8466 #define CAN_F7R1_FB7                         CAN_F7R1_FB7_Msk                  /*!< Filter bit 7 */
8467 #define CAN_F7R1_FB8_Pos                     (8U)
8468 #define CAN_F7R1_FB8_Msk                     (0x1UL << CAN_F7R1_FB8_Pos)        /*!< 0x00000100 */
8469 #define CAN_F7R1_FB8                         CAN_F7R1_FB8_Msk                  /*!< Filter bit 8 */
8470 #define CAN_F7R1_FB9_Pos                     (9U)
8471 #define CAN_F7R1_FB9_Msk                     (0x1UL << CAN_F7R1_FB9_Pos)        /*!< 0x00000200 */
8472 #define CAN_F7R1_FB9                         CAN_F7R1_FB9_Msk                  /*!< Filter bit 9 */
8473 #define CAN_F7R1_FB10_Pos                    (10U)
8474 #define CAN_F7R1_FB10_Msk                    (0x1UL << CAN_F7R1_FB10_Pos)       /*!< 0x00000400 */
8475 #define CAN_F7R1_FB10                        CAN_F7R1_FB10_Msk                 /*!< Filter bit 10 */
8476 #define CAN_F7R1_FB11_Pos                    (11U)
8477 #define CAN_F7R1_FB11_Msk                    (0x1UL << CAN_F7R1_FB11_Pos)       /*!< 0x00000800 */
8478 #define CAN_F7R1_FB11                        CAN_F7R1_FB11_Msk                 /*!< Filter bit 11 */
8479 #define CAN_F7R1_FB12_Pos                    (12U)
8480 #define CAN_F7R1_FB12_Msk                    (0x1UL << CAN_F7R1_FB12_Pos)       /*!< 0x00001000 */
8481 #define CAN_F7R1_FB12                        CAN_F7R1_FB12_Msk                 /*!< Filter bit 12 */
8482 #define CAN_F7R1_FB13_Pos                    (13U)
8483 #define CAN_F7R1_FB13_Msk                    (0x1UL << CAN_F7R1_FB13_Pos)       /*!< 0x00002000 */
8484 #define CAN_F7R1_FB13                        CAN_F7R1_FB13_Msk                 /*!< Filter bit 13 */
8485 #define CAN_F7R1_FB14_Pos                    (14U)
8486 #define CAN_F7R1_FB14_Msk                    (0x1UL << CAN_F7R1_FB14_Pos)       /*!< 0x00004000 */
8487 #define CAN_F7R1_FB14                        CAN_F7R1_FB14_Msk                 /*!< Filter bit 14 */
8488 #define CAN_F7R1_FB15_Pos                    (15U)
8489 #define CAN_F7R1_FB15_Msk                    (0x1UL << CAN_F7R1_FB15_Pos)       /*!< 0x00008000 */
8490 #define CAN_F7R1_FB15                        CAN_F7R1_FB15_Msk                 /*!< Filter bit 15 */
8491 #define CAN_F7R1_FB16_Pos                    (16U)
8492 #define CAN_F7R1_FB16_Msk                    (0x1UL << CAN_F7R1_FB16_Pos)       /*!< 0x00010000 */
8493 #define CAN_F7R1_FB16                        CAN_F7R1_FB16_Msk                 /*!< Filter bit 16 */
8494 #define CAN_F7R1_FB17_Pos                    (17U)
8495 #define CAN_F7R1_FB17_Msk                    (0x1UL << CAN_F7R1_FB17_Pos)       /*!< 0x00020000 */
8496 #define CAN_F7R1_FB17                        CAN_F7R1_FB17_Msk                 /*!< Filter bit 17 */
8497 #define CAN_F7R1_FB18_Pos                    (18U)
8498 #define CAN_F7R1_FB18_Msk                    (0x1UL << CAN_F7R1_FB18_Pos)       /*!< 0x00040000 */
8499 #define CAN_F7R1_FB18                        CAN_F7R1_FB18_Msk                 /*!< Filter bit 18 */
8500 #define CAN_F7R1_FB19_Pos                    (19U)
8501 #define CAN_F7R1_FB19_Msk                    (0x1UL << CAN_F7R1_FB19_Pos)       /*!< 0x00080000 */
8502 #define CAN_F7R1_FB19                        CAN_F7R1_FB19_Msk                 /*!< Filter bit 19 */
8503 #define CAN_F7R1_FB20_Pos                    (20U)
8504 #define CAN_F7R1_FB20_Msk                    (0x1UL << CAN_F7R1_FB20_Pos)       /*!< 0x00100000 */
8505 #define CAN_F7R1_FB20                        CAN_F7R1_FB20_Msk                 /*!< Filter bit 20 */
8506 #define CAN_F7R1_FB21_Pos                    (21U)
8507 #define CAN_F7R1_FB21_Msk                    (0x1UL << CAN_F7R1_FB21_Pos)       /*!< 0x00200000 */
8508 #define CAN_F7R1_FB21                        CAN_F7R1_FB21_Msk                 /*!< Filter bit 21 */
8509 #define CAN_F7R1_FB22_Pos                    (22U)
8510 #define CAN_F7R1_FB22_Msk                    (0x1UL << CAN_F7R1_FB22_Pos)       /*!< 0x00400000 */
8511 #define CAN_F7R1_FB22                        CAN_F7R1_FB22_Msk                 /*!< Filter bit 22 */
8512 #define CAN_F7R1_FB23_Pos                    (23U)
8513 #define CAN_F7R1_FB23_Msk                    (0x1UL << CAN_F7R1_FB23_Pos)       /*!< 0x00800000 */
8514 #define CAN_F7R1_FB23                        CAN_F7R1_FB23_Msk                 /*!< Filter bit 23 */
8515 #define CAN_F7R1_FB24_Pos                    (24U)
8516 #define CAN_F7R1_FB24_Msk                    (0x1UL << CAN_F7R1_FB24_Pos)       /*!< 0x01000000 */
8517 #define CAN_F7R1_FB24                        CAN_F7R1_FB24_Msk                 /*!< Filter bit 24 */
8518 #define CAN_F7R1_FB25_Pos                    (25U)
8519 #define CAN_F7R1_FB25_Msk                    (0x1UL << CAN_F7R1_FB25_Pos)       /*!< 0x02000000 */
8520 #define CAN_F7R1_FB25                        CAN_F7R1_FB25_Msk                 /*!< Filter bit 25 */
8521 #define CAN_F7R1_FB26_Pos                    (26U)
8522 #define CAN_F7R1_FB26_Msk                    (0x1UL << CAN_F7R1_FB26_Pos)       /*!< 0x04000000 */
8523 #define CAN_F7R1_FB26                        CAN_F7R1_FB26_Msk                 /*!< Filter bit 26 */
8524 #define CAN_F7R1_FB27_Pos                    (27U)
8525 #define CAN_F7R1_FB27_Msk                    (0x1UL << CAN_F7R1_FB27_Pos)       /*!< 0x08000000 */
8526 #define CAN_F7R1_FB27                        CAN_F7R1_FB27_Msk                 /*!< Filter bit 27 */
8527 #define CAN_F7R1_FB28_Pos                    (28U)
8528 #define CAN_F7R1_FB28_Msk                    (0x1UL << CAN_F7R1_FB28_Pos)       /*!< 0x10000000 */
8529 #define CAN_F7R1_FB28                        CAN_F7R1_FB28_Msk                 /*!< Filter bit 28 */
8530 #define CAN_F7R1_FB29_Pos                    (29U)
8531 #define CAN_F7R1_FB29_Msk                    (0x1UL << CAN_F7R1_FB29_Pos)       /*!< 0x20000000 */
8532 #define CAN_F7R1_FB29                        CAN_F7R1_FB29_Msk                 /*!< Filter bit 29 */
8533 #define CAN_F7R1_FB30_Pos                    (30U)
8534 #define CAN_F7R1_FB30_Msk                    (0x1UL << CAN_F7R1_FB30_Pos)       /*!< 0x40000000 */
8535 #define CAN_F7R1_FB30                        CAN_F7R1_FB30_Msk                 /*!< Filter bit 30 */
8536 #define CAN_F7R1_FB31_Pos                    (31U)
8537 #define CAN_F7R1_FB31_Msk                    (0x1UL << CAN_F7R1_FB31_Pos)       /*!< 0x80000000 */
8538 #define CAN_F7R1_FB31                        CAN_F7R1_FB31_Msk                 /*!< Filter bit 31 */
8539 
8540 /*******************  Bit definition for CAN_F8R1 register  *******************/
8541 #define CAN_F8R1_FB0_Pos                     (0U)
8542 #define CAN_F8R1_FB0_Msk                     (0x1UL << CAN_F8R1_FB0_Pos)        /*!< 0x00000001 */
8543 #define CAN_F8R1_FB0                         CAN_F8R1_FB0_Msk                  /*!< Filter bit 0 */
8544 #define CAN_F8R1_FB1_Pos                     (1U)
8545 #define CAN_F8R1_FB1_Msk                     (0x1UL << CAN_F8R1_FB1_Pos)        /*!< 0x00000002 */
8546 #define CAN_F8R1_FB1                         CAN_F8R1_FB1_Msk                  /*!< Filter bit 1 */
8547 #define CAN_F8R1_FB2_Pos                     (2U)
8548 #define CAN_F8R1_FB2_Msk                     (0x1UL << CAN_F8R1_FB2_Pos)        /*!< 0x00000004 */
8549 #define CAN_F8R1_FB2                         CAN_F8R1_FB2_Msk                  /*!< Filter bit 2 */
8550 #define CAN_F8R1_FB3_Pos                     (3U)
8551 #define CAN_F8R1_FB3_Msk                     (0x1UL << CAN_F8R1_FB3_Pos)        /*!< 0x00000008 */
8552 #define CAN_F8R1_FB3                         CAN_F8R1_FB3_Msk                  /*!< Filter bit 3 */
8553 #define CAN_F8R1_FB4_Pos                     (4U)
8554 #define CAN_F8R1_FB4_Msk                     (0x1UL << CAN_F8R1_FB4_Pos)        /*!< 0x00000010 */
8555 #define CAN_F8R1_FB4                         CAN_F8R1_FB4_Msk                  /*!< Filter bit 4 */
8556 #define CAN_F8R1_FB5_Pos                     (5U)
8557 #define CAN_F8R1_FB5_Msk                     (0x1UL << CAN_F8R1_FB5_Pos)        /*!< 0x00000020 */
8558 #define CAN_F8R1_FB5                         CAN_F8R1_FB5_Msk                  /*!< Filter bit 5 */
8559 #define CAN_F8R1_FB6_Pos                     (6U)
8560 #define CAN_F8R1_FB6_Msk                     (0x1UL << CAN_F8R1_FB6_Pos)        /*!< 0x00000040 */
8561 #define CAN_F8R1_FB6                         CAN_F8R1_FB6_Msk                  /*!< Filter bit 6 */
8562 #define CAN_F8R1_FB7_Pos                     (7U)
8563 #define CAN_F8R1_FB7_Msk                     (0x1UL << CAN_F8R1_FB7_Pos)        /*!< 0x00000080 */
8564 #define CAN_F8R1_FB7                         CAN_F8R1_FB7_Msk                  /*!< Filter bit 7 */
8565 #define CAN_F8R1_FB8_Pos                     (8U)
8566 #define CAN_F8R1_FB8_Msk                     (0x1UL << CAN_F8R1_FB8_Pos)        /*!< 0x00000100 */
8567 #define CAN_F8R1_FB8                         CAN_F8R1_FB8_Msk                  /*!< Filter bit 8 */
8568 #define CAN_F8R1_FB9_Pos                     (9U)
8569 #define CAN_F8R1_FB9_Msk                     (0x1UL << CAN_F8R1_FB9_Pos)        /*!< 0x00000200 */
8570 #define CAN_F8R1_FB9                         CAN_F8R1_FB9_Msk                  /*!< Filter bit 9 */
8571 #define CAN_F8R1_FB10_Pos                    (10U)
8572 #define CAN_F8R1_FB10_Msk                    (0x1UL << CAN_F8R1_FB10_Pos)       /*!< 0x00000400 */
8573 #define CAN_F8R1_FB10                        CAN_F8R1_FB10_Msk                 /*!< Filter bit 10 */
8574 #define CAN_F8R1_FB11_Pos                    (11U)
8575 #define CAN_F8R1_FB11_Msk                    (0x1UL << CAN_F8R1_FB11_Pos)       /*!< 0x00000800 */
8576 #define CAN_F8R1_FB11                        CAN_F8R1_FB11_Msk                 /*!< Filter bit 11 */
8577 #define CAN_F8R1_FB12_Pos                    (12U)
8578 #define CAN_F8R1_FB12_Msk                    (0x1UL << CAN_F8R1_FB12_Pos)       /*!< 0x00001000 */
8579 #define CAN_F8R1_FB12                        CAN_F8R1_FB12_Msk                 /*!< Filter bit 12 */
8580 #define CAN_F8R1_FB13_Pos                    (13U)
8581 #define CAN_F8R1_FB13_Msk                    (0x1UL << CAN_F8R1_FB13_Pos)       /*!< 0x00002000 */
8582 #define CAN_F8R1_FB13                        CAN_F8R1_FB13_Msk                 /*!< Filter bit 13 */
8583 #define CAN_F8R1_FB14_Pos                    (14U)
8584 #define CAN_F8R1_FB14_Msk                    (0x1UL << CAN_F8R1_FB14_Pos)       /*!< 0x00004000 */
8585 #define CAN_F8R1_FB14                        CAN_F8R1_FB14_Msk                 /*!< Filter bit 14 */
8586 #define CAN_F8R1_FB15_Pos                    (15U)
8587 #define CAN_F8R1_FB15_Msk                    (0x1UL << CAN_F8R1_FB15_Pos)       /*!< 0x00008000 */
8588 #define CAN_F8R1_FB15                        CAN_F8R1_FB15_Msk                 /*!< Filter bit 15 */
8589 #define CAN_F8R1_FB16_Pos                    (16U)
8590 #define CAN_F8R1_FB16_Msk                    (0x1UL << CAN_F8R1_FB16_Pos)       /*!< 0x00010000 */
8591 #define CAN_F8R1_FB16                        CAN_F8R1_FB16_Msk                 /*!< Filter bit 16 */
8592 #define CAN_F8R1_FB17_Pos                    (17U)
8593 #define CAN_F8R1_FB17_Msk                    (0x1UL << CAN_F8R1_FB17_Pos)       /*!< 0x00020000 */
8594 #define CAN_F8R1_FB17                        CAN_F8R1_FB17_Msk                 /*!< Filter bit 17 */
8595 #define CAN_F8R1_FB18_Pos                    (18U)
8596 #define CAN_F8R1_FB18_Msk                    (0x1UL << CAN_F8R1_FB18_Pos)       /*!< 0x00040000 */
8597 #define CAN_F8R1_FB18                        CAN_F8R1_FB18_Msk                 /*!< Filter bit 18 */
8598 #define CAN_F8R1_FB19_Pos                    (19U)
8599 #define CAN_F8R1_FB19_Msk                    (0x1UL << CAN_F8R1_FB19_Pos)       /*!< 0x00080000 */
8600 #define CAN_F8R1_FB19                        CAN_F8R1_FB19_Msk                 /*!< Filter bit 19 */
8601 #define CAN_F8R1_FB20_Pos                    (20U)
8602 #define CAN_F8R1_FB20_Msk                    (0x1UL << CAN_F8R1_FB20_Pos)       /*!< 0x00100000 */
8603 #define CAN_F8R1_FB20                        CAN_F8R1_FB20_Msk                 /*!< Filter bit 20 */
8604 #define CAN_F8R1_FB21_Pos                    (21U)
8605 #define CAN_F8R1_FB21_Msk                    (0x1UL << CAN_F8R1_FB21_Pos)       /*!< 0x00200000 */
8606 #define CAN_F8R1_FB21                        CAN_F8R1_FB21_Msk                 /*!< Filter bit 21 */
8607 #define CAN_F8R1_FB22_Pos                    (22U)
8608 #define CAN_F8R1_FB22_Msk                    (0x1UL << CAN_F8R1_FB22_Pos)       /*!< 0x00400000 */
8609 #define CAN_F8R1_FB22                        CAN_F8R1_FB22_Msk                 /*!< Filter bit 22 */
8610 #define CAN_F8R1_FB23_Pos                    (23U)
8611 #define CAN_F8R1_FB23_Msk                    (0x1UL << CAN_F8R1_FB23_Pos)       /*!< 0x00800000 */
8612 #define CAN_F8R1_FB23                        CAN_F8R1_FB23_Msk                 /*!< Filter bit 23 */
8613 #define CAN_F8R1_FB24_Pos                    (24U)
8614 #define CAN_F8R1_FB24_Msk                    (0x1UL << CAN_F8R1_FB24_Pos)       /*!< 0x01000000 */
8615 #define CAN_F8R1_FB24                        CAN_F8R1_FB24_Msk                 /*!< Filter bit 24 */
8616 #define CAN_F8R1_FB25_Pos                    (25U)
8617 #define CAN_F8R1_FB25_Msk                    (0x1UL << CAN_F8R1_FB25_Pos)       /*!< 0x02000000 */
8618 #define CAN_F8R1_FB25                        CAN_F8R1_FB25_Msk                 /*!< Filter bit 25 */
8619 #define CAN_F8R1_FB26_Pos                    (26U)
8620 #define CAN_F8R1_FB26_Msk                    (0x1UL << CAN_F8R1_FB26_Pos)       /*!< 0x04000000 */
8621 #define CAN_F8R1_FB26                        CAN_F8R1_FB26_Msk                 /*!< Filter bit 26 */
8622 #define CAN_F8R1_FB27_Pos                    (27U)
8623 #define CAN_F8R1_FB27_Msk                    (0x1UL << CAN_F8R1_FB27_Pos)       /*!< 0x08000000 */
8624 #define CAN_F8R1_FB27                        CAN_F8R1_FB27_Msk                 /*!< Filter bit 27 */
8625 #define CAN_F8R1_FB28_Pos                    (28U)
8626 #define CAN_F8R1_FB28_Msk                    (0x1UL << CAN_F8R1_FB28_Pos)       /*!< 0x10000000 */
8627 #define CAN_F8R1_FB28                        CAN_F8R1_FB28_Msk                 /*!< Filter bit 28 */
8628 #define CAN_F8R1_FB29_Pos                    (29U)
8629 #define CAN_F8R1_FB29_Msk                    (0x1UL << CAN_F8R1_FB29_Pos)       /*!< 0x20000000 */
8630 #define CAN_F8R1_FB29                        CAN_F8R1_FB29_Msk                 /*!< Filter bit 29 */
8631 #define CAN_F8R1_FB30_Pos                    (30U)
8632 #define CAN_F8R1_FB30_Msk                    (0x1UL << CAN_F8R1_FB30_Pos)       /*!< 0x40000000 */
8633 #define CAN_F8R1_FB30                        CAN_F8R1_FB30_Msk                 /*!< Filter bit 30 */
8634 #define CAN_F8R1_FB31_Pos                    (31U)
8635 #define CAN_F8R1_FB31_Msk                    (0x1UL << CAN_F8R1_FB31_Pos)       /*!< 0x80000000 */
8636 #define CAN_F8R1_FB31                        CAN_F8R1_FB31_Msk                 /*!< Filter bit 31 */
8637 
8638 /*******************  Bit definition for CAN_F9R1 register  *******************/
8639 #define CAN_F9R1_FB0_Pos                     (0U)
8640 #define CAN_F9R1_FB0_Msk                     (0x1UL << CAN_F9R1_FB0_Pos)        /*!< 0x00000001 */
8641 #define CAN_F9R1_FB0                         CAN_F9R1_FB0_Msk                  /*!< Filter bit 0 */
8642 #define CAN_F9R1_FB1_Pos                     (1U)
8643 #define CAN_F9R1_FB1_Msk                     (0x1UL << CAN_F9R1_FB1_Pos)        /*!< 0x00000002 */
8644 #define CAN_F9R1_FB1                         CAN_F9R1_FB1_Msk                  /*!< Filter bit 1 */
8645 #define CAN_F9R1_FB2_Pos                     (2U)
8646 #define CAN_F9R1_FB2_Msk                     (0x1UL << CAN_F9R1_FB2_Pos)        /*!< 0x00000004 */
8647 #define CAN_F9R1_FB2                         CAN_F9R1_FB2_Msk                  /*!< Filter bit 2 */
8648 #define CAN_F9R1_FB3_Pos                     (3U)
8649 #define CAN_F9R1_FB3_Msk                     (0x1UL << CAN_F9R1_FB3_Pos)        /*!< 0x00000008 */
8650 #define CAN_F9R1_FB3                         CAN_F9R1_FB3_Msk                  /*!< Filter bit 3 */
8651 #define CAN_F9R1_FB4_Pos                     (4U)
8652 #define CAN_F9R1_FB4_Msk                     (0x1UL << CAN_F9R1_FB4_Pos)        /*!< 0x00000010 */
8653 #define CAN_F9R1_FB4                         CAN_F9R1_FB4_Msk                  /*!< Filter bit 4 */
8654 #define CAN_F9R1_FB5_Pos                     (5U)
8655 #define CAN_F9R1_FB5_Msk                     (0x1UL << CAN_F9R1_FB5_Pos)        /*!< 0x00000020 */
8656 #define CAN_F9R1_FB5                         CAN_F9R1_FB5_Msk                  /*!< Filter bit 5 */
8657 #define CAN_F9R1_FB6_Pos                     (6U)
8658 #define CAN_F9R1_FB6_Msk                     (0x1UL << CAN_F9R1_FB6_Pos)        /*!< 0x00000040 */
8659 #define CAN_F9R1_FB6                         CAN_F9R1_FB6_Msk                  /*!< Filter bit 6 */
8660 #define CAN_F9R1_FB7_Pos                     (7U)
8661 #define CAN_F9R1_FB7_Msk                     (0x1UL << CAN_F9R1_FB7_Pos)        /*!< 0x00000080 */
8662 #define CAN_F9R1_FB7                         CAN_F9R1_FB7_Msk                  /*!< Filter bit 7 */
8663 #define CAN_F9R1_FB8_Pos                     (8U)
8664 #define CAN_F9R1_FB8_Msk                     (0x1UL << CAN_F9R1_FB8_Pos)        /*!< 0x00000100 */
8665 #define CAN_F9R1_FB8                         CAN_F9R1_FB8_Msk                  /*!< Filter bit 8 */
8666 #define CAN_F9R1_FB9_Pos                     (9U)
8667 #define CAN_F9R1_FB9_Msk                     (0x1UL << CAN_F9R1_FB9_Pos)        /*!< 0x00000200 */
8668 #define CAN_F9R1_FB9                         CAN_F9R1_FB9_Msk                  /*!< Filter bit 9 */
8669 #define CAN_F9R1_FB10_Pos                    (10U)
8670 #define CAN_F9R1_FB10_Msk                    (0x1UL << CAN_F9R1_FB10_Pos)       /*!< 0x00000400 */
8671 #define CAN_F9R1_FB10                        CAN_F9R1_FB10_Msk                 /*!< Filter bit 10 */
8672 #define CAN_F9R1_FB11_Pos                    (11U)
8673 #define CAN_F9R1_FB11_Msk                    (0x1UL << CAN_F9R1_FB11_Pos)       /*!< 0x00000800 */
8674 #define CAN_F9R1_FB11                        CAN_F9R1_FB11_Msk                 /*!< Filter bit 11 */
8675 #define CAN_F9R1_FB12_Pos                    (12U)
8676 #define CAN_F9R1_FB12_Msk                    (0x1UL << CAN_F9R1_FB12_Pos)       /*!< 0x00001000 */
8677 #define CAN_F9R1_FB12                        CAN_F9R1_FB12_Msk                 /*!< Filter bit 12 */
8678 #define CAN_F9R1_FB13_Pos                    (13U)
8679 #define CAN_F9R1_FB13_Msk                    (0x1UL << CAN_F9R1_FB13_Pos)       /*!< 0x00002000 */
8680 #define CAN_F9R1_FB13                        CAN_F9R1_FB13_Msk                 /*!< Filter bit 13 */
8681 #define CAN_F9R1_FB14_Pos                    (14U)
8682 #define CAN_F9R1_FB14_Msk                    (0x1UL << CAN_F9R1_FB14_Pos)       /*!< 0x00004000 */
8683 #define CAN_F9R1_FB14                        CAN_F9R1_FB14_Msk                 /*!< Filter bit 14 */
8684 #define CAN_F9R1_FB15_Pos                    (15U)
8685 #define CAN_F9R1_FB15_Msk                    (0x1UL << CAN_F9R1_FB15_Pos)       /*!< 0x00008000 */
8686 #define CAN_F9R1_FB15                        CAN_F9R1_FB15_Msk                 /*!< Filter bit 15 */
8687 #define CAN_F9R1_FB16_Pos                    (16U)
8688 #define CAN_F9R1_FB16_Msk                    (0x1UL << CAN_F9R1_FB16_Pos)       /*!< 0x00010000 */
8689 #define CAN_F9R1_FB16                        CAN_F9R1_FB16_Msk                 /*!< Filter bit 16 */
8690 #define CAN_F9R1_FB17_Pos                    (17U)
8691 #define CAN_F9R1_FB17_Msk                    (0x1UL << CAN_F9R1_FB17_Pos)       /*!< 0x00020000 */
8692 #define CAN_F9R1_FB17                        CAN_F9R1_FB17_Msk                 /*!< Filter bit 17 */
8693 #define CAN_F9R1_FB18_Pos                    (18U)
8694 #define CAN_F9R1_FB18_Msk                    (0x1UL << CAN_F9R1_FB18_Pos)       /*!< 0x00040000 */
8695 #define CAN_F9R1_FB18                        CAN_F9R1_FB18_Msk                 /*!< Filter bit 18 */
8696 #define CAN_F9R1_FB19_Pos                    (19U)
8697 #define CAN_F9R1_FB19_Msk                    (0x1UL << CAN_F9R1_FB19_Pos)       /*!< 0x00080000 */
8698 #define CAN_F9R1_FB19                        CAN_F9R1_FB19_Msk                 /*!< Filter bit 19 */
8699 #define CAN_F9R1_FB20_Pos                    (20U)
8700 #define CAN_F9R1_FB20_Msk                    (0x1UL << CAN_F9R1_FB20_Pos)       /*!< 0x00100000 */
8701 #define CAN_F9R1_FB20                        CAN_F9R1_FB20_Msk                 /*!< Filter bit 20 */
8702 #define CAN_F9R1_FB21_Pos                    (21U)
8703 #define CAN_F9R1_FB21_Msk                    (0x1UL << CAN_F9R1_FB21_Pos)       /*!< 0x00200000 */
8704 #define CAN_F9R1_FB21                        CAN_F9R1_FB21_Msk                 /*!< Filter bit 21 */
8705 #define CAN_F9R1_FB22_Pos                    (22U)
8706 #define CAN_F9R1_FB22_Msk                    (0x1UL << CAN_F9R1_FB22_Pos)       /*!< 0x00400000 */
8707 #define CAN_F9R1_FB22                        CAN_F9R1_FB22_Msk                 /*!< Filter bit 22 */
8708 #define CAN_F9R1_FB23_Pos                    (23U)
8709 #define CAN_F9R1_FB23_Msk                    (0x1UL << CAN_F9R1_FB23_Pos)       /*!< 0x00800000 */
8710 #define CAN_F9R1_FB23                        CAN_F9R1_FB23_Msk                 /*!< Filter bit 23 */
8711 #define CAN_F9R1_FB24_Pos                    (24U)
8712 #define CAN_F9R1_FB24_Msk                    (0x1UL << CAN_F9R1_FB24_Pos)       /*!< 0x01000000 */
8713 #define CAN_F9R1_FB24                        CAN_F9R1_FB24_Msk                 /*!< Filter bit 24 */
8714 #define CAN_F9R1_FB25_Pos                    (25U)
8715 #define CAN_F9R1_FB25_Msk                    (0x1UL << CAN_F9R1_FB25_Pos)       /*!< 0x02000000 */
8716 #define CAN_F9R1_FB25                        CAN_F9R1_FB25_Msk                 /*!< Filter bit 25 */
8717 #define CAN_F9R1_FB26_Pos                    (26U)
8718 #define CAN_F9R1_FB26_Msk                    (0x1UL << CAN_F9R1_FB26_Pos)       /*!< 0x04000000 */
8719 #define CAN_F9R1_FB26                        CAN_F9R1_FB26_Msk                 /*!< Filter bit 26 */
8720 #define CAN_F9R1_FB27_Pos                    (27U)
8721 #define CAN_F9R1_FB27_Msk                    (0x1UL << CAN_F9R1_FB27_Pos)       /*!< 0x08000000 */
8722 #define CAN_F9R1_FB27                        CAN_F9R1_FB27_Msk                 /*!< Filter bit 27 */
8723 #define CAN_F9R1_FB28_Pos                    (28U)
8724 #define CAN_F9R1_FB28_Msk                    (0x1UL << CAN_F9R1_FB28_Pos)       /*!< 0x10000000 */
8725 #define CAN_F9R1_FB28                        CAN_F9R1_FB28_Msk                 /*!< Filter bit 28 */
8726 #define CAN_F9R1_FB29_Pos                    (29U)
8727 #define CAN_F9R1_FB29_Msk                    (0x1UL << CAN_F9R1_FB29_Pos)       /*!< 0x20000000 */
8728 #define CAN_F9R1_FB29                        CAN_F9R1_FB29_Msk                 /*!< Filter bit 29 */
8729 #define CAN_F9R1_FB30_Pos                    (30U)
8730 #define CAN_F9R1_FB30_Msk                    (0x1UL << CAN_F9R1_FB30_Pos)       /*!< 0x40000000 */
8731 #define CAN_F9R1_FB30                        CAN_F9R1_FB30_Msk                 /*!< Filter bit 30 */
8732 #define CAN_F9R1_FB31_Pos                    (31U)
8733 #define CAN_F9R1_FB31_Msk                    (0x1UL << CAN_F9R1_FB31_Pos)       /*!< 0x80000000 */
8734 #define CAN_F9R1_FB31                        CAN_F9R1_FB31_Msk                 /*!< Filter bit 31 */
8735 
8736 /*******************  Bit definition for CAN_F10R1 register  ******************/
8737 #define CAN_F10R1_FB0_Pos                    (0U)
8738 #define CAN_F10R1_FB0_Msk                    (0x1UL << CAN_F10R1_FB0_Pos)       /*!< 0x00000001 */
8739 #define CAN_F10R1_FB0                        CAN_F10R1_FB0_Msk                 /*!< Filter bit 0 */
8740 #define CAN_F10R1_FB1_Pos                    (1U)
8741 #define CAN_F10R1_FB1_Msk                    (0x1UL << CAN_F10R1_FB1_Pos)       /*!< 0x00000002 */
8742 #define CAN_F10R1_FB1                        CAN_F10R1_FB1_Msk                 /*!< Filter bit 1 */
8743 #define CAN_F10R1_FB2_Pos                    (2U)
8744 #define CAN_F10R1_FB2_Msk                    (0x1UL << CAN_F10R1_FB2_Pos)       /*!< 0x00000004 */
8745 #define CAN_F10R1_FB2                        CAN_F10R1_FB2_Msk                 /*!< Filter bit 2 */
8746 #define CAN_F10R1_FB3_Pos                    (3U)
8747 #define CAN_F10R1_FB3_Msk                    (0x1UL << CAN_F10R1_FB3_Pos)       /*!< 0x00000008 */
8748 #define CAN_F10R1_FB3                        CAN_F10R1_FB3_Msk                 /*!< Filter bit 3 */
8749 #define CAN_F10R1_FB4_Pos                    (4U)
8750 #define CAN_F10R1_FB4_Msk                    (0x1UL << CAN_F10R1_FB4_Pos)       /*!< 0x00000010 */
8751 #define CAN_F10R1_FB4                        CAN_F10R1_FB4_Msk                 /*!< Filter bit 4 */
8752 #define CAN_F10R1_FB5_Pos                    (5U)
8753 #define CAN_F10R1_FB5_Msk                    (0x1UL << CAN_F10R1_FB5_Pos)       /*!< 0x00000020 */
8754 #define CAN_F10R1_FB5                        CAN_F10R1_FB5_Msk                 /*!< Filter bit 5 */
8755 #define CAN_F10R1_FB6_Pos                    (6U)
8756 #define CAN_F10R1_FB6_Msk                    (0x1UL << CAN_F10R1_FB6_Pos)       /*!< 0x00000040 */
8757 #define CAN_F10R1_FB6                        CAN_F10R1_FB6_Msk                 /*!< Filter bit 6 */
8758 #define CAN_F10R1_FB7_Pos                    (7U)
8759 #define CAN_F10R1_FB7_Msk                    (0x1UL << CAN_F10R1_FB7_Pos)       /*!< 0x00000080 */
8760 #define CAN_F10R1_FB7                        CAN_F10R1_FB7_Msk                 /*!< Filter bit 7 */
8761 #define CAN_F10R1_FB8_Pos                    (8U)
8762 #define CAN_F10R1_FB8_Msk                    (0x1UL << CAN_F10R1_FB8_Pos)       /*!< 0x00000100 */
8763 #define CAN_F10R1_FB8                        CAN_F10R1_FB8_Msk                 /*!< Filter bit 8 */
8764 #define CAN_F10R1_FB9_Pos                    (9U)
8765 #define CAN_F10R1_FB9_Msk                    (0x1UL << CAN_F10R1_FB9_Pos)       /*!< 0x00000200 */
8766 #define CAN_F10R1_FB9                        CAN_F10R1_FB9_Msk                 /*!< Filter bit 9 */
8767 #define CAN_F10R1_FB10_Pos                   (10U)
8768 #define CAN_F10R1_FB10_Msk                   (0x1UL << CAN_F10R1_FB10_Pos)      /*!< 0x00000400 */
8769 #define CAN_F10R1_FB10                       CAN_F10R1_FB10_Msk                /*!< Filter bit 10 */
8770 #define CAN_F10R1_FB11_Pos                   (11U)
8771 #define CAN_F10R1_FB11_Msk                   (0x1UL << CAN_F10R1_FB11_Pos)      /*!< 0x00000800 */
8772 #define CAN_F10R1_FB11                       CAN_F10R1_FB11_Msk                /*!< Filter bit 11 */
8773 #define CAN_F10R1_FB12_Pos                   (12U)
8774 #define CAN_F10R1_FB12_Msk                   (0x1UL << CAN_F10R1_FB12_Pos)      /*!< 0x00001000 */
8775 #define CAN_F10R1_FB12                       CAN_F10R1_FB12_Msk                /*!< Filter bit 12 */
8776 #define CAN_F10R1_FB13_Pos                   (13U)
8777 #define CAN_F10R1_FB13_Msk                   (0x1UL << CAN_F10R1_FB13_Pos)      /*!< 0x00002000 */
8778 #define CAN_F10R1_FB13                       CAN_F10R1_FB13_Msk                /*!< Filter bit 13 */
8779 #define CAN_F10R1_FB14_Pos                   (14U)
8780 #define CAN_F10R1_FB14_Msk                   (0x1UL << CAN_F10R1_FB14_Pos)      /*!< 0x00004000 */
8781 #define CAN_F10R1_FB14                       CAN_F10R1_FB14_Msk                /*!< Filter bit 14 */
8782 #define CAN_F10R1_FB15_Pos                   (15U)
8783 #define CAN_F10R1_FB15_Msk                   (0x1UL << CAN_F10R1_FB15_Pos)      /*!< 0x00008000 */
8784 #define CAN_F10R1_FB15                       CAN_F10R1_FB15_Msk                /*!< Filter bit 15 */
8785 #define CAN_F10R1_FB16_Pos                   (16U)
8786 #define CAN_F10R1_FB16_Msk                   (0x1UL << CAN_F10R1_FB16_Pos)      /*!< 0x00010000 */
8787 #define CAN_F10R1_FB16                       CAN_F10R1_FB16_Msk                /*!< Filter bit 16 */
8788 #define CAN_F10R1_FB17_Pos                   (17U)
8789 #define CAN_F10R1_FB17_Msk                   (0x1UL << CAN_F10R1_FB17_Pos)      /*!< 0x00020000 */
8790 #define CAN_F10R1_FB17                       CAN_F10R1_FB17_Msk                /*!< Filter bit 17 */
8791 #define CAN_F10R1_FB18_Pos                   (18U)
8792 #define CAN_F10R1_FB18_Msk                   (0x1UL << CAN_F10R1_FB18_Pos)      /*!< 0x00040000 */
8793 #define CAN_F10R1_FB18                       CAN_F10R1_FB18_Msk                /*!< Filter bit 18 */
8794 #define CAN_F10R1_FB19_Pos                   (19U)
8795 #define CAN_F10R1_FB19_Msk                   (0x1UL << CAN_F10R1_FB19_Pos)      /*!< 0x00080000 */
8796 #define CAN_F10R1_FB19                       CAN_F10R1_FB19_Msk                /*!< Filter bit 19 */
8797 #define CAN_F10R1_FB20_Pos                   (20U)
8798 #define CAN_F10R1_FB20_Msk                   (0x1UL << CAN_F10R1_FB20_Pos)      /*!< 0x00100000 */
8799 #define CAN_F10R1_FB20                       CAN_F10R1_FB20_Msk                /*!< Filter bit 20 */
8800 #define CAN_F10R1_FB21_Pos                   (21U)
8801 #define CAN_F10R1_FB21_Msk                   (0x1UL << CAN_F10R1_FB21_Pos)      /*!< 0x00200000 */
8802 #define CAN_F10R1_FB21                       CAN_F10R1_FB21_Msk                /*!< Filter bit 21 */
8803 #define CAN_F10R1_FB22_Pos                   (22U)
8804 #define CAN_F10R1_FB22_Msk                   (0x1UL << CAN_F10R1_FB22_Pos)      /*!< 0x00400000 */
8805 #define CAN_F10R1_FB22                       CAN_F10R1_FB22_Msk                /*!< Filter bit 22 */
8806 #define CAN_F10R1_FB23_Pos                   (23U)
8807 #define CAN_F10R1_FB23_Msk                   (0x1UL << CAN_F10R1_FB23_Pos)      /*!< 0x00800000 */
8808 #define CAN_F10R1_FB23                       CAN_F10R1_FB23_Msk                /*!< Filter bit 23 */
8809 #define CAN_F10R1_FB24_Pos                   (24U)
8810 #define CAN_F10R1_FB24_Msk                   (0x1UL << CAN_F10R1_FB24_Pos)      /*!< 0x01000000 */
8811 #define CAN_F10R1_FB24                       CAN_F10R1_FB24_Msk                /*!< Filter bit 24 */
8812 #define CAN_F10R1_FB25_Pos                   (25U)
8813 #define CAN_F10R1_FB25_Msk                   (0x1UL << CAN_F10R1_FB25_Pos)      /*!< 0x02000000 */
8814 #define CAN_F10R1_FB25                       CAN_F10R1_FB25_Msk                /*!< Filter bit 25 */
8815 #define CAN_F10R1_FB26_Pos                   (26U)
8816 #define CAN_F10R1_FB26_Msk                   (0x1UL << CAN_F10R1_FB26_Pos)      /*!< 0x04000000 */
8817 #define CAN_F10R1_FB26                       CAN_F10R1_FB26_Msk                /*!< Filter bit 26 */
8818 #define CAN_F10R1_FB27_Pos                   (27U)
8819 #define CAN_F10R1_FB27_Msk                   (0x1UL << CAN_F10R1_FB27_Pos)      /*!< 0x08000000 */
8820 #define CAN_F10R1_FB27                       CAN_F10R1_FB27_Msk                /*!< Filter bit 27 */
8821 #define CAN_F10R1_FB28_Pos                   (28U)
8822 #define CAN_F10R1_FB28_Msk                   (0x1UL << CAN_F10R1_FB28_Pos)      /*!< 0x10000000 */
8823 #define CAN_F10R1_FB28                       CAN_F10R1_FB28_Msk                /*!< Filter bit 28 */
8824 #define CAN_F10R1_FB29_Pos                   (29U)
8825 #define CAN_F10R1_FB29_Msk                   (0x1UL << CAN_F10R1_FB29_Pos)      /*!< 0x20000000 */
8826 #define CAN_F10R1_FB29                       CAN_F10R1_FB29_Msk                /*!< Filter bit 29 */
8827 #define CAN_F10R1_FB30_Pos                   (30U)
8828 #define CAN_F10R1_FB30_Msk                   (0x1UL << CAN_F10R1_FB30_Pos)      /*!< 0x40000000 */
8829 #define CAN_F10R1_FB30                       CAN_F10R1_FB30_Msk                /*!< Filter bit 30 */
8830 #define CAN_F10R1_FB31_Pos                   (31U)
8831 #define CAN_F10R1_FB31_Msk                   (0x1UL << CAN_F10R1_FB31_Pos)      /*!< 0x80000000 */
8832 #define CAN_F10R1_FB31                       CAN_F10R1_FB31_Msk                /*!< Filter bit 31 */
8833 
8834 /*******************  Bit definition for CAN_F11R1 register  ******************/
8835 #define CAN_F11R1_FB0_Pos                    (0U)
8836 #define CAN_F11R1_FB0_Msk                    (0x1UL << CAN_F11R1_FB0_Pos)       /*!< 0x00000001 */
8837 #define CAN_F11R1_FB0                        CAN_F11R1_FB0_Msk                 /*!< Filter bit 0 */
8838 #define CAN_F11R1_FB1_Pos                    (1U)
8839 #define CAN_F11R1_FB1_Msk                    (0x1UL << CAN_F11R1_FB1_Pos)       /*!< 0x00000002 */
8840 #define CAN_F11R1_FB1                        CAN_F11R1_FB1_Msk                 /*!< Filter bit 1 */
8841 #define CAN_F11R1_FB2_Pos                    (2U)
8842 #define CAN_F11R1_FB2_Msk                    (0x1UL << CAN_F11R1_FB2_Pos)       /*!< 0x00000004 */
8843 #define CAN_F11R1_FB2                        CAN_F11R1_FB2_Msk                 /*!< Filter bit 2 */
8844 #define CAN_F11R1_FB3_Pos                    (3U)
8845 #define CAN_F11R1_FB3_Msk                    (0x1UL << CAN_F11R1_FB3_Pos)       /*!< 0x00000008 */
8846 #define CAN_F11R1_FB3                        CAN_F11R1_FB3_Msk                 /*!< Filter bit 3 */
8847 #define CAN_F11R1_FB4_Pos                    (4U)
8848 #define CAN_F11R1_FB4_Msk                    (0x1UL << CAN_F11R1_FB4_Pos)       /*!< 0x00000010 */
8849 #define CAN_F11R1_FB4                        CAN_F11R1_FB4_Msk                 /*!< Filter bit 4 */
8850 #define CAN_F11R1_FB5_Pos                    (5U)
8851 #define CAN_F11R1_FB5_Msk                    (0x1UL << CAN_F11R1_FB5_Pos)       /*!< 0x00000020 */
8852 #define CAN_F11R1_FB5                        CAN_F11R1_FB5_Msk                 /*!< Filter bit 5 */
8853 #define CAN_F11R1_FB6_Pos                    (6U)
8854 #define CAN_F11R1_FB6_Msk                    (0x1UL << CAN_F11R1_FB6_Pos)       /*!< 0x00000040 */
8855 #define CAN_F11R1_FB6                        CAN_F11R1_FB6_Msk                 /*!< Filter bit 6 */
8856 #define CAN_F11R1_FB7_Pos                    (7U)
8857 #define CAN_F11R1_FB7_Msk                    (0x1UL << CAN_F11R1_FB7_Pos)       /*!< 0x00000080 */
8858 #define CAN_F11R1_FB7                        CAN_F11R1_FB7_Msk                 /*!< Filter bit 7 */
8859 #define CAN_F11R1_FB8_Pos                    (8U)
8860 #define CAN_F11R1_FB8_Msk                    (0x1UL << CAN_F11R1_FB8_Pos)       /*!< 0x00000100 */
8861 #define CAN_F11R1_FB8                        CAN_F11R1_FB8_Msk                 /*!< Filter bit 8 */
8862 #define CAN_F11R1_FB9_Pos                    (9U)
8863 #define CAN_F11R1_FB9_Msk                    (0x1UL << CAN_F11R1_FB9_Pos)       /*!< 0x00000200 */
8864 #define CAN_F11R1_FB9                        CAN_F11R1_FB9_Msk                 /*!< Filter bit 9 */
8865 #define CAN_F11R1_FB10_Pos                   (10U)
8866 #define CAN_F11R1_FB10_Msk                   (0x1UL << CAN_F11R1_FB10_Pos)      /*!< 0x00000400 */
8867 #define CAN_F11R1_FB10                       CAN_F11R1_FB10_Msk                /*!< Filter bit 10 */
8868 #define CAN_F11R1_FB11_Pos                   (11U)
8869 #define CAN_F11R1_FB11_Msk                   (0x1UL << CAN_F11R1_FB11_Pos)      /*!< 0x00000800 */
8870 #define CAN_F11R1_FB11                       CAN_F11R1_FB11_Msk                /*!< Filter bit 11 */
8871 #define CAN_F11R1_FB12_Pos                   (12U)
8872 #define CAN_F11R1_FB12_Msk                   (0x1UL << CAN_F11R1_FB12_Pos)      /*!< 0x00001000 */
8873 #define CAN_F11R1_FB12                       CAN_F11R1_FB12_Msk                /*!< Filter bit 12 */
8874 #define CAN_F11R1_FB13_Pos                   (13U)
8875 #define CAN_F11R1_FB13_Msk                   (0x1UL << CAN_F11R1_FB13_Pos)      /*!< 0x00002000 */
8876 #define CAN_F11R1_FB13                       CAN_F11R1_FB13_Msk                /*!< Filter bit 13 */
8877 #define CAN_F11R1_FB14_Pos                   (14U)
8878 #define CAN_F11R1_FB14_Msk                   (0x1UL << CAN_F11R1_FB14_Pos)      /*!< 0x00004000 */
8879 #define CAN_F11R1_FB14                       CAN_F11R1_FB14_Msk                /*!< Filter bit 14 */
8880 #define CAN_F11R1_FB15_Pos                   (15U)
8881 #define CAN_F11R1_FB15_Msk                   (0x1UL << CAN_F11R1_FB15_Pos)      /*!< 0x00008000 */
8882 #define CAN_F11R1_FB15                       CAN_F11R1_FB15_Msk                /*!< Filter bit 15 */
8883 #define CAN_F11R1_FB16_Pos                   (16U)
8884 #define CAN_F11R1_FB16_Msk                   (0x1UL << CAN_F11R1_FB16_Pos)      /*!< 0x00010000 */
8885 #define CAN_F11R1_FB16                       CAN_F11R1_FB16_Msk                /*!< Filter bit 16 */
8886 #define CAN_F11R1_FB17_Pos                   (17U)
8887 #define CAN_F11R1_FB17_Msk                   (0x1UL << CAN_F11R1_FB17_Pos)      /*!< 0x00020000 */
8888 #define CAN_F11R1_FB17                       CAN_F11R1_FB17_Msk                /*!< Filter bit 17 */
8889 #define CAN_F11R1_FB18_Pos                   (18U)
8890 #define CAN_F11R1_FB18_Msk                   (0x1UL << CAN_F11R1_FB18_Pos)      /*!< 0x00040000 */
8891 #define CAN_F11R1_FB18                       CAN_F11R1_FB18_Msk                /*!< Filter bit 18 */
8892 #define CAN_F11R1_FB19_Pos                   (19U)
8893 #define CAN_F11R1_FB19_Msk                   (0x1UL << CAN_F11R1_FB19_Pos)      /*!< 0x00080000 */
8894 #define CAN_F11R1_FB19                       CAN_F11R1_FB19_Msk                /*!< Filter bit 19 */
8895 #define CAN_F11R1_FB20_Pos                   (20U)
8896 #define CAN_F11R1_FB20_Msk                   (0x1UL << CAN_F11R1_FB20_Pos)      /*!< 0x00100000 */
8897 #define CAN_F11R1_FB20                       CAN_F11R1_FB20_Msk                /*!< Filter bit 20 */
8898 #define CAN_F11R1_FB21_Pos                   (21U)
8899 #define CAN_F11R1_FB21_Msk                   (0x1UL << CAN_F11R1_FB21_Pos)      /*!< 0x00200000 */
8900 #define CAN_F11R1_FB21                       CAN_F11R1_FB21_Msk                /*!< Filter bit 21 */
8901 #define CAN_F11R1_FB22_Pos                   (22U)
8902 #define CAN_F11R1_FB22_Msk                   (0x1UL << CAN_F11R1_FB22_Pos)      /*!< 0x00400000 */
8903 #define CAN_F11R1_FB22                       CAN_F11R1_FB22_Msk                /*!< Filter bit 22 */
8904 #define CAN_F11R1_FB23_Pos                   (23U)
8905 #define CAN_F11R1_FB23_Msk                   (0x1UL << CAN_F11R1_FB23_Pos)      /*!< 0x00800000 */
8906 #define CAN_F11R1_FB23                       CAN_F11R1_FB23_Msk                /*!< Filter bit 23 */
8907 #define CAN_F11R1_FB24_Pos                   (24U)
8908 #define CAN_F11R1_FB24_Msk                   (0x1UL << CAN_F11R1_FB24_Pos)      /*!< 0x01000000 */
8909 #define CAN_F11R1_FB24                       CAN_F11R1_FB24_Msk                /*!< Filter bit 24 */
8910 #define CAN_F11R1_FB25_Pos                   (25U)
8911 #define CAN_F11R1_FB25_Msk                   (0x1UL << CAN_F11R1_FB25_Pos)      /*!< 0x02000000 */
8912 #define CAN_F11R1_FB25                       CAN_F11R1_FB25_Msk                /*!< Filter bit 25 */
8913 #define CAN_F11R1_FB26_Pos                   (26U)
8914 #define CAN_F11R1_FB26_Msk                   (0x1UL << CAN_F11R1_FB26_Pos)      /*!< 0x04000000 */
8915 #define CAN_F11R1_FB26                       CAN_F11R1_FB26_Msk                /*!< Filter bit 26 */
8916 #define CAN_F11R1_FB27_Pos                   (27U)
8917 #define CAN_F11R1_FB27_Msk                   (0x1UL << CAN_F11R1_FB27_Pos)      /*!< 0x08000000 */
8918 #define CAN_F11R1_FB27                       CAN_F11R1_FB27_Msk                /*!< Filter bit 27 */
8919 #define CAN_F11R1_FB28_Pos                   (28U)
8920 #define CAN_F11R1_FB28_Msk                   (0x1UL << CAN_F11R1_FB28_Pos)      /*!< 0x10000000 */
8921 #define CAN_F11R1_FB28                       CAN_F11R1_FB28_Msk                /*!< Filter bit 28 */
8922 #define CAN_F11R1_FB29_Pos                   (29U)
8923 #define CAN_F11R1_FB29_Msk                   (0x1UL << CAN_F11R1_FB29_Pos)      /*!< 0x20000000 */
8924 #define CAN_F11R1_FB29                       CAN_F11R1_FB29_Msk                /*!< Filter bit 29 */
8925 #define CAN_F11R1_FB30_Pos                   (30U)
8926 #define CAN_F11R1_FB30_Msk                   (0x1UL << CAN_F11R1_FB30_Pos)      /*!< 0x40000000 */
8927 #define CAN_F11R1_FB30                       CAN_F11R1_FB30_Msk                /*!< Filter bit 30 */
8928 #define CAN_F11R1_FB31_Pos                   (31U)
8929 #define CAN_F11R1_FB31_Msk                   (0x1UL << CAN_F11R1_FB31_Pos)      /*!< 0x80000000 */
8930 #define CAN_F11R1_FB31                       CAN_F11R1_FB31_Msk                /*!< Filter bit 31 */
8931 
8932 /*******************  Bit definition for CAN_F12R1 register  ******************/
8933 #define CAN_F12R1_FB0_Pos                    (0U)
8934 #define CAN_F12R1_FB0_Msk                    (0x1UL << CAN_F12R1_FB0_Pos)       /*!< 0x00000001 */
8935 #define CAN_F12R1_FB0                        CAN_F12R1_FB0_Msk                 /*!< Filter bit 0 */
8936 #define CAN_F12R1_FB1_Pos                    (1U)
8937 #define CAN_F12R1_FB1_Msk                    (0x1UL << CAN_F12R1_FB1_Pos)       /*!< 0x00000002 */
8938 #define CAN_F12R1_FB1                        CAN_F12R1_FB1_Msk                 /*!< Filter bit 1 */
8939 #define CAN_F12R1_FB2_Pos                    (2U)
8940 #define CAN_F12R1_FB2_Msk                    (0x1UL << CAN_F12R1_FB2_Pos)       /*!< 0x00000004 */
8941 #define CAN_F12R1_FB2                        CAN_F12R1_FB2_Msk                 /*!< Filter bit 2 */
8942 #define CAN_F12R1_FB3_Pos                    (3U)
8943 #define CAN_F12R1_FB3_Msk                    (0x1UL << CAN_F12R1_FB3_Pos)       /*!< 0x00000008 */
8944 #define CAN_F12R1_FB3                        CAN_F12R1_FB3_Msk                 /*!< Filter bit 3 */
8945 #define CAN_F12R1_FB4_Pos                    (4U)
8946 #define CAN_F12R1_FB4_Msk                    (0x1UL << CAN_F12R1_FB4_Pos)       /*!< 0x00000010 */
8947 #define CAN_F12R1_FB4                        CAN_F12R1_FB4_Msk                 /*!< Filter bit 4 */
8948 #define CAN_F12R1_FB5_Pos                    (5U)
8949 #define CAN_F12R1_FB5_Msk                    (0x1UL << CAN_F12R1_FB5_Pos)       /*!< 0x00000020 */
8950 #define CAN_F12R1_FB5                        CAN_F12R1_FB5_Msk                 /*!< Filter bit 5 */
8951 #define CAN_F12R1_FB6_Pos                    (6U)
8952 #define CAN_F12R1_FB6_Msk                    (0x1UL << CAN_F12R1_FB6_Pos)       /*!< 0x00000040 */
8953 #define CAN_F12R1_FB6                        CAN_F12R1_FB6_Msk                 /*!< Filter bit 6 */
8954 #define CAN_F12R1_FB7_Pos                    (7U)
8955 #define CAN_F12R1_FB7_Msk                    (0x1UL << CAN_F12R1_FB7_Pos)       /*!< 0x00000080 */
8956 #define CAN_F12R1_FB7                        CAN_F12R1_FB7_Msk                 /*!< Filter bit 7 */
8957 #define CAN_F12R1_FB8_Pos                    (8U)
8958 #define CAN_F12R1_FB8_Msk                    (0x1UL << CAN_F12R1_FB8_Pos)       /*!< 0x00000100 */
8959 #define CAN_F12R1_FB8                        CAN_F12R1_FB8_Msk                 /*!< Filter bit 8 */
8960 #define CAN_F12R1_FB9_Pos                    (9U)
8961 #define CAN_F12R1_FB9_Msk                    (0x1UL << CAN_F12R1_FB9_Pos)       /*!< 0x00000200 */
8962 #define CAN_F12R1_FB9                        CAN_F12R1_FB9_Msk                 /*!< Filter bit 9 */
8963 #define CAN_F12R1_FB10_Pos                   (10U)
8964 #define CAN_F12R1_FB10_Msk                   (0x1UL << CAN_F12R1_FB10_Pos)      /*!< 0x00000400 */
8965 #define CAN_F12R1_FB10                       CAN_F12R1_FB10_Msk                /*!< Filter bit 10 */
8966 #define CAN_F12R1_FB11_Pos                   (11U)
8967 #define CAN_F12R1_FB11_Msk                   (0x1UL << CAN_F12R1_FB11_Pos)      /*!< 0x00000800 */
8968 #define CAN_F12R1_FB11                       CAN_F12R1_FB11_Msk                /*!< Filter bit 11 */
8969 #define CAN_F12R1_FB12_Pos                   (12U)
8970 #define CAN_F12R1_FB12_Msk                   (0x1UL << CAN_F12R1_FB12_Pos)      /*!< 0x00001000 */
8971 #define CAN_F12R1_FB12                       CAN_F12R1_FB12_Msk                /*!< Filter bit 12 */
8972 #define CAN_F12R1_FB13_Pos                   (13U)
8973 #define CAN_F12R1_FB13_Msk                   (0x1UL << CAN_F12R1_FB13_Pos)      /*!< 0x00002000 */
8974 #define CAN_F12R1_FB13                       CAN_F12R1_FB13_Msk                /*!< Filter bit 13 */
8975 #define CAN_F12R1_FB14_Pos                   (14U)
8976 #define CAN_F12R1_FB14_Msk                   (0x1UL << CAN_F12R1_FB14_Pos)      /*!< 0x00004000 */
8977 #define CAN_F12R1_FB14                       CAN_F12R1_FB14_Msk                /*!< Filter bit 14 */
8978 #define CAN_F12R1_FB15_Pos                   (15U)
8979 #define CAN_F12R1_FB15_Msk                   (0x1UL << CAN_F12R1_FB15_Pos)      /*!< 0x00008000 */
8980 #define CAN_F12R1_FB15                       CAN_F12R1_FB15_Msk                /*!< Filter bit 15 */
8981 #define CAN_F12R1_FB16_Pos                   (16U)
8982 #define CAN_F12R1_FB16_Msk                   (0x1UL << CAN_F12R1_FB16_Pos)      /*!< 0x00010000 */
8983 #define CAN_F12R1_FB16                       CAN_F12R1_FB16_Msk                /*!< Filter bit 16 */
8984 #define CAN_F12R1_FB17_Pos                   (17U)
8985 #define CAN_F12R1_FB17_Msk                   (0x1UL << CAN_F12R1_FB17_Pos)      /*!< 0x00020000 */
8986 #define CAN_F12R1_FB17                       CAN_F12R1_FB17_Msk                /*!< Filter bit 17 */
8987 #define CAN_F12R1_FB18_Pos                   (18U)
8988 #define CAN_F12R1_FB18_Msk                   (0x1UL << CAN_F12R1_FB18_Pos)      /*!< 0x00040000 */
8989 #define CAN_F12R1_FB18                       CAN_F12R1_FB18_Msk                /*!< Filter bit 18 */
8990 #define CAN_F12R1_FB19_Pos                   (19U)
8991 #define CAN_F12R1_FB19_Msk                   (0x1UL << CAN_F12R1_FB19_Pos)      /*!< 0x00080000 */
8992 #define CAN_F12R1_FB19                       CAN_F12R1_FB19_Msk                /*!< Filter bit 19 */
8993 #define CAN_F12R1_FB20_Pos                   (20U)
8994 #define CAN_F12R1_FB20_Msk                   (0x1UL << CAN_F12R1_FB20_Pos)      /*!< 0x00100000 */
8995 #define CAN_F12R1_FB20                       CAN_F12R1_FB20_Msk                /*!< Filter bit 20 */
8996 #define CAN_F12R1_FB21_Pos                   (21U)
8997 #define CAN_F12R1_FB21_Msk                   (0x1UL << CAN_F12R1_FB21_Pos)      /*!< 0x00200000 */
8998 #define CAN_F12R1_FB21                       CAN_F12R1_FB21_Msk                /*!< Filter bit 21 */
8999 #define CAN_F12R1_FB22_Pos                   (22U)
9000 #define CAN_F12R1_FB22_Msk                   (0x1UL << CAN_F12R1_FB22_Pos)      /*!< 0x00400000 */
9001 #define CAN_F12R1_FB22                       CAN_F12R1_FB22_Msk                /*!< Filter bit 22 */
9002 #define CAN_F12R1_FB23_Pos                   (23U)
9003 #define CAN_F12R1_FB23_Msk                   (0x1UL << CAN_F12R1_FB23_Pos)      /*!< 0x00800000 */
9004 #define CAN_F12R1_FB23                       CAN_F12R1_FB23_Msk                /*!< Filter bit 23 */
9005 #define CAN_F12R1_FB24_Pos                   (24U)
9006 #define CAN_F12R1_FB24_Msk                   (0x1UL << CAN_F12R1_FB24_Pos)      /*!< 0x01000000 */
9007 #define CAN_F12R1_FB24                       CAN_F12R1_FB24_Msk                /*!< Filter bit 24 */
9008 #define CAN_F12R1_FB25_Pos                   (25U)
9009 #define CAN_F12R1_FB25_Msk                   (0x1UL << CAN_F12R1_FB25_Pos)      /*!< 0x02000000 */
9010 #define CAN_F12R1_FB25                       CAN_F12R1_FB25_Msk                /*!< Filter bit 25 */
9011 #define CAN_F12R1_FB26_Pos                   (26U)
9012 #define CAN_F12R1_FB26_Msk                   (0x1UL << CAN_F12R1_FB26_Pos)      /*!< 0x04000000 */
9013 #define CAN_F12R1_FB26                       CAN_F12R1_FB26_Msk                /*!< Filter bit 26 */
9014 #define CAN_F12R1_FB27_Pos                   (27U)
9015 #define CAN_F12R1_FB27_Msk                   (0x1UL << CAN_F12R1_FB27_Pos)      /*!< 0x08000000 */
9016 #define CAN_F12R1_FB27                       CAN_F12R1_FB27_Msk                /*!< Filter bit 27 */
9017 #define CAN_F12R1_FB28_Pos                   (28U)
9018 #define CAN_F12R1_FB28_Msk                   (0x1UL << CAN_F12R1_FB28_Pos)      /*!< 0x10000000 */
9019 #define CAN_F12R1_FB28                       CAN_F12R1_FB28_Msk                /*!< Filter bit 28 */
9020 #define CAN_F12R1_FB29_Pos                   (29U)
9021 #define CAN_F12R1_FB29_Msk                   (0x1UL << CAN_F12R1_FB29_Pos)      /*!< 0x20000000 */
9022 #define CAN_F12R1_FB29                       CAN_F12R1_FB29_Msk                /*!< Filter bit 29 */
9023 #define CAN_F12R1_FB30_Pos                   (30U)
9024 #define CAN_F12R1_FB30_Msk                   (0x1UL << CAN_F12R1_FB30_Pos)      /*!< 0x40000000 */
9025 #define CAN_F12R1_FB30                       CAN_F12R1_FB30_Msk                /*!< Filter bit 30 */
9026 #define CAN_F12R1_FB31_Pos                   (31U)
9027 #define CAN_F12R1_FB31_Msk                   (0x1UL << CAN_F12R1_FB31_Pos)      /*!< 0x80000000 */
9028 #define CAN_F12R1_FB31                       CAN_F12R1_FB31_Msk                /*!< Filter bit 31 */
9029 
9030 /*******************  Bit definition for CAN_F13R1 register  ******************/
9031 #define CAN_F13R1_FB0_Pos                    (0U)
9032 #define CAN_F13R1_FB0_Msk                    (0x1UL << CAN_F13R1_FB0_Pos)       /*!< 0x00000001 */
9033 #define CAN_F13R1_FB0                        CAN_F13R1_FB0_Msk                 /*!< Filter bit 0 */
9034 #define CAN_F13R1_FB1_Pos                    (1U)
9035 #define CAN_F13R1_FB1_Msk                    (0x1UL << CAN_F13R1_FB1_Pos)       /*!< 0x00000002 */
9036 #define CAN_F13R1_FB1                        CAN_F13R1_FB1_Msk                 /*!< Filter bit 1 */
9037 #define CAN_F13R1_FB2_Pos                    (2U)
9038 #define CAN_F13R1_FB2_Msk                    (0x1UL << CAN_F13R1_FB2_Pos)       /*!< 0x00000004 */
9039 #define CAN_F13R1_FB2                        CAN_F13R1_FB2_Msk                 /*!< Filter bit 2 */
9040 #define CAN_F13R1_FB3_Pos                    (3U)
9041 #define CAN_F13R1_FB3_Msk                    (0x1UL << CAN_F13R1_FB3_Pos)       /*!< 0x00000008 */
9042 #define CAN_F13R1_FB3                        CAN_F13R1_FB3_Msk                 /*!< Filter bit 3 */
9043 #define CAN_F13R1_FB4_Pos                    (4U)
9044 #define CAN_F13R1_FB4_Msk                    (0x1UL << CAN_F13R1_FB4_Pos)       /*!< 0x00000010 */
9045 #define CAN_F13R1_FB4                        CAN_F13R1_FB4_Msk                 /*!< Filter bit 4 */
9046 #define CAN_F13R1_FB5_Pos                    (5U)
9047 #define CAN_F13R1_FB5_Msk                    (0x1UL << CAN_F13R1_FB5_Pos)       /*!< 0x00000020 */
9048 #define CAN_F13R1_FB5                        CAN_F13R1_FB5_Msk                 /*!< Filter bit 5 */
9049 #define CAN_F13R1_FB6_Pos                    (6U)
9050 #define CAN_F13R1_FB6_Msk                    (0x1UL << CAN_F13R1_FB6_Pos)       /*!< 0x00000040 */
9051 #define CAN_F13R1_FB6                        CAN_F13R1_FB6_Msk                 /*!< Filter bit 6 */
9052 #define CAN_F13R1_FB7_Pos                    (7U)
9053 #define CAN_F13R1_FB7_Msk                    (0x1UL << CAN_F13R1_FB7_Pos)       /*!< 0x00000080 */
9054 #define CAN_F13R1_FB7                        CAN_F13R1_FB7_Msk                 /*!< Filter bit 7 */
9055 #define CAN_F13R1_FB8_Pos                    (8U)
9056 #define CAN_F13R1_FB8_Msk                    (0x1UL << CAN_F13R1_FB8_Pos)       /*!< 0x00000100 */
9057 #define CAN_F13R1_FB8                        CAN_F13R1_FB8_Msk                 /*!< Filter bit 8 */
9058 #define CAN_F13R1_FB9_Pos                    (9U)
9059 #define CAN_F13R1_FB9_Msk                    (0x1UL << CAN_F13R1_FB9_Pos)       /*!< 0x00000200 */
9060 #define CAN_F13R1_FB9                        CAN_F13R1_FB9_Msk                 /*!< Filter bit 9 */
9061 #define CAN_F13R1_FB10_Pos                   (10U)
9062 #define CAN_F13R1_FB10_Msk                   (0x1UL << CAN_F13R1_FB10_Pos)      /*!< 0x00000400 */
9063 #define CAN_F13R1_FB10                       CAN_F13R1_FB10_Msk                /*!< Filter bit 10 */
9064 #define CAN_F13R1_FB11_Pos                   (11U)
9065 #define CAN_F13R1_FB11_Msk                   (0x1UL << CAN_F13R1_FB11_Pos)      /*!< 0x00000800 */
9066 #define CAN_F13R1_FB11                       CAN_F13R1_FB11_Msk                /*!< Filter bit 11 */
9067 #define CAN_F13R1_FB12_Pos                   (12U)
9068 #define CAN_F13R1_FB12_Msk                   (0x1UL << CAN_F13R1_FB12_Pos)      /*!< 0x00001000 */
9069 #define CAN_F13R1_FB12                       CAN_F13R1_FB12_Msk                /*!< Filter bit 12 */
9070 #define CAN_F13R1_FB13_Pos                   (13U)
9071 #define CAN_F13R1_FB13_Msk                   (0x1UL << CAN_F13R1_FB13_Pos)      /*!< 0x00002000 */
9072 #define CAN_F13R1_FB13                       CAN_F13R1_FB13_Msk                /*!< Filter bit 13 */
9073 #define CAN_F13R1_FB14_Pos                   (14U)
9074 #define CAN_F13R1_FB14_Msk                   (0x1UL << CAN_F13R1_FB14_Pos)      /*!< 0x00004000 */
9075 #define CAN_F13R1_FB14                       CAN_F13R1_FB14_Msk                /*!< Filter bit 14 */
9076 #define CAN_F13R1_FB15_Pos                   (15U)
9077 #define CAN_F13R1_FB15_Msk                   (0x1UL << CAN_F13R1_FB15_Pos)      /*!< 0x00008000 */
9078 #define CAN_F13R1_FB15                       CAN_F13R1_FB15_Msk                /*!< Filter bit 15 */
9079 #define CAN_F13R1_FB16_Pos                   (16U)
9080 #define CAN_F13R1_FB16_Msk                   (0x1UL << CAN_F13R1_FB16_Pos)      /*!< 0x00010000 */
9081 #define CAN_F13R1_FB16                       CAN_F13R1_FB16_Msk                /*!< Filter bit 16 */
9082 #define CAN_F13R1_FB17_Pos                   (17U)
9083 #define CAN_F13R1_FB17_Msk                   (0x1UL << CAN_F13R1_FB17_Pos)      /*!< 0x00020000 */
9084 #define CAN_F13R1_FB17                       CAN_F13R1_FB17_Msk                /*!< Filter bit 17 */
9085 #define CAN_F13R1_FB18_Pos                   (18U)
9086 #define CAN_F13R1_FB18_Msk                   (0x1UL << CAN_F13R1_FB18_Pos)      /*!< 0x00040000 */
9087 #define CAN_F13R1_FB18                       CAN_F13R1_FB18_Msk                /*!< Filter bit 18 */
9088 #define CAN_F13R1_FB19_Pos                   (19U)
9089 #define CAN_F13R1_FB19_Msk                   (0x1UL << CAN_F13R1_FB19_Pos)      /*!< 0x00080000 */
9090 #define CAN_F13R1_FB19                       CAN_F13R1_FB19_Msk                /*!< Filter bit 19 */
9091 #define CAN_F13R1_FB20_Pos                   (20U)
9092 #define CAN_F13R1_FB20_Msk                   (0x1UL << CAN_F13R1_FB20_Pos)      /*!< 0x00100000 */
9093 #define CAN_F13R1_FB20                       CAN_F13R1_FB20_Msk                /*!< Filter bit 20 */
9094 #define CAN_F13R1_FB21_Pos                   (21U)
9095 #define CAN_F13R1_FB21_Msk                   (0x1UL << CAN_F13R1_FB21_Pos)      /*!< 0x00200000 */
9096 #define CAN_F13R1_FB21                       CAN_F13R1_FB21_Msk                /*!< Filter bit 21 */
9097 #define CAN_F13R1_FB22_Pos                   (22U)
9098 #define CAN_F13R1_FB22_Msk                   (0x1UL << CAN_F13R1_FB22_Pos)      /*!< 0x00400000 */
9099 #define CAN_F13R1_FB22                       CAN_F13R1_FB22_Msk                /*!< Filter bit 22 */
9100 #define CAN_F13R1_FB23_Pos                   (23U)
9101 #define CAN_F13R1_FB23_Msk                   (0x1UL << CAN_F13R1_FB23_Pos)      /*!< 0x00800000 */
9102 #define CAN_F13R1_FB23                       CAN_F13R1_FB23_Msk                /*!< Filter bit 23 */
9103 #define CAN_F13R1_FB24_Pos                   (24U)
9104 #define CAN_F13R1_FB24_Msk                   (0x1UL << CAN_F13R1_FB24_Pos)      /*!< 0x01000000 */
9105 #define CAN_F13R1_FB24                       CAN_F13R1_FB24_Msk                /*!< Filter bit 24 */
9106 #define CAN_F13R1_FB25_Pos                   (25U)
9107 #define CAN_F13R1_FB25_Msk                   (0x1UL << CAN_F13R1_FB25_Pos)      /*!< 0x02000000 */
9108 #define CAN_F13R1_FB25                       CAN_F13R1_FB25_Msk                /*!< Filter bit 25 */
9109 #define CAN_F13R1_FB26_Pos                   (26U)
9110 #define CAN_F13R1_FB26_Msk                   (0x1UL << CAN_F13R1_FB26_Pos)      /*!< 0x04000000 */
9111 #define CAN_F13R1_FB26                       CAN_F13R1_FB26_Msk                /*!< Filter bit 26 */
9112 #define CAN_F13R1_FB27_Pos                   (27U)
9113 #define CAN_F13R1_FB27_Msk                   (0x1UL << CAN_F13R1_FB27_Pos)      /*!< 0x08000000 */
9114 #define CAN_F13R1_FB27                       CAN_F13R1_FB27_Msk                /*!< Filter bit 27 */
9115 #define CAN_F13R1_FB28_Pos                   (28U)
9116 #define CAN_F13R1_FB28_Msk                   (0x1UL << CAN_F13R1_FB28_Pos)      /*!< 0x10000000 */
9117 #define CAN_F13R1_FB28                       CAN_F13R1_FB28_Msk                /*!< Filter bit 28 */
9118 #define CAN_F13R1_FB29_Pos                   (29U)
9119 #define CAN_F13R1_FB29_Msk                   (0x1UL << CAN_F13R1_FB29_Pos)      /*!< 0x20000000 */
9120 #define CAN_F13R1_FB29                       CAN_F13R1_FB29_Msk                /*!< Filter bit 29 */
9121 #define CAN_F13R1_FB30_Pos                   (30U)
9122 #define CAN_F13R1_FB30_Msk                   (0x1UL << CAN_F13R1_FB30_Pos)      /*!< 0x40000000 */
9123 #define CAN_F13R1_FB30                       CAN_F13R1_FB30_Msk                /*!< Filter bit 30 */
9124 #define CAN_F13R1_FB31_Pos                   (31U)
9125 #define CAN_F13R1_FB31_Msk                   (0x1UL << CAN_F13R1_FB31_Pos)      /*!< 0x80000000 */
9126 #define CAN_F13R1_FB31                       CAN_F13R1_FB31_Msk                /*!< Filter bit 31 */
9127 
9128 /*******************  Bit definition for CAN_F0R2 register  *******************/
9129 #define CAN_F0R2_FB0_Pos                     (0U)
9130 #define CAN_F0R2_FB0_Msk                     (0x1UL << CAN_F0R2_FB0_Pos)        /*!< 0x00000001 */
9131 #define CAN_F0R2_FB0                         CAN_F0R2_FB0_Msk                  /*!< Filter bit 0 */
9132 #define CAN_F0R2_FB1_Pos                     (1U)
9133 #define CAN_F0R2_FB1_Msk                     (0x1UL << CAN_F0R2_FB1_Pos)        /*!< 0x00000002 */
9134 #define CAN_F0R2_FB1                         CAN_F0R2_FB1_Msk                  /*!< Filter bit 1 */
9135 #define CAN_F0R2_FB2_Pos                     (2U)
9136 #define CAN_F0R2_FB2_Msk                     (0x1UL << CAN_F0R2_FB2_Pos)        /*!< 0x00000004 */
9137 #define CAN_F0R2_FB2                         CAN_F0R2_FB2_Msk                  /*!< Filter bit 2 */
9138 #define CAN_F0R2_FB3_Pos                     (3U)
9139 #define CAN_F0R2_FB3_Msk                     (0x1UL << CAN_F0R2_FB3_Pos)        /*!< 0x00000008 */
9140 #define CAN_F0R2_FB3                         CAN_F0R2_FB3_Msk                  /*!< Filter bit 3 */
9141 #define CAN_F0R2_FB4_Pos                     (4U)
9142 #define CAN_F0R2_FB4_Msk                     (0x1UL << CAN_F0R2_FB4_Pos)        /*!< 0x00000010 */
9143 #define CAN_F0R2_FB4                         CAN_F0R2_FB4_Msk                  /*!< Filter bit 4 */
9144 #define CAN_F0R2_FB5_Pos                     (5U)
9145 #define CAN_F0R2_FB5_Msk                     (0x1UL << CAN_F0R2_FB5_Pos)        /*!< 0x00000020 */
9146 #define CAN_F0R2_FB5                         CAN_F0R2_FB5_Msk                  /*!< Filter bit 5 */
9147 #define CAN_F0R2_FB6_Pos                     (6U)
9148 #define CAN_F0R2_FB6_Msk                     (0x1UL << CAN_F0R2_FB6_Pos)        /*!< 0x00000040 */
9149 #define CAN_F0R2_FB6                         CAN_F0R2_FB6_Msk                  /*!< Filter bit 6 */
9150 #define CAN_F0R2_FB7_Pos                     (7U)
9151 #define CAN_F0R2_FB7_Msk                     (0x1UL << CAN_F0R2_FB7_Pos)        /*!< 0x00000080 */
9152 #define CAN_F0R2_FB7                         CAN_F0R2_FB7_Msk                  /*!< Filter bit 7 */
9153 #define CAN_F0R2_FB8_Pos                     (8U)
9154 #define CAN_F0R2_FB8_Msk                     (0x1UL << CAN_F0R2_FB8_Pos)        /*!< 0x00000100 */
9155 #define CAN_F0R2_FB8                         CAN_F0R2_FB8_Msk                  /*!< Filter bit 8 */
9156 #define CAN_F0R2_FB9_Pos                     (9U)
9157 #define CAN_F0R2_FB9_Msk                     (0x1UL << CAN_F0R2_FB9_Pos)        /*!< 0x00000200 */
9158 #define CAN_F0R2_FB9                         CAN_F0R2_FB9_Msk                  /*!< Filter bit 9 */
9159 #define CAN_F0R2_FB10_Pos                    (10U)
9160 #define CAN_F0R2_FB10_Msk                    (0x1UL << CAN_F0R2_FB10_Pos)       /*!< 0x00000400 */
9161 #define CAN_F0R2_FB10                        CAN_F0R2_FB10_Msk                 /*!< Filter bit 10 */
9162 #define CAN_F0R2_FB11_Pos                    (11U)
9163 #define CAN_F0R2_FB11_Msk                    (0x1UL << CAN_F0R2_FB11_Pos)       /*!< 0x00000800 */
9164 #define CAN_F0R2_FB11                        CAN_F0R2_FB11_Msk                 /*!< Filter bit 11 */
9165 #define CAN_F0R2_FB12_Pos                    (12U)
9166 #define CAN_F0R2_FB12_Msk                    (0x1UL << CAN_F0R2_FB12_Pos)       /*!< 0x00001000 */
9167 #define CAN_F0R2_FB12                        CAN_F0R2_FB12_Msk                 /*!< Filter bit 12 */
9168 #define CAN_F0R2_FB13_Pos                    (13U)
9169 #define CAN_F0R2_FB13_Msk                    (0x1UL << CAN_F0R2_FB13_Pos)       /*!< 0x00002000 */
9170 #define CAN_F0R2_FB13                        CAN_F0R2_FB13_Msk                 /*!< Filter bit 13 */
9171 #define CAN_F0R2_FB14_Pos                    (14U)
9172 #define CAN_F0R2_FB14_Msk                    (0x1UL << CAN_F0R2_FB14_Pos)       /*!< 0x00004000 */
9173 #define CAN_F0R2_FB14                        CAN_F0R2_FB14_Msk                 /*!< Filter bit 14 */
9174 #define CAN_F0R2_FB15_Pos                    (15U)
9175 #define CAN_F0R2_FB15_Msk                    (0x1UL << CAN_F0R2_FB15_Pos)       /*!< 0x00008000 */
9176 #define CAN_F0R2_FB15                        CAN_F0R2_FB15_Msk                 /*!< Filter bit 15 */
9177 #define CAN_F0R2_FB16_Pos                    (16U)
9178 #define CAN_F0R2_FB16_Msk                    (0x1UL << CAN_F0R2_FB16_Pos)       /*!< 0x00010000 */
9179 #define CAN_F0R2_FB16                        CAN_F0R2_FB16_Msk                 /*!< Filter bit 16 */
9180 #define CAN_F0R2_FB17_Pos                    (17U)
9181 #define CAN_F0R2_FB17_Msk                    (0x1UL << CAN_F0R2_FB17_Pos)       /*!< 0x00020000 */
9182 #define CAN_F0R2_FB17                        CAN_F0R2_FB17_Msk                 /*!< Filter bit 17 */
9183 #define CAN_F0R2_FB18_Pos                    (18U)
9184 #define CAN_F0R2_FB18_Msk                    (0x1UL << CAN_F0R2_FB18_Pos)       /*!< 0x00040000 */
9185 #define CAN_F0R2_FB18                        CAN_F0R2_FB18_Msk                 /*!< Filter bit 18 */
9186 #define CAN_F0R2_FB19_Pos                    (19U)
9187 #define CAN_F0R2_FB19_Msk                    (0x1UL << CAN_F0R2_FB19_Pos)       /*!< 0x00080000 */
9188 #define CAN_F0R2_FB19                        CAN_F0R2_FB19_Msk                 /*!< Filter bit 19 */
9189 #define CAN_F0R2_FB20_Pos                    (20U)
9190 #define CAN_F0R2_FB20_Msk                    (0x1UL << CAN_F0R2_FB20_Pos)       /*!< 0x00100000 */
9191 #define CAN_F0R2_FB20                        CAN_F0R2_FB20_Msk                 /*!< Filter bit 20 */
9192 #define CAN_F0R2_FB21_Pos                    (21U)
9193 #define CAN_F0R2_FB21_Msk                    (0x1UL << CAN_F0R2_FB21_Pos)       /*!< 0x00200000 */
9194 #define CAN_F0R2_FB21                        CAN_F0R2_FB21_Msk                 /*!< Filter bit 21 */
9195 #define CAN_F0R2_FB22_Pos                    (22U)
9196 #define CAN_F0R2_FB22_Msk                    (0x1UL << CAN_F0R2_FB22_Pos)       /*!< 0x00400000 */
9197 #define CAN_F0R2_FB22                        CAN_F0R2_FB22_Msk                 /*!< Filter bit 22 */
9198 #define CAN_F0R2_FB23_Pos                    (23U)
9199 #define CAN_F0R2_FB23_Msk                    (0x1UL << CAN_F0R2_FB23_Pos)       /*!< 0x00800000 */
9200 #define CAN_F0R2_FB23                        CAN_F0R2_FB23_Msk                 /*!< Filter bit 23 */
9201 #define CAN_F0R2_FB24_Pos                    (24U)
9202 #define CAN_F0R2_FB24_Msk                    (0x1UL << CAN_F0R2_FB24_Pos)       /*!< 0x01000000 */
9203 #define CAN_F0R2_FB24                        CAN_F0R2_FB24_Msk                 /*!< Filter bit 24 */
9204 #define CAN_F0R2_FB25_Pos                    (25U)
9205 #define CAN_F0R2_FB25_Msk                    (0x1UL << CAN_F0R2_FB25_Pos)       /*!< 0x02000000 */
9206 #define CAN_F0R2_FB25                        CAN_F0R2_FB25_Msk                 /*!< Filter bit 25 */
9207 #define CAN_F0R2_FB26_Pos                    (26U)
9208 #define CAN_F0R2_FB26_Msk                    (0x1UL << CAN_F0R2_FB26_Pos)       /*!< 0x04000000 */
9209 #define CAN_F0R2_FB26                        CAN_F0R2_FB26_Msk                 /*!< Filter bit 26 */
9210 #define CAN_F0R2_FB27_Pos                    (27U)
9211 #define CAN_F0R2_FB27_Msk                    (0x1UL << CAN_F0R2_FB27_Pos)       /*!< 0x08000000 */
9212 #define CAN_F0R2_FB27                        CAN_F0R2_FB27_Msk                 /*!< Filter bit 27 */
9213 #define CAN_F0R2_FB28_Pos                    (28U)
9214 #define CAN_F0R2_FB28_Msk                    (0x1UL << CAN_F0R2_FB28_Pos)       /*!< 0x10000000 */
9215 #define CAN_F0R2_FB28                        CAN_F0R2_FB28_Msk                 /*!< Filter bit 28 */
9216 #define CAN_F0R2_FB29_Pos                    (29U)
9217 #define CAN_F0R2_FB29_Msk                    (0x1UL << CAN_F0R2_FB29_Pos)       /*!< 0x20000000 */
9218 #define CAN_F0R2_FB29                        CAN_F0R2_FB29_Msk                 /*!< Filter bit 29 */
9219 #define CAN_F0R2_FB30_Pos                    (30U)
9220 #define CAN_F0R2_FB30_Msk                    (0x1UL << CAN_F0R2_FB30_Pos)       /*!< 0x40000000 */
9221 #define CAN_F0R2_FB30                        CAN_F0R2_FB30_Msk                 /*!< Filter bit 30 */
9222 #define CAN_F0R2_FB31_Pos                    (31U)
9223 #define CAN_F0R2_FB31_Msk                    (0x1UL << CAN_F0R2_FB31_Pos)       /*!< 0x80000000 */
9224 #define CAN_F0R2_FB31                        CAN_F0R2_FB31_Msk                 /*!< Filter bit 31 */
9225 
9226 /*******************  Bit definition for CAN_F1R2 register  *******************/
9227 #define CAN_F1R2_FB0_Pos                     (0U)
9228 #define CAN_F1R2_FB0_Msk                     (0x1UL << CAN_F1R2_FB0_Pos)        /*!< 0x00000001 */
9229 #define CAN_F1R2_FB0                         CAN_F1R2_FB0_Msk                  /*!< Filter bit 0 */
9230 #define CAN_F1R2_FB1_Pos                     (1U)
9231 #define CAN_F1R2_FB1_Msk                     (0x1UL << CAN_F1R2_FB1_Pos)        /*!< 0x00000002 */
9232 #define CAN_F1R2_FB1                         CAN_F1R2_FB1_Msk                  /*!< Filter bit 1 */
9233 #define CAN_F1R2_FB2_Pos                     (2U)
9234 #define CAN_F1R2_FB2_Msk                     (0x1UL << CAN_F1R2_FB2_Pos)        /*!< 0x00000004 */
9235 #define CAN_F1R2_FB2                         CAN_F1R2_FB2_Msk                  /*!< Filter bit 2 */
9236 #define CAN_F1R2_FB3_Pos                     (3U)
9237 #define CAN_F1R2_FB3_Msk                     (0x1UL << CAN_F1R2_FB3_Pos)        /*!< 0x00000008 */
9238 #define CAN_F1R2_FB3                         CAN_F1R2_FB3_Msk                  /*!< Filter bit 3 */
9239 #define CAN_F1R2_FB4_Pos                     (4U)
9240 #define CAN_F1R2_FB4_Msk                     (0x1UL << CAN_F1R2_FB4_Pos)        /*!< 0x00000010 */
9241 #define CAN_F1R2_FB4                         CAN_F1R2_FB4_Msk                  /*!< Filter bit 4 */
9242 #define CAN_F1R2_FB5_Pos                     (5U)
9243 #define CAN_F1R2_FB5_Msk                     (0x1UL << CAN_F1R2_FB5_Pos)        /*!< 0x00000020 */
9244 #define CAN_F1R2_FB5                         CAN_F1R2_FB5_Msk                  /*!< Filter bit 5 */
9245 #define CAN_F1R2_FB6_Pos                     (6U)
9246 #define CAN_F1R2_FB6_Msk                     (0x1UL << CAN_F1R2_FB6_Pos)        /*!< 0x00000040 */
9247 #define CAN_F1R2_FB6                         CAN_F1R2_FB6_Msk                  /*!< Filter bit 6 */
9248 #define CAN_F1R2_FB7_Pos                     (7U)
9249 #define CAN_F1R2_FB7_Msk                     (0x1UL << CAN_F1R2_FB7_Pos)        /*!< 0x00000080 */
9250 #define CAN_F1R2_FB7                         CAN_F1R2_FB7_Msk                  /*!< Filter bit 7 */
9251 #define CAN_F1R2_FB8_Pos                     (8U)
9252 #define CAN_F1R2_FB8_Msk                     (0x1UL << CAN_F1R2_FB8_Pos)        /*!< 0x00000100 */
9253 #define CAN_F1R2_FB8                         CAN_F1R2_FB8_Msk                  /*!< Filter bit 8 */
9254 #define CAN_F1R2_FB9_Pos                     (9U)
9255 #define CAN_F1R2_FB9_Msk                     (0x1UL << CAN_F1R2_FB9_Pos)        /*!< 0x00000200 */
9256 #define CAN_F1R2_FB9                         CAN_F1R2_FB9_Msk                  /*!< Filter bit 9 */
9257 #define CAN_F1R2_FB10_Pos                    (10U)
9258 #define CAN_F1R2_FB10_Msk                    (0x1UL << CAN_F1R2_FB10_Pos)       /*!< 0x00000400 */
9259 #define CAN_F1R2_FB10                        CAN_F1R2_FB10_Msk                 /*!< Filter bit 10 */
9260 #define CAN_F1R2_FB11_Pos                    (11U)
9261 #define CAN_F1R2_FB11_Msk                    (0x1UL << CAN_F1R2_FB11_Pos)       /*!< 0x00000800 */
9262 #define CAN_F1R2_FB11                        CAN_F1R2_FB11_Msk                 /*!< Filter bit 11 */
9263 #define CAN_F1R2_FB12_Pos                    (12U)
9264 #define CAN_F1R2_FB12_Msk                    (0x1UL << CAN_F1R2_FB12_Pos)       /*!< 0x00001000 */
9265 #define CAN_F1R2_FB12                        CAN_F1R2_FB12_Msk                 /*!< Filter bit 12 */
9266 #define CAN_F1R2_FB13_Pos                    (13U)
9267 #define CAN_F1R2_FB13_Msk                    (0x1UL << CAN_F1R2_FB13_Pos)       /*!< 0x00002000 */
9268 #define CAN_F1R2_FB13                        CAN_F1R2_FB13_Msk                 /*!< Filter bit 13 */
9269 #define CAN_F1R2_FB14_Pos                    (14U)
9270 #define CAN_F1R2_FB14_Msk                    (0x1UL << CAN_F1R2_FB14_Pos)       /*!< 0x00004000 */
9271 #define CAN_F1R2_FB14                        CAN_F1R2_FB14_Msk                 /*!< Filter bit 14 */
9272 #define CAN_F1R2_FB15_Pos                    (15U)
9273 #define CAN_F1R2_FB15_Msk                    (0x1UL << CAN_F1R2_FB15_Pos)       /*!< 0x00008000 */
9274 #define CAN_F1R2_FB15                        CAN_F1R2_FB15_Msk                 /*!< Filter bit 15 */
9275 #define CAN_F1R2_FB16_Pos                    (16U)
9276 #define CAN_F1R2_FB16_Msk                    (0x1UL << CAN_F1R2_FB16_Pos)       /*!< 0x00010000 */
9277 #define CAN_F1R2_FB16                        CAN_F1R2_FB16_Msk                 /*!< Filter bit 16 */
9278 #define CAN_F1R2_FB17_Pos                    (17U)
9279 #define CAN_F1R2_FB17_Msk                    (0x1UL << CAN_F1R2_FB17_Pos)       /*!< 0x00020000 */
9280 #define CAN_F1R2_FB17                        CAN_F1R2_FB17_Msk                 /*!< Filter bit 17 */
9281 #define CAN_F1R2_FB18_Pos                    (18U)
9282 #define CAN_F1R2_FB18_Msk                    (0x1UL << CAN_F1R2_FB18_Pos)       /*!< 0x00040000 */
9283 #define CAN_F1R2_FB18                        CAN_F1R2_FB18_Msk                 /*!< Filter bit 18 */
9284 #define CAN_F1R2_FB19_Pos                    (19U)
9285 #define CAN_F1R2_FB19_Msk                    (0x1UL << CAN_F1R2_FB19_Pos)       /*!< 0x00080000 */
9286 #define CAN_F1R2_FB19                        CAN_F1R2_FB19_Msk                 /*!< Filter bit 19 */
9287 #define CAN_F1R2_FB20_Pos                    (20U)
9288 #define CAN_F1R2_FB20_Msk                    (0x1UL << CAN_F1R2_FB20_Pos)       /*!< 0x00100000 */
9289 #define CAN_F1R2_FB20                        CAN_F1R2_FB20_Msk                 /*!< Filter bit 20 */
9290 #define CAN_F1R2_FB21_Pos                    (21U)
9291 #define CAN_F1R2_FB21_Msk                    (0x1UL << CAN_F1R2_FB21_Pos)       /*!< 0x00200000 */
9292 #define CAN_F1R2_FB21                        CAN_F1R2_FB21_Msk                 /*!< Filter bit 21 */
9293 #define CAN_F1R2_FB22_Pos                    (22U)
9294 #define CAN_F1R2_FB22_Msk                    (0x1UL << CAN_F1R2_FB22_Pos)       /*!< 0x00400000 */
9295 #define CAN_F1R2_FB22                        CAN_F1R2_FB22_Msk                 /*!< Filter bit 22 */
9296 #define CAN_F1R2_FB23_Pos                    (23U)
9297 #define CAN_F1R2_FB23_Msk                    (0x1UL << CAN_F1R2_FB23_Pos)       /*!< 0x00800000 */
9298 #define CAN_F1R2_FB23                        CAN_F1R2_FB23_Msk                 /*!< Filter bit 23 */
9299 #define CAN_F1R2_FB24_Pos                    (24U)
9300 #define CAN_F1R2_FB24_Msk                    (0x1UL << CAN_F1R2_FB24_Pos)       /*!< 0x01000000 */
9301 #define CAN_F1R2_FB24                        CAN_F1R2_FB24_Msk                 /*!< Filter bit 24 */
9302 #define CAN_F1R2_FB25_Pos                    (25U)
9303 #define CAN_F1R2_FB25_Msk                    (0x1UL << CAN_F1R2_FB25_Pos)       /*!< 0x02000000 */
9304 #define CAN_F1R2_FB25                        CAN_F1R2_FB25_Msk                 /*!< Filter bit 25 */
9305 #define CAN_F1R2_FB26_Pos                    (26U)
9306 #define CAN_F1R2_FB26_Msk                    (0x1UL << CAN_F1R2_FB26_Pos)       /*!< 0x04000000 */
9307 #define CAN_F1R2_FB26                        CAN_F1R2_FB26_Msk                 /*!< Filter bit 26 */
9308 #define CAN_F1R2_FB27_Pos                    (27U)
9309 #define CAN_F1R2_FB27_Msk                    (0x1UL << CAN_F1R2_FB27_Pos)       /*!< 0x08000000 */
9310 #define CAN_F1R2_FB27                        CAN_F1R2_FB27_Msk                 /*!< Filter bit 27 */
9311 #define CAN_F1R2_FB28_Pos                    (28U)
9312 #define CAN_F1R2_FB28_Msk                    (0x1UL << CAN_F1R2_FB28_Pos)       /*!< 0x10000000 */
9313 #define CAN_F1R2_FB28                        CAN_F1R2_FB28_Msk                 /*!< Filter bit 28 */
9314 #define CAN_F1R2_FB29_Pos                    (29U)
9315 #define CAN_F1R2_FB29_Msk                    (0x1UL << CAN_F1R2_FB29_Pos)       /*!< 0x20000000 */
9316 #define CAN_F1R2_FB29                        CAN_F1R2_FB29_Msk                 /*!< Filter bit 29 */
9317 #define CAN_F1R2_FB30_Pos                    (30U)
9318 #define CAN_F1R2_FB30_Msk                    (0x1UL << CAN_F1R2_FB30_Pos)       /*!< 0x40000000 */
9319 #define CAN_F1R2_FB30                        CAN_F1R2_FB30_Msk                 /*!< Filter bit 30 */
9320 #define CAN_F1R2_FB31_Pos                    (31U)
9321 #define CAN_F1R2_FB31_Msk                    (0x1UL << CAN_F1R2_FB31_Pos)       /*!< 0x80000000 */
9322 #define CAN_F1R2_FB31                        CAN_F1R2_FB31_Msk                 /*!< Filter bit 31 */
9323 
9324 /*******************  Bit definition for CAN_F2R2 register  *******************/
9325 #define CAN_F2R2_FB0_Pos                     (0U)
9326 #define CAN_F2R2_FB0_Msk                     (0x1UL << CAN_F2R2_FB0_Pos)        /*!< 0x00000001 */
9327 #define CAN_F2R2_FB0                         CAN_F2R2_FB0_Msk                  /*!< Filter bit 0 */
9328 #define CAN_F2R2_FB1_Pos                     (1U)
9329 #define CAN_F2R2_FB1_Msk                     (0x1UL << CAN_F2R2_FB1_Pos)        /*!< 0x00000002 */
9330 #define CAN_F2R2_FB1                         CAN_F2R2_FB1_Msk                  /*!< Filter bit 1 */
9331 #define CAN_F2R2_FB2_Pos                     (2U)
9332 #define CAN_F2R2_FB2_Msk                     (0x1UL << CAN_F2R2_FB2_Pos)        /*!< 0x00000004 */
9333 #define CAN_F2R2_FB2                         CAN_F2R2_FB2_Msk                  /*!< Filter bit 2 */
9334 #define CAN_F2R2_FB3_Pos                     (3U)
9335 #define CAN_F2R2_FB3_Msk                     (0x1UL << CAN_F2R2_FB3_Pos)        /*!< 0x00000008 */
9336 #define CAN_F2R2_FB3                         CAN_F2R2_FB3_Msk                  /*!< Filter bit 3 */
9337 #define CAN_F2R2_FB4_Pos                     (4U)
9338 #define CAN_F2R2_FB4_Msk                     (0x1UL << CAN_F2R2_FB4_Pos)        /*!< 0x00000010 */
9339 #define CAN_F2R2_FB4                         CAN_F2R2_FB4_Msk                  /*!< Filter bit 4 */
9340 #define CAN_F2R2_FB5_Pos                     (5U)
9341 #define CAN_F2R2_FB5_Msk                     (0x1UL << CAN_F2R2_FB5_Pos)        /*!< 0x00000020 */
9342 #define CAN_F2R2_FB5                         CAN_F2R2_FB5_Msk                  /*!< Filter bit 5 */
9343 #define CAN_F2R2_FB6_Pos                     (6U)
9344 #define CAN_F2R2_FB6_Msk                     (0x1UL << CAN_F2R2_FB6_Pos)        /*!< 0x00000040 */
9345 #define CAN_F2R2_FB6                         CAN_F2R2_FB6_Msk                  /*!< Filter bit 6 */
9346 #define CAN_F2R2_FB7_Pos                     (7U)
9347 #define CAN_F2R2_FB7_Msk                     (0x1UL << CAN_F2R2_FB7_Pos)        /*!< 0x00000080 */
9348 #define CAN_F2R2_FB7                         CAN_F2R2_FB7_Msk                  /*!< Filter bit 7 */
9349 #define CAN_F2R2_FB8_Pos                     (8U)
9350 #define CAN_F2R2_FB8_Msk                     (0x1UL << CAN_F2R2_FB8_Pos)        /*!< 0x00000100 */
9351 #define CAN_F2R2_FB8                         CAN_F2R2_FB8_Msk                  /*!< Filter bit 8 */
9352 #define CAN_F2R2_FB9_Pos                     (9U)
9353 #define CAN_F2R2_FB9_Msk                     (0x1UL << CAN_F2R2_FB9_Pos)        /*!< 0x00000200 */
9354 #define CAN_F2R2_FB9                         CAN_F2R2_FB9_Msk                  /*!< Filter bit 9 */
9355 #define CAN_F2R2_FB10_Pos                    (10U)
9356 #define CAN_F2R2_FB10_Msk                    (0x1UL << CAN_F2R2_FB10_Pos)       /*!< 0x00000400 */
9357 #define CAN_F2R2_FB10                        CAN_F2R2_FB10_Msk                 /*!< Filter bit 10 */
9358 #define CAN_F2R2_FB11_Pos                    (11U)
9359 #define CAN_F2R2_FB11_Msk                    (0x1UL << CAN_F2R2_FB11_Pos)       /*!< 0x00000800 */
9360 #define CAN_F2R2_FB11                        CAN_F2R2_FB11_Msk                 /*!< Filter bit 11 */
9361 #define CAN_F2R2_FB12_Pos                    (12U)
9362 #define CAN_F2R2_FB12_Msk                    (0x1UL << CAN_F2R2_FB12_Pos)       /*!< 0x00001000 */
9363 #define CAN_F2R2_FB12                        CAN_F2R2_FB12_Msk                 /*!< Filter bit 12 */
9364 #define CAN_F2R2_FB13_Pos                    (13U)
9365 #define CAN_F2R2_FB13_Msk                    (0x1UL << CAN_F2R2_FB13_Pos)       /*!< 0x00002000 */
9366 #define CAN_F2R2_FB13                        CAN_F2R2_FB13_Msk                 /*!< Filter bit 13 */
9367 #define CAN_F2R2_FB14_Pos                    (14U)
9368 #define CAN_F2R2_FB14_Msk                    (0x1UL << CAN_F2R2_FB14_Pos)       /*!< 0x00004000 */
9369 #define CAN_F2R2_FB14                        CAN_F2R2_FB14_Msk                 /*!< Filter bit 14 */
9370 #define CAN_F2R2_FB15_Pos                    (15U)
9371 #define CAN_F2R2_FB15_Msk                    (0x1UL << CAN_F2R2_FB15_Pos)       /*!< 0x00008000 */
9372 #define CAN_F2R2_FB15                        CAN_F2R2_FB15_Msk                 /*!< Filter bit 15 */
9373 #define CAN_F2R2_FB16_Pos                    (16U)
9374 #define CAN_F2R2_FB16_Msk                    (0x1UL << CAN_F2R2_FB16_Pos)       /*!< 0x00010000 */
9375 #define CAN_F2R2_FB16                        CAN_F2R2_FB16_Msk                 /*!< Filter bit 16 */
9376 #define CAN_F2R2_FB17_Pos                    (17U)
9377 #define CAN_F2R2_FB17_Msk                    (0x1UL << CAN_F2R2_FB17_Pos)       /*!< 0x00020000 */
9378 #define CAN_F2R2_FB17                        CAN_F2R2_FB17_Msk                 /*!< Filter bit 17 */
9379 #define CAN_F2R2_FB18_Pos                    (18U)
9380 #define CAN_F2R2_FB18_Msk                    (0x1UL << CAN_F2R2_FB18_Pos)       /*!< 0x00040000 */
9381 #define CAN_F2R2_FB18                        CAN_F2R2_FB18_Msk                 /*!< Filter bit 18 */
9382 #define CAN_F2R2_FB19_Pos                    (19U)
9383 #define CAN_F2R2_FB19_Msk                    (0x1UL << CAN_F2R2_FB19_Pos)       /*!< 0x00080000 */
9384 #define CAN_F2R2_FB19                        CAN_F2R2_FB19_Msk                 /*!< Filter bit 19 */
9385 #define CAN_F2R2_FB20_Pos                    (20U)
9386 #define CAN_F2R2_FB20_Msk                    (0x1UL << CAN_F2R2_FB20_Pos)       /*!< 0x00100000 */
9387 #define CAN_F2R2_FB20                        CAN_F2R2_FB20_Msk                 /*!< Filter bit 20 */
9388 #define CAN_F2R2_FB21_Pos                    (21U)
9389 #define CAN_F2R2_FB21_Msk                    (0x1UL << CAN_F2R2_FB21_Pos)       /*!< 0x00200000 */
9390 #define CAN_F2R2_FB21                        CAN_F2R2_FB21_Msk                 /*!< Filter bit 21 */
9391 #define CAN_F2R2_FB22_Pos                    (22U)
9392 #define CAN_F2R2_FB22_Msk                    (0x1UL << CAN_F2R2_FB22_Pos)       /*!< 0x00400000 */
9393 #define CAN_F2R2_FB22                        CAN_F2R2_FB22_Msk                 /*!< Filter bit 22 */
9394 #define CAN_F2R2_FB23_Pos                    (23U)
9395 #define CAN_F2R2_FB23_Msk                    (0x1UL << CAN_F2R2_FB23_Pos)       /*!< 0x00800000 */
9396 #define CAN_F2R2_FB23                        CAN_F2R2_FB23_Msk                 /*!< Filter bit 23 */
9397 #define CAN_F2R2_FB24_Pos                    (24U)
9398 #define CAN_F2R2_FB24_Msk                    (0x1UL << CAN_F2R2_FB24_Pos)       /*!< 0x01000000 */
9399 #define CAN_F2R2_FB24                        CAN_F2R2_FB24_Msk                 /*!< Filter bit 24 */
9400 #define CAN_F2R2_FB25_Pos                    (25U)
9401 #define CAN_F2R2_FB25_Msk                    (0x1UL << CAN_F2R2_FB25_Pos)       /*!< 0x02000000 */
9402 #define CAN_F2R2_FB25                        CAN_F2R2_FB25_Msk                 /*!< Filter bit 25 */
9403 #define CAN_F2R2_FB26_Pos                    (26U)
9404 #define CAN_F2R2_FB26_Msk                    (0x1UL << CAN_F2R2_FB26_Pos)       /*!< 0x04000000 */
9405 #define CAN_F2R2_FB26                        CAN_F2R2_FB26_Msk                 /*!< Filter bit 26 */
9406 #define CAN_F2R2_FB27_Pos                    (27U)
9407 #define CAN_F2R2_FB27_Msk                    (0x1UL << CAN_F2R2_FB27_Pos)       /*!< 0x08000000 */
9408 #define CAN_F2R2_FB27                        CAN_F2R2_FB27_Msk                 /*!< Filter bit 27 */
9409 #define CAN_F2R2_FB28_Pos                    (28U)
9410 #define CAN_F2R2_FB28_Msk                    (0x1UL << CAN_F2R2_FB28_Pos)       /*!< 0x10000000 */
9411 #define CAN_F2R2_FB28                        CAN_F2R2_FB28_Msk                 /*!< Filter bit 28 */
9412 #define CAN_F2R2_FB29_Pos                    (29U)
9413 #define CAN_F2R2_FB29_Msk                    (0x1UL << CAN_F2R2_FB29_Pos)       /*!< 0x20000000 */
9414 #define CAN_F2R2_FB29                        CAN_F2R2_FB29_Msk                 /*!< Filter bit 29 */
9415 #define CAN_F2R2_FB30_Pos                    (30U)
9416 #define CAN_F2R2_FB30_Msk                    (0x1UL << CAN_F2R2_FB30_Pos)       /*!< 0x40000000 */
9417 #define CAN_F2R2_FB30                        CAN_F2R2_FB30_Msk                 /*!< Filter bit 30 */
9418 #define CAN_F2R2_FB31_Pos                    (31U)
9419 #define CAN_F2R2_FB31_Msk                    (0x1UL << CAN_F2R2_FB31_Pos)       /*!< 0x80000000 */
9420 #define CAN_F2R2_FB31                        CAN_F2R2_FB31_Msk                 /*!< Filter bit 31 */
9421 
9422 /*******************  Bit definition for CAN_F3R2 register  *******************/
9423 #define CAN_F3R2_FB0_Pos                     (0U)
9424 #define CAN_F3R2_FB0_Msk                     (0x1UL << CAN_F3R2_FB0_Pos)        /*!< 0x00000001 */
9425 #define CAN_F3R2_FB0                         CAN_F3R2_FB0_Msk                  /*!< Filter bit 0 */
9426 #define CAN_F3R2_FB1_Pos                     (1U)
9427 #define CAN_F3R2_FB1_Msk                     (0x1UL << CAN_F3R2_FB1_Pos)        /*!< 0x00000002 */
9428 #define CAN_F3R2_FB1                         CAN_F3R2_FB1_Msk                  /*!< Filter bit 1 */
9429 #define CAN_F3R2_FB2_Pos                     (2U)
9430 #define CAN_F3R2_FB2_Msk                     (0x1UL << CAN_F3R2_FB2_Pos)        /*!< 0x00000004 */
9431 #define CAN_F3R2_FB2                         CAN_F3R2_FB2_Msk                  /*!< Filter bit 2 */
9432 #define CAN_F3R2_FB3_Pos                     (3U)
9433 #define CAN_F3R2_FB3_Msk                     (0x1UL << CAN_F3R2_FB3_Pos)        /*!< 0x00000008 */
9434 #define CAN_F3R2_FB3                         CAN_F3R2_FB3_Msk                  /*!< Filter bit 3 */
9435 #define CAN_F3R2_FB4_Pos                     (4U)
9436 #define CAN_F3R2_FB4_Msk                     (0x1UL << CAN_F3R2_FB4_Pos)        /*!< 0x00000010 */
9437 #define CAN_F3R2_FB4                         CAN_F3R2_FB4_Msk                  /*!< Filter bit 4 */
9438 #define CAN_F3R2_FB5_Pos                     (5U)
9439 #define CAN_F3R2_FB5_Msk                     (0x1UL << CAN_F3R2_FB5_Pos)        /*!< 0x00000020 */
9440 #define CAN_F3R2_FB5                         CAN_F3R2_FB5_Msk                  /*!< Filter bit 5 */
9441 #define CAN_F3R2_FB6_Pos                     (6U)
9442 #define CAN_F3R2_FB6_Msk                     (0x1UL << CAN_F3R2_FB6_Pos)        /*!< 0x00000040 */
9443 #define CAN_F3R2_FB6                         CAN_F3R2_FB6_Msk                  /*!< Filter bit 6 */
9444 #define CAN_F3R2_FB7_Pos                     (7U)
9445 #define CAN_F3R2_FB7_Msk                     (0x1UL << CAN_F3R2_FB7_Pos)        /*!< 0x00000080 */
9446 #define CAN_F3R2_FB7                         CAN_F3R2_FB7_Msk                  /*!< Filter bit 7 */
9447 #define CAN_F3R2_FB8_Pos                     (8U)
9448 #define CAN_F3R2_FB8_Msk                     (0x1UL << CAN_F3R2_FB8_Pos)        /*!< 0x00000100 */
9449 #define CAN_F3R2_FB8                         CAN_F3R2_FB8_Msk                  /*!< Filter bit 8 */
9450 #define CAN_F3R2_FB9_Pos                     (9U)
9451 #define CAN_F3R2_FB9_Msk                     (0x1UL << CAN_F3R2_FB9_Pos)        /*!< 0x00000200 */
9452 #define CAN_F3R2_FB9                         CAN_F3R2_FB9_Msk                  /*!< Filter bit 9 */
9453 #define CAN_F3R2_FB10_Pos                    (10U)
9454 #define CAN_F3R2_FB10_Msk                    (0x1UL << CAN_F3R2_FB10_Pos)       /*!< 0x00000400 */
9455 #define CAN_F3R2_FB10                        CAN_F3R2_FB10_Msk                 /*!< Filter bit 10 */
9456 #define CAN_F3R2_FB11_Pos                    (11U)
9457 #define CAN_F3R2_FB11_Msk                    (0x1UL << CAN_F3R2_FB11_Pos)       /*!< 0x00000800 */
9458 #define CAN_F3R2_FB11                        CAN_F3R2_FB11_Msk                 /*!< Filter bit 11 */
9459 #define CAN_F3R2_FB12_Pos                    (12U)
9460 #define CAN_F3R2_FB12_Msk                    (0x1UL << CAN_F3R2_FB12_Pos)       /*!< 0x00001000 */
9461 #define CAN_F3R2_FB12                        CAN_F3R2_FB12_Msk                 /*!< Filter bit 12 */
9462 #define CAN_F3R2_FB13_Pos                    (13U)
9463 #define CAN_F3R2_FB13_Msk                    (0x1UL << CAN_F3R2_FB13_Pos)       /*!< 0x00002000 */
9464 #define CAN_F3R2_FB13                        CAN_F3R2_FB13_Msk                 /*!< Filter bit 13 */
9465 #define CAN_F3R2_FB14_Pos                    (14U)
9466 #define CAN_F3R2_FB14_Msk                    (0x1UL << CAN_F3R2_FB14_Pos)       /*!< 0x00004000 */
9467 #define CAN_F3R2_FB14                        CAN_F3R2_FB14_Msk                 /*!< Filter bit 14 */
9468 #define CAN_F3R2_FB15_Pos                    (15U)
9469 #define CAN_F3R2_FB15_Msk                    (0x1UL << CAN_F3R2_FB15_Pos)       /*!< 0x00008000 */
9470 #define CAN_F3R2_FB15                        CAN_F3R2_FB15_Msk                 /*!< Filter bit 15 */
9471 #define CAN_F3R2_FB16_Pos                    (16U)
9472 #define CAN_F3R2_FB16_Msk                    (0x1UL << CAN_F3R2_FB16_Pos)       /*!< 0x00010000 */
9473 #define CAN_F3R2_FB16                        CAN_F3R2_FB16_Msk                 /*!< Filter bit 16 */
9474 #define CAN_F3R2_FB17_Pos                    (17U)
9475 #define CAN_F3R2_FB17_Msk                    (0x1UL << CAN_F3R2_FB17_Pos)       /*!< 0x00020000 */
9476 #define CAN_F3R2_FB17                        CAN_F3R2_FB17_Msk                 /*!< Filter bit 17 */
9477 #define CAN_F3R2_FB18_Pos                    (18U)
9478 #define CAN_F3R2_FB18_Msk                    (0x1UL << CAN_F3R2_FB18_Pos)       /*!< 0x00040000 */
9479 #define CAN_F3R2_FB18                        CAN_F3R2_FB18_Msk                 /*!< Filter bit 18 */
9480 #define CAN_F3R2_FB19_Pos                    (19U)
9481 #define CAN_F3R2_FB19_Msk                    (0x1UL << CAN_F3R2_FB19_Pos)       /*!< 0x00080000 */
9482 #define CAN_F3R2_FB19                        CAN_F3R2_FB19_Msk                 /*!< Filter bit 19 */
9483 #define CAN_F3R2_FB20_Pos                    (20U)
9484 #define CAN_F3R2_FB20_Msk                    (0x1UL << CAN_F3R2_FB20_Pos)       /*!< 0x00100000 */
9485 #define CAN_F3R2_FB20                        CAN_F3R2_FB20_Msk                 /*!< Filter bit 20 */
9486 #define CAN_F3R2_FB21_Pos                    (21U)
9487 #define CAN_F3R2_FB21_Msk                    (0x1UL << CAN_F3R2_FB21_Pos)       /*!< 0x00200000 */
9488 #define CAN_F3R2_FB21                        CAN_F3R2_FB21_Msk                 /*!< Filter bit 21 */
9489 #define CAN_F3R2_FB22_Pos                    (22U)
9490 #define CAN_F3R2_FB22_Msk                    (0x1UL << CAN_F3R2_FB22_Pos)       /*!< 0x00400000 */
9491 #define CAN_F3R2_FB22                        CAN_F3R2_FB22_Msk                 /*!< Filter bit 22 */
9492 #define CAN_F3R2_FB23_Pos                    (23U)
9493 #define CAN_F3R2_FB23_Msk                    (0x1UL << CAN_F3R2_FB23_Pos)       /*!< 0x00800000 */
9494 #define CAN_F3R2_FB23                        CAN_F3R2_FB23_Msk                 /*!< Filter bit 23 */
9495 #define CAN_F3R2_FB24_Pos                    (24U)
9496 #define CAN_F3R2_FB24_Msk                    (0x1UL << CAN_F3R2_FB24_Pos)       /*!< 0x01000000 */
9497 #define CAN_F3R2_FB24                        CAN_F3R2_FB24_Msk                 /*!< Filter bit 24 */
9498 #define CAN_F3R2_FB25_Pos                    (25U)
9499 #define CAN_F3R2_FB25_Msk                    (0x1UL << CAN_F3R2_FB25_Pos)       /*!< 0x02000000 */
9500 #define CAN_F3R2_FB25                        CAN_F3R2_FB25_Msk                 /*!< Filter bit 25 */
9501 #define CAN_F3R2_FB26_Pos                    (26U)
9502 #define CAN_F3R2_FB26_Msk                    (0x1UL << CAN_F3R2_FB26_Pos)       /*!< 0x04000000 */
9503 #define CAN_F3R2_FB26                        CAN_F3R2_FB26_Msk                 /*!< Filter bit 26 */
9504 #define CAN_F3R2_FB27_Pos                    (27U)
9505 #define CAN_F3R2_FB27_Msk                    (0x1UL << CAN_F3R2_FB27_Pos)       /*!< 0x08000000 */
9506 #define CAN_F3R2_FB27                        CAN_F3R2_FB27_Msk                 /*!< Filter bit 27 */
9507 #define CAN_F3R2_FB28_Pos                    (28U)
9508 #define CAN_F3R2_FB28_Msk                    (0x1UL << CAN_F3R2_FB28_Pos)       /*!< 0x10000000 */
9509 #define CAN_F3R2_FB28                        CAN_F3R2_FB28_Msk                 /*!< Filter bit 28 */
9510 #define CAN_F3R2_FB29_Pos                    (29U)
9511 #define CAN_F3R2_FB29_Msk                    (0x1UL << CAN_F3R2_FB29_Pos)       /*!< 0x20000000 */
9512 #define CAN_F3R2_FB29                        CAN_F3R2_FB29_Msk                 /*!< Filter bit 29 */
9513 #define CAN_F3R2_FB30_Pos                    (30U)
9514 #define CAN_F3R2_FB30_Msk                    (0x1UL << CAN_F3R2_FB30_Pos)       /*!< 0x40000000 */
9515 #define CAN_F3R2_FB30                        CAN_F3R2_FB30_Msk                 /*!< Filter bit 30 */
9516 #define CAN_F3R2_FB31_Pos                    (31U)
9517 #define CAN_F3R2_FB31_Msk                    (0x1UL << CAN_F3R2_FB31_Pos)       /*!< 0x80000000 */
9518 #define CAN_F3R2_FB31                        CAN_F3R2_FB31_Msk                 /*!< Filter bit 31 */
9519 
9520 /*******************  Bit definition for CAN_F4R2 register  *******************/
9521 #define CAN_F4R2_FB0_Pos                     (0U)
9522 #define CAN_F4R2_FB0_Msk                     (0x1UL << CAN_F4R2_FB0_Pos)        /*!< 0x00000001 */
9523 #define CAN_F4R2_FB0                         CAN_F4R2_FB0_Msk                  /*!< Filter bit 0 */
9524 #define CAN_F4R2_FB1_Pos                     (1U)
9525 #define CAN_F4R2_FB1_Msk                     (0x1UL << CAN_F4R2_FB1_Pos)        /*!< 0x00000002 */
9526 #define CAN_F4R2_FB1                         CAN_F4R2_FB1_Msk                  /*!< Filter bit 1 */
9527 #define CAN_F4R2_FB2_Pos                     (2U)
9528 #define CAN_F4R2_FB2_Msk                     (0x1UL << CAN_F4R2_FB2_Pos)        /*!< 0x00000004 */
9529 #define CAN_F4R2_FB2                         CAN_F4R2_FB2_Msk                  /*!< Filter bit 2 */
9530 #define CAN_F4R2_FB3_Pos                     (3U)
9531 #define CAN_F4R2_FB3_Msk                     (0x1UL << CAN_F4R2_FB3_Pos)        /*!< 0x00000008 */
9532 #define CAN_F4R2_FB3                         CAN_F4R2_FB3_Msk                  /*!< Filter bit 3 */
9533 #define CAN_F4R2_FB4_Pos                     (4U)
9534 #define CAN_F4R2_FB4_Msk                     (0x1UL << CAN_F4R2_FB4_Pos)        /*!< 0x00000010 */
9535 #define CAN_F4R2_FB4                         CAN_F4R2_FB4_Msk                  /*!< Filter bit 4 */
9536 #define CAN_F4R2_FB5_Pos                     (5U)
9537 #define CAN_F4R2_FB5_Msk                     (0x1UL << CAN_F4R2_FB5_Pos)        /*!< 0x00000020 */
9538 #define CAN_F4R2_FB5                         CAN_F4R2_FB5_Msk                  /*!< Filter bit 5 */
9539 #define CAN_F4R2_FB6_Pos                     (6U)
9540 #define CAN_F4R2_FB6_Msk                     (0x1UL << CAN_F4R2_FB6_Pos)        /*!< 0x00000040 */
9541 #define CAN_F4R2_FB6                         CAN_F4R2_FB6_Msk                  /*!< Filter bit 6 */
9542 #define CAN_F4R2_FB7_Pos                     (7U)
9543 #define CAN_F4R2_FB7_Msk                     (0x1UL << CAN_F4R2_FB7_Pos)        /*!< 0x00000080 */
9544 #define CAN_F4R2_FB7                         CAN_F4R2_FB7_Msk                  /*!< Filter bit 7 */
9545 #define CAN_F4R2_FB8_Pos                     (8U)
9546 #define CAN_F4R2_FB8_Msk                     (0x1UL << CAN_F4R2_FB8_Pos)        /*!< 0x00000100 */
9547 #define CAN_F4R2_FB8                         CAN_F4R2_FB8_Msk                  /*!< Filter bit 8 */
9548 #define CAN_F4R2_FB9_Pos                     (9U)
9549 #define CAN_F4R2_FB9_Msk                     (0x1UL << CAN_F4R2_FB9_Pos)        /*!< 0x00000200 */
9550 #define CAN_F4R2_FB9                         CAN_F4R2_FB9_Msk                  /*!< Filter bit 9 */
9551 #define CAN_F4R2_FB10_Pos                    (10U)
9552 #define CAN_F4R2_FB10_Msk                    (0x1UL << CAN_F4R2_FB10_Pos)       /*!< 0x00000400 */
9553 #define CAN_F4R2_FB10                        CAN_F4R2_FB10_Msk                 /*!< Filter bit 10 */
9554 #define CAN_F4R2_FB11_Pos                    (11U)
9555 #define CAN_F4R2_FB11_Msk                    (0x1UL << CAN_F4R2_FB11_Pos)       /*!< 0x00000800 */
9556 #define CAN_F4R2_FB11                        CAN_F4R2_FB11_Msk                 /*!< Filter bit 11 */
9557 #define CAN_F4R2_FB12_Pos                    (12U)
9558 #define CAN_F4R2_FB12_Msk                    (0x1UL << CAN_F4R2_FB12_Pos)       /*!< 0x00001000 */
9559 #define CAN_F4R2_FB12                        CAN_F4R2_FB12_Msk                 /*!< Filter bit 12 */
9560 #define CAN_F4R2_FB13_Pos                    (13U)
9561 #define CAN_F4R2_FB13_Msk                    (0x1UL << CAN_F4R2_FB13_Pos)       /*!< 0x00002000 */
9562 #define CAN_F4R2_FB13                        CAN_F4R2_FB13_Msk                 /*!< Filter bit 13 */
9563 #define CAN_F4R2_FB14_Pos                    (14U)
9564 #define CAN_F4R2_FB14_Msk                    (0x1UL << CAN_F4R2_FB14_Pos)       /*!< 0x00004000 */
9565 #define CAN_F4R2_FB14                        CAN_F4R2_FB14_Msk                 /*!< Filter bit 14 */
9566 #define CAN_F4R2_FB15_Pos                    (15U)
9567 #define CAN_F4R2_FB15_Msk                    (0x1UL << CAN_F4R2_FB15_Pos)       /*!< 0x00008000 */
9568 #define CAN_F4R2_FB15                        CAN_F4R2_FB15_Msk                 /*!< Filter bit 15 */
9569 #define CAN_F4R2_FB16_Pos                    (16U)
9570 #define CAN_F4R2_FB16_Msk                    (0x1UL << CAN_F4R2_FB16_Pos)       /*!< 0x00010000 */
9571 #define CAN_F4R2_FB16                        CAN_F4R2_FB16_Msk                 /*!< Filter bit 16 */
9572 #define CAN_F4R2_FB17_Pos                    (17U)
9573 #define CAN_F4R2_FB17_Msk                    (0x1UL << CAN_F4R2_FB17_Pos)       /*!< 0x00020000 */
9574 #define CAN_F4R2_FB17                        CAN_F4R2_FB17_Msk                 /*!< Filter bit 17 */
9575 #define CAN_F4R2_FB18_Pos                    (18U)
9576 #define CAN_F4R2_FB18_Msk                    (0x1UL << CAN_F4R2_FB18_Pos)       /*!< 0x00040000 */
9577 #define CAN_F4R2_FB18                        CAN_F4R2_FB18_Msk                 /*!< Filter bit 18 */
9578 #define CAN_F4R2_FB19_Pos                    (19U)
9579 #define CAN_F4R2_FB19_Msk                    (0x1UL << CAN_F4R2_FB19_Pos)       /*!< 0x00080000 */
9580 #define CAN_F4R2_FB19                        CAN_F4R2_FB19_Msk                 /*!< Filter bit 19 */
9581 #define CAN_F4R2_FB20_Pos                    (20U)
9582 #define CAN_F4R2_FB20_Msk                    (0x1UL << CAN_F4R2_FB20_Pos)       /*!< 0x00100000 */
9583 #define CAN_F4R2_FB20                        CAN_F4R2_FB20_Msk                 /*!< Filter bit 20 */
9584 #define CAN_F4R2_FB21_Pos                    (21U)
9585 #define CAN_F4R2_FB21_Msk                    (0x1UL << CAN_F4R2_FB21_Pos)       /*!< 0x00200000 */
9586 #define CAN_F4R2_FB21                        CAN_F4R2_FB21_Msk                 /*!< Filter bit 21 */
9587 #define CAN_F4R2_FB22_Pos                    (22U)
9588 #define CAN_F4R2_FB22_Msk                    (0x1UL << CAN_F4R2_FB22_Pos)       /*!< 0x00400000 */
9589 #define CAN_F4R2_FB22                        CAN_F4R2_FB22_Msk                 /*!< Filter bit 22 */
9590 #define CAN_F4R2_FB23_Pos                    (23U)
9591 #define CAN_F4R2_FB23_Msk                    (0x1UL << CAN_F4R2_FB23_Pos)       /*!< 0x00800000 */
9592 #define CAN_F4R2_FB23                        CAN_F4R2_FB23_Msk                 /*!< Filter bit 23 */
9593 #define CAN_F4R2_FB24_Pos                    (24U)
9594 #define CAN_F4R2_FB24_Msk                    (0x1UL << CAN_F4R2_FB24_Pos)       /*!< 0x01000000 */
9595 #define CAN_F4R2_FB24                        CAN_F4R2_FB24_Msk                 /*!< Filter bit 24 */
9596 #define CAN_F4R2_FB25_Pos                    (25U)
9597 #define CAN_F4R2_FB25_Msk                    (0x1UL << CAN_F4R2_FB25_Pos)       /*!< 0x02000000 */
9598 #define CAN_F4R2_FB25                        CAN_F4R2_FB25_Msk                 /*!< Filter bit 25 */
9599 #define CAN_F4R2_FB26_Pos                    (26U)
9600 #define CAN_F4R2_FB26_Msk                    (0x1UL << CAN_F4R2_FB26_Pos)       /*!< 0x04000000 */
9601 #define CAN_F4R2_FB26                        CAN_F4R2_FB26_Msk                 /*!< Filter bit 26 */
9602 #define CAN_F4R2_FB27_Pos                    (27U)
9603 #define CAN_F4R2_FB27_Msk                    (0x1UL << CAN_F4R2_FB27_Pos)       /*!< 0x08000000 */
9604 #define CAN_F4R2_FB27                        CAN_F4R2_FB27_Msk                 /*!< Filter bit 27 */
9605 #define CAN_F4R2_FB28_Pos                    (28U)
9606 #define CAN_F4R2_FB28_Msk                    (0x1UL << CAN_F4R2_FB28_Pos)       /*!< 0x10000000 */
9607 #define CAN_F4R2_FB28                        CAN_F4R2_FB28_Msk                 /*!< Filter bit 28 */
9608 #define CAN_F4R2_FB29_Pos                    (29U)
9609 #define CAN_F4R2_FB29_Msk                    (0x1UL << CAN_F4R2_FB29_Pos)       /*!< 0x20000000 */
9610 #define CAN_F4R2_FB29                        CAN_F4R2_FB29_Msk                 /*!< Filter bit 29 */
9611 #define CAN_F4R2_FB30_Pos                    (30U)
9612 #define CAN_F4R2_FB30_Msk                    (0x1UL << CAN_F4R2_FB30_Pos)       /*!< 0x40000000 */
9613 #define CAN_F4R2_FB30                        CAN_F4R2_FB30_Msk                 /*!< Filter bit 30 */
9614 #define CAN_F4R2_FB31_Pos                    (31U)
9615 #define CAN_F4R2_FB31_Msk                    (0x1UL << CAN_F4R2_FB31_Pos)       /*!< 0x80000000 */
9616 #define CAN_F4R2_FB31                        CAN_F4R2_FB31_Msk                 /*!< Filter bit 31 */
9617 
9618 /*******************  Bit definition for CAN_F5R2 register  *******************/
9619 #define CAN_F5R2_FB0_Pos                     (0U)
9620 #define CAN_F5R2_FB0_Msk                     (0x1UL << CAN_F5R2_FB0_Pos)        /*!< 0x00000001 */
9621 #define CAN_F5R2_FB0                         CAN_F5R2_FB0_Msk                  /*!< Filter bit 0 */
9622 #define CAN_F5R2_FB1_Pos                     (1U)
9623 #define CAN_F5R2_FB1_Msk                     (0x1UL << CAN_F5R2_FB1_Pos)        /*!< 0x00000002 */
9624 #define CAN_F5R2_FB1                         CAN_F5R2_FB1_Msk                  /*!< Filter bit 1 */
9625 #define CAN_F5R2_FB2_Pos                     (2U)
9626 #define CAN_F5R2_FB2_Msk                     (0x1UL << CAN_F5R2_FB2_Pos)        /*!< 0x00000004 */
9627 #define CAN_F5R2_FB2                         CAN_F5R2_FB2_Msk                  /*!< Filter bit 2 */
9628 #define CAN_F5R2_FB3_Pos                     (3U)
9629 #define CAN_F5R2_FB3_Msk                     (0x1UL << CAN_F5R2_FB3_Pos)        /*!< 0x00000008 */
9630 #define CAN_F5R2_FB3                         CAN_F5R2_FB3_Msk                  /*!< Filter bit 3 */
9631 #define CAN_F5R2_FB4_Pos                     (4U)
9632 #define CAN_F5R2_FB4_Msk                     (0x1UL << CAN_F5R2_FB4_Pos)        /*!< 0x00000010 */
9633 #define CAN_F5R2_FB4                         CAN_F5R2_FB4_Msk                  /*!< Filter bit 4 */
9634 #define CAN_F5R2_FB5_Pos                     (5U)
9635 #define CAN_F5R2_FB5_Msk                     (0x1UL << CAN_F5R2_FB5_Pos)        /*!< 0x00000020 */
9636 #define CAN_F5R2_FB5                         CAN_F5R2_FB5_Msk                  /*!< Filter bit 5 */
9637 #define CAN_F5R2_FB6_Pos                     (6U)
9638 #define CAN_F5R2_FB6_Msk                     (0x1UL << CAN_F5R2_FB6_Pos)        /*!< 0x00000040 */
9639 #define CAN_F5R2_FB6                         CAN_F5R2_FB6_Msk                  /*!< Filter bit 6 */
9640 #define CAN_F5R2_FB7_Pos                     (7U)
9641 #define CAN_F5R2_FB7_Msk                     (0x1UL << CAN_F5R2_FB7_Pos)        /*!< 0x00000080 */
9642 #define CAN_F5R2_FB7                         CAN_F5R2_FB7_Msk                  /*!< Filter bit 7 */
9643 #define CAN_F5R2_FB8_Pos                     (8U)
9644 #define CAN_F5R2_FB8_Msk                     (0x1UL << CAN_F5R2_FB8_Pos)        /*!< 0x00000100 */
9645 #define CAN_F5R2_FB8                         CAN_F5R2_FB8_Msk                  /*!< Filter bit 8 */
9646 #define CAN_F5R2_FB9_Pos                     (9U)
9647 #define CAN_F5R2_FB9_Msk                     (0x1UL << CAN_F5R2_FB9_Pos)        /*!< 0x00000200 */
9648 #define CAN_F5R2_FB9                         CAN_F5R2_FB9_Msk                  /*!< Filter bit 9 */
9649 #define CAN_F5R2_FB10_Pos                    (10U)
9650 #define CAN_F5R2_FB10_Msk                    (0x1UL << CAN_F5R2_FB10_Pos)       /*!< 0x00000400 */
9651 #define CAN_F5R2_FB10                        CAN_F5R2_FB10_Msk                 /*!< Filter bit 10 */
9652 #define CAN_F5R2_FB11_Pos                    (11U)
9653 #define CAN_F5R2_FB11_Msk                    (0x1UL << CAN_F5R2_FB11_Pos)       /*!< 0x00000800 */
9654 #define CAN_F5R2_FB11                        CAN_F5R2_FB11_Msk                 /*!< Filter bit 11 */
9655 #define CAN_F5R2_FB12_Pos                    (12U)
9656 #define CAN_F5R2_FB12_Msk                    (0x1UL << CAN_F5R2_FB12_Pos)       /*!< 0x00001000 */
9657 #define CAN_F5R2_FB12                        CAN_F5R2_FB12_Msk                 /*!< Filter bit 12 */
9658 #define CAN_F5R2_FB13_Pos                    (13U)
9659 #define CAN_F5R2_FB13_Msk                    (0x1UL << CAN_F5R2_FB13_Pos)       /*!< 0x00002000 */
9660 #define CAN_F5R2_FB13                        CAN_F5R2_FB13_Msk                 /*!< Filter bit 13 */
9661 #define CAN_F5R2_FB14_Pos                    (14U)
9662 #define CAN_F5R2_FB14_Msk                    (0x1UL << CAN_F5R2_FB14_Pos)       /*!< 0x00004000 */
9663 #define CAN_F5R2_FB14                        CAN_F5R2_FB14_Msk                 /*!< Filter bit 14 */
9664 #define CAN_F5R2_FB15_Pos                    (15U)
9665 #define CAN_F5R2_FB15_Msk                    (0x1UL << CAN_F5R2_FB15_Pos)       /*!< 0x00008000 */
9666 #define CAN_F5R2_FB15                        CAN_F5R2_FB15_Msk                 /*!< Filter bit 15 */
9667 #define CAN_F5R2_FB16_Pos                    (16U)
9668 #define CAN_F5R2_FB16_Msk                    (0x1UL << CAN_F5R2_FB16_Pos)       /*!< 0x00010000 */
9669 #define CAN_F5R2_FB16                        CAN_F5R2_FB16_Msk                 /*!< Filter bit 16 */
9670 #define CAN_F5R2_FB17_Pos                    (17U)
9671 #define CAN_F5R2_FB17_Msk                    (0x1UL << CAN_F5R2_FB17_Pos)       /*!< 0x00020000 */
9672 #define CAN_F5R2_FB17                        CAN_F5R2_FB17_Msk                 /*!< Filter bit 17 */
9673 #define CAN_F5R2_FB18_Pos                    (18U)
9674 #define CAN_F5R2_FB18_Msk                    (0x1UL << CAN_F5R2_FB18_Pos)       /*!< 0x00040000 */
9675 #define CAN_F5R2_FB18                        CAN_F5R2_FB18_Msk                 /*!< Filter bit 18 */
9676 #define CAN_F5R2_FB19_Pos                    (19U)
9677 #define CAN_F5R2_FB19_Msk                    (0x1UL << CAN_F5R2_FB19_Pos)       /*!< 0x00080000 */
9678 #define CAN_F5R2_FB19                        CAN_F5R2_FB19_Msk                 /*!< Filter bit 19 */
9679 #define CAN_F5R2_FB20_Pos                    (20U)
9680 #define CAN_F5R2_FB20_Msk                    (0x1UL << CAN_F5R2_FB20_Pos)       /*!< 0x00100000 */
9681 #define CAN_F5R2_FB20                        CAN_F5R2_FB20_Msk                 /*!< Filter bit 20 */
9682 #define CAN_F5R2_FB21_Pos                    (21U)
9683 #define CAN_F5R2_FB21_Msk                    (0x1UL << CAN_F5R2_FB21_Pos)       /*!< 0x00200000 */
9684 #define CAN_F5R2_FB21                        CAN_F5R2_FB21_Msk                 /*!< Filter bit 21 */
9685 #define CAN_F5R2_FB22_Pos                    (22U)
9686 #define CAN_F5R2_FB22_Msk                    (0x1UL << CAN_F5R2_FB22_Pos)       /*!< 0x00400000 */
9687 #define CAN_F5R2_FB22                        CAN_F5R2_FB22_Msk                 /*!< Filter bit 22 */
9688 #define CAN_F5R2_FB23_Pos                    (23U)
9689 #define CAN_F5R2_FB23_Msk                    (0x1UL << CAN_F5R2_FB23_Pos)       /*!< 0x00800000 */
9690 #define CAN_F5R2_FB23                        CAN_F5R2_FB23_Msk                 /*!< Filter bit 23 */
9691 #define CAN_F5R2_FB24_Pos                    (24U)
9692 #define CAN_F5R2_FB24_Msk                    (0x1UL << CAN_F5R2_FB24_Pos)       /*!< 0x01000000 */
9693 #define CAN_F5R2_FB24                        CAN_F5R2_FB24_Msk                 /*!< Filter bit 24 */
9694 #define CAN_F5R2_FB25_Pos                    (25U)
9695 #define CAN_F5R2_FB25_Msk                    (0x1UL << CAN_F5R2_FB25_Pos)       /*!< 0x02000000 */
9696 #define CAN_F5R2_FB25                        CAN_F5R2_FB25_Msk                 /*!< Filter bit 25 */
9697 #define CAN_F5R2_FB26_Pos                    (26U)
9698 #define CAN_F5R2_FB26_Msk                    (0x1UL << CAN_F5R2_FB26_Pos)       /*!< 0x04000000 */
9699 #define CAN_F5R2_FB26                        CAN_F5R2_FB26_Msk                 /*!< Filter bit 26 */
9700 #define CAN_F5R2_FB27_Pos                    (27U)
9701 #define CAN_F5R2_FB27_Msk                    (0x1UL << CAN_F5R2_FB27_Pos)       /*!< 0x08000000 */
9702 #define CAN_F5R2_FB27                        CAN_F5R2_FB27_Msk                 /*!< Filter bit 27 */
9703 #define CAN_F5R2_FB28_Pos                    (28U)
9704 #define CAN_F5R2_FB28_Msk                    (0x1UL << CAN_F5R2_FB28_Pos)       /*!< 0x10000000 */
9705 #define CAN_F5R2_FB28                        CAN_F5R2_FB28_Msk                 /*!< Filter bit 28 */
9706 #define CAN_F5R2_FB29_Pos                    (29U)
9707 #define CAN_F5R2_FB29_Msk                    (0x1UL << CAN_F5R2_FB29_Pos)       /*!< 0x20000000 */
9708 #define CAN_F5R2_FB29                        CAN_F5R2_FB29_Msk                 /*!< Filter bit 29 */
9709 #define CAN_F5R2_FB30_Pos                    (30U)
9710 #define CAN_F5R2_FB30_Msk                    (0x1UL << CAN_F5R2_FB30_Pos)       /*!< 0x40000000 */
9711 #define CAN_F5R2_FB30                        CAN_F5R2_FB30_Msk                 /*!< Filter bit 30 */
9712 #define CAN_F5R2_FB31_Pos                    (31U)
9713 #define CAN_F5R2_FB31_Msk                    (0x1UL << CAN_F5R2_FB31_Pos)       /*!< 0x80000000 */
9714 #define CAN_F5R2_FB31                        CAN_F5R2_FB31_Msk                 /*!< Filter bit 31 */
9715 
9716 /*******************  Bit definition for CAN_F6R2 register  *******************/
9717 #define CAN_F6R2_FB0_Pos                     (0U)
9718 #define CAN_F6R2_FB0_Msk                     (0x1UL << CAN_F6R2_FB0_Pos)        /*!< 0x00000001 */
9719 #define CAN_F6R2_FB0                         CAN_F6R2_FB0_Msk                  /*!< Filter bit 0 */
9720 #define CAN_F6R2_FB1_Pos                     (1U)
9721 #define CAN_F6R2_FB1_Msk                     (0x1UL << CAN_F6R2_FB1_Pos)        /*!< 0x00000002 */
9722 #define CAN_F6R2_FB1                         CAN_F6R2_FB1_Msk                  /*!< Filter bit 1 */
9723 #define CAN_F6R2_FB2_Pos                     (2U)
9724 #define CAN_F6R2_FB2_Msk                     (0x1UL << CAN_F6R2_FB2_Pos)        /*!< 0x00000004 */
9725 #define CAN_F6R2_FB2                         CAN_F6R2_FB2_Msk                  /*!< Filter bit 2 */
9726 #define CAN_F6R2_FB3_Pos                     (3U)
9727 #define CAN_F6R2_FB3_Msk                     (0x1UL << CAN_F6R2_FB3_Pos)        /*!< 0x00000008 */
9728 #define CAN_F6R2_FB3                         CAN_F6R2_FB3_Msk                  /*!< Filter bit 3 */
9729 #define CAN_F6R2_FB4_Pos                     (4U)
9730 #define CAN_F6R2_FB4_Msk                     (0x1UL << CAN_F6R2_FB4_Pos)        /*!< 0x00000010 */
9731 #define CAN_F6R2_FB4                         CAN_F6R2_FB4_Msk                  /*!< Filter bit 4 */
9732 #define CAN_F6R2_FB5_Pos                     (5U)
9733 #define CAN_F6R2_FB5_Msk                     (0x1UL << CAN_F6R2_FB5_Pos)        /*!< 0x00000020 */
9734 #define CAN_F6R2_FB5                         CAN_F6R2_FB5_Msk                  /*!< Filter bit 5 */
9735 #define CAN_F6R2_FB6_Pos                     (6U)
9736 #define CAN_F6R2_FB6_Msk                     (0x1UL << CAN_F6R2_FB6_Pos)        /*!< 0x00000040 */
9737 #define CAN_F6R2_FB6                         CAN_F6R2_FB6_Msk                  /*!< Filter bit 6 */
9738 #define CAN_F6R2_FB7_Pos                     (7U)
9739 #define CAN_F6R2_FB7_Msk                     (0x1UL << CAN_F6R2_FB7_Pos)        /*!< 0x00000080 */
9740 #define CAN_F6R2_FB7                         CAN_F6R2_FB7_Msk                  /*!< Filter bit 7 */
9741 #define CAN_F6R2_FB8_Pos                     (8U)
9742 #define CAN_F6R2_FB8_Msk                     (0x1UL << CAN_F6R2_FB8_Pos)        /*!< 0x00000100 */
9743 #define CAN_F6R2_FB8                         CAN_F6R2_FB8_Msk                  /*!< Filter bit 8 */
9744 #define CAN_F6R2_FB9_Pos                     (9U)
9745 #define CAN_F6R2_FB9_Msk                     (0x1UL << CAN_F6R2_FB9_Pos)        /*!< 0x00000200 */
9746 #define CAN_F6R2_FB9                         CAN_F6R2_FB9_Msk                  /*!< Filter bit 9 */
9747 #define CAN_F6R2_FB10_Pos                    (10U)
9748 #define CAN_F6R2_FB10_Msk                    (0x1UL << CAN_F6R2_FB10_Pos)       /*!< 0x00000400 */
9749 #define CAN_F6R2_FB10                        CAN_F6R2_FB10_Msk                 /*!< Filter bit 10 */
9750 #define CAN_F6R2_FB11_Pos                    (11U)
9751 #define CAN_F6R2_FB11_Msk                    (0x1UL << CAN_F6R2_FB11_Pos)       /*!< 0x00000800 */
9752 #define CAN_F6R2_FB11                        CAN_F6R2_FB11_Msk                 /*!< Filter bit 11 */
9753 #define CAN_F6R2_FB12_Pos                    (12U)
9754 #define CAN_F6R2_FB12_Msk                    (0x1UL << CAN_F6R2_FB12_Pos)       /*!< 0x00001000 */
9755 #define CAN_F6R2_FB12                        CAN_F6R2_FB12_Msk                 /*!< Filter bit 12 */
9756 #define CAN_F6R2_FB13_Pos                    (13U)
9757 #define CAN_F6R2_FB13_Msk                    (0x1UL << CAN_F6R2_FB13_Pos)       /*!< 0x00002000 */
9758 #define CAN_F6R2_FB13                        CAN_F6R2_FB13_Msk                 /*!< Filter bit 13 */
9759 #define CAN_F6R2_FB14_Pos                    (14U)
9760 #define CAN_F6R2_FB14_Msk                    (0x1UL << CAN_F6R2_FB14_Pos)       /*!< 0x00004000 */
9761 #define CAN_F6R2_FB14                        CAN_F6R2_FB14_Msk                 /*!< Filter bit 14 */
9762 #define CAN_F6R2_FB15_Pos                    (15U)
9763 #define CAN_F6R2_FB15_Msk                    (0x1UL << CAN_F6R2_FB15_Pos)       /*!< 0x00008000 */
9764 #define CAN_F6R2_FB15                        CAN_F6R2_FB15_Msk                 /*!< Filter bit 15 */
9765 #define CAN_F6R2_FB16_Pos                    (16U)
9766 #define CAN_F6R2_FB16_Msk                    (0x1UL << CAN_F6R2_FB16_Pos)       /*!< 0x00010000 */
9767 #define CAN_F6R2_FB16                        CAN_F6R2_FB16_Msk                 /*!< Filter bit 16 */
9768 #define CAN_F6R2_FB17_Pos                    (17U)
9769 #define CAN_F6R2_FB17_Msk                    (0x1UL << CAN_F6R2_FB17_Pos)       /*!< 0x00020000 */
9770 #define CAN_F6R2_FB17                        CAN_F6R2_FB17_Msk                 /*!< Filter bit 17 */
9771 #define CAN_F6R2_FB18_Pos                    (18U)
9772 #define CAN_F6R2_FB18_Msk                    (0x1UL << CAN_F6R2_FB18_Pos)       /*!< 0x00040000 */
9773 #define CAN_F6R2_FB18                        CAN_F6R2_FB18_Msk                 /*!< Filter bit 18 */
9774 #define CAN_F6R2_FB19_Pos                    (19U)
9775 #define CAN_F6R2_FB19_Msk                    (0x1UL << CAN_F6R2_FB19_Pos)       /*!< 0x00080000 */
9776 #define CAN_F6R2_FB19                        CAN_F6R2_FB19_Msk                 /*!< Filter bit 19 */
9777 #define CAN_F6R2_FB20_Pos                    (20U)
9778 #define CAN_F6R2_FB20_Msk                    (0x1UL << CAN_F6R2_FB20_Pos)       /*!< 0x00100000 */
9779 #define CAN_F6R2_FB20                        CAN_F6R2_FB20_Msk                 /*!< Filter bit 20 */
9780 #define CAN_F6R2_FB21_Pos                    (21U)
9781 #define CAN_F6R2_FB21_Msk                    (0x1UL << CAN_F6R2_FB21_Pos)       /*!< 0x00200000 */
9782 #define CAN_F6R2_FB21                        CAN_F6R2_FB21_Msk                 /*!< Filter bit 21 */
9783 #define CAN_F6R2_FB22_Pos                    (22U)
9784 #define CAN_F6R2_FB22_Msk                    (0x1UL << CAN_F6R2_FB22_Pos)       /*!< 0x00400000 */
9785 #define CAN_F6R2_FB22                        CAN_F6R2_FB22_Msk                 /*!< Filter bit 22 */
9786 #define CAN_F6R2_FB23_Pos                    (23U)
9787 #define CAN_F6R2_FB23_Msk                    (0x1UL << CAN_F6R2_FB23_Pos)       /*!< 0x00800000 */
9788 #define CAN_F6R2_FB23                        CAN_F6R2_FB23_Msk                 /*!< Filter bit 23 */
9789 #define CAN_F6R2_FB24_Pos                    (24U)
9790 #define CAN_F6R2_FB24_Msk                    (0x1UL << CAN_F6R2_FB24_Pos)       /*!< 0x01000000 */
9791 #define CAN_F6R2_FB24                        CAN_F6R2_FB24_Msk                 /*!< Filter bit 24 */
9792 #define CAN_F6R2_FB25_Pos                    (25U)
9793 #define CAN_F6R2_FB25_Msk                    (0x1UL << CAN_F6R2_FB25_Pos)       /*!< 0x02000000 */
9794 #define CAN_F6R2_FB25                        CAN_F6R2_FB25_Msk                 /*!< Filter bit 25 */
9795 #define CAN_F6R2_FB26_Pos                    (26U)
9796 #define CAN_F6R2_FB26_Msk                    (0x1UL << CAN_F6R2_FB26_Pos)       /*!< 0x04000000 */
9797 #define CAN_F6R2_FB26                        CAN_F6R2_FB26_Msk                 /*!< Filter bit 26 */
9798 #define CAN_F6R2_FB27_Pos                    (27U)
9799 #define CAN_F6R2_FB27_Msk                    (0x1UL << CAN_F6R2_FB27_Pos)       /*!< 0x08000000 */
9800 #define CAN_F6R2_FB27                        CAN_F6R2_FB27_Msk                 /*!< Filter bit 27 */
9801 #define CAN_F6R2_FB28_Pos                    (28U)
9802 #define CAN_F6R2_FB28_Msk                    (0x1UL << CAN_F6R2_FB28_Pos)       /*!< 0x10000000 */
9803 #define CAN_F6R2_FB28                        CAN_F6R2_FB28_Msk                 /*!< Filter bit 28 */
9804 #define CAN_F6R2_FB29_Pos                    (29U)
9805 #define CAN_F6R2_FB29_Msk                    (0x1UL << CAN_F6R2_FB29_Pos)       /*!< 0x20000000 */
9806 #define CAN_F6R2_FB29                        CAN_F6R2_FB29_Msk                 /*!< Filter bit 29 */
9807 #define CAN_F6R2_FB30_Pos                    (30U)
9808 #define CAN_F6R2_FB30_Msk                    (0x1UL << CAN_F6R2_FB30_Pos)       /*!< 0x40000000 */
9809 #define CAN_F6R2_FB30                        CAN_F6R2_FB30_Msk                 /*!< Filter bit 30 */
9810 #define CAN_F6R2_FB31_Pos                    (31U)
9811 #define CAN_F6R2_FB31_Msk                    (0x1UL << CAN_F6R2_FB31_Pos)       /*!< 0x80000000 */
9812 #define CAN_F6R2_FB31                        CAN_F6R2_FB31_Msk                 /*!< Filter bit 31 */
9813 
9814 /*******************  Bit definition for CAN_F7R2 register  *******************/
9815 #define CAN_F7R2_FB0_Pos                     (0U)
9816 #define CAN_F7R2_FB0_Msk                     (0x1UL << CAN_F7R2_FB0_Pos)        /*!< 0x00000001 */
9817 #define CAN_F7R2_FB0                         CAN_F7R2_FB0_Msk                  /*!< Filter bit 0 */
9818 #define CAN_F7R2_FB1_Pos                     (1U)
9819 #define CAN_F7R2_FB1_Msk                     (0x1UL << CAN_F7R2_FB1_Pos)        /*!< 0x00000002 */
9820 #define CAN_F7R2_FB1                         CAN_F7R2_FB1_Msk                  /*!< Filter bit 1 */
9821 #define CAN_F7R2_FB2_Pos                     (2U)
9822 #define CAN_F7R2_FB2_Msk                     (0x1UL << CAN_F7R2_FB2_Pos)        /*!< 0x00000004 */
9823 #define CAN_F7R2_FB2                         CAN_F7R2_FB2_Msk                  /*!< Filter bit 2 */
9824 #define CAN_F7R2_FB3_Pos                     (3U)
9825 #define CAN_F7R2_FB3_Msk                     (0x1UL << CAN_F7R2_FB3_Pos)        /*!< 0x00000008 */
9826 #define CAN_F7R2_FB3                         CAN_F7R2_FB3_Msk                  /*!< Filter bit 3 */
9827 #define CAN_F7R2_FB4_Pos                     (4U)
9828 #define CAN_F7R2_FB4_Msk                     (0x1UL << CAN_F7R2_FB4_Pos)        /*!< 0x00000010 */
9829 #define CAN_F7R2_FB4                         CAN_F7R2_FB4_Msk                  /*!< Filter bit 4 */
9830 #define CAN_F7R2_FB5_Pos                     (5U)
9831 #define CAN_F7R2_FB5_Msk                     (0x1UL << CAN_F7R2_FB5_Pos)        /*!< 0x00000020 */
9832 #define CAN_F7R2_FB5                         CAN_F7R2_FB5_Msk                  /*!< Filter bit 5 */
9833 #define CAN_F7R2_FB6_Pos                     (6U)
9834 #define CAN_F7R2_FB6_Msk                     (0x1UL << CAN_F7R2_FB6_Pos)        /*!< 0x00000040 */
9835 #define CAN_F7R2_FB6                         CAN_F7R2_FB6_Msk                  /*!< Filter bit 6 */
9836 #define CAN_F7R2_FB7_Pos                     (7U)
9837 #define CAN_F7R2_FB7_Msk                     (0x1UL << CAN_F7R2_FB7_Pos)        /*!< 0x00000080 */
9838 #define CAN_F7R2_FB7                         CAN_F7R2_FB7_Msk                  /*!< Filter bit 7 */
9839 #define CAN_F7R2_FB8_Pos                     (8U)
9840 #define CAN_F7R2_FB8_Msk                     (0x1UL << CAN_F7R2_FB8_Pos)        /*!< 0x00000100 */
9841 #define CAN_F7R2_FB8                         CAN_F7R2_FB8_Msk                  /*!< Filter bit 8 */
9842 #define CAN_F7R2_FB9_Pos                     (9U)
9843 #define CAN_F7R2_FB9_Msk                     (0x1UL << CAN_F7R2_FB9_Pos)        /*!< 0x00000200 */
9844 #define CAN_F7R2_FB9                         CAN_F7R2_FB9_Msk                  /*!< Filter bit 9 */
9845 #define CAN_F7R2_FB10_Pos                    (10U)
9846 #define CAN_F7R2_FB10_Msk                    (0x1UL << CAN_F7R2_FB10_Pos)       /*!< 0x00000400 */
9847 #define CAN_F7R2_FB10                        CAN_F7R2_FB10_Msk                 /*!< Filter bit 10 */
9848 #define CAN_F7R2_FB11_Pos                    (11U)
9849 #define CAN_F7R2_FB11_Msk                    (0x1UL << CAN_F7R2_FB11_Pos)       /*!< 0x00000800 */
9850 #define CAN_F7R2_FB11                        CAN_F7R2_FB11_Msk                 /*!< Filter bit 11 */
9851 #define CAN_F7R2_FB12_Pos                    (12U)
9852 #define CAN_F7R2_FB12_Msk                    (0x1UL << CAN_F7R2_FB12_Pos)       /*!< 0x00001000 */
9853 #define CAN_F7R2_FB12                        CAN_F7R2_FB12_Msk                 /*!< Filter bit 12 */
9854 #define CAN_F7R2_FB13_Pos                    (13U)
9855 #define CAN_F7R2_FB13_Msk                    (0x1UL << CAN_F7R2_FB13_Pos)       /*!< 0x00002000 */
9856 #define CAN_F7R2_FB13                        CAN_F7R2_FB13_Msk                 /*!< Filter bit 13 */
9857 #define CAN_F7R2_FB14_Pos                    (14U)
9858 #define CAN_F7R2_FB14_Msk                    (0x1UL << CAN_F7R2_FB14_Pos)       /*!< 0x00004000 */
9859 #define CAN_F7R2_FB14                        CAN_F7R2_FB14_Msk                 /*!< Filter bit 14 */
9860 #define CAN_F7R2_FB15_Pos                    (15U)
9861 #define CAN_F7R2_FB15_Msk                    (0x1UL << CAN_F7R2_FB15_Pos)       /*!< 0x00008000 */
9862 #define CAN_F7R2_FB15                        CAN_F7R2_FB15_Msk                 /*!< Filter bit 15 */
9863 #define CAN_F7R2_FB16_Pos                    (16U)
9864 #define CAN_F7R2_FB16_Msk                    (0x1UL << CAN_F7R2_FB16_Pos)       /*!< 0x00010000 */
9865 #define CAN_F7R2_FB16                        CAN_F7R2_FB16_Msk                 /*!< Filter bit 16 */
9866 #define CAN_F7R2_FB17_Pos                    (17U)
9867 #define CAN_F7R2_FB17_Msk                    (0x1UL << CAN_F7R2_FB17_Pos)       /*!< 0x00020000 */
9868 #define CAN_F7R2_FB17                        CAN_F7R2_FB17_Msk                 /*!< Filter bit 17 */
9869 #define CAN_F7R2_FB18_Pos                    (18U)
9870 #define CAN_F7R2_FB18_Msk                    (0x1UL << CAN_F7R2_FB18_Pos)       /*!< 0x00040000 */
9871 #define CAN_F7R2_FB18                        CAN_F7R2_FB18_Msk                 /*!< Filter bit 18 */
9872 #define CAN_F7R2_FB19_Pos                    (19U)
9873 #define CAN_F7R2_FB19_Msk                    (0x1UL << CAN_F7R2_FB19_Pos)       /*!< 0x00080000 */
9874 #define CAN_F7R2_FB19                        CAN_F7R2_FB19_Msk                 /*!< Filter bit 19 */
9875 #define CAN_F7R2_FB20_Pos                    (20U)
9876 #define CAN_F7R2_FB20_Msk                    (0x1UL << CAN_F7R2_FB20_Pos)       /*!< 0x00100000 */
9877 #define CAN_F7R2_FB20                        CAN_F7R2_FB20_Msk                 /*!< Filter bit 20 */
9878 #define CAN_F7R2_FB21_Pos                    (21U)
9879 #define CAN_F7R2_FB21_Msk                    (0x1UL << CAN_F7R2_FB21_Pos)       /*!< 0x00200000 */
9880 #define CAN_F7R2_FB21                        CAN_F7R2_FB21_Msk                 /*!< Filter bit 21 */
9881 #define CAN_F7R2_FB22_Pos                    (22U)
9882 #define CAN_F7R2_FB22_Msk                    (0x1UL << CAN_F7R2_FB22_Pos)       /*!< 0x00400000 */
9883 #define CAN_F7R2_FB22                        CAN_F7R2_FB22_Msk                 /*!< Filter bit 22 */
9884 #define CAN_F7R2_FB23_Pos                    (23U)
9885 #define CAN_F7R2_FB23_Msk                    (0x1UL << CAN_F7R2_FB23_Pos)       /*!< 0x00800000 */
9886 #define CAN_F7R2_FB23                        CAN_F7R2_FB23_Msk                 /*!< Filter bit 23 */
9887 #define CAN_F7R2_FB24_Pos                    (24U)
9888 #define CAN_F7R2_FB24_Msk                    (0x1UL << CAN_F7R2_FB24_Pos)       /*!< 0x01000000 */
9889 #define CAN_F7R2_FB24                        CAN_F7R2_FB24_Msk                 /*!< Filter bit 24 */
9890 #define CAN_F7R2_FB25_Pos                    (25U)
9891 #define CAN_F7R2_FB25_Msk                    (0x1UL << CAN_F7R2_FB25_Pos)       /*!< 0x02000000 */
9892 #define CAN_F7R2_FB25                        CAN_F7R2_FB25_Msk                 /*!< Filter bit 25 */
9893 #define CAN_F7R2_FB26_Pos                    (26U)
9894 #define CAN_F7R2_FB26_Msk                    (0x1UL << CAN_F7R2_FB26_Pos)       /*!< 0x04000000 */
9895 #define CAN_F7R2_FB26                        CAN_F7R2_FB26_Msk                 /*!< Filter bit 26 */
9896 #define CAN_F7R2_FB27_Pos                    (27U)
9897 #define CAN_F7R2_FB27_Msk                    (0x1UL << CAN_F7R2_FB27_Pos)       /*!< 0x08000000 */
9898 #define CAN_F7R2_FB27                        CAN_F7R2_FB27_Msk                 /*!< Filter bit 27 */
9899 #define CAN_F7R2_FB28_Pos                    (28U)
9900 #define CAN_F7R2_FB28_Msk                    (0x1UL << CAN_F7R2_FB28_Pos)       /*!< 0x10000000 */
9901 #define CAN_F7R2_FB28                        CAN_F7R2_FB28_Msk                 /*!< Filter bit 28 */
9902 #define CAN_F7R2_FB29_Pos                    (29U)
9903 #define CAN_F7R2_FB29_Msk                    (0x1UL << CAN_F7R2_FB29_Pos)       /*!< 0x20000000 */
9904 #define CAN_F7R2_FB29                        CAN_F7R2_FB29_Msk                 /*!< Filter bit 29 */
9905 #define CAN_F7R2_FB30_Pos                    (30U)
9906 #define CAN_F7R2_FB30_Msk                    (0x1UL << CAN_F7R2_FB30_Pos)       /*!< 0x40000000 */
9907 #define CAN_F7R2_FB30                        CAN_F7R2_FB30_Msk                 /*!< Filter bit 30 */
9908 #define CAN_F7R2_FB31_Pos                    (31U)
9909 #define CAN_F7R2_FB31_Msk                    (0x1UL << CAN_F7R2_FB31_Pos)       /*!< 0x80000000 */
9910 #define CAN_F7R2_FB31                        CAN_F7R2_FB31_Msk                 /*!< Filter bit 31 */
9911 
9912 /*******************  Bit definition for CAN_F8R2 register  *******************/
9913 #define CAN_F8R2_FB0_Pos                     (0U)
9914 #define CAN_F8R2_FB0_Msk                     (0x1UL << CAN_F8R2_FB0_Pos)        /*!< 0x00000001 */
9915 #define CAN_F8R2_FB0                         CAN_F8R2_FB0_Msk                  /*!< Filter bit 0 */
9916 #define CAN_F8R2_FB1_Pos                     (1U)
9917 #define CAN_F8R2_FB1_Msk                     (0x1UL << CAN_F8R2_FB1_Pos)        /*!< 0x00000002 */
9918 #define CAN_F8R2_FB1                         CAN_F8R2_FB1_Msk                  /*!< Filter bit 1 */
9919 #define CAN_F8R2_FB2_Pos                     (2U)
9920 #define CAN_F8R2_FB2_Msk                     (0x1UL << CAN_F8R2_FB2_Pos)        /*!< 0x00000004 */
9921 #define CAN_F8R2_FB2                         CAN_F8R2_FB2_Msk                  /*!< Filter bit 2 */
9922 #define CAN_F8R2_FB3_Pos                     (3U)
9923 #define CAN_F8R2_FB3_Msk                     (0x1UL << CAN_F8R2_FB3_Pos)        /*!< 0x00000008 */
9924 #define CAN_F8R2_FB3                         CAN_F8R2_FB3_Msk                  /*!< Filter bit 3 */
9925 #define CAN_F8R2_FB4_Pos                     (4U)
9926 #define CAN_F8R2_FB4_Msk                     (0x1UL << CAN_F8R2_FB4_Pos)        /*!< 0x00000010 */
9927 #define CAN_F8R2_FB4                         CAN_F8R2_FB4_Msk                  /*!< Filter bit 4 */
9928 #define CAN_F8R2_FB5_Pos                     (5U)
9929 #define CAN_F8R2_FB5_Msk                     (0x1UL << CAN_F8R2_FB5_Pos)        /*!< 0x00000020 */
9930 #define CAN_F8R2_FB5                         CAN_F8R2_FB5_Msk                  /*!< Filter bit 5 */
9931 #define CAN_F8R2_FB6_Pos                     (6U)
9932 #define CAN_F8R2_FB6_Msk                     (0x1UL << CAN_F8R2_FB6_Pos)        /*!< 0x00000040 */
9933 #define CAN_F8R2_FB6                         CAN_F8R2_FB6_Msk                  /*!< Filter bit 6 */
9934 #define CAN_F8R2_FB7_Pos                     (7U)
9935 #define CAN_F8R2_FB7_Msk                     (0x1UL << CAN_F8R2_FB7_Pos)        /*!< 0x00000080 */
9936 #define CAN_F8R2_FB7                         CAN_F8R2_FB7_Msk                  /*!< Filter bit 7 */
9937 #define CAN_F8R2_FB8_Pos                     (8U)
9938 #define CAN_F8R2_FB8_Msk                     (0x1UL << CAN_F8R2_FB8_Pos)        /*!< 0x00000100 */
9939 #define CAN_F8R2_FB8                         CAN_F8R2_FB8_Msk                  /*!< Filter bit 8 */
9940 #define CAN_F8R2_FB9_Pos                     (9U)
9941 #define CAN_F8R2_FB9_Msk                     (0x1UL << CAN_F8R2_FB9_Pos)        /*!< 0x00000200 */
9942 #define CAN_F8R2_FB9                         CAN_F8R2_FB9_Msk                  /*!< Filter bit 9 */
9943 #define CAN_F8R2_FB10_Pos                    (10U)
9944 #define CAN_F8R2_FB10_Msk                    (0x1UL << CAN_F8R2_FB10_Pos)       /*!< 0x00000400 */
9945 #define CAN_F8R2_FB10                        CAN_F8R2_FB10_Msk                 /*!< Filter bit 10 */
9946 #define CAN_F8R2_FB11_Pos                    (11U)
9947 #define CAN_F8R2_FB11_Msk                    (0x1UL << CAN_F8R2_FB11_Pos)       /*!< 0x00000800 */
9948 #define CAN_F8R2_FB11                        CAN_F8R2_FB11_Msk                 /*!< Filter bit 11 */
9949 #define CAN_F8R2_FB12_Pos                    (12U)
9950 #define CAN_F8R2_FB12_Msk                    (0x1UL << CAN_F8R2_FB12_Pos)       /*!< 0x00001000 */
9951 #define CAN_F8R2_FB12                        CAN_F8R2_FB12_Msk                 /*!< Filter bit 12 */
9952 #define CAN_F8R2_FB13_Pos                    (13U)
9953 #define CAN_F8R2_FB13_Msk                    (0x1UL << CAN_F8R2_FB13_Pos)       /*!< 0x00002000 */
9954 #define CAN_F8R2_FB13                        CAN_F8R2_FB13_Msk                 /*!< Filter bit 13 */
9955 #define CAN_F8R2_FB14_Pos                    (14U)
9956 #define CAN_F8R2_FB14_Msk                    (0x1UL << CAN_F8R2_FB14_Pos)       /*!< 0x00004000 */
9957 #define CAN_F8R2_FB14                        CAN_F8R2_FB14_Msk                 /*!< Filter bit 14 */
9958 #define CAN_F8R2_FB15_Pos                    (15U)
9959 #define CAN_F8R2_FB15_Msk                    (0x1UL << CAN_F8R2_FB15_Pos)       /*!< 0x00008000 */
9960 #define CAN_F8R2_FB15                        CAN_F8R2_FB15_Msk                 /*!< Filter bit 15 */
9961 #define CAN_F8R2_FB16_Pos                    (16U)
9962 #define CAN_F8R2_FB16_Msk                    (0x1UL << CAN_F8R2_FB16_Pos)       /*!< 0x00010000 */
9963 #define CAN_F8R2_FB16                        CAN_F8R2_FB16_Msk                 /*!< Filter bit 16 */
9964 #define CAN_F8R2_FB17_Pos                    (17U)
9965 #define CAN_F8R2_FB17_Msk                    (0x1UL << CAN_F8R2_FB17_Pos)       /*!< 0x00020000 */
9966 #define CAN_F8R2_FB17                        CAN_F8R2_FB17_Msk                 /*!< Filter bit 17 */
9967 #define CAN_F8R2_FB18_Pos                    (18U)
9968 #define CAN_F8R2_FB18_Msk                    (0x1UL << CAN_F8R2_FB18_Pos)       /*!< 0x00040000 */
9969 #define CAN_F8R2_FB18                        CAN_F8R2_FB18_Msk                 /*!< Filter bit 18 */
9970 #define CAN_F8R2_FB19_Pos                    (19U)
9971 #define CAN_F8R2_FB19_Msk                    (0x1UL << CAN_F8R2_FB19_Pos)       /*!< 0x00080000 */
9972 #define CAN_F8R2_FB19                        CAN_F8R2_FB19_Msk                 /*!< Filter bit 19 */
9973 #define CAN_F8R2_FB20_Pos                    (20U)
9974 #define CAN_F8R2_FB20_Msk                    (0x1UL << CAN_F8R2_FB20_Pos)       /*!< 0x00100000 */
9975 #define CAN_F8R2_FB20                        CAN_F8R2_FB20_Msk                 /*!< Filter bit 20 */
9976 #define CAN_F8R2_FB21_Pos                    (21U)
9977 #define CAN_F8R2_FB21_Msk                    (0x1UL << CAN_F8R2_FB21_Pos)       /*!< 0x00200000 */
9978 #define CAN_F8R2_FB21                        CAN_F8R2_FB21_Msk                 /*!< Filter bit 21 */
9979 #define CAN_F8R2_FB22_Pos                    (22U)
9980 #define CAN_F8R2_FB22_Msk                    (0x1UL << CAN_F8R2_FB22_Pos)       /*!< 0x00400000 */
9981 #define CAN_F8R2_FB22                        CAN_F8R2_FB22_Msk                 /*!< Filter bit 22 */
9982 #define CAN_F8R2_FB23_Pos                    (23U)
9983 #define CAN_F8R2_FB23_Msk                    (0x1UL << CAN_F8R2_FB23_Pos)       /*!< 0x00800000 */
9984 #define CAN_F8R2_FB23                        CAN_F8R2_FB23_Msk                 /*!< Filter bit 23 */
9985 #define CAN_F8R2_FB24_Pos                    (24U)
9986 #define CAN_F8R2_FB24_Msk                    (0x1UL << CAN_F8R2_FB24_Pos)       /*!< 0x01000000 */
9987 #define CAN_F8R2_FB24                        CAN_F8R2_FB24_Msk                 /*!< Filter bit 24 */
9988 #define CAN_F8R2_FB25_Pos                    (25U)
9989 #define CAN_F8R2_FB25_Msk                    (0x1UL << CAN_F8R2_FB25_Pos)       /*!< 0x02000000 */
9990 #define CAN_F8R2_FB25                        CAN_F8R2_FB25_Msk                 /*!< Filter bit 25 */
9991 #define CAN_F8R2_FB26_Pos                    (26U)
9992 #define CAN_F8R2_FB26_Msk                    (0x1UL << CAN_F8R2_FB26_Pos)       /*!< 0x04000000 */
9993 #define CAN_F8R2_FB26                        CAN_F8R2_FB26_Msk                 /*!< Filter bit 26 */
9994 #define CAN_F8R2_FB27_Pos                    (27U)
9995 #define CAN_F8R2_FB27_Msk                    (0x1UL << CAN_F8R2_FB27_Pos)       /*!< 0x08000000 */
9996 #define CAN_F8R2_FB27                        CAN_F8R2_FB27_Msk                 /*!< Filter bit 27 */
9997 #define CAN_F8R2_FB28_Pos                    (28U)
9998 #define CAN_F8R2_FB28_Msk                    (0x1UL << CAN_F8R2_FB28_Pos)       /*!< 0x10000000 */
9999 #define CAN_F8R2_FB28                        CAN_F8R2_FB28_Msk                 /*!< Filter bit 28 */
10000 #define CAN_F8R2_FB29_Pos                    (29U)
10001 #define CAN_F8R2_FB29_Msk                    (0x1UL << CAN_F8R2_FB29_Pos)       /*!< 0x20000000 */
10002 #define CAN_F8R2_FB29                        CAN_F8R2_FB29_Msk                 /*!< Filter bit 29 */
10003 #define CAN_F8R2_FB30_Pos                    (30U)
10004 #define CAN_F8R2_FB30_Msk                    (0x1UL << CAN_F8R2_FB30_Pos)       /*!< 0x40000000 */
10005 #define CAN_F8R2_FB30                        CAN_F8R2_FB30_Msk                 /*!< Filter bit 30 */
10006 #define CAN_F8R2_FB31_Pos                    (31U)
10007 #define CAN_F8R2_FB31_Msk                    (0x1UL << CAN_F8R2_FB31_Pos)       /*!< 0x80000000 */
10008 #define CAN_F8R2_FB31                        CAN_F8R2_FB31_Msk                 /*!< Filter bit 31 */
10009 
10010 /*******************  Bit definition for CAN_F9R2 register  *******************/
10011 #define CAN_F9R2_FB0_Pos                     (0U)
10012 #define CAN_F9R2_FB0_Msk                     (0x1UL << CAN_F9R2_FB0_Pos)        /*!< 0x00000001 */
10013 #define CAN_F9R2_FB0                         CAN_F9R2_FB0_Msk                  /*!< Filter bit 0 */
10014 #define CAN_F9R2_FB1_Pos                     (1U)
10015 #define CAN_F9R2_FB1_Msk                     (0x1UL << CAN_F9R2_FB1_Pos)        /*!< 0x00000002 */
10016 #define CAN_F9R2_FB1                         CAN_F9R2_FB1_Msk                  /*!< Filter bit 1 */
10017 #define CAN_F9R2_FB2_Pos                     (2U)
10018 #define CAN_F9R2_FB2_Msk                     (0x1UL << CAN_F9R2_FB2_Pos)        /*!< 0x00000004 */
10019 #define CAN_F9R2_FB2                         CAN_F9R2_FB2_Msk                  /*!< Filter bit 2 */
10020 #define CAN_F9R2_FB3_Pos                     (3U)
10021 #define CAN_F9R2_FB3_Msk                     (0x1UL << CAN_F9R2_FB3_Pos)        /*!< 0x00000008 */
10022 #define CAN_F9R2_FB3                         CAN_F9R2_FB3_Msk                  /*!< Filter bit 3 */
10023 #define CAN_F9R2_FB4_Pos                     (4U)
10024 #define CAN_F9R2_FB4_Msk                     (0x1UL << CAN_F9R2_FB4_Pos)        /*!< 0x00000010 */
10025 #define CAN_F9R2_FB4                         CAN_F9R2_FB4_Msk                  /*!< Filter bit 4 */
10026 #define CAN_F9R2_FB5_Pos                     (5U)
10027 #define CAN_F9R2_FB5_Msk                     (0x1UL << CAN_F9R2_FB5_Pos)        /*!< 0x00000020 */
10028 #define CAN_F9R2_FB5                         CAN_F9R2_FB5_Msk                  /*!< Filter bit 5 */
10029 #define CAN_F9R2_FB6_Pos                     (6U)
10030 #define CAN_F9R2_FB6_Msk                     (0x1UL << CAN_F9R2_FB6_Pos)        /*!< 0x00000040 */
10031 #define CAN_F9R2_FB6                         CAN_F9R2_FB6_Msk                  /*!< Filter bit 6 */
10032 #define CAN_F9R2_FB7_Pos                     (7U)
10033 #define CAN_F9R2_FB7_Msk                     (0x1UL << CAN_F9R2_FB7_Pos)        /*!< 0x00000080 */
10034 #define CAN_F9R2_FB7                         CAN_F9R2_FB7_Msk                  /*!< Filter bit 7 */
10035 #define CAN_F9R2_FB8_Pos                     (8U)
10036 #define CAN_F9R2_FB8_Msk                     (0x1UL << CAN_F9R2_FB8_Pos)        /*!< 0x00000100 */
10037 #define CAN_F9R2_FB8                         CAN_F9R2_FB8_Msk                  /*!< Filter bit 8 */
10038 #define CAN_F9R2_FB9_Pos                     (9U)
10039 #define CAN_F9R2_FB9_Msk                     (0x1UL << CAN_F9R2_FB9_Pos)        /*!< 0x00000200 */
10040 #define CAN_F9R2_FB9                         CAN_F9R2_FB9_Msk                  /*!< Filter bit 9 */
10041 #define CAN_F9R2_FB10_Pos                    (10U)
10042 #define CAN_F9R2_FB10_Msk                    (0x1UL << CAN_F9R2_FB10_Pos)       /*!< 0x00000400 */
10043 #define CAN_F9R2_FB10                        CAN_F9R2_FB10_Msk                 /*!< Filter bit 10 */
10044 #define CAN_F9R2_FB11_Pos                    (11U)
10045 #define CAN_F9R2_FB11_Msk                    (0x1UL << CAN_F9R2_FB11_Pos)       /*!< 0x00000800 */
10046 #define CAN_F9R2_FB11                        CAN_F9R2_FB11_Msk                 /*!< Filter bit 11 */
10047 #define CAN_F9R2_FB12_Pos                    (12U)
10048 #define CAN_F9R2_FB12_Msk                    (0x1UL << CAN_F9R2_FB12_Pos)       /*!< 0x00001000 */
10049 #define CAN_F9R2_FB12                        CAN_F9R2_FB12_Msk                 /*!< Filter bit 12 */
10050 #define CAN_F9R2_FB13_Pos                    (13U)
10051 #define CAN_F9R2_FB13_Msk                    (0x1UL << CAN_F9R2_FB13_Pos)       /*!< 0x00002000 */
10052 #define CAN_F9R2_FB13                        CAN_F9R2_FB13_Msk                 /*!< Filter bit 13 */
10053 #define CAN_F9R2_FB14_Pos                    (14U)
10054 #define CAN_F9R2_FB14_Msk                    (0x1UL << CAN_F9R2_FB14_Pos)       /*!< 0x00004000 */
10055 #define CAN_F9R2_FB14                        CAN_F9R2_FB14_Msk                 /*!< Filter bit 14 */
10056 #define CAN_F9R2_FB15_Pos                    (15U)
10057 #define CAN_F9R2_FB15_Msk                    (0x1UL << CAN_F9R2_FB15_Pos)       /*!< 0x00008000 */
10058 #define CAN_F9R2_FB15                        CAN_F9R2_FB15_Msk                 /*!< Filter bit 15 */
10059 #define CAN_F9R2_FB16_Pos                    (16U)
10060 #define CAN_F9R2_FB16_Msk                    (0x1UL << CAN_F9R2_FB16_Pos)       /*!< 0x00010000 */
10061 #define CAN_F9R2_FB16                        CAN_F9R2_FB16_Msk                 /*!< Filter bit 16 */
10062 #define CAN_F9R2_FB17_Pos                    (17U)
10063 #define CAN_F9R2_FB17_Msk                    (0x1UL << CAN_F9R2_FB17_Pos)       /*!< 0x00020000 */
10064 #define CAN_F9R2_FB17                        CAN_F9R2_FB17_Msk                 /*!< Filter bit 17 */
10065 #define CAN_F9R2_FB18_Pos                    (18U)
10066 #define CAN_F9R2_FB18_Msk                    (0x1UL << CAN_F9R2_FB18_Pos)       /*!< 0x00040000 */
10067 #define CAN_F9R2_FB18                        CAN_F9R2_FB18_Msk                 /*!< Filter bit 18 */
10068 #define CAN_F9R2_FB19_Pos                    (19U)
10069 #define CAN_F9R2_FB19_Msk                    (0x1UL << CAN_F9R2_FB19_Pos)       /*!< 0x00080000 */
10070 #define CAN_F9R2_FB19                        CAN_F9R2_FB19_Msk                 /*!< Filter bit 19 */
10071 #define CAN_F9R2_FB20_Pos                    (20U)
10072 #define CAN_F9R2_FB20_Msk                    (0x1UL << CAN_F9R2_FB20_Pos)       /*!< 0x00100000 */
10073 #define CAN_F9R2_FB20                        CAN_F9R2_FB20_Msk                 /*!< Filter bit 20 */
10074 #define CAN_F9R2_FB21_Pos                    (21U)
10075 #define CAN_F9R2_FB21_Msk                    (0x1UL << CAN_F9R2_FB21_Pos)       /*!< 0x00200000 */
10076 #define CAN_F9R2_FB21                        CAN_F9R2_FB21_Msk                 /*!< Filter bit 21 */
10077 #define CAN_F9R2_FB22_Pos                    (22U)
10078 #define CAN_F9R2_FB22_Msk                    (0x1UL << CAN_F9R2_FB22_Pos)       /*!< 0x00400000 */
10079 #define CAN_F9R2_FB22                        CAN_F9R2_FB22_Msk                 /*!< Filter bit 22 */
10080 #define CAN_F9R2_FB23_Pos                    (23U)
10081 #define CAN_F9R2_FB23_Msk                    (0x1UL << CAN_F9R2_FB23_Pos)       /*!< 0x00800000 */
10082 #define CAN_F9R2_FB23                        CAN_F9R2_FB23_Msk                 /*!< Filter bit 23 */
10083 #define CAN_F9R2_FB24_Pos                    (24U)
10084 #define CAN_F9R2_FB24_Msk                    (0x1UL << CAN_F9R2_FB24_Pos)       /*!< 0x01000000 */
10085 #define CAN_F9R2_FB24                        CAN_F9R2_FB24_Msk                 /*!< Filter bit 24 */
10086 #define CAN_F9R2_FB25_Pos                    (25U)
10087 #define CAN_F9R2_FB25_Msk                    (0x1UL << CAN_F9R2_FB25_Pos)       /*!< 0x02000000 */
10088 #define CAN_F9R2_FB25                        CAN_F9R2_FB25_Msk                 /*!< Filter bit 25 */
10089 #define CAN_F9R2_FB26_Pos                    (26U)
10090 #define CAN_F9R2_FB26_Msk                    (0x1UL << CAN_F9R2_FB26_Pos)       /*!< 0x04000000 */
10091 #define CAN_F9R2_FB26                        CAN_F9R2_FB26_Msk                 /*!< Filter bit 26 */
10092 #define CAN_F9R2_FB27_Pos                    (27U)
10093 #define CAN_F9R2_FB27_Msk                    (0x1UL << CAN_F9R2_FB27_Pos)       /*!< 0x08000000 */
10094 #define CAN_F9R2_FB27                        CAN_F9R2_FB27_Msk                 /*!< Filter bit 27 */
10095 #define CAN_F9R2_FB28_Pos                    (28U)
10096 #define CAN_F9R2_FB28_Msk                    (0x1UL << CAN_F9R2_FB28_Pos)       /*!< 0x10000000 */
10097 #define CAN_F9R2_FB28                        CAN_F9R2_FB28_Msk                 /*!< Filter bit 28 */
10098 #define CAN_F9R2_FB29_Pos                    (29U)
10099 #define CAN_F9R2_FB29_Msk                    (0x1UL << CAN_F9R2_FB29_Pos)       /*!< 0x20000000 */
10100 #define CAN_F9R2_FB29                        CAN_F9R2_FB29_Msk                 /*!< Filter bit 29 */
10101 #define CAN_F9R2_FB30_Pos                    (30U)
10102 #define CAN_F9R2_FB30_Msk                    (0x1UL << CAN_F9R2_FB30_Pos)       /*!< 0x40000000 */
10103 #define CAN_F9R2_FB30                        CAN_F9R2_FB30_Msk                 /*!< Filter bit 30 */
10104 #define CAN_F9R2_FB31_Pos                    (31U)
10105 #define CAN_F9R2_FB31_Msk                    (0x1UL << CAN_F9R2_FB31_Pos)       /*!< 0x80000000 */
10106 #define CAN_F9R2_FB31                        CAN_F9R2_FB31_Msk                 /*!< Filter bit 31 */
10107 
10108 /*******************  Bit definition for CAN_F10R2 register  ******************/
10109 #define CAN_F10R2_FB0_Pos                    (0U)
10110 #define CAN_F10R2_FB0_Msk                    (0x1UL << CAN_F10R2_FB0_Pos)       /*!< 0x00000001 */
10111 #define CAN_F10R2_FB0                        CAN_F10R2_FB0_Msk                 /*!< Filter bit 0 */
10112 #define CAN_F10R2_FB1_Pos                    (1U)
10113 #define CAN_F10R2_FB1_Msk                    (0x1UL << CAN_F10R2_FB1_Pos)       /*!< 0x00000002 */
10114 #define CAN_F10R2_FB1                        CAN_F10R2_FB1_Msk                 /*!< Filter bit 1 */
10115 #define CAN_F10R2_FB2_Pos                    (2U)
10116 #define CAN_F10R2_FB2_Msk                    (0x1UL << CAN_F10R2_FB2_Pos)       /*!< 0x00000004 */
10117 #define CAN_F10R2_FB2                        CAN_F10R2_FB2_Msk                 /*!< Filter bit 2 */
10118 #define CAN_F10R2_FB3_Pos                    (3U)
10119 #define CAN_F10R2_FB3_Msk                    (0x1UL << CAN_F10R2_FB3_Pos)       /*!< 0x00000008 */
10120 #define CAN_F10R2_FB3                        CAN_F10R2_FB3_Msk                 /*!< Filter bit 3 */
10121 #define CAN_F10R2_FB4_Pos                    (4U)
10122 #define CAN_F10R2_FB4_Msk                    (0x1UL << CAN_F10R2_FB4_Pos)       /*!< 0x00000010 */
10123 #define CAN_F10R2_FB4                        CAN_F10R2_FB4_Msk                 /*!< Filter bit 4 */
10124 #define CAN_F10R2_FB5_Pos                    (5U)
10125 #define CAN_F10R2_FB5_Msk                    (0x1UL << CAN_F10R2_FB5_Pos)       /*!< 0x00000020 */
10126 #define CAN_F10R2_FB5                        CAN_F10R2_FB5_Msk                 /*!< Filter bit 5 */
10127 #define CAN_F10R2_FB6_Pos                    (6U)
10128 #define CAN_F10R2_FB6_Msk                    (0x1UL << CAN_F10R2_FB6_Pos)       /*!< 0x00000040 */
10129 #define CAN_F10R2_FB6                        CAN_F10R2_FB6_Msk                 /*!< Filter bit 6 */
10130 #define CAN_F10R2_FB7_Pos                    (7U)
10131 #define CAN_F10R2_FB7_Msk                    (0x1UL << CAN_F10R2_FB7_Pos)       /*!< 0x00000080 */
10132 #define CAN_F10R2_FB7                        CAN_F10R2_FB7_Msk                 /*!< Filter bit 7 */
10133 #define CAN_F10R2_FB8_Pos                    (8U)
10134 #define CAN_F10R2_FB8_Msk                    (0x1UL << CAN_F10R2_FB8_Pos)       /*!< 0x00000100 */
10135 #define CAN_F10R2_FB8                        CAN_F10R2_FB8_Msk                 /*!< Filter bit 8 */
10136 #define CAN_F10R2_FB9_Pos                    (9U)
10137 #define CAN_F10R2_FB9_Msk                    (0x1UL << CAN_F10R2_FB9_Pos)       /*!< 0x00000200 */
10138 #define CAN_F10R2_FB9                        CAN_F10R2_FB9_Msk                 /*!< Filter bit 9 */
10139 #define CAN_F10R2_FB10_Pos                   (10U)
10140 #define CAN_F10R2_FB10_Msk                   (0x1UL << CAN_F10R2_FB10_Pos)      /*!< 0x00000400 */
10141 #define CAN_F10R2_FB10                       CAN_F10R2_FB10_Msk                /*!< Filter bit 10 */
10142 #define CAN_F10R2_FB11_Pos                   (11U)
10143 #define CAN_F10R2_FB11_Msk                   (0x1UL << CAN_F10R2_FB11_Pos)      /*!< 0x00000800 */
10144 #define CAN_F10R2_FB11                       CAN_F10R2_FB11_Msk                /*!< Filter bit 11 */
10145 #define CAN_F10R2_FB12_Pos                   (12U)
10146 #define CAN_F10R2_FB12_Msk                   (0x1UL << CAN_F10R2_FB12_Pos)      /*!< 0x00001000 */
10147 #define CAN_F10R2_FB12                       CAN_F10R2_FB12_Msk                /*!< Filter bit 12 */
10148 #define CAN_F10R2_FB13_Pos                   (13U)
10149 #define CAN_F10R2_FB13_Msk                   (0x1UL << CAN_F10R2_FB13_Pos)      /*!< 0x00002000 */
10150 #define CAN_F10R2_FB13                       CAN_F10R2_FB13_Msk                /*!< Filter bit 13 */
10151 #define CAN_F10R2_FB14_Pos                   (14U)
10152 #define CAN_F10R2_FB14_Msk                   (0x1UL << CAN_F10R2_FB14_Pos)      /*!< 0x00004000 */
10153 #define CAN_F10R2_FB14                       CAN_F10R2_FB14_Msk                /*!< Filter bit 14 */
10154 #define CAN_F10R2_FB15_Pos                   (15U)
10155 #define CAN_F10R2_FB15_Msk                   (0x1UL << CAN_F10R2_FB15_Pos)      /*!< 0x00008000 */
10156 #define CAN_F10R2_FB15                       CAN_F10R2_FB15_Msk                /*!< Filter bit 15 */
10157 #define CAN_F10R2_FB16_Pos                   (16U)
10158 #define CAN_F10R2_FB16_Msk                   (0x1UL << CAN_F10R2_FB16_Pos)      /*!< 0x00010000 */
10159 #define CAN_F10R2_FB16                       CAN_F10R2_FB16_Msk                /*!< Filter bit 16 */
10160 #define CAN_F10R2_FB17_Pos                   (17U)
10161 #define CAN_F10R2_FB17_Msk                   (0x1UL << CAN_F10R2_FB17_Pos)      /*!< 0x00020000 */
10162 #define CAN_F10R2_FB17                       CAN_F10R2_FB17_Msk                /*!< Filter bit 17 */
10163 #define CAN_F10R2_FB18_Pos                   (18U)
10164 #define CAN_F10R2_FB18_Msk                   (0x1UL << CAN_F10R2_FB18_Pos)      /*!< 0x00040000 */
10165 #define CAN_F10R2_FB18                       CAN_F10R2_FB18_Msk                /*!< Filter bit 18 */
10166 #define CAN_F10R2_FB19_Pos                   (19U)
10167 #define CAN_F10R2_FB19_Msk                   (0x1UL << CAN_F10R2_FB19_Pos)      /*!< 0x00080000 */
10168 #define CAN_F10R2_FB19                       CAN_F10R2_FB19_Msk                /*!< Filter bit 19 */
10169 #define CAN_F10R2_FB20_Pos                   (20U)
10170 #define CAN_F10R2_FB20_Msk                   (0x1UL << CAN_F10R2_FB20_Pos)      /*!< 0x00100000 */
10171 #define CAN_F10R2_FB20                       CAN_F10R2_FB20_Msk                /*!< Filter bit 20 */
10172 #define CAN_F10R2_FB21_Pos                   (21U)
10173 #define CAN_F10R2_FB21_Msk                   (0x1UL << CAN_F10R2_FB21_Pos)      /*!< 0x00200000 */
10174 #define CAN_F10R2_FB21                       CAN_F10R2_FB21_Msk                /*!< Filter bit 21 */
10175 #define CAN_F10R2_FB22_Pos                   (22U)
10176 #define CAN_F10R2_FB22_Msk                   (0x1UL << CAN_F10R2_FB22_Pos)      /*!< 0x00400000 */
10177 #define CAN_F10R2_FB22                       CAN_F10R2_FB22_Msk                /*!< Filter bit 22 */
10178 #define CAN_F10R2_FB23_Pos                   (23U)
10179 #define CAN_F10R2_FB23_Msk                   (0x1UL << CAN_F10R2_FB23_Pos)      /*!< 0x00800000 */
10180 #define CAN_F10R2_FB23                       CAN_F10R2_FB23_Msk                /*!< Filter bit 23 */
10181 #define CAN_F10R2_FB24_Pos                   (24U)
10182 #define CAN_F10R2_FB24_Msk                   (0x1UL << CAN_F10R2_FB24_Pos)      /*!< 0x01000000 */
10183 #define CAN_F10R2_FB24                       CAN_F10R2_FB24_Msk                /*!< Filter bit 24 */
10184 #define CAN_F10R2_FB25_Pos                   (25U)
10185 #define CAN_F10R2_FB25_Msk                   (0x1UL << CAN_F10R2_FB25_Pos)      /*!< 0x02000000 */
10186 #define CAN_F10R2_FB25                       CAN_F10R2_FB25_Msk                /*!< Filter bit 25 */
10187 #define CAN_F10R2_FB26_Pos                   (26U)
10188 #define CAN_F10R2_FB26_Msk                   (0x1UL << CAN_F10R2_FB26_Pos)      /*!< 0x04000000 */
10189 #define CAN_F10R2_FB26                       CAN_F10R2_FB26_Msk                /*!< Filter bit 26 */
10190 #define CAN_F10R2_FB27_Pos                   (27U)
10191 #define CAN_F10R2_FB27_Msk                   (0x1UL << CAN_F10R2_FB27_Pos)      /*!< 0x08000000 */
10192 #define CAN_F10R2_FB27                       CAN_F10R2_FB27_Msk                /*!< Filter bit 27 */
10193 #define CAN_F10R2_FB28_Pos                   (28U)
10194 #define CAN_F10R2_FB28_Msk                   (0x1UL << CAN_F10R2_FB28_Pos)      /*!< 0x10000000 */
10195 #define CAN_F10R2_FB28                       CAN_F10R2_FB28_Msk                /*!< Filter bit 28 */
10196 #define CAN_F10R2_FB29_Pos                   (29U)
10197 #define CAN_F10R2_FB29_Msk                   (0x1UL << CAN_F10R2_FB29_Pos)      /*!< 0x20000000 */
10198 #define CAN_F10R2_FB29                       CAN_F10R2_FB29_Msk                /*!< Filter bit 29 */
10199 #define CAN_F10R2_FB30_Pos                   (30U)
10200 #define CAN_F10R2_FB30_Msk                   (0x1UL << CAN_F10R2_FB30_Pos)      /*!< 0x40000000 */
10201 #define CAN_F10R2_FB30                       CAN_F10R2_FB30_Msk                /*!< Filter bit 30 */
10202 #define CAN_F10R2_FB31_Pos                   (31U)
10203 #define CAN_F10R2_FB31_Msk                   (0x1UL << CAN_F10R2_FB31_Pos)      /*!< 0x80000000 */
10204 #define CAN_F10R2_FB31                       CAN_F10R2_FB31_Msk                /*!< Filter bit 31 */
10205 
10206 /*******************  Bit definition for CAN_F11R2 register  ******************/
10207 #define CAN_F11R2_FB0_Pos                    (0U)
10208 #define CAN_F11R2_FB0_Msk                    (0x1UL << CAN_F11R2_FB0_Pos)       /*!< 0x00000001 */
10209 #define CAN_F11R2_FB0                        CAN_F11R2_FB0_Msk                 /*!< Filter bit 0 */
10210 #define CAN_F11R2_FB1_Pos                    (1U)
10211 #define CAN_F11R2_FB1_Msk                    (0x1UL << CAN_F11R2_FB1_Pos)       /*!< 0x00000002 */
10212 #define CAN_F11R2_FB1                        CAN_F11R2_FB1_Msk                 /*!< Filter bit 1 */
10213 #define CAN_F11R2_FB2_Pos                    (2U)
10214 #define CAN_F11R2_FB2_Msk                    (0x1UL << CAN_F11R2_FB2_Pos)       /*!< 0x00000004 */
10215 #define CAN_F11R2_FB2                        CAN_F11R2_FB2_Msk                 /*!< Filter bit 2 */
10216 #define CAN_F11R2_FB3_Pos                    (3U)
10217 #define CAN_F11R2_FB3_Msk                    (0x1UL << CAN_F11R2_FB3_Pos)       /*!< 0x00000008 */
10218 #define CAN_F11R2_FB3                        CAN_F11R2_FB3_Msk                 /*!< Filter bit 3 */
10219 #define CAN_F11R2_FB4_Pos                    (4U)
10220 #define CAN_F11R2_FB4_Msk                    (0x1UL << CAN_F11R2_FB4_Pos)       /*!< 0x00000010 */
10221 #define CAN_F11R2_FB4                        CAN_F11R2_FB4_Msk                 /*!< Filter bit 4 */
10222 #define CAN_F11R2_FB5_Pos                    (5U)
10223 #define CAN_F11R2_FB5_Msk                    (0x1UL << CAN_F11R2_FB5_Pos)       /*!< 0x00000020 */
10224 #define CAN_F11R2_FB5                        CAN_F11R2_FB5_Msk                 /*!< Filter bit 5 */
10225 #define CAN_F11R2_FB6_Pos                    (6U)
10226 #define CAN_F11R2_FB6_Msk                    (0x1UL << CAN_F11R2_FB6_Pos)       /*!< 0x00000040 */
10227 #define CAN_F11R2_FB6                        CAN_F11R2_FB6_Msk                 /*!< Filter bit 6 */
10228 #define CAN_F11R2_FB7_Pos                    (7U)
10229 #define CAN_F11R2_FB7_Msk                    (0x1UL << CAN_F11R2_FB7_Pos)       /*!< 0x00000080 */
10230 #define CAN_F11R2_FB7                        CAN_F11R2_FB7_Msk                 /*!< Filter bit 7 */
10231 #define CAN_F11R2_FB8_Pos                    (8U)
10232 #define CAN_F11R2_FB8_Msk                    (0x1UL << CAN_F11R2_FB8_Pos)       /*!< 0x00000100 */
10233 #define CAN_F11R2_FB8                        CAN_F11R2_FB8_Msk                 /*!< Filter bit 8 */
10234 #define CAN_F11R2_FB9_Pos                    (9U)
10235 #define CAN_F11R2_FB9_Msk                    (0x1UL << CAN_F11R2_FB9_Pos)       /*!< 0x00000200 */
10236 #define CAN_F11R2_FB9                        CAN_F11R2_FB9_Msk                 /*!< Filter bit 9 */
10237 #define CAN_F11R2_FB10_Pos                   (10U)
10238 #define CAN_F11R2_FB10_Msk                   (0x1UL << CAN_F11R2_FB10_Pos)      /*!< 0x00000400 */
10239 #define CAN_F11R2_FB10                       CAN_F11R2_FB10_Msk                /*!< Filter bit 10 */
10240 #define CAN_F11R2_FB11_Pos                   (11U)
10241 #define CAN_F11R2_FB11_Msk                   (0x1UL << CAN_F11R2_FB11_Pos)      /*!< 0x00000800 */
10242 #define CAN_F11R2_FB11                       CAN_F11R2_FB11_Msk                /*!< Filter bit 11 */
10243 #define CAN_F11R2_FB12_Pos                   (12U)
10244 #define CAN_F11R2_FB12_Msk                   (0x1UL << CAN_F11R2_FB12_Pos)      /*!< 0x00001000 */
10245 #define CAN_F11R2_FB12                       CAN_F11R2_FB12_Msk                /*!< Filter bit 12 */
10246 #define CAN_F11R2_FB13_Pos                   (13U)
10247 #define CAN_F11R2_FB13_Msk                   (0x1UL << CAN_F11R2_FB13_Pos)      /*!< 0x00002000 */
10248 #define CAN_F11R2_FB13                       CAN_F11R2_FB13_Msk                /*!< Filter bit 13 */
10249 #define CAN_F11R2_FB14_Pos                   (14U)
10250 #define CAN_F11R2_FB14_Msk                   (0x1UL << CAN_F11R2_FB14_Pos)      /*!< 0x00004000 */
10251 #define CAN_F11R2_FB14                       CAN_F11R2_FB14_Msk                /*!< Filter bit 14 */
10252 #define CAN_F11R2_FB15_Pos                   (15U)
10253 #define CAN_F11R2_FB15_Msk                   (0x1UL << CAN_F11R2_FB15_Pos)      /*!< 0x00008000 */
10254 #define CAN_F11R2_FB15                       CAN_F11R2_FB15_Msk                /*!< Filter bit 15 */
10255 #define CAN_F11R2_FB16_Pos                   (16U)
10256 #define CAN_F11R2_FB16_Msk                   (0x1UL << CAN_F11R2_FB16_Pos)      /*!< 0x00010000 */
10257 #define CAN_F11R2_FB16                       CAN_F11R2_FB16_Msk                /*!< Filter bit 16 */
10258 #define CAN_F11R2_FB17_Pos                   (17U)
10259 #define CAN_F11R2_FB17_Msk                   (0x1UL << CAN_F11R2_FB17_Pos)      /*!< 0x00020000 */
10260 #define CAN_F11R2_FB17                       CAN_F11R2_FB17_Msk                /*!< Filter bit 17 */
10261 #define CAN_F11R2_FB18_Pos                   (18U)
10262 #define CAN_F11R2_FB18_Msk                   (0x1UL << CAN_F11R2_FB18_Pos)      /*!< 0x00040000 */
10263 #define CAN_F11R2_FB18                       CAN_F11R2_FB18_Msk                /*!< Filter bit 18 */
10264 #define CAN_F11R2_FB19_Pos                   (19U)
10265 #define CAN_F11R2_FB19_Msk                   (0x1UL << CAN_F11R2_FB19_Pos)      /*!< 0x00080000 */
10266 #define CAN_F11R2_FB19                       CAN_F11R2_FB19_Msk                /*!< Filter bit 19 */
10267 #define CAN_F11R2_FB20_Pos                   (20U)
10268 #define CAN_F11R2_FB20_Msk                   (0x1UL << CAN_F11R2_FB20_Pos)      /*!< 0x00100000 */
10269 #define CAN_F11R2_FB20                       CAN_F11R2_FB20_Msk                /*!< Filter bit 20 */
10270 #define CAN_F11R2_FB21_Pos                   (21U)
10271 #define CAN_F11R2_FB21_Msk                   (0x1UL << CAN_F11R2_FB21_Pos)      /*!< 0x00200000 */
10272 #define CAN_F11R2_FB21                       CAN_F11R2_FB21_Msk                /*!< Filter bit 21 */
10273 #define CAN_F11R2_FB22_Pos                   (22U)
10274 #define CAN_F11R2_FB22_Msk                   (0x1UL << CAN_F11R2_FB22_Pos)      /*!< 0x00400000 */
10275 #define CAN_F11R2_FB22                       CAN_F11R2_FB22_Msk                /*!< Filter bit 22 */
10276 #define CAN_F11R2_FB23_Pos                   (23U)
10277 #define CAN_F11R2_FB23_Msk                   (0x1UL << CAN_F11R2_FB23_Pos)      /*!< 0x00800000 */
10278 #define CAN_F11R2_FB23                       CAN_F11R2_FB23_Msk                /*!< Filter bit 23 */
10279 #define CAN_F11R2_FB24_Pos                   (24U)
10280 #define CAN_F11R2_FB24_Msk                   (0x1UL << CAN_F11R2_FB24_Pos)      /*!< 0x01000000 */
10281 #define CAN_F11R2_FB24                       CAN_F11R2_FB24_Msk                /*!< Filter bit 24 */
10282 #define CAN_F11R2_FB25_Pos                   (25U)
10283 #define CAN_F11R2_FB25_Msk                   (0x1UL << CAN_F11R2_FB25_Pos)      /*!< 0x02000000 */
10284 #define CAN_F11R2_FB25                       CAN_F11R2_FB25_Msk                /*!< Filter bit 25 */
10285 #define CAN_F11R2_FB26_Pos                   (26U)
10286 #define CAN_F11R2_FB26_Msk                   (0x1UL << CAN_F11R2_FB26_Pos)      /*!< 0x04000000 */
10287 #define CAN_F11R2_FB26                       CAN_F11R2_FB26_Msk                /*!< Filter bit 26 */
10288 #define CAN_F11R2_FB27_Pos                   (27U)
10289 #define CAN_F11R2_FB27_Msk                   (0x1UL << CAN_F11R2_FB27_Pos)      /*!< 0x08000000 */
10290 #define CAN_F11R2_FB27                       CAN_F11R2_FB27_Msk                /*!< Filter bit 27 */
10291 #define CAN_F11R2_FB28_Pos                   (28U)
10292 #define CAN_F11R2_FB28_Msk                   (0x1UL << CAN_F11R2_FB28_Pos)      /*!< 0x10000000 */
10293 #define CAN_F11R2_FB28                       CAN_F11R2_FB28_Msk                /*!< Filter bit 28 */
10294 #define CAN_F11R2_FB29_Pos                   (29U)
10295 #define CAN_F11R2_FB29_Msk                   (0x1UL << CAN_F11R2_FB29_Pos)      /*!< 0x20000000 */
10296 #define CAN_F11R2_FB29                       CAN_F11R2_FB29_Msk                /*!< Filter bit 29 */
10297 #define CAN_F11R2_FB30_Pos                   (30U)
10298 #define CAN_F11R2_FB30_Msk                   (0x1UL << CAN_F11R2_FB30_Pos)      /*!< 0x40000000 */
10299 #define CAN_F11R2_FB30                       CAN_F11R2_FB30_Msk                /*!< Filter bit 30 */
10300 #define CAN_F11R2_FB31_Pos                   (31U)
10301 #define CAN_F11R2_FB31_Msk                   (0x1UL << CAN_F11R2_FB31_Pos)      /*!< 0x80000000 */
10302 #define CAN_F11R2_FB31                       CAN_F11R2_FB31_Msk                /*!< Filter bit 31 */
10303 
10304 /*******************  Bit definition for CAN_F12R2 register  ******************/
10305 #define CAN_F12R2_FB0_Pos                    (0U)
10306 #define CAN_F12R2_FB0_Msk                    (0x1UL << CAN_F12R2_FB0_Pos)       /*!< 0x00000001 */
10307 #define CAN_F12R2_FB0                        CAN_F12R2_FB0_Msk                 /*!< Filter bit 0 */
10308 #define CAN_F12R2_FB1_Pos                    (1U)
10309 #define CAN_F12R2_FB1_Msk                    (0x1UL << CAN_F12R2_FB1_Pos)       /*!< 0x00000002 */
10310 #define CAN_F12R2_FB1                        CAN_F12R2_FB1_Msk                 /*!< Filter bit 1 */
10311 #define CAN_F12R2_FB2_Pos                    (2U)
10312 #define CAN_F12R2_FB2_Msk                    (0x1UL << CAN_F12R2_FB2_Pos)       /*!< 0x00000004 */
10313 #define CAN_F12R2_FB2                        CAN_F12R2_FB2_Msk                 /*!< Filter bit 2 */
10314 #define CAN_F12R2_FB3_Pos                    (3U)
10315 #define CAN_F12R2_FB3_Msk                    (0x1UL << CAN_F12R2_FB3_Pos)       /*!< 0x00000008 */
10316 #define CAN_F12R2_FB3                        CAN_F12R2_FB3_Msk                 /*!< Filter bit 3 */
10317 #define CAN_F12R2_FB4_Pos                    (4U)
10318 #define CAN_F12R2_FB4_Msk                    (0x1UL << CAN_F12R2_FB4_Pos)       /*!< 0x00000010 */
10319 #define CAN_F12R2_FB4                        CAN_F12R2_FB4_Msk                 /*!< Filter bit 4 */
10320 #define CAN_F12R2_FB5_Pos                    (5U)
10321 #define CAN_F12R2_FB5_Msk                    (0x1UL << CAN_F12R2_FB5_Pos)       /*!< 0x00000020 */
10322 #define CAN_F12R2_FB5                        CAN_F12R2_FB5_Msk                 /*!< Filter bit 5 */
10323 #define CAN_F12R2_FB6_Pos                    (6U)
10324 #define CAN_F12R2_FB6_Msk                    (0x1UL << CAN_F12R2_FB6_Pos)       /*!< 0x00000040 */
10325 #define CAN_F12R2_FB6                        CAN_F12R2_FB6_Msk                 /*!< Filter bit 6 */
10326 #define CAN_F12R2_FB7_Pos                    (7U)
10327 #define CAN_F12R2_FB7_Msk                    (0x1UL << CAN_F12R2_FB7_Pos)       /*!< 0x00000080 */
10328 #define CAN_F12R2_FB7                        CAN_F12R2_FB7_Msk                 /*!< Filter bit 7 */
10329 #define CAN_F12R2_FB8_Pos                    (8U)
10330 #define CAN_F12R2_FB8_Msk                    (0x1UL << CAN_F12R2_FB8_Pos)       /*!< 0x00000100 */
10331 #define CAN_F12R2_FB8                        CAN_F12R2_FB8_Msk                 /*!< Filter bit 8 */
10332 #define CAN_F12R2_FB9_Pos                    (9U)
10333 #define CAN_F12R2_FB9_Msk                    (0x1UL << CAN_F12R2_FB9_Pos)       /*!< 0x00000200 */
10334 #define CAN_F12R2_FB9                        CAN_F12R2_FB9_Msk                 /*!< Filter bit 9 */
10335 #define CAN_F12R2_FB10_Pos                   (10U)
10336 #define CAN_F12R2_FB10_Msk                   (0x1UL << CAN_F12R2_FB10_Pos)      /*!< 0x00000400 */
10337 #define CAN_F12R2_FB10                       CAN_F12R2_FB10_Msk                /*!< Filter bit 10 */
10338 #define CAN_F12R2_FB11_Pos                   (11U)
10339 #define CAN_F12R2_FB11_Msk                   (0x1UL << CAN_F12R2_FB11_Pos)      /*!< 0x00000800 */
10340 #define CAN_F12R2_FB11                       CAN_F12R2_FB11_Msk                /*!< Filter bit 11 */
10341 #define CAN_F12R2_FB12_Pos                   (12U)
10342 #define CAN_F12R2_FB12_Msk                   (0x1UL << CAN_F12R2_FB12_Pos)      /*!< 0x00001000 */
10343 #define CAN_F12R2_FB12                       CAN_F12R2_FB12_Msk                /*!< Filter bit 12 */
10344 #define CAN_F12R2_FB13_Pos                   (13U)
10345 #define CAN_F12R2_FB13_Msk                   (0x1UL << CAN_F12R2_FB13_Pos)      /*!< 0x00002000 */
10346 #define CAN_F12R2_FB13                       CAN_F12R2_FB13_Msk                /*!< Filter bit 13 */
10347 #define CAN_F12R2_FB14_Pos                   (14U)
10348 #define CAN_F12R2_FB14_Msk                   (0x1UL << CAN_F12R2_FB14_Pos)      /*!< 0x00004000 */
10349 #define CAN_F12R2_FB14                       CAN_F12R2_FB14_Msk                /*!< Filter bit 14 */
10350 #define CAN_F12R2_FB15_Pos                   (15U)
10351 #define CAN_F12R2_FB15_Msk                   (0x1UL << CAN_F12R2_FB15_Pos)      /*!< 0x00008000 */
10352 #define CAN_F12R2_FB15                       CAN_F12R2_FB15_Msk                /*!< Filter bit 15 */
10353 #define CAN_F12R2_FB16_Pos                   (16U)
10354 #define CAN_F12R2_FB16_Msk                   (0x1UL << CAN_F12R2_FB16_Pos)      /*!< 0x00010000 */
10355 #define CAN_F12R2_FB16                       CAN_F12R2_FB16_Msk                /*!< Filter bit 16 */
10356 #define CAN_F12R2_FB17_Pos                   (17U)
10357 #define CAN_F12R2_FB17_Msk                   (0x1UL << CAN_F12R2_FB17_Pos)      /*!< 0x00020000 */
10358 #define CAN_F12R2_FB17                       CAN_F12R2_FB17_Msk                /*!< Filter bit 17 */
10359 #define CAN_F12R2_FB18_Pos                   (18U)
10360 #define CAN_F12R2_FB18_Msk                   (0x1UL << CAN_F12R2_FB18_Pos)      /*!< 0x00040000 */
10361 #define CAN_F12R2_FB18                       CAN_F12R2_FB18_Msk                /*!< Filter bit 18 */
10362 #define CAN_F12R2_FB19_Pos                   (19U)
10363 #define CAN_F12R2_FB19_Msk                   (0x1UL << CAN_F12R2_FB19_Pos)      /*!< 0x00080000 */
10364 #define CAN_F12R2_FB19                       CAN_F12R2_FB19_Msk                /*!< Filter bit 19 */
10365 #define CAN_F12R2_FB20_Pos                   (20U)
10366 #define CAN_F12R2_FB20_Msk                   (0x1UL << CAN_F12R2_FB20_Pos)      /*!< 0x00100000 */
10367 #define CAN_F12R2_FB20                       CAN_F12R2_FB20_Msk                /*!< Filter bit 20 */
10368 #define CAN_F12R2_FB21_Pos                   (21U)
10369 #define CAN_F12R2_FB21_Msk                   (0x1UL << CAN_F12R2_FB21_Pos)      /*!< 0x00200000 */
10370 #define CAN_F12R2_FB21                       CAN_F12R2_FB21_Msk                /*!< Filter bit 21 */
10371 #define CAN_F12R2_FB22_Pos                   (22U)
10372 #define CAN_F12R2_FB22_Msk                   (0x1UL << CAN_F12R2_FB22_Pos)      /*!< 0x00400000 */
10373 #define CAN_F12R2_FB22                       CAN_F12R2_FB22_Msk                /*!< Filter bit 22 */
10374 #define CAN_F12R2_FB23_Pos                   (23U)
10375 #define CAN_F12R2_FB23_Msk                   (0x1UL << CAN_F12R2_FB23_Pos)      /*!< 0x00800000 */
10376 #define CAN_F12R2_FB23                       CAN_F12R2_FB23_Msk                /*!< Filter bit 23 */
10377 #define CAN_F12R2_FB24_Pos                   (24U)
10378 #define CAN_F12R2_FB24_Msk                   (0x1UL << CAN_F12R2_FB24_Pos)      /*!< 0x01000000 */
10379 #define CAN_F12R2_FB24                       CAN_F12R2_FB24_Msk                /*!< Filter bit 24 */
10380 #define CAN_F12R2_FB25_Pos                   (25U)
10381 #define CAN_F12R2_FB25_Msk                   (0x1UL << CAN_F12R2_FB25_Pos)      /*!< 0x02000000 */
10382 #define CAN_F12R2_FB25                       CAN_F12R2_FB25_Msk                /*!< Filter bit 25 */
10383 #define CAN_F12R2_FB26_Pos                   (26U)
10384 #define CAN_F12R2_FB26_Msk                   (0x1UL << CAN_F12R2_FB26_Pos)      /*!< 0x04000000 */
10385 #define CAN_F12R2_FB26                       CAN_F12R2_FB26_Msk                /*!< Filter bit 26 */
10386 #define CAN_F12R2_FB27_Pos                   (27U)
10387 #define CAN_F12R2_FB27_Msk                   (0x1UL << CAN_F12R2_FB27_Pos)      /*!< 0x08000000 */
10388 #define CAN_F12R2_FB27                       CAN_F12R2_FB27_Msk                /*!< Filter bit 27 */
10389 #define CAN_F12R2_FB28_Pos                   (28U)
10390 #define CAN_F12R2_FB28_Msk                   (0x1UL << CAN_F12R2_FB28_Pos)      /*!< 0x10000000 */
10391 #define CAN_F12R2_FB28                       CAN_F12R2_FB28_Msk                /*!< Filter bit 28 */
10392 #define CAN_F12R2_FB29_Pos                   (29U)
10393 #define CAN_F12R2_FB29_Msk                   (0x1UL << CAN_F12R2_FB29_Pos)      /*!< 0x20000000 */
10394 #define CAN_F12R2_FB29                       CAN_F12R2_FB29_Msk                /*!< Filter bit 29 */
10395 #define CAN_F12R2_FB30_Pos                   (30U)
10396 #define CAN_F12R2_FB30_Msk                   (0x1UL << CAN_F12R2_FB30_Pos)      /*!< 0x40000000 */
10397 #define CAN_F12R2_FB30                       CAN_F12R2_FB30_Msk                /*!< Filter bit 30 */
10398 #define CAN_F12R2_FB31_Pos                   (31U)
10399 #define CAN_F12R2_FB31_Msk                   (0x1UL << CAN_F12R2_FB31_Pos)      /*!< 0x80000000 */
10400 #define CAN_F12R2_FB31                       CAN_F12R2_FB31_Msk                /*!< Filter bit 31 */
10401 
10402 /*******************  Bit definition for CAN_F13R2 register  ******************/
10403 #define CAN_F13R2_FB0_Pos                    (0U)
10404 #define CAN_F13R2_FB0_Msk                    (0x1UL << CAN_F13R2_FB0_Pos)       /*!< 0x00000001 */
10405 #define CAN_F13R2_FB0                        CAN_F13R2_FB0_Msk                 /*!< Filter bit 0 */
10406 #define CAN_F13R2_FB1_Pos                    (1U)
10407 #define CAN_F13R2_FB1_Msk                    (0x1UL << CAN_F13R2_FB1_Pos)       /*!< 0x00000002 */
10408 #define CAN_F13R2_FB1                        CAN_F13R2_FB1_Msk                 /*!< Filter bit 1 */
10409 #define CAN_F13R2_FB2_Pos                    (2U)
10410 #define CAN_F13R2_FB2_Msk                    (0x1UL << CAN_F13R2_FB2_Pos)       /*!< 0x00000004 */
10411 #define CAN_F13R2_FB2                        CAN_F13R2_FB2_Msk                 /*!< Filter bit 2 */
10412 #define CAN_F13R2_FB3_Pos                    (3U)
10413 #define CAN_F13R2_FB3_Msk                    (0x1UL << CAN_F13R2_FB3_Pos)       /*!< 0x00000008 */
10414 #define CAN_F13R2_FB3                        CAN_F13R2_FB3_Msk                 /*!< Filter bit 3 */
10415 #define CAN_F13R2_FB4_Pos                    (4U)
10416 #define CAN_F13R2_FB4_Msk                    (0x1UL << CAN_F13R2_FB4_Pos)       /*!< 0x00000010 */
10417 #define CAN_F13R2_FB4                        CAN_F13R2_FB4_Msk                 /*!< Filter bit 4 */
10418 #define CAN_F13R2_FB5_Pos                    (5U)
10419 #define CAN_F13R2_FB5_Msk                    (0x1UL << CAN_F13R2_FB5_Pos)       /*!< 0x00000020 */
10420 #define CAN_F13R2_FB5                        CAN_F13R2_FB5_Msk                 /*!< Filter bit 5 */
10421 #define CAN_F13R2_FB6_Pos                    (6U)
10422 #define CAN_F13R2_FB6_Msk                    (0x1UL << CAN_F13R2_FB6_Pos)       /*!< 0x00000040 */
10423 #define CAN_F13R2_FB6                        CAN_F13R2_FB6_Msk                 /*!< Filter bit 6 */
10424 #define CAN_F13R2_FB7_Pos                    (7U)
10425 #define CAN_F13R2_FB7_Msk                    (0x1UL << CAN_F13R2_FB7_Pos)       /*!< 0x00000080 */
10426 #define CAN_F13R2_FB7                        CAN_F13R2_FB7_Msk                 /*!< Filter bit 7 */
10427 #define CAN_F13R2_FB8_Pos                    (8U)
10428 #define CAN_F13R2_FB8_Msk                    (0x1UL << CAN_F13R2_FB8_Pos)       /*!< 0x00000100 */
10429 #define CAN_F13R2_FB8                        CAN_F13R2_FB8_Msk                 /*!< Filter bit 8 */
10430 #define CAN_F13R2_FB9_Pos                    (9U)
10431 #define CAN_F13R2_FB9_Msk                    (0x1UL << CAN_F13R2_FB9_Pos)       /*!< 0x00000200 */
10432 #define CAN_F13R2_FB9                        CAN_F13R2_FB9_Msk                 /*!< Filter bit 9 */
10433 #define CAN_F13R2_FB10_Pos                   (10U)
10434 #define CAN_F13R2_FB10_Msk                   (0x1UL << CAN_F13R2_FB10_Pos)      /*!< 0x00000400 */
10435 #define CAN_F13R2_FB10                       CAN_F13R2_FB10_Msk                /*!< Filter bit 10 */
10436 #define CAN_F13R2_FB11_Pos                   (11U)
10437 #define CAN_F13R2_FB11_Msk                   (0x1UL << CAN_F13R2_FB11_Pos)      /*!< 0x00000800 */
10438 #define CAN_F13R2_FB11                       CAN_F13R2_FB11_Msk                /*!< Filter bit 11 */
10439 #define CAN_F13R2_FB12_Pos                   (12U)
10440 #define CAN_F13R2_FB12_Msk                   (0x1UL << CAN_F13R2_FB12_Pos)      /*!< 0x00001000 */
10441 #define CAN_F13R2_FB12                       CAN_F13R2_FB12_Msk                /*!< Filter bit 12 */
10442 #define CAN_F13R2_FB13_Pos                   (13U)
10443 #define CAN_F13R2_FB13_Msk                   (0x1UL << CAN_F13R2_FB13_Pos)      /*!< 0x00002000 */
10444 #define CAN_F13R2_FB13                       CAN_F13R2_FB13_Msk                /*!< Filter bit 13 */
10445 #define CAN_F13R2_FB14_Pos                   (14U)
10446 #define CAN_F13R2_FB14_Msk                   (0x1UL << CAN_F13R2_FB14_Pos)      /*!< 0x00004000 */
10447 #define CAN_F13R2_FB14                       CAN_F13R2_FB14_Msk                /*!< Filter bit 14 */
10448 #define CAN_F13R2_FB15_Pos                   (15U)
10449 #define CAN_F13R2_FB15_Msk                   (0x1UL << CAN_F13R2_FB15_Pos)      /*!< 0x00008000 */
10450 #define CAN_F13R2_FB15                       CAN_F13R2_FB15_Msk                /*!< Filter bit 15 */
10451 #define CAN_F13R2_FB16_Pos                   (16U)
10452 #define CAN_F13R2_FB16_Msk                   (0x1UL << CAN_F13R2_FB16_Pos)      /*!< 0x00010000 */
10453 #define CAN_F13R2_FB16                       CAN_F13R2_FB16_Msk                /*!< Filter bit 16 */
10454 #define CAN_F13R2_FB17_Pos                   (17U)
10455 #define CAN_F13R2_FB17_Msk                   (0x1UL << CAN_F13R2_FB17_Pos)      /*!< 0x00020000 */
10456 #define CAN_F13R2_FB17                       CAN_F13R2_FB17_Msk                /*!< Filter bit 17 */
10457 #define CAN_F13R2_FB18_Pos                   (18U)
10458 #define CAN_F13R2_FB18_Msk                   (0x1UL << CAN_F13R2_FB18_Pos)      /*!< 0x00040000 */
10459 #define CAN_F13R2_FB18                       CAN_F13R2_FB18_Msk                /*!< Filter bit 18 */
10460 #define CAN_F13R2_FB19_Pos                   (19U)
10461 #define CAN_F13R2_FB19_Msk                   (0x1UL << CAN_F13R2_FB19_Pos)      /*!< 0x00080000 */
10462 #define CAN_F13R2_FB19                       CAN_F13R2_FB19_Msk                /*!< Filter bit 19 */
10463 #define CAN_F13R2_FB20_Pos                   (20U)
10464 #define CAN_F13R2_FB20_Msk                   (0x1UL << CAN_F13R2_FB20_Pos)      /*!< 0x00100000 */
10465 #define CAN_F13R2_FB20                       CAN_F13R2_FB20_Msk                /*!< Filter bit 20 */
10466 #define CAN_F13R2_FB21_Pos                   (21U)
10467 #define CAN_F13R2_FB21_Msk                   (0x1UL << CAN_F13R2_FB21_Pos)      /*!< 0x00200000 */
10468 #define CAN_F13R2_FB21                       CAN_F13R2_FB21_Msk                /*!< Filter bit 21 */
10469 #define CAN_F13R2_FB22_Pos                   (22U)
10470 #define CAN_F13R2_FB22_Msk                   (0x1UL << CAN_F13R2_FB22_Pos)      /*!< 0x00400000 */
10471 #define CAN_F13R2_FB22                       CAN_F13R2_FB22_Msk                /*!< Filter bit 22 */
10472 #define CAN_F13R2_FB23_Pos                   (23U)
10473 #define CAN_F13R2_FB23_Msk                   (0x1UL << CAN_F13R2_FB23_Pos)      /*!< 0x00800000 */
10474 #define CAN_F13R2_FB23                       CAN_F13R2_FB23_Msk                /*!< Filter bit 23 */
10475 #define CAN_F13R2_FB24_Pos                   (24U)
10476 #define CAN_F13R2_FB24_Msk                   (0x1UL << CAN_F13R2_FB24_Pos)      /*!< 0x01000000 */
10477 #define CAN_F13R2_FB24                       CAN_F13R2_FB24_Msk                /*!< Filter bit 24 */
10478 #define CAN_F13R2_FB25_Pos                   (25U)
10479 #define CAN_F13R2_FB25_Msk                   (0x1UL << CAN_F13R2_FB25_Pos)      /*!< 0x02000000 */
10480 #define CAN_F13R2_FB25                       CAN_F13R2_FB25_Msk                /*!< Filter bit 25 */
10481 #define CAN_F13R2_FB26_Pos                   (26U)
10482 #define CAN_F13R2_FB26_Msk                   (0x1UL << CAN_F13R2_FB26_Pos)      /*!< 0x04000000 */
10483 #define CAN_F13R2_FB26                       CAN_F13R2_FB26_Msk                /*!< Filter bit 26 */
10484 #define CAN_F13R2_FB27_Pos                   (27U)
10485 #define CAN_F13R2_FB27_Msk                   (0x1UL << CAN_F13R2_FB27_Pos)      /*!< 0x08000000 */
10486 #define CAN_F13R2_FB27                       CAN_F13R2_FB27_Msk                /*!< Filter bit 27 */
10487 #define CAN_F13R2_FB28_Pos                   (28U)
10488 #define CAN_F13R2_FB28_Msk                   (0x1UL << CAN_F13R2_FB28_Pos)      /*!< 0x10000000 */
10489 #define CAN_F13R2_FB28                       CAN_F13R2_FB28_Msk                /*!< Filter bit 28 */
10490 #define CAN_F13R2_FB29_Pos                   (29U)
10491 #define CAN_F13R2_FB29_Msk                   (0x1UL << CAN_F13R2_FB29_Pos)      /*!< 0x20000000 */
10492 #define CAN_F13R2_FB29                       CAN_F13R2_FB29_Msk                /*!< Filter bit 29 */
10493 #define CAN_F13R2_FB30_Pos                   (30U)
10494 #define CAN_F13R2_FB30_Msk                   (0x1UL << CAN_F13R2_FB30_Pos)      /*!< 0x40000000 */
10495 #define CAN_F13R2_FB30                       CAN_F13R2_FB30_Msk                /*!< Filter bit 30 */
10496 #define CAN_F13R2_FB31_Pos                   (31U)
10497 #define CAN_F13R2_FB31_Msk                   (0x1UL << CAN_F13R2_FB31_Pos)      /*!< 0x80000000 */
10498 #define CAN_F13R2_FB31                       CAN_F13R2_FB31_Msk                /*!< Filter bit 31 */
10499 
10500 /******************************************************************************/
10501 /*                                                                            */
10502 /*                        Serial Peripheral Interface                         */
10503 /*                                                                            */
10504 /******************************************************************************/
10505 /*
10506  * @brief Specific device feature definitions (not present on all devices in the STM32F1 series)
10507  */
10508 #define SPI_I2S_SUPPORT       /*!< I2S support */
10509 
10510 /*******************  Bit definition for SPI_CR1 register  ********************/
10511 #define SPI_CR1_CPHA_Pos                    (0U)
10512 #define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
10513 #define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
10514 #define SPI_CR1_CPOL_Pos                    (1U)
10515 #define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
10516 #define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
10517 #define SPI_CR1_MSTR_Pos                    (2U)
10518 #define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
10519 #define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
10520 
10521 #define SPI_CR1_BR_Pos                      (3U)
10522 #define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
10523 #define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
10524 #define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
10525 #define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
10526 #define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
10527 
10528 #define SPI_CR1_SPE_Pos                     (6U)
10529 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
10530 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
10531 #define SPI_CR1_LSBFIRST_Pos                (7U)
10532 #define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
10533 #define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
10534 #define SPI_CR1_SSI_Pos                     (8U)
10535 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
10536 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
10537 #define SPI_CR1_SSM_Pos                     (9U)
10538 #define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
10539 #define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
10540 #define SPI_CR1_RXONLY_Pos                  (10U)
10541 #define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
10542 #define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
10543 #define SPI_CR1_DFF_Pos                     (11U)
10544 #define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
10545 #define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
10546 #define SPI_CR1_CRCNEXT_Pos                 (12U)
10547 #define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
10548 #define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
10549 #define SPI_CR1_CRCEN_Pos                   (13U)
10550 #define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
10551 #define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
10552 #define SPI_CR1_BIDIOE_Pos                  (14U)
10553 #define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
10554 #define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
10555 #define SPI_CR1_BIDIMODE_Pos                (15U)
10556 #define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
10557 #define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
10558 
10559 /*******************  Bit definition for SPI_CR2 register  ********************/
10560 #define SPI_CR2_RXDMAEN_Pos                 (0U)
10561 #define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
10562 #define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
10563 #define SPI_CR2_TXDMAEN_Pos                 (1U)
10564 #define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
10565 #define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
10566 #define SPI_CR2_SSOE_Pos                    (2U)
10567 #define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
10568 #define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
10569 #define SPI_CR2_ERRIE_Pos                   (5U)
10570 #define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
10571 #define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
10572 #define SPI_CR2_RXNEIE_Pos                  (6U)
10573 #define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
10574 #define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
10575 #define SPI_CR2_TXEIE_Pos                   (7U)
10576 #define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
10577 #define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
10578 
10579 /********************  Bit definition for SPI_SR register  ********************/
10580 #define SPI_SR_RXNE_Pos                     (0U)
10581 #define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
10582 #define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
10583 #define SPI_SR_TXE_Pos                      (1U)
10584 #define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
10585 #define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
10586 #define SPI_SR_CHSIDE_Pos                   (2U)
10587 #define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
10588 #define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
10589 #define SPI_SR_UDR_Pos                      (3U)
10590 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
10591 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
10592 #define SPI_SR_CRCERR_Pos                   (4U)
10593 #define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
10594 #define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
10595 #define SPI_SR_MODF_Pos                     (5U)
10596 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
10597 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
10598 #define SPI_SR_OVR_Pos                      (6U)
10599 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
10600 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
10601 #define SPI_SR_BSY_Pos                      (7U)
10602 #define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
10603 #define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
10604 
10605 /********************  Bit definition for SPI_DR register  ********************/
10606 #define SPI_DR_DR_Pos                       (0U)
10607 #define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
10608 #define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
10609 
10610 /*******************  Bit definition for SPI_CRCPR register  ******************/
10611 #define SPI_CRCPR_CRCPOLY_Pos               (0U)
10612 #define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
10613 #define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
10614 
10615 /******************  Bit definition for SPI_RXCRCR register  ******************/
10616 #define SPI_RXCRCR_RXCRC_Pos                (0U)
10617 #define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
10618 #define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
10619 
10620 /******************  Bit definition for SPI_TXCRCR register  ******************/
10621 #define SPI_TXCRCR_TXCRC_Pos                (0U)
10622 #define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
10623 #define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
10624 
10625 /******************  Bit definition for SPI_I2SCFGR register  *****************/
10626 #define SPI_I2SCFGR_CHLEN_Pos               (0U)
10627 #define SPI_I2SCFGR_CHLEN_Msk               (0x1UL << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
10628 #define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!< Channel length (number of bits per audio channel) */
10629 
10630 #define SPI_I2SCFGR_DATLEN_Pos              (1U)
10631 #define SPI_I2SCFGR_DATLEN_Msk              (0x3UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
10632 #define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!< DATLEN[1:0] bits (Data length to be transferred) */
10633 #define SPI_I2SCFGR_DATLEN_0                (0x1UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
10634 #define SPI_I2SCFGR_DATLEN_1                (0x2UL << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
10635 
10636 #define SPI_I2SCFGR_CKPOL_Pos               (3U)
10637 #define SPI_I2SCFGR_CKPOL_Msk               (0x1UL << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
10638 #define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!< steady state clock polarity */
10639 
10640 #define SPI_I2SCFGR_I2SSTD_Pos              (4U)
10641 #define SPI_I2SCFGR_I2SSTD_Msk              (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
10642 #define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!< I2SSTD[1:0] bits (I2S standard selection) */
10643 #define SPI_I2SCFGR_I2SSTD_0                (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
10644 #define SPI_I2SCFGR_I2SSTD_1                (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
10645 
10646 #define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
10647 #define SPI_I2SCFGR_PCMSYNC_Msk             (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
10648 #define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!< PCM frame synchronization */
10649 
10650 #define SPI_I2SCFGR_I2SCFG_Pos              (8U)
10651 #define SPI_I2SCFGR_I2SCFG_Msk              (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
10652 #define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!< I2SCFG[1:0] bits (I2S configuration mode) */
10653 #define SPI_I2SCFGR_I2SCFG_0                (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
10654 #define SPI_I2SCFGR_I2SCFG_1                (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
10655 
10656 #define SPI_I2SCFGR_I2SE_Pos                (10U)
10657 #define SPI_I2SCFGR_I2SE_Msk                (0x1UL << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
10658 #define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!< I2S Enable */
10659 #define SPI_I2SCFGR_I2SMOD_Pos              (11U)
10660 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
10661 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!< I2S mode selection */
10662 /******************  Bit definition for SPI_I2SPR register  *******************/
10663 #define SPI_I2SPR_I2SDIV_Pos                (0U)
10664 #define SPI_I2SPR_I2SDIV_Msk                (0xFFUL << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
10665 #define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!< I2S Linear prescaler */
10666 #define SPI_I2SPR_ODD_Pos                   (8U)
10667 #define SPI_I2SPR_ODD_Msk                   (0x1UL << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
10668 #define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!< Odd factor for the prescaler */
10669 #define SPI_I2SPR_MCKOE_Pos                 (9U)
10670 #define SPI_I2SPR_MCKOE_Msk                 (0x1UL << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
10671 #define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!< Master Clock Output Enable */
10672 
10673 /******************************************************************************/
10674 /*                                                                            */
10675 /*                      Inter-integrated Circuit Interface                    */
10676 /*                                                                            */
10677 /******************************************************************************/
10678 
10679 /*******************  Bit definition for I2C_CR1 register  ********************/
10680 #define I2C_CR1_PE_Pos                      (0U)
10681 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
10682 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
10683 #define I2C_CR1_SMBUS_Pos                   (1U)
10684 #define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
10685 #define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
10686 #define I2C_CR1_SMBTYPE_Pos                 (3U)
10687 #define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
10688 #define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
10689 #define I2C_CR1_ENARP_Pos                   (4U)
10690 #define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
10691 #define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
10692 #define I2C_CR1_ENPEC_Pos                   (5U)
10693 #define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
10694 #define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
10695 #define I2C_CR1_ENGC_Pos                    (6U)
10696 #define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
10697 #define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
10698 #define I2C_CR1_NOSTRETCH_Pos               (7U)
10699 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
10700 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
10701 #define I2C_CR1_START_Pos                   (8U)
10702 #define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
10703 #define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
10704 #define I2C_CR1_STOP_Pos                    (9U)
10705 #define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
10706 #define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
10707 #define I2C_CR1_ACK_Pos                     (10U)
10708 #define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
10709 #define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
10710 #define I2C_CR1_POS_Pos                     (11U)
10711 #define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
10712 #define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
10713 #define I2C_CR1_PEC_Pos                     (12U)
10714 #define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
10715 #define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
10716 #define I2C_CR1_ALERT_Pos                   (13U)
10717 #define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
10718 #define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
10719 #define I2C_CR1_SWRST_Pos                   (15U)
10720 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
10721 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
10722 
10723 /*******************  Bit definition for I2C_CR2 register  ********************/
10724 #define I2C_CR2_FREQ_Pos                    (0U)
10725 #define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
10726 #define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
10727 #define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
10728 #define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
10729 #define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
10730 #define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
10731 #define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
10732 #define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
10733 
10734 #define I2C_CR2_ITERREN_Pos                 (8U)
10735 #define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
10736 #define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
10737 #define I2C_CR2_ITEVTEN_Pos                 (9U)
10738 #define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
10739 #define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
10740 #define I2C_CR2_ITBUFEN_Pos                 (10U)
10741 #define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
10742 #define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
10743 #define I2C_CR2_DMAEN_Pos                   (11U)
10744 #define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
10745 #define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
10746 #define I2C_CR2_LAST_Pos                    (12U)
10747 #define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
10748 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
10749 
10750 /*******************  Bit definition for I2C_OAR1 register  *******************/
10751 #define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */
10752 #define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */
10753 
10754 #define I2C_OAR1_ADD0_Pos                   (0U)
10755 #define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
10756 #define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
10757 #define I2C_OAR1_ADD1_Pos                   (1U)
10758 #define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
10759 #define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
10760 #define I2C_OAR1_ADD2_Pos                   (2U)
10761 #define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
10762 #define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
10763 #define I2C_OAR1_ADD3_Pos                   (3U)
10764 #define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
10765 #define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
10766 #define I2C_OAR1_ADD4_Pos                   (4U)
10767 #define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
10768 #define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
10769 #define I2C_OAR1_ADD5_Pos                   (5U)
10770 #define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
10771 #define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
10772 #define I2C_OAR1_ADD6_Pos                   (6U)
10773 #define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
10774 #define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
10775 #define I2C_OAR1_ADD7_Pos                   (7U)
10776 #define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
10777 #define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
10778 #define I2C_OAR1_ADD8_Pos                   (8U)
10779 #define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
10780 #define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
10781 #define I2C_OAR1_ADD9_Pos                   (9U)
10782 #define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
10783 #define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
10784 
10785 #define I2C_OAR1_ADDMODE_Pos                (15U)
10786 #define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
10787 #define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
10788 
10789 /*******************  Bit definition for I2C_OAR2 register  *******************/
10790 #define I2C_OAR2_ENDUAL_Pos                 (0U)
10791 #define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
10792 #define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
10793 #define I2C_OAR2_ADD2_Pos                   (1U)
10794 #define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
10795 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
10796 
10797 /********************  Bit definition for I2C_DR register  ********************/
10798 #define I2C_DR_DR_Pos             (0U)
10799 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
10800 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */
10801 
10802 /*******************  Bit definition for I2C_SR1 register  ********************/
10803 #define I2C_SR1_SB_Pos                      (0U)
10804 #define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
10805 #define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
10806 #define I2C_SR1_ADDR_Pos                    (1U)
10807 #define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
10808 #define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
10809 #define I2C_SR1_BTF_Pos                     (2U)
10810 #define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
10811 #define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
10812 #define I2C_SR1_ADD10_Pos                   (3U)
10813 #define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
10814 #define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
10815 #define I2C_SR1_STOPF_Pos                   (4U)
10816 #define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
10817 #define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
10818 #define I2C_SR1_RXNE_Pos                    (6U)
10819 #define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
10820 #define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
10821 #define I2C_SR1_TXE_Pos                     (7U)
10822 #define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
10823 #define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
10824 #define I2C_SR1_BERR_Pos                    (8U)
10825 #define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
10826 #define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
10827 #define I2C_SR1_ARLO_Pos                    (9U)
10828 #define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
10829 #define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
10830 #define I2C_SR1_AF_Pos                      (10U)
10831 #define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
10832 #define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
10833 #define I2C_SR1_OVR_Pos                     (11U)
10834 #define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
10835 #define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
10836 #define I2C_SR1_PECERR_Pos                  (12U)
10837 #define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
10838 #define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
10839 #define I2C_SR1_TIMEOUT_Pos                 (14U)
10840 #define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
10841 #define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
10842 #define I2C_SR1_SMBALERT_Pos                (15U)
10843 #define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
10844 #define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
10845 
10846 /*******************  Bit definition for I2C_SR2 register  ********************/
10847 #define I2C_SR2_MSL_Pos                     (0U)
10848 #define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
10849 #define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
10850 #define I2C_SR2_BUSY_Pos                    (1U)
10851 #define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
10852 #define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
10853 #define I2C_SR2_TRA_Pos                     (2U)
10854 #define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
10855 #define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
10856 #define I2C_SR2_GENCALL_Pos                 (4U)
10857 #define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
10858 #define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
10859 #define I2C_SR2_SMBDEFAULT_Pos              (5U)
10860 #define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
10861 #define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
10862 #define I2C_SR2_SMBHOST_Pos                 (6U)
10863 #define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
10864 #define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
10865 #define I2C_SR2_DUALF_Pos                   (7U)
10866 #define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
10867 #define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
10868 #define I2C_SR2_PEC_Pos                     (8U)
10869 #define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
10870 #define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
10871 
10872 /*******************  Bit definition for I2C_CCR register  ********************/
10873 #define I2C_CCR_CCR_Pos                     (0U)
10874 #define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
10875 #define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
10876 #define I2C_CCR_DUTY_Pos                    (14U)
10877 #define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
10878 #define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
10879 #define I2C_CCR_FS_Pos                      (15U)
10880 #define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
10881 #define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
10882 
10883 /******************  Bit definition for I2C_TRISE register  *******************/
10884 #define I2C_TRISE_TRISE_Pos                 (0U)
10885 #define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
10886 #define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
10887 
10888 /******************************************************************************/
10889 /*                                                                            */
10890 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
10891 /*                                                                            */
10892 /******************************************************************************/
10893 
10894 /*******************  Bit definition for USART_SR register  *******************/
10895 #define USART_SR_PE_Pos                     (0U)
10896 #define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
10897 #define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
10898 #define USART_SR_FE_Pos                     (1U)
10899 #define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
10900 #define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
10901 #define USART_SR_NE_Pos                     (2U)
10902 #define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
10903 #define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
10904 #define USART_SR_ORE_Pos                    (3U)
10905 #define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
10906 #define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
10907 #define USART_SR_IDLE_Pos                   (4U)
10908 #define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
10909 #define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
10910 #define USART_SR_RXNE_Pos                   (5U)
10911 #define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
10912 #define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
10913 #define USART_SR_TC_Pos                     (6U)
10914 #define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
10915 #define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
10916 #define USART_SR_TXE_Pos                    (7U)
10917 #define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
10918 #define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
10919 #define USART_SR_LBD_Pos                    (8U)
10920 #define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
10921 #define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
10922 #define USART_SR_CTS_Pos                    (9U)
10923 #define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
10924 #define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
10925 
10926 /*******************  Bit definition for USART_DR register  *******************/
10927 #define USART_DR_DR_Pos                     (0U)
10928 #define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
10929 #define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
10930 
10931 /******************  Bit definition for USART_BRR register  *******************/
10932 #define USART_BRR_DIV_Fraction_Pos          (0U)
10933 #define USART_BRR_DIV_Fraction_Msk          (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
10934 #define USART_BRR_DIV_Fraction              USART_BRR_DIV_Fraction_Msk         /*!< Fraction of USARTDIV */
10935 #define USART_BRR_DIV_Mantissa_Pos          (4U)
10936 #define USART_BRR_DIV_Mantissa_Msk          (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
10937 #define USART_BRR_DIV_Mantissa              USART_BRR_DIV_Mantissa_Msk         /*!< Mantissa of USARTDIV */
10938 
10939 /******************  Bit definition for USART_CR1 register  *******************/
10940 #define USART_CR1_SBK_Pos                   (0U)
10941 #define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
10942 #define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
10943 #define USART_CR1_RWU_Pos                   (1U)
10944 #define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
10945 #define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
10946 #define USART_CR1_RE_Pos                    (2U)
10947 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
10948 #define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
10949 #define USART_CR1_TE_Pos                    (3U)
10950 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
10951 #define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
10952 #define USART_CR1_IDLEIE_Pos                (4U)
10953 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
10954 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
10955 #define USART_CR1_RXNEIE_Pos                (5U)
10956 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
10957 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
10958 #define USART_CR1_TCIE_Pos                  (6U)
10959 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
10960 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
10961 #define USART_CR1_TXEIE_Pos                 (7U)
10962 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
10963 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
10964 #define USART_CR1_PEIE_Pos                  (8U)
10965 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
10966 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
10967 #define USART_CR1_PS_Pos                    (9U)
10968 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
10969 #define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
10970 #define USART_CR1_PCE_Pos                   (10U)
10971 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
10972 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
10973 #define USART_CR1_WAKE_Pos                  (11U)
10974 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
10975 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
10976 #define USART_CR1_M_Pos                     (12U)
10977 #define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
10978 #define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
10979 #define USART_CR1_UE_Pos                    (13U)
10980 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
10981 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
10982 
10983 /******************  Bit definition for USART_CR2 register  *******************/
10984 #define USART_CR2_ADD_Pos                   (0U)
10985 #define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
10986 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
10987 #define USART_CR2_LBDL_Pos                  (5U)
10988 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
10989 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
10990 #define USART_CR2_LBDIE_Pos                 (6U)
10991 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
10992 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
10993 #define USART_CR2_LBCL_Pos                  (8U)
10994 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
10995 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
10996 #define USART_CR2_CPHA_Pos                  (9U)
10997 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
10998 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
10999 #define USART_CR2_CPOL_Pos                  (10U)
11000 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
11001 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
11002 #define USART_CR2_CLKEN_Pos                 (11U)
11003 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
11004 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
11005 
11006 #define USART_CR2_STOP_Pos                  (12U)
11007 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
11008 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
11009 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
11010 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
11011 
11012 #define USART_CR2_LINEN_Pos                 (14U)
11013 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
11014 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
11015 
11016 /******************  Bit definition for USART_CR3 register  *******************/
11017 #define USART_CR3_EIE_Pos                   (0U)
11018 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
11019 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
11020 #define USART_CR3_IREN_Pos                  (1U)
11021 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
11022 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
11023 #define USART_CR3_IRLP_Pos                  (2U)
11024 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
11025 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
11026 #define USART_CR3_HDSEL_Pos                 (3U)
11027 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
11028 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
11029 #define USART_CR3_NACK_Pos                  (4U)
11030 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
11031 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
11032 #define USART_CR3_SCEN_Pos                  (5U)
11033 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
11034 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
11035 #define USART_CR3_DMAR_Pos                  (6U)
11036 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
11037 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
11038 #define USART_CR3_DMAT_Pos                  (7U)
11039 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
11040 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
11041 #define USART_CR3_RTSE_Pos                  (8U)
11042 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
11043 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
11044 #define USART_CR3_CTSE_Pos                  (9U)
11045 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
11046 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
11047 #define USART_CR3_CTSIE_Pos                 (10U)
11048 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
11049 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
11050 
11051 /******************  Bit definition for USART_GTPR register  ******************/
11052 #define USART_GTPR_PSC_Pos                  (0U)
11053 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
11054 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
11055 #define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
11056 #define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
11057 #define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
11058 #define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
11059 #define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
11060 #define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
11061 #define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
11062 #define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
11063 
11064 #define USART_GTPR_GT_Pos                   (8U)
11065 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
11066 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
11067 
11068 /******************************************************************************/
11069 /*                                                                            */
11070 /*                                 Debug MCU                                  */
11071 /*                                                                            */
11072 /******************************************************************************/
11073 
11074 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
11075 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
11076 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
11077 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk           /*!< Device Identifier */
11078 
11079 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
11080 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
11081 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk           /*!< REV_ID[15:0] bits (Revision Identifier) */
11082 #define DBGMCU_IDCODE_REV_ID_0              (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
11083 #define DBGMCU_IDCODE_REV_ID_1              (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
11084 #define DBGMCU_IDCODE_REV_ID_2              (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
11085 #define DBGMCU_IDCODE_REV_ID_3              (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
11086 #define DBGMCU_IDCODE_REV_ID_4              (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
11087 #define DBGMCU_IDCODE_REV_ID_5              (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
11088 #define DBGMCU_IDCODE_REV_ID_6              (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
11089 #define DBGMCU_IDCODE_REV_ID_7              (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
11090 #define DBGMCU_IDCODE_REV_ID_8              (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
11091 #define DBGMCU_IDCODE_REV_ID_9              (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
11092 #define DBGMCU_IDCODE_REV_ID_10             (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
11093 #define DBGMCU_IDCODE_REV_ID_11             (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
11094 #define DBGMCU_IDCODE_REV_ID_12             (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
11095 #define DBGMCU_IDCODE_REV_ID_13             (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
11096 #define DBGMCU_IDCODE_REV_ID_14             (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
11097 #define DBGMCU_IDCODE_REV_ID_15             (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
11098 
11099 /******************  Bit definition for DBGMCU_CR register  *******************/
11100 #define DBGMCU_CR_DBG_SLEEP_Pos             (0U)
11101 #define DBGMCU_CR_DBG_SLEEP_Msk             (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
11102 #define DBGMCU_CR_DBG_SLEEP                 DBGMCU_CR_DBG_SLEEP_Msk            /*!< Debug Sleep Mode */
11103 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
11104 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
11105 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk             /*!< Debug Stop Mode */
11106 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
11107 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
11108 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk          /*!< Debug Standby mode */
11109 #define DBGMCU_CR_TRACE_IOEN_Pos            (5U)
11110 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
11111 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk           /*!< Trace Pin Assignment Control */
11112 
11113 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
11114 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
11115 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk           /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
11116 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
11117 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
11118 
11119 #define DBGMCU_CR_DBG_IWDG_STOP_Pos         (8U)
11120 #define DBGMCU_CR_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
11121 #define DBGMCU_CR_DBG_IWDG_STOP             DBGMCU_CR_DBG_IWDG_STOP_Msk        /*!< Debug Independent Watchdog stopped when Core is halted */
11122 #define DBGMCU_CR_DBG_WWDG_STOP_Pos         (9U)
11123 #define DBGMCU_CR_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
11124 #define DBGMCU_CR_DBG_WWDG_STOP             DBGMCU_CR_DBG_WWDG_STOP_Msk        /*!< Debug Window Watchdog stopped when Core is halted */
11125 #define DBGMCU_CR_DBG_TIM1_STOP_Pos         (10U)
11126 #define DBGMCU_CR_DBG_TIM1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
11127 #define DBGMCU_CR_DBG_TIM1_STOP             DBGMCU_CR_DBG_TIM1_STOP_Msk        /*!< TIM1 counter stopped when core is halted */
11128 #define DBGMCU_CR_DBG_TIM2_STOP_Pos         (11U)
11129 #define DBGMCU_CR_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
11130 #define DBGMCU_CR_DBG_TIM2_STOP             DBGMCU_CR_DBG_TIM2_STOP_Msk        /*!< TIM2 counter stopped when core is halted */
11131 #define DBGMCU_CR_DBG_TIM3_STOP_Pos         (12U)
11132 #define DBGMCU_CR_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
11133 #define DBGMCU_CR_DBG_TIM3_STOP             DBGMCU_CR_DBG_TIM3_STOP_Msk        /*!< TIM3 counter stopped when core is halted */
11134 #define DBGMCU_CR_DBG_TIM4_STOP_Pos         (13U)
11135 #define DBGMCU_CR_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
11136 #define DBGMCU_CR_DBG_TIM4_STOP             DBGMCU_CR_DBG_TIM4_STOP_Msk        /*!< TIM4 counter stopped when core is halted */
11137 #define DBGMCU_CR_DBG_CAN1_STOP_Pos         (14U)
11138 #define DBGMCU_CR_DBG_CAN1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
11139 #define DBGMCU_CR_DBG_CAN1_STOP             DBGMCU_CR_DBG_CAN1_STOP_Msk        /*!< Debug CAN1 stopped when Core is halted */
11140 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
11141 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
11142 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
11143 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
11144 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
11145 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
11146 #define DBGMCU_CR_DBG_TIM8_STOP_Pos         (17U)
11147 #define DBGMCU_CR_DBG_TIM8_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM8_STOP_Pos) /*!< 0x00020000 */
11148 #define DBGMCU_CR_DBG_TIM8_STOP             DBGMCU_CR_DBG_TIM8_STOP_Msk        /*!< TIM8 counter stopped when core is halted */
11149 #define DBGMCU_CR_DBG_TIM5_STOP_Pos         (18U)
11150 #define DBGMCU_CR_DBG_TIM5_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
11151 #define DBGMCU_CR_DBG_TIM5_STOP             DBGMCU_CR_DBG_TIM5_STOP_Msk        /*!< TIM5 counter stopped when core is halted */
11152 #define DBGMCU_CR_DBG_TIM6_STOP_Pos         (19U)
11153 #define DBGMCU_CR_DBG_TIM6_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
11154 #define DBGMCU_CR_DBG_TIM6_STOP             DBGMCU_CR_DBG_TIM6_STOP_Msk        /*!< TIM6 counter stopped when core is halted */
11155 #define DBGMCU_CR_DBG_TIM7_STOP_Pos         (20U)
11156 #define DBGMCU_CR_DBG_TIM7_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
11157 #define DBGMCU_CR_DBG_TIM7_STOP             DBGMCU_CR_DBG_TIM7_STOP_Msk        /*!< TIM7 counter stopped when core is halted */
11158 #define DBGMCU_CR_DBG_TIM12_STOP_Pos        (25U)
11159 #define DBGMCU_CR_DBG_TIM12_STOP_Msk        (0x1UL << DBGMCU_CR_DBG_TIM12_STOP_Pos) /*!< 0x02000000 */
11160 #define DBGMCU_CR_DBG_TIM12_STOP            DBGMCU_CR_DBG_TIM12_STOP_Msk       /*!< Debug TIM12 stopped when Core is halted */
11161 #define DBGMCU_CR_DBG_TIM13_STOP_Pos        (26U)
11162 #define DBGMCU_CR_DBG_TIM13_STOP_Msk        (0x1UL << DBGMCU_CR_DBG_TIM13_STOP_Pos) /*!< 0x04000000 */
11163 #define DBGMCU_CR_DBG_TIM13_STOP            DBGMCU_CR_DBG_TIM13_STOP_Msk       /*!< Debug TIM13 stopped when Core is halted */
11164 #define DBGMCU_CR_DBG_TIM14_STOP_Pos        (27U)
11165 #define DBGMCU_CR_DBG_TIM14_STOP_Msk        (0x1UL << DBGMCU_CR_DBG_TIM14_STOP_Pos) /*!< 0x08000000 */
11166 #define DBGMCU_CR_DBG_TIM14_STOP            DBGMCU_CR_DBG_TIM14_STOP_Msk       /*!< Debug TIM14 stopped when Core is halted */
11167 #define DBGMCU_CR_DBG_TIM9_STOP_Pos         (28U)
11168 #define DBGMCU_CR_DBG_TIM9_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
11169 #define DBGMCU_CR_DBG_TIM9_STOP             DBGMCU_CR_DBG_TIM9_STOP_Msk        /*!< Debug TIM9 stopped when Core is halted */
11170 #define DBGMCU_CR_DBG_TIM10_STOP_Pos        (29U)
11171 #define DBGMCU_CR_DBG_TIM10_STOP_Msk        (0x1UL << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
11172 #define DBGMCU_CR_DBG_TIM10_STOP            DBGMCU_CR_DBG_TIM10_STOP_Msk       /*!< Debug TIM10 stopped when Core is halted */
11173 #define DBGMCU_CR_DBG_TIM11_STOP_Pos        (30U)
11174 #define DBGMCU_CR_DBG_TIM11_STOP_Msk        (0x1UL << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
11175 #define DBGMCU_CR_DBG_TIM11_STOP            DBGMCU_CR_DBG_TIM11_STOP_Msk       /*!< Debug TIM11 stopped when Core is halted */
11176 
11177 /******************************************************************************/
11178 /*                                                                            */
11179 /*                      FLASH and Option Bytes Registers                      */
11180 /*                                                                            */
11181 /******************************************************************************/
11182 /*******************  Bit definition for FLASH_ACR register  ******************/
11183 #define FLASH_ACR_LATENCY_Pos               (0U)
11184 #define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000007 */
11185 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< LATENCY[2:0] bits (Latency) */
11186 #define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */
11187 #define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */
11188 #define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000004 */
11189 
11190 #define FLASH_ACR_HLFCYA_Pos                (3U)
11191 #define FLASH_ACR_HLFCYA_Msk                (0x1UL << FLASH_ACR_HLFCYA_Pos)     /*!< 0x00000008 */
11192 #define FLASH_ACR_HLFCYA                    FLASH_ACR_HLFCYA_Msk               /*!< Flash Half Cycle Access Enable */
11193 #define FLASH_ACR_PRFTBE_Pos                (4U)
11194 #define FLASH_ACR_PRFTBE_Msk                (0x1UL << FLASH_ACR_PRFTBE_Pos)     /*!< 0x00000010 */
11195 #define FLASH_ACR_PRFTBE                    FLASH_ACR_PRFTBE_Msk               /*!< Prefetch Buffer Enable */
11196 #define FLASH_ACR_PRFTBS_Pos                (5U)
11197 #define FLASH_ACR_PRFTBS_Msk                (0x1UL << FLASH_ACR_PRFTBS_Pos)     /*!< 0x00000020 */
11198 #define FLASH_ACR_PRFTBS                    FLASH_ACR_PRFTBS_Msk               /*!< Prefetch Buffer Status */
11199 
11200 /******************  Bit definition for FLASH_KEYR register  ******************/
11201 #define FLASH_KEYR_FKEYR_Pos                (0U)
11202 #define FLASH_KEYR_FKEYR_Msk                (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
11203 #define FLASH_KEYR_FKEYR                    FLASH_KEYR_FKEYR_Msk               /*!< FPEC Key */
11204 
11205 #define RDP_KEY_Pos                         (0U)
11206 #define RDP_KEY_Msk                         (0xA5UL << RDP_KEY_Pos)             /*!< 0x000000A5 */
11207 #define RDP_KEY                             RDP_KEY_Msk                        /*!< RDP Key */
11208 #define FLASH_KEY1_Pos                      (0U)
11209 #define FLASH_KEY1_Msk                      (0x45670123UL << FLASH_KEY1_Pos)    /*!< 0x45670123 */
11210 #define FLASH_KEY1                          FLASH_KEY1_Msk                     /*!< FPEC Key1 */
11211 #define FLASH_KEY2_Pos                      (0U)
11212 #define FLASH_KEY2_Msk                      (0xCDEF89ABUL << FLASH_KEY2_Pos)    /*!< 0xCDEF89AB */
11213 #define FLASH_KEY2                          FLASH_KEY2_Msk                     /*!< FPEC Key2 */
11214 
11215 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
11216 #define FLASH_OPTKEYR_OPTKEYR_Pos           (0U)
11217 #define FLASH_OPTKEYR_OPTKEYR_Msk           (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
11218 #define FLASH_OPTKEYR_OPTKEYR               FLASH_OPTKEYR_OPTKEYR_Msk          /*!< Option Byte Key */
11219 
11220 #define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
11221 #define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
11222 
11223 /******************  Bit definition for FLASH_SR register  ********************/
11224 #define FLASH_SR_BSY_Pos                    (0U)
11225 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)         /*!< 0x00000001 */
11226 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Busy */
11227 #define FLASH_SR_PGERR_Pos                  (2U)
11228 #define FLASH_SR_PGERR_Msk                  (0x1UL << FLASH_SR_PGERR_Pos)       /*!< 0x00000004 */
11229 #define FLASH_SR_PGERR                      FLASH_SR_PGERR_Msk                 /*!< Programming Error */
11230 #define FLASH_SR_WRPRTERR_Pos               (4U)
11231 #define FLASH_SR_WRPRTERR_Msk               (0x1UL << FLASH_SR_WRPRTERR_Pos)    /*!< 0x00000010 */
11232 #define FLASH_SR_WRPRTERR                   FLASH_SR_WRPRTERR_Msk              /*!< Write Protection Error */
11233 #define FLASH_SR_EOP_Pos                    (5U)
11234 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)         /*!< 0x00000020 */
11235 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of operation */
11236 
11237 /*******************  Bit definition for FLASH_CR register  *******************/
11238 #define FLASH_CR_PG_Pos                     (0U)
11239 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)          /*!< 0x00000001 */
11240 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Programming */
11241 #define FLASH_CR_PER_Pos                    (1U)
11242 #define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)         /*!< 0x00000002 */
11243 #define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page Erase */
11244 #define FLASH_CR_MER_Pos                    (2U)
11245 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)         /*!< 0x00000004 */
11246 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass Erase */
11247 #define FLASH_CR_OPTPG_Pos                  (4U)
11248 #define FLASH_CR_OPTPG_Msk                  (0x1UL << FLASH_CR_OPTPG_Pos)       /*!< 0x00000010 */
11249 #define FLASH_CR_OPTPG                      FLASH_CR_OPTPG_Msk                 /*!< Option Byte Programming */
11250 #define FLASH_CR_OPTER_Pos                  (5U)
11251 #define FLASH_CR_OPTER_Msk                  (0x1UL << FLASH_CR_OPTER_Pos)       /*!< 0x00000020 */
11252 #define FLASH_CR_OPTER                      FLASH_CR_OPTER_Msk                 /*!< Option Byte Erase */
11253 #define FLASH_CR_STRT_Pos                   (6U)
11254 #define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)        /*!< 0x00000040 */
11255 #define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start */
11256 #define FLASH_CR_LOCK_Pos                   (7U)
11257 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)        /*!< 0x00000080 */
11258 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Lock */
11259 #define FLASH_CR_OPTWRE_Pos                 (9U)
11260 #define FLASH_CR_OPTWRE_Msk                 (0x1UL << FLASH_CR_OPTWRE_Pos)      /*!< 0x00000200 */
11261 #define FLASH_CR_OPTWRE                     FLASH_CR_OPTWRE_Msk                /*!< Option Bytes Write Enable */
11262 #define FLASH_CR_ERRIE_Pos                  (10U)
11263 #define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)       /*!< 0x00000400 */
11264 #define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error Interrupt Enable */
11265 #define FLASH_CR_EOPIE_Pos                  (12U)
11266 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)       /*!< 0x00001000 */
11267 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable */
11268 
11269 /*******************  Bit definition for FLASH_AR register  *******************/
11270 #define FLASH_AR_FAR_Pos                    (0U)
11271 #define FLASH_AR_FAR_Msk                    (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)  /*!< 0xFFFFFFFF */
11272 #define FLASH_AR_FAR                        FLASH_AR_FAR_Msk                   /*!< Flash Address */
11273 
11274 /******************  Bit definition for FLASH_OBR register  *******************/
11275 #define FLASH_OBR_OPTERR_Pos                (0U)
11276 #define FLASH_OBR_OPTERR_Msk                (0x1UL << FLASH_OBR_OPTERR_Pos)     /*!< 0x00000001 */
11277 #define FLASH_OBR_OPTERR                    FLASH_OBR_OPTERR_Msk               /*!< Option Byte Error */
11278 #define FLASH_OBR_RDPRT_Pos                 (1U)
11279 #define FLASH_OBR_RDPRT_Msk                 (0x1UL << FLASH_OBR_RDPRT_Pos)      /*!< 0x00000002 */
11280 #define FLASH_OBR_RDPRT                     FLASH_OBR_RDPRT_Msk                /*!< Read protection */
11281 
11282 #define FLASH_OBR_IWDG_SW_Pos               (2U)
11283 #define FLASH_OBR_IWDG_SW_Msk               (0x1UL << FLASH_OBR_IWDG_SW_Pos)    /*!< 0x00000004 */
11284 #define FLASH_OBR_IWDG_SW                   FLASH_OBR_IWDG_SW_Msk              /*!< IWDG SW */
11285 #define FLASH_OBR_nRST_STOP_Pos             (3U)
11286 #define FLASH_OBR_nRST_STOP_Msk             (0x1UL << FLASH_OBR_nRST_STOP_Pos)  /*!< 0x00000008 */
11287 #define FLASH_OBR_nRST_STOP                 FLASH_OBR_nRST_STOP_Msk            /*!< nRST_STOP */
11288 #define FLASH_OBR_nRST_STDBY_Pos            (4U)
11289 #define FLASH_OBR_nRST_STDBY_Msk            (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
11290 #define FLASH_OBR_nRST_STDBY                FLASH_OBR_nRST_STDBY_Msk           /*!< nRST_STDBY */
11291 #define FLASH_OBR_BFB2_Pos                  (5U)
11292 #define FLASH_OBR_BFB2_Msk                  (0x1UL << FLASH_OBR_BFB2_Pos)       /*!< 0x00000020 */
11293 #define FLASH_OBR_BFB2                      FLASH_OBR_BFB2_Msk                 /*!< BFB2 */
11294 #define FLASH_OBR_USER_Pos                  (2U)
11295 #define FLASH_OBR_USER_Msk                  (0xFUL << FLASH_OBR_USER_Pos)       /*!< 0x0000003C */
11296 #define FLASH_OBR_USER                      FLASH_OBR_USER_Msk                 /*!< User Option Bytes */
11297 #define FLASH_OBR_DATA0_Pos                 (10U)
11298 #define FLASH_OBR_DATA0_Msk                 (0xFFUL << FLASH_OBR_DATA0_Pos)     /*!< 0x0003FC00 */
11299 #define FLASH_OBR_DATA0                     FLASH_OBR_DATA0_Msk                /*!< Data0 */
11300 #define FLASH_OBR_DATA1_Pos                 (18U)
11301 #define FLASH_OBR_DATA1_Msk                 (0xFFUL << FLASH_OBR_DATA1_Pos)     /*!< 0x03FC0000 */
11302 #define FLASH_OBR_DATA1                     FLASH_OBR_DATA1_Msk                /*!< Data1 */
11303 
11304 /******************  Bit definition for FLASH_WRPR register  ******************/
11305 #define FLASH_WRPR_WRP_Pos                  (0U)
11306 #define FLASH_WRPR_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
11307 #define FLASH_WRPR_WRP                      FLASH_WRPR_WRP_Msk                 /*!< Write Protect */
11308 
11309 /*****************  Bit definition for FLASH_OPTKEYR2 register ****************/
11310 #define FLASH_OPTKEYR_OPTKEYR2_Pos          (0U)
11311 #define FLASH_OPTKEYR_OPTKEYR2_Msk          (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR2_Pos) /*!< 0xFFFFFFFF */
11312 #define FLASH_OPTKEYR_OPTKEYR2              FLASH_OPTKEYR_OPTKEYR2_Msk         /*!< Option Byte Key */
11313 
11314 /******************  Bit definition for FLASH_SR2 register ********************/
11315 #define FLASH_SR2_BSY_Pos                   (0U)
11316 #define FLASH_SR2_BSY_Msk                   (0x1UL << FLASH_SR2_BSY_Pos)        /*!< 0x00000001 */
11317 #define FLASH_SR2_BSY                       FLASH_SR2_BSY_Msk                  /*!< Busy */
11318 #define FLASH_SR2_PGERR_Pos                 (2U)
11319 #define FLASH_SR2_PGERR_Msk                 (0x1UL << FLASH_SR2_PGERR_Pos)      /*!< 0x00000004 */
11320 #define FLASH_SR2_PGERR                     FLASH_SR2_PGERR_Msk                /*!< Programming Error */
11321 #define FLASH_SR2_WRPRTERR_Pos              (4U)
11322 #define FLASH_SR2_WRPRTERR_Msk              (0x1UL << FLASH_SR2_WRPRTERR_Pos)   /*!< 0x00000010 */
11323 #define FLASH_SR2_WRPRTERR                  FLASH_SR2_WRPRTERR_Msk             /*!< Write Protection Error */
11324 #define FLASH_SR2_EOP_Pos                   (5U)
11325 #define FLASH_SR2_EOP_Msk                   (0x1UL << FLASH_SR2_EOP_Pos)        /*!< 0x00000020 */
11326 #define FLASH_SR2_EOP                       FLASH_SR2_EOP_Msk                  /*!< End of operation */
11327 
11328 /*******************  Bit definition for FLASH_CR2 register *******************/
11329 #define FLASH_CR2_PG_Pos                    (0U)
11330 #define FLASH_CR2_PG_Msk                    (0x1UL << FLASH_CR2_PG_Pos)         /*!< 0x00000001 */
11331 #define FLASH_CR2_PG                        FLASH_CR2_PG_Msk                   /*!< Programming */
11332 #define FLASH_CR2_PER_Pos                   (1U)
11333 #define FLASH_CR2_PER_Msk                   (0x1UL << FLASH_CR2_PER_Pos)        /*!< 0x00000002 */
11334 #define FLASH_CR2_PER                       FLASH_CR2_PER_Msk                  /*!< Page Erase */
11335 #define FLASH_CR2_MER_Pos                   (2U)
11336 #define FLASH_CR2_MER_Msk                   (0x1UL << FLASH_CR2_MER_Pos)        /*!< 0x00000004 */
11337 #define FLASH_CR2_MER                       FLASH_CR2_MER_Msk                  /*!< Mass Erase */
11338 #define FLASH_CR2_STRT_Pos                  (6U)
11339 #define FLASH_CR2_STRT_Msk                  (0x1UL << FLASH_CR2_STRT_Pos)       /*!< 0x00000040 */
11340 #define FLASH_CR2_STRT                      FLASH_CR2_STRT_Msk                 /*!< Start */
11341 #define FLASH_CR2_LOCK_Pos                  (7U)
11342 #define FLASH_CR2_LOCK_Msk                  (0x1UL << FLASH_CR2_LOCK_Pos)       /*!< 0x00000080 */
11343 #define FLASH_CR2_LOCK                      FLASH_CR2_LOCK_Msk                 /*!< Lock */
11344 #define FLASH_CR2_ERRIE_Pos                 (10U)
11345 #define FLASH_CR2_ERRIE_Msk                 (0x1UL << FLASH_CR2_ERRIE_Pos)      /*!< 0x00000400 */
11346 #define FLASH_CR2_ERRIE                     FLASH_CR2_ERRIE_Msk                /*!< Error Interrupt Enable */
11347 #define FLASH_CR2_EOPIE_Pos                 (12U)
11348 #define FLASH_CR2_EOPIE_Msk                 (0x1UL << FLASH_CR2_EOPIE_Pos)      /*!< 0x00001000 */
11349 #define FLASH_CR2_EOPIE                     FLASH_CR2_EOPIE_Msk                /*!< End of operation interrupt enable */
11350 
11351 /*******************  Bit definition for FLASH_AR2 register *******************/
11352 #define FLASH_AR_FAR2_Pos                   (0U)
11353 #define FLASH_AR_FAR2_Msk                   (0xFFFFFFFFUL << FLASH_AR_FAR2_Pos) /*!< 0xFFFFFFFF */
11354 #define FLASH_AR_FAR2                       FLASH_AR_FAR2_Msk                  /*!< Flash Address */
11355 
11356 /*----------------------------------------------------------------------------*/
11357 
11358 /******************  Bit definition for FLASH_RDP register  *******************/
11359 #define FLASH_RDP_RDP_Pos                   (0U)
11360 #define FLASH_RDP_RDP_Msk                   (0xFFUL << FLASH_RDP_RDP_Pos)       /*!< 0x000000FF */
11361 #define FLASH_RDP_RDP                       FLASH_RDP_RDP_Msk                  /*!< Read protection option byte */
11362 #define FLASH_RDP_nRDP_Pos                  (8U)
11363 #define FLASH_RDP_nRDP_Msk                  (0xFFUL << FLASH_RDP_nRDP_Pos)      /*!< 0x0000FF00 */
11364 #define FLASH_RDP_nRDP                      FLASH_RDP_nRDP_Msk                 /*!< Read protection complemented option byte */
11365 
11366 /******************  Bit definition for FLASH_USER register  ******************/
11367 #define FLASH_USER_USER_Pos                 (16U)
11368 #define FLASH_USER_USER_Msk                 (0xFFUL << FLASH_USER_USER_Pos)     /*!< 0x00FF0000 */
11369 #define FLASH_USER_USER                     FLASH_USER_USER_Msk                /*!< User option byte */
11370 #define FLASH_USER_nUSER_Pos                (24U)
11371 #define FLASH_USER_nUSER_Msk                (0xFFUL << FLASH_USER_nUSER_Pos)    /*!< 0xFF000000 */
11372 #define FLASH_USER_nUSER                    FLASH_USER_nUSER_Msk               /*!< User complemented option byte */
11373 
11374 /******************  Bit definition for FLASH_Data0 register  *****************/
11375 #define FLASH_DATA0_DATA0_Pos               (0U)
11376 #define FLASH_DATA0_DATA0_Msk               (0xFFUL << FLASH_DATA0_DATA0_Pos)   /*!< 0x000000FF */
11377 #define FLASH_DATA0_DATA0                   FLASH_DATA0_DATA0_Msk              /*!< User data storage option byte */
11378 #define FLASH_DATA0_nDATA0_Pos              (8U)
11379 #define FLASH_DATA0_nDATA0_Msk              (0xFFUL << FLASH_DATA0_nDATA0_Pos)  /*!< 0x0000FF00 */
11380 #define FLASH_DATA0_nDATA0                  FLASH_DATA0_nDATA0_Msk             /*!< User data storage complemented option byte */
11381 
11382 /******************  Bit definition for FLASH_Data1 register  *****************/
11383 #define FLASH_DATA1_DATA1_Pos               (16U)
11384 #define FLASH_DATA1_DATA1_Msk               (0xFFUL << FLASH_DATA1_DATA1_Pos)   /*!< 0x00FF0000 */
11385 #define FLASH_DATA1_DATA1                   FLASH_DATA1_DATA1_Msk              /*!< User data storage option byte */
11386 #define FLASH_DATA1_nDATA1_Pos              (24U)
11387 #define FLASH_DATA1_nDATA1_Msk              (0xFFUL << FLASH_DATA1_nDATA1_Pos)  /*!< 0xFF000000 */
11388 #define FLASH_DATA1_nDATA1                  FLASH_DATA1_nDATA1_Msk             /*!< User data storage complemented option byte */
11389 
11390 /******************  Bit definition for FLASH_WRP0 register  ******************/
11391 #define FLASH_WRP0_WRP0_Pos                 (0U)
11392 #define FLASH_WRP0_WRP0_Msk                 (0xFFUL << FLASH_WRP0_WRP0_Pos)     /*!< 0x000000FF */
11393 #define FLASH_WRP0_WRP0                     FLASH_WRP0_WRP0_Msk                /*!< Flash memory write protection option bytes */
11394 #define FLASH_WRP0_nWRP0_Pos                (8U)
11395 #define FLASH_WRP0_nWRP0_Msk                (0xFFUL << FLASH_WRP0_nWRP0_Pos)    /*!< 0x0000FF00 */
11396 #define FLASH_WRP0_nWRP0                    FLASH_WRP0_nWRP0_Msk               /*!< Flash memory write protection complemented option bytes */
11397 
11398 /******************  Bit definition for FLASH_WRP1 register  ******************/
11399 #define FLASH_WRP1_WRP1_Pos                 (16U)
11400 #define FLASH_WRP1_WRP1_Msk                 (0xFFUL << FLASH_WRP1_WRP1_Pos)     /*!< 0x00FF0000 */
11401 #define FLASH_WRP1_WRP1                     FLASH_WRP1_WRP1_Msk                /*!< Flash memory write protection option bytes */
11402 #define FLASH_WRP1_nWRP1_Pos                (24U)
11403 #define FLASH_WRP1_nWRP1_Msk                (0xFFUL << FLASH_WRP1_nWRP1_Pos)    /*!< 0xFF000000 */
11404 #define FLASH_WRP1_nWRP1                    FLASH_WRP1_nWRP1_Msk               /*!< Flash memory write protection complemented option bytes */
11405 
11406 /******************  Bit definition for FLASH_WRP2 register  ******************/
11407 #define FLASH_WRP2_WRP2_Pos                 (0U)
11408 #define FLASH_WRP2_WRP2_Msk                 (0xFFUL << FLASH_WRP2_WRP2_Pos)     /*!< 0x000000FF */
11409 #define FLASH_WRP2_WRP2                     FLASH_WRP2_WRP2_Msk                /*!< Flash memory write protection option bytes */
11410 #define FLASH_WRP2_nWRP2_Pos                (8U)
11411 #define FLASH_WRP2_nWRP2_Msk                (0xFFUL << FLASH_WRP2_nWRP2_Pos)    /*!< 0x0000FF00 */
11412 #define FLASH_WRP2_nWRP2                    FLASH_WRP2_nWRP2_Msk               /*!< Flash memory write protection complemented option bytes */
11413 
11414 /******************  Bit definition for FLASH_WRP3 register  ******************/
11415 #define FLASH_WRP3_WRP3_Pos                 (16U)
11416 #define FLASH_WRP3_WRP3_Msk                 (0xFFUL << FLASH_WRP3_WRP3_Pos)     /*!< 0x00FF0000 */
11417 #define FLASH_WRP3_WRP3                     FLASH_WRP3_WRP3_Msk                /*!< Flash memory write protection option bytes */
11418 #define FLASH_WRP3_nWRP3_Pos                (24U)
11419 #define FLASH_WRP3_nWRP3_Msk                (0xFFUL << FLASH_WRP3_nWRP3_Pos)    /*!< 0xFF000000 */
11420 #define FLASH_WRP3_nWRP3                    FLASH_WRP3_nWRP3_Msk               /*!< Flash memory write protection complemented option bytes */
11421 
11422 
11423 
11424 /**
11425   * @}
11426 */
11427 
11428 /**
11429   * @}
11430 */
11431 
11432 /** @addtogroup Exported_macro
11433   * @{
11434   */
11435 
11436 /****************************** ADC Instances *********************************/
11437 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
11438                                        ((INSTANCE) == ADC2) || \
11439                                        ((INSTANCE) == ADC3))
11440 
11441 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
11442 
11443 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
11444 
11445 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
11446                                                   ((INSTANCE) == ADC3))
11447 
11448 /****************************** CAN Instances *********************************/
11449 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
11450 
11451 /****************************** CRC Instances *********************************/
11452 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
11453 
11454 /****************************** DAC Instances *********************************/
11455 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
11456 
11457 /****************************** DMA Instances *********************************/
11458 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
11459                                        ((INSTANCE) == DMA1_Channel2) || \
11460                                        ((INSTANCE) == DMA1_Channel3) || \
11461                                        ((INSTANCE) == DMA1_Channel4) || \
11462                                        ((INSTANCE) == DMA1_Channel5) || \
11463                                        ((INSTANCE) == DMA1_Channel6) || \
11464                                        ((INSTANCE) == DMA1_Channel7) || \
11465                                        ((INSTANCE) == DMA2_Channel1) || \
11466                                        ((INSTANCE) == DMA2_Channel2) || \
11467                                        ((INSTANCE) == DMA2_Channel3) || \
11468                                        ((INSTANCE) == DMA2_Channel4) || \
11469                                        ((INSTANCE) == DMA2_Channel5))
11470 
11471 /******************************* GPIO Instances *******************************/
11472 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
11473                                         ((INSTANCE) == GPIOB) || \
11474                                         ((INSTANCE) == GPIOC) || \
11475                                         ((INSTANCE) == GPIOD) || \
11476                                         ((INSTANCE) == GPIOE) || \
11477                                         ((INSTANCE) == GPIOF) || \
11478                                         ((INSTANCE) == GPIOG))
11479 
11480 /**************************** GPIO Alternate Function Instances ***************/
11481 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
11482 
11483 /**************************** GPIO Lock Instances *****************************/
11484 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
11485 
11486 /******************************** I2C Instances *******************************/
11487 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
11488                                        ((INSTANCE) == I2C2))
11489 
11490 /******************************* SMBUS Instances ******************************/
11491 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
11492 
11493 /******************************** I2S Instances *******************************/
11494 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
11495                                        ((INSTANCE) == SPI3))
11496 
11497 /****************************** IWDG Instances ********************************/
11498 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
11499 
11500 /****************************** SDIO Instances *********************************/
11501 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
11502 
11503 /******************************** SPI Instances *******************************/
11504 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
11505                                        ((INSTANCE) == SPI2) || \
11506                                        ((INSTANCE) == SPI3))
11507 
11508 /****************************** START TIM Instances ***************************/
11509 /****************************** TIM Instances *********************************/
11510 #define IS_TIM_INSTANCE(INSTANCE)\
11511   (((INSTANCE) == TIM1)    || \
11512    ((INSTANCE) == TIM8)    || \
11513    ((INSTANCE) == TIM2)    || \
11514    ((INSTANCE) == TIM3)    || \
11515    ((INSTANCE) == TIM4)    || \
11516    ((INSTANCE) == TIM5)    || \
11517    ((INSTANCE) == TIM6)    || \
11518    ((INSTANCE) == TIM7)    || \
11519    ((INSTANCE) == TIM9)    || \
11520    ((INSTANCE) == TIM10)   || \
11521    ((INSTANCE) == TIM11)   || \
11522    ((INSTANCE) == TIM12)   || \
11523    ((INSTANCE) == TIM13)   || \
11524    ((INSTANCE) == TIM14))
11525 
11526 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
11527   (((INSTANCE) == TIM1)    || \
11528    ((INSTANCE) == TIM8))
11529 
11530 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
11531   (((INSTANCE) == TIM1)    || \
11532    ((INSTANCE) == TIM8)    || \
11533    ((INSTANCE) == TIM2)    || \
11534    ((INSTANCE) == TIM3)    || \
11535    ((INSTANCE) == TIM4)    || \
11536    ((INSTANCE) == TIM5)    || \
11537    ((INSTANCE) == TIM9)    || \
11538    ((INSTANCE) == TIM10)   || \
11539    ((INSTANCE) == TIM11)   || \
11540    ((INSTANCE) == TIM12)   || \
11541    ((INSTANCE) == TIM13)   || \
11542    ((INSTANCE) == TIM14))
11543 
11544 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
11545   (((INSTANCE) == TIM1)    || \
11546    ((INSTANCE) == TIM8)    || \
11547    ((INSTANCE) == TIM2)    || \
11548    ((INSTANCE) == TIM3)    || \
11549    ((INSTANCE) == TIM4)    || \
11550    ((INSTANCE) == TIM5)    || \
11551    ((INSTANCE) == TIM9)    || \
11552    ((INSTANCE) == TIM12))
11553 
11554 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
11555   (((INSTANCE) == TIM1)    || \
11556    ((INSTANCE) == TIM8)    || \
11557    ((INSTANCE) == TIM2)    || \
11558    ((INSTANCE) == TIM3)    || \
11559    ((INSTANCE) == TIM4)    || \
11560    ((INSTANCE) == TIM5))
11561 
11562 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
11563   (((INSTANCE) == TIM1)    || \
11564    ((INSTANCE) == TIM8)    || \
11565    ((INSTANCE) == TIM2)    || \
11566    ((INSTANCE) == TIM3)    || \
11567    ((INSTANCE) == TIM4)    || \
11568    ((INSTANCE) == TIM5))
11569 
11570 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
11571   (((INSTANCE) == TIM1)    || \
11572    ((INSTANCE) == TIM8)    || \
11573    ((INSTANCE) == TIM2)    || \
11574    ((INSTANCE) == TIM3)    || \
11575    ((INSTANCE) == TIM4)    || \
11576    ((INSTANCE) == TIM5))
11577 
11578 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
11579   (((INSTANCE) == TIM1)    || \
11580    ((INSTANCE) == TIM8)    || \
11581    ((INSTANCE) == TIM2)    || \
11582    ((INSTANCE) == TIM3)    || \
11583    ((INSTANCE) == TIM4)    || \
11584    ((INSTANCE) == TIM5))
11585 
11586 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
11587   (((INSTANCE) == TIM1)    || \
11588    ((INSTANCE) == TIM8)    || \
11589    ((INSTANCE) == TIM2)    || \
11590    ((INSTANCE) == TIM3)    || \
11591    ((INSTANCE) == TIM4)    || \
11592    ((INSTANCE) == TIM5)    || \
11593    ((INSTANCE) == TIM9)    || \
11594    ((INSTANCE) == TIM12))
11595 
11596 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
11597   (((INSTANCE) == TIM1)    || \
11598    ((INSTANCE) == TIM8)    || \
11599    ((INSTANCE) == TIM2)    || \
11600    ((INSTANCE) == TIM3)    || \
11601    ((INSTANCE) == TIM4)    || \
11602    ((INSTANCE) == TIM5)    || \
11603    ((INSTANCE) == TIM9)    || \
11604    ((INSTANCE) == TIM12))
11605 
11606 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
11607   (((INSTANCE) == TIM1)    || \
11608    ((INSTANCE) == TIM8)    || \
11609    ((INSTANCE) == TIM2)    || \
11610    ((INSTANCE) == TIM3)    || \
11611    ((INSTANCE) == TIM4)    || \
11612    ((INSTANCE) == TIM5))
11613 
11614 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
11615   (((INSTANCE) == TIM1)    || \
11616    ((INSTANCE) == TIM8)    || \
11617    ((INSTANCE) == TIM2)    || \
11618    ((INSTANCE) == TIM3)    || \
11619    ((INSTANCE) == TIM4)    || \
11620    ((INSTANCE) == TIM5))
11621 
11622 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
11623   (((INSTANCE) == TIM1)    || \
11624    ((INSTANCE) == TIM8)    || \
11625    ((INSTANCE) == TIM2)    || \
11626    ((INSTANCE) == TIM3)    || \
11627    ((INSTANCE) == TIM4)    || \
11628    ((INSTANCE) == TIM5))
11629 
11630 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
11631   (((INSTANCE) == TIM1)    || \
11632    ((INSTANCE) == TIM8)    || \
11633    ((INSTANCE) == TIM2)    || \
11634    ((INSTANCE) == TIM3)    || \
11635    ((INSTANCE) == TIM4)    || \
11636    ((INSTANCE) == TIM5)    || \
11637    ((INSTANCE) == TIM6)    || \
11638    ((INSTANCE) == TIM7)    || \
11639    ((INSTANCE) == TIM12))
11640 
11641 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
11642   (((INSTANCE) == TIM1)    || \
11643    ((INSTANCE) == TIM8)    || \
11644    ((INSTANCE) == TIM2)    || \
11645    ((INSTANCE) == TIM3)    || \
11646    ((INSTANCE) == TIM4)    || \
11647    ((INSTANCE) == TIM5)    || \
11648    ((INSTANCE) == TIM9)    || \
11649    ((INSTANCE) == TIM12))
11650 
11651 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
11652   (((INSTANCE) == TIM1)    || \
11653    ((INSTANCE) == TIM8)    || \
11654    ((INSTANCE) == TIM2)    || \
11655    ((INSTANCE) == TIM3)    || \
11656    ((INSTANCE) == TIM4)    || \
11657    ((INSTANCE) == TIM5))
11658 
11659 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
11660   (((INSTANCE) == TIM1)    || \
11661    ((INSTANCE) == TIM8))
11662 
11663 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
11664    ((((INSTANCE) == TIM1) &&                  \
11665      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11666       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11667       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11668       ((CHANNEL) == TIM_CHANNEL_4)))           \
11669     ||                                         \
11670     (((INSTANCE) == TIM8) &&                   \
11671      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11672       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11673       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11674       ((CHANNEL) == TIM_CHANNEL_4)))           \
11675     ||                                         \
11676     (((INSTANCE) == TIM2) &&                   \
11677      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11678       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11679       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11680       ((CHANNEL) == TIM_CHANNEL_4)))           \
11681     ||                                         \
11682     (((INSTANCE) == TIM3) &&                   \
11683      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11684       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11685       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11686       ((CHANNEL) == TIM_CHANNEL_4)))           \
11687     ||                                         \
11688     (((INSTANCE) == TIM4) &&                   \
11689      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11690       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11691       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11692       ((CHANNEL) == TIM_CHANNEL_4)))           \
11693     ||                                         \
11694     (((INSTANCE) == TIM5) &&                   \
11695      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11696       ((CHANNEL) == TIM_CHANNEL_2) ||          \
11697       ((CHANNEL) == TIM_CHANNEL_3) ||          \
11698       ((CHANNEL) == TIM_CHANNEL_4)))           \
11699     ||                                         \
11700     (((INSTANCE) == TIM9) &&                   \
11701      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11702       ((CHANNEL) == TIM_CHANNEL_2)))           \
11703     ||                                         \
11704     (((INSTANCE) == TIM10) &&                  \
11705      (((CHANNEL) == TIM_CHANNEL_1)))           \
11706     ||                                         \
11707     (((INSTANCE) == TIM11) &&                  \
11708      (((CHANNEL) == TIM_CHANNEL_1)))           \
11709     ||                                         \
11710     (((INSTANCE) == TIM12) &&                  \
11711      (((CHANNEL) == TIM_CHANNEL_1) ||          \
11712       ((CHANNEL) == TIM_CHANNEL_2)))           \
11713     ||                                         \
11714     (((INSTANCE) == TIM13) &&                  \
11715      (((CHANNEL) == TIM_CHANNEL_1)))           \
11716     ||                                         \
11717     (((INSTANCE) == TIM14) &&                  \
11718      (((CHANNEL) == TIM_CHANNEL_1))))
11719 
11720 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
11721    ((((INSTANCE) == TIM1) &&                    \
11722      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11723       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11724       ((CHANNEL) == TIM_CHANNEL_3)))            \
11725     ||                                          \
11726     (((INSTANCE) == TIM8) &&                    \
11727      (((CHANNEL) == TIM_CHANNEL_1) ||           \
11728       ((CHANNEL) == TIM_CHANNEL_2) ||           \
11729       ((CHANNEL) == TIM_CHANNEL_3))))
11730 
11731 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
11732   (((INSTANCE) == TIM1)    || \
11733    ((INSTANCE) == TIM8)    || \
11734    ((INSTANCE) == TIM2)    || \
11735    ((INSTANCE) == TIM3)    || \
11736    ((INSTANCE) == TIM4)    || \
11737    ((INSTANCE) == TIM5))
11738 
11739 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
11740   (((INSTANCE) == TIM1)    || \
11741    ((INSTANCE) == TIM8))
11742 
11743 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
11744   (((INSTANCE) == TIM1)    || \
11745    ((INSTANCE) == TIM8)    || \
11746    ((INSTANCE) == TIM2)    || \
11747    ((INSTANCE) == TIM3)    || \
11748    ((INSTANCE) == TIM4)    || \
11749    ((INSTANCE) == TIM5)    || \
11750    ((INSTANCE) == TIM9)    || \
11751    ((INSTANCE) == TIM10)   || \
11752    ((INSTANCE) == TIM11)   || \
11753    ((INSTANCE) == TIM12)   || \
11754    ((INSTANCE) == TIM13)   || \
11755    ((INSTANCE) == TIM14))
11756 
11757 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
11758   (((INSTANCE) == TIM1)    || \
11759    ((INSTANCE) == TIM8)    || \
11760    ((INSTANCE) == TIM2)    || \
11761    ((INSTANCE) == TIM3)    || \
11762    ((INSTANCE) == TIM4)    || \
11763    ((INSTANCE) == TIM5)    || \
11764    ((INSTANCE) == TIM6)    || \
11765    ((INSTANCE) == TIM7))
11766 
11767 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
11768   (((INSTANCE) == TIM1)    || \
11769    ((INSTANCE) == TIM8)    || \
11770    ((INSTANCE) == TIM2)    || \
11771    ((INSTANCE) == TIM3)    || \
11772    ((INSTANCE) == TIM4)    || \
11773    ((INSTANCE) == TIM5))
11774 
11775 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
11776   (((INSTANCE) == TIM1)    || \
11777    ((INSTANCE) == TIM8))
11778 
11779 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \
11780                                         ((INSTANCE) == TIM2)    || \
11781                                         ((INSTANCE) == TIM3)    || \
11782                                         ((INSTANCE) == TIM4)    || \
11783                                         ((INSTANCE) == TIM5)    || \
11784                                         ((INSTANCE) == TIM8))
11785 
11786 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
11787                                                          ((INSTANCE) == TIM2)    || \
11788                                                          ((INSTANCE) == TIM3)    || \
11789                                                          ((INSTANCE) == TIM4)    || \
11790                                                          ((INSTANCE) == TIM5)    || \
11791                                                          ((INSTANCE) == TIM8))
11792 
11793 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U
11794 
11795 /****************************** END TIM Instances *****************************/
11796 
11797 
11798 /******************** USART Instances : Synchronous mode **********************/
11799 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11800                                      ((INSTANCE) == USART2) || \
11801                                      ((INSTANCE) == USART3))
11802 
11803 /******************** UART Instances : Asynchronous mode **********************/
11804 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11805                                     ((INSTANCE) == USART2) || \
11806                                     ((INSTANCE) == USART3) || \
11807                                     ((INSTANCE) == UART4)  || \
11808                                     ((INSTANCE) == UART5))
11809 
11810 /******************** UART Instances : Half-Duplex mode **********************/
11811 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11812                                                ((INSTANCE) == USART2) || \
11813                                                ((INSTANCE) == USART3) || \
11814                                                ((INSTANCE) == UART4)  || \
11815                                                ((INSTANCE) == UART5))
11816 
11817 /******************** UART Instances : LIN mode **********************/
11818 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11819                                         ((INSTANCE) == USART2) || \
11820                                         ((INSTANCE) == USART3) || \
11821                                         ((INSTANCE) == UART4)  || \
11822                                         ((INSTANCE) == UART5))
11823 
11824 /****************** UART Instances : Hardware Flow control ********************/
11825 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11826                                            ((INSTANCE) == USART2) || \
11827                                            ((INSTANCE) == USART3))
11828 
11829 /********************* UART Instances : Smard card mode ***********************/
11830 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11831                                          ((INSTANCE) == USART2) || \
11832                                          ((INSTANCE) == USART3))
11833 
11834 /*********************** UART Instances : IRDA mode ***************************/
11835 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11836                                     ((INSTANCE) == USART2) || \
11837                                     ((INSTANCE) == USART3) || \
11838                                     ((INSTANCE) == UART4)  || \
11839                                     ((INSTANCE) == UART5))
11840 
11841 /***************** UART Instances : Multi-Processor mode **********************/
11842 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11843                                                    ((INSTANCE) == USART2) || \
11844                                                    ((INSTANCE) == USART3) || \
11845                                                    ((INSTANCE) == UART4)  || \
11846                                                    ((INSTANCE) == UART5))
11847 
11848 /***************** UART Instances : DMA mode available **********************/
11849 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
11850                                         ((INSTANCE) == USART2) || \
11851                                         ((INSTANCE) == USART3) || \
11852                                         ((INSTANCE) == UART4))
11853 
11854 /****************************** RTC Instances *********************************/
11855 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
11856 
11857 /**************************** WWDG Instances *****************************/
11858 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
11859 
11860 /****************************** USB Instances ********************************/
11861 #define IS_PCD_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == USB)
11862 
11863 
11864 
11865 #define RCC_HSE_MIN         4000000U
11866 #define RCC_HSE_MAX        16000000U
11867 
11868 #define RCC_MAX_FREQUENCY  72000000U
11869 
11870 /**
11871   * @}
11872   */
11873 /******************************************************************************/
11874 /*  For a painless codes migration between the STM32F1xx device product       */
11875 /*  lines, the aliases defined below are put in place to overcome the         */
11876 /*  differences in the interrupt handlers and IRQn definitions.               */
11877 /*  No need to update developed interrupt code when moving across             */
11878 /*  product lines within the same STM32F1 Family                              */
11879 /******************************************************************************/
11880 
11881 /* Aliases for __IRQn */
11882 #define ADC1_IRQn               ADC1_2_IRQn
11883 #define DMA2_Channel4_IRQn      DMA2_Channel4_5_IRQn
11884 #define TIM1_BRK_IRQn           TIM1_BRK_TIM9_IRQn
11885 #define TIM1_BRK_TIM15_IRQn     TIM1_BRK_TIM9_IRQn
11886 #define TIM9_IRQn               TIM1_BRK_TIM9_IRQn
11887 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
11888 #define TIM11_IRQn              TIM1_TRG_COM_TIM11_IRQn
11889 #define TIM1_TRG_COM_IRQn       TIM1_TRG_COM_TIM11_IRQn
11890 #define TIM1_UP_IRQn            TIM1_UP_TIM10_IRQn
11891 #define TIM10_IRQn              TIM1_UP_TIM10_IRQn
11892 #define TIM1_UP_TIM16_IRQn      TIM1_UP_TIM10_IRQn
11893 #define TIM6_DAC_IRQn           TIM6_IRQn
11894 #define TIM8_BRK_IRQn           TIM8_BRK_TIM12_IRQn
11895 #define TIM12_IRQn              TIM8_BRK_TIM12_IRQn
11896 #define TIM8_TRG_COM_IRQn       TIM8_TRG_COM_TIM14_IRQn
11897 #define TIM14_IRQn              TIM8_TRG_COM_TIM14_IRQn
11898 #define TIM8_UP_IRQn            TIM8_UP_TIM13_IRQn
11899 #define TIM13_IRQn              TIM8_UP_TIM13_IRQn
11900 #define CEC_IRQn                USBWakeUp_IRQn
11901 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn
11902 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn
11903 #define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn
11904 #define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn
11905 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn
11906 
11907 
11908 /* Aliases for __IRQHandler */
11909 #define ADC1_IRQHandler               ADC1_2_IRQHandler
11910 #define DMA2_Channel4_IRQHandler      DMA2_Channel4_5_IRQHandler
11911 #define TIM1_BRK_IRQHandler           TIM1_BRK_TIM9_IRQHandler
11912 #define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_TIM9_IRQHandler
11913 #define TIM9_IRQHandler               TIM1_BRK_TIM9_IRQHandler
11914 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
11915 #define TIM11_IRQHandler              TIM1_TRG_COM_TIM11_IRQHandler
11916 #define TIM1_TRG_COM_IRQHandler       TIM1_TRG_COM_TIM11_IRQHandler
11917 #define TIM1_UP_IRQHandler            TIM1_UP_TIM10_IRQHandler
11918 #define TIM10_IRQHandler              TIM1_UP_TIM10_IRQHandler
11919 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_TIM10_IRQHandler
11920 #define TIM6_DAC_IRQHandler           TIM6_IRQHandler
11921 #define TIM8_BRK_IRQHandler           TIM8_BRK_TIM12_IRQHandler
11922 #define TIM12_IRQHandler              TIM8_BRK_TIM12_IRQHandler
11923 #define TIM8_TRG_COM_IRQHandler       TIM8_TRG_COM_TIM14_IRQHandler
11924 #define TIM14_IRQHandler              TIM8_TRG_COM_TIM14_IRQHandler
11925 #define TIM8_UP_IRQHandler            TIM8_UP_TIM13_IRQHandler
11926 #define TIM13_IRQHandler              TIM8_UP_TIM13_IRQHandler
11927 #define CEC_IRQHandler                USBWakeUp_IRQHandler
11928 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler
11929 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler
11930 #define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler
11931 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler
11932 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler
11933 
11934 
11935 /**
11936   * @}
11937   */
11938 
11939 /**
11940   * @}
11941   */
11942 
11943 
11944 #ifdef __cplusplus
11945   }
11946 #endif /* __cplusplus */
11947 
11948 #endif /* __STM32F103xG_H */
11949 
11950 
11951 
11952